Three-dimensional memory and methods of making the same

Abstract

The application provides a three-dimensional memory and a manufacturing method thereof, the three-dimensional memory comprising a stack structure, a dummy structure and a gate line slit, wherein the stack structure comprises gate line layers and isolation layers which are alternately stacked in a vertical direction, the dummy structure and the gate line slit both penetrate the stack structure in the vertical direction, the dummy structure comprises a first dummy part and a second dummy part, one end of the gate line slit extends into a gap formed by the first dummy part and / or the second dummy part, and at least one of the first dummy part and the second dummy part overlaps a projection part of the gate line slit on a horizontal plane, so as to realize the connection between the dummy structure and the gate line slit. The dummy structure design which wraps the end of the gate line slit but does not completely overlap can effectively improve the process window problem of the gate line slit etching at the junction of the dummy structure and the gate line slit, effectively reduces / eliminates the weak point at the junction of the dummy structure and the gate line slit, and helps to improve the device reliability.

Description

[0001] This application is a divisional application of the patent application filed on September 29, 2020, with application number 202011046857.9, entitled "A Three-Dimensional Memory and a Method for Manufacturing the Same". Technical Field

[0002] This invention belongs to the field of semiconductor integrated circuit technology and relates to a three-dimensional memory and its fabrication method. Background Technology

[0003] With the development of planar flash memory, semiconductor manufacturing processes have made tremendous progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, limitations of existing development technologies, and limits of storage electron density. Against this backdrop, to address the difficulties encountered by planar flash memory and to pursue lower production costs per unit storage cell, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D Narrow) flash memory and 3D NAND (3D NAND) flash memory. Among them, 3D NAND memory, with its small size and large capacity, adopts a highly integrated design concept of stacking storage cells in a three-dimensional pattern, producing memory with high storage density per unit area and efficient storage cell performance, and has become the mainstream process for emerging memory design and production.

[0004] In the fabrication of 3D memory, gate line slots (GLS) are used to provide etchant application channels to remove sacrificial layers in the stacked structure and obtain lateral grooves, and to provide thin film deposition material channels to deposit conductor layers in the lateral grooves. Furthermore, gate line slots can be used to fabricate array common sources (ACS) and can be used to divide the memory array region or step connection region into multiple small regions.

[0005] However, when it is necessary to form a dummy channel via connected to the gate line slot (GLS), the weak point at the junction of the gate line slot and the dummy channel via reduces the process window for forming the gate line slot, thus increasing the process difficulty. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a three-dimensional memory and its manufacturing method, which solves the problem that the process window for forming the gate line gap is reduced when the gate line gap overlaps with the dummy structure in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a three-dimensional memory, comprising:

[0008] A stacked structure comprising alternating gate layers and dielectric layers stacked in the vertical direction;

[0009] A dummy structure extends vertically through the stacked structure, the dummy structure comprising a first dummy part and a second dummy part;

[0010] A grid line slot extends vertically through the stacked structure, with one end of the grid line slot extending into the gap formed by the first dummy portion and / or the second dummy portion. At least one of the first dummy portion and the second dummy portion overlaps with the projection portion of the grid line slot on the horizontal plane.

[0011] Optionally, in the extension direction perpendicular to the grid line slot, the width of the overlapping portion of the projection of the dummy structure and the grid line slot onto the horizontal plane is M, and the width of the grid line slot is N, where M < 0.1N.

[0012] Optionally, the first dummy part and the second dummy part are independently disposed, and the gap is located between the first dummy part and the second dummy part.

[0013] Optionally, the first dummy part and the second dummy part are arranged parallel to each other along the extension direction of the grid line gap.

[0014] Optionally, the gap is located between the first dummy part and the second dummy part, and the dummy structure further includes a third dummy part, which is located in the gap and connected to the first dummy part and the second dummy part, and the third dummy part is spaced at a preset distance from the gate line gap.

[0015] Optionally, the gaps are located in the regions enclosed by the first dummy part and the regions enclosed by the second dummy part, respectively. The dummy structure further includes a third dummy part, which is located between the first dummy part and the second dummy part and is connected to the first dummy part and the second dummy part, respectively. The third dummy part is spaced at a preset distance from the gate line gap.

[0016] Optionally, the gap is located between the first dummy part and the second dummy part, and the dummy structure further includes a third dummy part, which is connected to the end of the first dummy part away from the grid line gap and the end of the second dummy part away from the grid line gap, and the third dummy part is spaced apart from the grid line gap by a preset distance.

[0017] Optionally, the three-dimensional memory includes multiple blocks in a first horizontal direction, which are divided into stacked structures by the grid gaps. The blocks include a first core area, a step area, and a second core area arranged sequentially in a second horizontal direction, wherein the first horizontal direction and the second horizontal direction are perpendicular to each other.

[0018] Optionally, the multiple blocks include an adjacent first block and a second block, and the grid line gap includes a first grid line gap and a second grid line gap located between the first block and the second block and respectively located in the first core area and the second core area. The first grid line gap is connected to a dummy structure at one end facing the step area, and the second grid line gap is connected to a dummy structure at one end facing the step area.

[0019] Optionally, the gap is located between the first dummy part and the second dummy part, and the dummy structure further includes a third dummy part, which is connected to the end of the first dummy part away from the grid line gap and the end of the second dummy part away from the grid line gap, and the third dummy part is spaced apart from the grid line gap by a preset distance.

[0020] Optionally, the grid line gaps include multiple spaced third grid line gaps located on the side of the first block away from the second block and multiple spaced fourth grid line gaps located on the side of the second block away from the first block. The third grid line gaps and the fourth grid line gaps are located in the stepped area, and adjacent third grid line gaps are connected by the dummy structure; adjacent fourth grid line gaps are connected by the dummy structure.

[0021] Optionally, the first dummy part and the second dummy part are independently disposed, and the gap is located between the first dummy part and the second dummy part; or the gap is located between the first dummy part and the second dummy part, and the dummy structure further includes a third dummy part, which is located in the gap and connected to the first dummy part and the second dummy part, and the third dummy part is spaced apart from the gate line gap by a preset distance; or the gap is located in the area enclosed by the first dummy part and the area enclosed by the second dummy part respectively, and the dummy structure further includes a third dummy part, which is located between the first dummy part and the second dummy part and connected to the first dummy part and the second dummy part respectively, and the third dummy part is spaced apart from the gate line gap by a preset distance.

[0022] Optionally, the first block has a first retaining wall structure located in the stepped area in the edge region away from the second block, and the second block has a second retaining wall structure located in the stepped area in the edge region away from the first block. The third grid line gap is located on the side of the first retaining wall structure away from the second retaining wall structure, and the fourth grid line gap is located on the side of the second retaining wall structure away from the first retaining wall structure. Both the first retaining wall structure and the second retaining wall structure include conductive layers and insulating layers that are alternately stacked in the vertical direction.

[0023] Optionally, the dummy structure is made of insulating material.

[0024] Optionally, the bottom surface of the dummy structure is lower than the bottom surface of the grid line gap.

[0025] Optionally, it further includes a polysilicon layer, the stacked structure being disposed on the polysilicon, and the bottom of the gate gap extending at least to the surface of the polysilicon layer.

[0026] This invention also provides a method for manufacturing a three-dimensional memory, comprising the following steps:

[0027] A substrate is provided, and a stacked structure is formed on the substrate, the stacked structure including gate sacrificial layers and dielectric layers that are alternately stacked in a vertical direction;

[0028] A dummy structure is formed, which penetrates the stacked structure in a vertical direction, and the dummy structure includes a first dummy part and a second dummy part;

[0029] A grid line gap is formed, which penetrates the stacked structure in a vertical direction. One end of the grid line gap extends into the gap formed by the first dummy part and / or the second dummy part. At least one of the first dummy part and the second dummy part overlaps with the projection portion of the grid line gap on the horizontal plane.

[0030] Optionally, in the extension direction perpendicular to the grid line slot, the width of the overlapping portion of the projection of the dummy structure and the grid line slot onto the horizontal plane is M, and the width of the grid line slot is N, where M < 0.1N.

[0031] Optionally, the first dummy part and the second dummy part are independently disposed, and the gap is located between the first dummy part and the second dummy part.

[0032] Optionally, the gap is located between the first dummy part and the second dummy part, and the dummy structure further includes a third dummy part, which is located in the gap and connected to the first dummy part and the second dummy part, and the third dummy part is spaced apart from the gate line gap by a preset distance; or the gap is located in the area enclosed by the first dummy part and the area enclosed by the second dummy part, respectively, and the dummy structure further includes a third dummy part, which is located between the first dummy part and the second dummy part and connected to the first dummy part and the second dummy part, respectively, and the third dummy part is spaced apart from the gate line gap by a preset distance; or the gap is located between the first dummy part and the second dummy part, and the dummy structure further includes a third dummy part, which is connected to the end of the first dummy part away from the gate line gap and the end of the second dummy part away from the gate line gap, and the third dummy part is spaced apart from the gate line gap by a preset distance.

[0033] Optionally, the three-dimensional memory includes multiple blocks in a first horizontal direction, which are divided into stacked structures by the grid gaps. The blocks include a first core area, a step area, and a second core area arranged sequentially in a second horizontal direction, wherein the first horizontal direction and the second horizontal direction are perpendicular to each other.

[0034] Optionally, the multiple blocks include an adjacent first block and a second block, and the grid line gap includes a first grid line gap and a second grid line gap located between the first block and the second block and respectively located in the first core area and the second core area. The first grid line gap is connected to a dummy structure at one end facing the step area, and the second grid line gap is connected to a dummy structure at one end facing the step area.

[0035] Optionally, the gap is located between the first dummy part and the second dummy part, and the dummy structure further includes a third dummy part, which is connected to the end of the first dummy part away from the grid line gap and the end of the second dummy part away from the grid line gap, and the third dummy part is spaced apart from the grid line gap by a preset distance.

[0036] Optionally, the gate line gaps include multiple spaced third gate line gaps located on the side of the first block away from the second block and multiple spaced fourth gate line gaps located on the side of the second block away from the first block, with adjacent third gate line gaps connected by the dummy structure; and adjacent fourth gate line gaps connected by the dummy structure.

[0037] Optionally, the first dummy part and the second dummy part are independently disposed, and the gap is located between the first dummy part and the second dummy part; or the gap is located between the first dummy part and the second dummy part, and the dummy structure further includes a third dummy part, which is located in the gap and connected to the first dummy part and the second dummy part, and the third dummy part is spaced apart from the gate line gap by a preset distance; or the gap is located in the area enclosed by the first dummy part and the area enclosed by the second dummy part respectively, and the dummy structure further includes a third dummy part, which is located between the first dummy part and the second dummy part and connected to the first dummy part and the second dummy part respectively, and the third dummy part is spaced apart from the gate line gap by a preset distance.

[0038] Optionally, the first block has a first retaining wall structure located in the stepped area at its edge region away from the second block, and the second block has a second retaining wall structure located in the stepped area at its edge region away from the first block. The third grid line slot is located on the side of the first retaining wall structure away from the second retaining wall structure, and the fourth grid line slot is located on the side of the second retaining wall structure away from the first retaining wall structure. Both the first retaining wall structure and the second retaining wall structure include the grid line sacrificial layer and the dielectric layer that are alternately stacked in the vertical direction.

[0039] Optionally, the substrate includes, from bottom to top, a bottom polysilicon layer, a first spacer layer, a middle polysilicon layer, a second spacer layer, and a top polysilicon layer, wherein the bottom of the dummy structure extends at least to the surface of the second spacer layer, and the bottom of the gate gap extends at least to the surface of the top polysilicon layer.

[0040] As described above, in the three-dimensional memory of the present invention, the dummy structure includes a first dummy portion and a second dummy portion, with a gap between the first dummy portion and the second dummy portion. One end of the gate line slot extends into the gap, and at least one of the first dummy portion and the second dummy portion overlaps with the projection portion of the gate line slot on the horizontal plane, thereby achieving the connection between the dummy structure and the gate line slot. This dummy structure design, which wraps around the end of the gate line slot but does not completely overlap, can effectively improve the process window problem of gate line slot etching at the junction of the dummy structure and the gate line slot, effectively reduce / eliminate the weak points at the junction of the dummy structure and the gate line slot, and help improve device reliability. Attached Figure Description

[0041] Figure 1 The image shown is a cross-sectional view of the three-dimensional memory of the present invention.

[0042] Figure 2 The image shown is a partial top view of the three-dimensional memory of the present invention.

[0043] Figure 3 The first plan view shows the connection between the dummy structure and the grid line gaps.

[0044] Figure 4 The second plan view shows the connection between the dummy structure and the grid line gap.

[0045] Figure 5 The third plan view shows the connection between the dummy structure and the grid line gap.

[0046] Figure 6 The fourth plan view shows the connection between the dummy structure and the grid line gap.

[0047] Figure 7 The diagram shown is a planar layout of the three-dimensional memory of the present invention.

[0048] Figure 8 The diagram shown illustrates the process flow of the fabrication method for the three-dimensional memory of this invention.

[0049] Figure 9 The diagram shown illustrates the method for fabricating a three-dimensional memory according to the present invention, in which a multilayer structure is formed on a substrate.

[0050] Figure 10 The diagram shown illustrates the method for fabricating a three-dimensional memory according to the present invention, forming a virtual structure.

[0051] Figure 11 The diagram shown illustrates the formation of grid line slots in the fabrication method of the three-dimensional memory of the present invention.

[0052] Figure 12 The image shown is a partial top view of the structure obtained in step S3 of the method for manufacturing the three-dimensional memory of the present invention.

[0053] Component designation explanation

[0054] 1, 1a, 1b, 1c, 1d: Dummy structures

[0055] 101 First Virtual Department

[0056] 102 Second Virtual Department

[0057] 103 Third Virtual Department

[0058] 2. Grid line gap

[0059] 3 gate line layers

[0060] 4. Isolation layer

[0061] 5. Insulation materials

[0062] 6 Bottom polycrystalline silicon layer

[0063] 7 First Spacer Layer

[0064] 8. Middle polycrystalline silicon layer

[0065] 9 Second Spacer Layer

[0066] 10 Top polycrystalline silicon layer

[0067] 11 Basal layer

[0068] 12 protective layers

[0069] 13 Silicon nitride layer

[0070] 14. Silicon oxide layer

[0071] 15 First Block

[0072] 15a First finger structure

[0073] 15b Second finger structure

[0074] 15c Third finger structure

[0075] 16 Second Block

[0076] 16a Fourth finger structure

[0077] 16b Fifth finger structure

[0078] 16c sixth finger structure

[0079] 17 First grid line gap

[0080] 18 Second grid line gap

[0081] 19 Step Structure

[0082] 20 contacts

[0083] 21. Select the top grid cutout.

[0084] 22 First retaining wall structure

[0085] 23 Second retaining wall structure

[0086] 24 Third grid line gap

[0087] 25. Fourth grid line gap

[0088] 26-line sacrificial layer

[0089] Steps S1 to S3 Detailed Implementation

[0090] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0091] Please see Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0092] In a three-dimensional memory with storage array areas on both sides and a stepped connection area in the middle, to prevent structural collapse due to excessively long and dense gate line gaps, the middle portion of the gate line gap between two blocks is removed. The silicon nitride / silicon oxide remaining after the removal of the gate line sacrificial layer (silicon nitride) is used to achieve isolation between blocks. However, at the beginning of the gate line gaps, a dummy structure is needed to assist in achieving isolation between blocks. To reinforce all blocks, the gate line gaps on the great wall structure are designed to be intermittent, using the dummy structure to achieve isolation between blocks. However, a weak point exists at the junction of the gate line gaps and the dummy structure. Because the etching of the gate line gaps needs to stop on the top layer of polysilicon, but due to inconsistent etching rates caused by material differences, at the junction of the gate line gaps and the dummy structure, the dummy structure consumes a portion of the polysilicon, reducing the process window for the gate line gap etching to stop on the polysilicon. Therefore, the present invention improves the above problems through a new virtual structure design, as detailed in the following embodiments.

[0093] Example 1

[0094] This embodiment provides a three-dimensional memory. Please refer to [link / reference]. Figure 1 The image shown is a cross-sectional view of the three-dimensional memory, including a stacked structure, a dummy structure 1, and a gate line gap 2. The stacked structure includes gate line layers 3 and isolation layers 4 that are alternately stacked in the vertical direction. The dummy structure 1 and the gate line gap 2 both penetrate the stacked structure in the vertical direction.

[0095] As an example, the gate line layer 3 includes, but is not limited to, a tungsten layer; the isolation layer 4 includes, but is not limited to, a silicon oxide layer; and the dummy structure 1 and the gate line gaps are filled with insulating material 5.

[0096] As an example, the three-dimensional memory further includes a polysilicon layer, the stacked structure is disposed on the polysilicon layer, and the bottom of the gate line gap 2 extends at least to the surface of the polysilicon layer. In this embodiment, the polysilicon layer includes, from bottom to top, a bottom polysilicon layer 6, a first spacer layer 7, a middle polysilicon layer 8, a second spacer layer 9, and a top polysilicon layer 10. The bottom of both the gate line gap 2 and the dummy structure 1 is higher than the top surface of the middle polysilicon layer 8. In this embodiment, the bottom of the gate line gap 2 reaches the surface of the top polysilicon layer 10, the bottom surface of the dummy structure 1 is lower than the bottom surface of the gate line gap 2, and reaches the surface of the second spacer layer 9. The material of the first spacer layer 7 or the second spacer layer 9 includes, but is not limited to, silicon oxynitride.

[0097] As an example, below the polycrystalline silicon layer, from bottom to top, there are a substrate layer 11, a protective layer 12, a silicon nitride layer 13, and a silicon oxide layer 14. The substrate layer 11 includes, but is not limited to, a Si substrate, a Ge substrate, a SiGe substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc., and the substrate layer 11 can be P-type doped or N-type doped. The material of the protective layer 12 includes, but is not limited to, silicon oxide.

[0098] It should be noted that this is merely an example. In other embodiments, the structural layers below the stacked structure can be adjusted as needed, and this should not unduly limit the scope of protection of the present invention.

[0099] For example, please refer to Figure 2 The image is shown as a partial top view of the three-dimensional memory, wherein the aforementioned Figure 1 Presented as Figure 2 A-A' section.

[0100] Specifically, such as Figure 2 As shown, the dummy structure 1 includes a first dummy part 101 and a second dummy part 102. One end of the grid line gap 2 extends into the gap formed by the first dummy part 101 and / or the second dummy part 102. At least one of the first dummy part 101 and the second dummy part 102 overlaps with the projection portion of the grid line gap 2 on the horizontal plane.

[0101] Specifically, the gap width formed by the first dummy part 101 and / or the second dummy part 102 is smaller than the width of the grid line gap 2, so as to ensure that the projections of the dummy structure 1 and the grid line gap 2 on the horizontal plane overlap, thereby realizing the connection between the dummy structure 1 and the grid line gap 2. Ideally, the grid line gap 2 is located in the exact center of the gap formed by the first dummy part 101 and the second dummy part 102, and both the first dummy part 101 and the second dummy part 102 overlap with the projection of the grid line gap 2 on the horizontal plane; or the grid line gap 2 is located in the exact center of the gap formed by the first dummy part 101 or the second dummy part 102, and both sides of the first dummy part 101 or the second dummy part 102 overlap with the grid line gap 2. In a non-ideal situation, the grid line gap 2 deviates from the exact center of the gap, but because the gap width is smaller than the width of the grid line gap 2, regardless of which side the grid line gap 2 shifts to, it can be ensured that the projection of the dummy structure 1 and the grid line gap 2 on the horizontal plane overlaps.

[0102] As an example, in the extension direction perpendicular to the gate line slot 2, the width of the overlapping portion of the projections of the dummy structure 1 and the gate line slot 2 onto the horizontal plane is M, and the width of the gate line slot 2 is N, where M < 0.1N. That is, the width of the overlapping portion accounts for a very small proportion of the total width of the gate line slot 2, thereby effectively reducing / eliminating the weak point at the junction of the dummy structure 1 and the gate line slot 2, and helping to improve device reliability.

[0103] Specifically, under the premise of satisfying the above principles, the virtual structure 1 can have multiple forms.

[0104] For example, please refer to Figure 3 The diagram shows a first plan view of the connection between the dummy structure 1 and the gate line gap 2. In this view, the first dummy portion 101 and the second dummy portion 102 of the dummy structure 1 are independently disposed, and the gap is located between the first dummy portion 101 and the second dummy portion 102. In this embodiment, the first dummy portion 101 and the second dummy portion 102 are arranged parallel to each other along the extension direction of the gate line gap 2 and are linear.

[0105] For example, please refer to Figure 4 The diagram shows a second plan view of the connection between the dummy structure 1 and the grid line gap 2. The gap is located between the first dummy part 101 and the second dummy part 102. The dummy structure 1 also includes a third dummy part 103, which is located in the gap and connected to the first dummy part 101 and the second dummy part 102. The third dummy part 103 is spaced from the grid line gap 2 by a preset distance.

[0106] For example, please refer to Figure 5 The diagram shows a third plan view of the connection between the dummy structure 1 and the grid line gap 2. The gaps are located in the areas enclosed by the first dummy part 101 and the second dummy part 102, respectively. The dummy structure also includes a third dummy part 103, which is located between the first dummy part 101 and the second dummy part 102 and is connected to both the first dummy part 101 and the second dummy part 102. The third dummy part 103 is spaced from the grid line gap 2 by a preset distance.

[0107] For example, please refer to Figure 6 The diagram shows a fourth plan view of the connection between the dummy structure 1 and the grid line gap 2. In this view, the gap is located between the first dummy part 101 and the second dummy part 102. The first dummy part 101 and the second dummy part 102 of the dummy structure 1 are connected by a third dummy part 103. Specifically, the third dummy part 103 is connected to the end of the first dummy part 101 away from the grid line gap 2 and the end of the second dummy part 102 away from the grid line gap 2, and the third dummy part 103 is spaced from the grid line gap 2 by a preset distance.

[0108] In the aforementioned different forms of virtual structures, Figure 3 , Figure 4 and Figure 5 The dummy structure shown is more suitable for connecting the gaps between two grid lines. Figure 6 The dummy structure shown is more suitable for connecting gaps in a single grid line.

[0109] It should be noted that in other embodiments, the dummy structure may also take other forms to wrap the ends of the grid line gaps, and this should not unduly limit the scope of protection of the present invention.

[0110] For example, please refer to Figure 7 The image shows a planar layout of the three-dimensional memory. The three-dimensional memory includes multiple blocks in the first horizontal direction Y, which are divided into stacked structures by the grid gaps. The blocks include a first core area, a step area, and a second core area arranged sequentially in the second horizontal direction X. The first horizontal direction Y and the second horizontal direction X are perpendicular to each other. The step area is provided with a step structure 19, which serves as a connection area and includes multiple steps. The platform of the steps is provided with multiple contacts 20 that are connected to the grid layer.

[0111] As an example, the multiple blocks include adjacent first block 15 and second block 16. The grid line gaps include a first grid line gap 17 and a second grid line gap 18 located between the first block 15 and the second block 16, and respectively located in the first core region and the second core region. A dummy structure 1a is connected to one end of the first grid line gap 17 facing the step region, and a dummy structure 1b is connected to one end of the second grid line gap 18 facing the step region. In this embodiment, the dummy structure 1a connected to the first grid line gap 17 and the dummy structure 1b connected to the second grid line gap 17 are as described above. Figure 6 The shape shown is as follows. The first gate line gap 17, the dummy structure 1a, the insulating material (not shown) remaining between the first block 15 and the second block 16 after the gate line sacrificial layer is etched, the dummy structure 1b and the second gate line gap 18 are connected in sequence to achieve isolation between the first block 15 and the second block 16.

[0112] As an example, both the first block 15 and the second block 16 include multiple finger structures, such as 2-10 finger structures. In this embodiment, in the direction from the first block 15 to the second block, the first block 15 sequentially includes a first finger structure 15a, a second finger structure 15b, and a third finger structure 15c, and the second block 16 sequentially includes a fourth finger structure 16a, a fifth finger structure 16b, and a sixth finger structure 16c. In each block, adjacent finger structures are separated by discontinuously arranged gate line gaps. The purpose of using discontinuously arranged gate line gaps is to ensure that the gate line layers of adjacent finger structures remain connected.

[0113] As an example, the storage area of ​​the finger structure has a top selection gate cutout 21 in the middle, which divides the top selection gate layer of the storage area into two parts to divide the storage area into two independent programmable (read / write) pages.

[0114] As an example, to achieve reinforcement between all blocks, the grid line slots further include multiple spaced third grid line slots 24 located on the side of the first block 15 away from the second block 16, and multiple spaced fourth grid line slots 25 located on the side of the second block 16 away from the first block 15. The third and fourth grid line slots 24 are located in the stepped area, and adjacent third grid line slots 24 are connected by a dummy structure 1c; adjacent fourth grid line slots 25 are connected by a dummy structure 1d. The dummy structure 1c and d are preferably constructed using... Figure 3 , Figure 4 , Figure 5 The virtual structure shown.

[0115] As an example, the first block 15 is provided with a first barrier structure 22 in the edge region away from the second block 16 (in this embodiment, the edge region of the first finger structure 15a), and the second block 16 is provided with a second barrier structure 23 in the edge region away from the first block 15 (in this embodiment, the edge region of the sixth finger structure 16c). The third gate line gap 1c is located on the side of the first barrier structure 22 away from the second barrier structure 23, and the fourth gate line gap 1d is located on the side of the second barrier structure 23 away from the first barrier structure 23. Both the first barrier structure 22 and the second barrier structure 23 include conductive layers (e.g., tungsten layers) and insulating layers (e.g., silicon oxide layers) that are alternately stacked in the vertical direction. The first barrier structure 22 and the second barrier structure 23 are used for electrical connection at both ends of the block structure. The cross-sectional areas of the first retaining wall structure 22 and the second retaining wall structure 23 can gradually increase from top to bottom. The dashed box area in the first finger structure 15a is shown as the projection area of ​​the first conductive wall 22 on the horizontal plane, and its area is larger than the top area of ​​the first conductive wall 22. The dashed box area in the sixth finger structure 16c is shown as the projection area of ​​the second conductive wall 23 on the horizontal plane, and its area is larger than the top area of ​​the second conductive wall 23.

[0116] In this embodiment of the three-dimensional memory, the dummy structure includes a first dummy portion and a second dummy portion, with a gap between them. One end of the gate line slot extends into the gap. At least one of the first dummy portion and the second dummy portion overlaps with the projection of the gate line slot on the horizontal plane, thereby connecting the dummy structure to the gate line slot. This dummy structure design, which wraps around the end of the gate line slot but does not completely overlap it, can effectively improve the process window problem of gate line slot etching at the junction of the dummy structure and the gate line slot, effectively reducing / eliminating the weak points at the junction of the dummy structure and the gate line slot, and helping to improve device reliability.

[0117] Example 2

[0118] This embodiment provides a method for fabricating a three-dimensional memory. Please refer to [link / reference]. Figure 8 The diagram shows the process flow of this method, which includes the following steps:

[0119] S1: A substrate is provided, and a stacked structure is formed on the substrate, the stacked structure including gate sacrificial layers and isolation layers that are alternately stacked in the vertical direction;

[0120] S2: A dummy structure is formed, the dummy structure penetrating the stacked structure in a vertical direction, the dummy structure including a first dummy part and a second dummy part;

[0121] S3: Forming a grid line gap, the grid line gap penetrating the stacked structure vertically, one end of the grid line gap extending into the gap formed by the first dummy part and / or the second dummy part, at least one of the first dummy part and the second dummy part overlapping the projection portion of the grid line gap on the horizontal plane.

[0122] Please refer to the following first. Figure 9 Step S1: A substrate is provided, and a stacked structure is formed on the substrate. The stacked structure includes gate line sacrificial layers 26 and isolation layers 4 alternately stacked in the vertical direction. The gate line sacrificial layers 26 include, but are not limited to, silicon nitride layers, and the isolation layers 4 include, but are not limited to, silicon oxide layers. The gate line sacrificial layers will be removed in subsequent processes and refilled with gate line material, such as tungsten, to obtain gate lines.

[0123] As an example, the substrate, from bottom to top, includes a base layer 11, a protective layer 12, a silicon nitride layer 13, a silicon oxide layer 14, a bottom polysilicon layer 6, a first spacer layer 7, a middle polysilicon layer 8, a second spacer layer 9, and a top polysilicon layer 10. The base layer 11 includes, but is not limited to, Si substrates, Ge substrates, SiGe substrates, silicon-on-insulator (SOI) substrates, or germanium-on-insulator (GOI) substrates, and can be P-type doped or N-type doped. The protective layer 12 is made of, but is not limited to, silicon oxide. The first spacer layer 7 or the second spacer layer 9 is made of, but is not limited to, silicon oxynitride. The middle polysilicon layer 8 serves as a sacrificial layer and will be removed and refilled later. It should be noted that this is merely an example; in other embodiments, the structural layers in the substrate can be adjusted as needed, and this should not unduly limit the scope of the invention.

[0124] Then please see Figure 10 Step S2: A dummy structure 1 is formed by one or more wet etching and / or dry etching processes (e.g., deep reactive ion etching (DRIE)), and an insulating material 5 is filled into the dummy structure 1, wherein the dummy structure 1 penetrates the stacked structure in a vertical direction. In this embodiment, the bottom of the dummy structure 1 reaches the surface of the second spacer layer 9.

[0125] Please see again Figure 11 Step S3 is performed: a gate line slot 2 is formed by one or more wet etching and / or dry etching processes, the gate line slot 2 penetrating the stacked structure in a vertical direction. In this embodiment, the bottom of the gate line slot 2 reaches the surface of the top polysilicon layer 10.

[0126] For example, please refer to Figure 12The image shows a partial top view of the structure obtained in this step. It can be seen that the dummy structure 1 includes a first dummy part 101 and a second dummy part 102. One end of the grid line gap 2 extends into the gap formed by the first dummy part 101 and / or the second dummy part 102. At least one of the first dummy part 101 and the second dummy part 102 overlaps with the projection portion of the grid line gap 2 on the horizontal plane.

[0127] Specifically, the gap width formed by the first dummy part 101 and / or the second dummy part 102 is smaller than the width of the grid line gap 2, so as to ensure that the projections of the dummy structure 1 and the grid line gap 2 on the horizontal plane overlap, thereby realizing the connection between the dummy structure 1 and the grid line gap 2. Ideally, the grid line gap 2 is located in the exact center of the gap formed by the first dummy part 101 and the second dummy part 102, and both the first dummy part 101 and the second dummy part 102 overlap with the projection of the grid line gap 2 on the horizontal plane; or the grid line gap 2 is located in the exact center of the gap formed by the first dummy part 101 or the second dummy part 102, and both sides of the first dummy part 101 or the second dummy part 102 overlap with the grid line gap 2. In a non-ideal situation, the grid line gap 2 deviates from the exact center of the gap, but because the gap width is smaller than the width of the grid line gap 2, regardless of which side the grid line gap 2 shifts to, it can be ensured that the projection of the dummy structure 1 and the grid line gap 2 on the horizontal plane overlaps.

[0128] As an example, in the extension direction perpendicular to the gate slot 2, the width of the overlapping portion of the projections of the dummy structure 1 and the gate slot 2 onto the horizontal plane is M, and the width of the gate slot 2 is N, where M < 0.1N. That is, the width of the overlapping portion accounts for a very small proportion of the total width of the gate slot 2, thereby effectively reducing / eliminating the weak point at the junction of the dummy trench structure 1 and the gate slot 2, and helping to improve device reliability.

[0129] Specifically, under the premise of satisfying the above principles, the virtual structure 1 can have multiple forms.

[0130] For example, please refer to Figure 3 The diagram shows a first plan view of the connection between the dummy structure 1 and the gate line gap 2. In this view, the first dummy portion 101 and the second dummy portion 102 of the dummy structure 1 are independently disposed, and the gap is located between the first dummy portion 101 and the second dummy portion 102. In this embodiment, the first dummy portion 101 and the second dummy portion 102 are arranged parallel to each other along the extension direction of the gate line gap 2 and are linear.

[0131] For example, please refer to Figure 4 The diagram shows a second plan view of the connection between the dummy structure 1 and the grid line gap 2. The gap is located between the first dummy part 101 and the second dummy part 102. The dummy structure 1 also includes a third dummy part 103, which is located in the gap and connected to the first dummy part 101 and the second dummy part 102. The third dummy part 103 is spaced from the grid line gap 2 by a preset distance.

[0132] For example, please refer to Figure 5 The diagram shows a third plan view of the connection between the dummy structure 1 and the grid line gap 2. The gaps are located in the areas enclosed by the first dummy part 101 and the second dummy part 102, respectively. The dummy structure also includes a third dummy part 103, which is located between the first dummy part 101 and the second dummy part 102 and is connected to both the first dummy part 101 and the second dummy part 102. The third dummy part 103 is spaced from the grid line gap 2 by a preset distance.

[0133] For example, please refer to Figure 6 The diagram shows a fourth plan view of the connection between the dummy structure 1 and the grid line gap 2. In this view, the gap is located between the first dummy part 101 and the second dummy part 102. The first dummy part 101 and the second dummy part 102 of the dummy structure 1 are connected by a third dummy part 103. Specifically, the third dummy part 103 is connected to the end of the first dummy part 101 away from the grid line gap 2 and the end of the second dummy part 102 away from the grid line gap 2, and the third dummy part 103 is spaced from the grid line gap 2 by a preset distance.

[0134] It should be noted that the above Figure 12 The invention presents three different forms of virtual structures, but in practical applications, the same or different forms of virtual structures can be flexibly selected as needed. This should not excessively limit the scope of protection of the invention. Figure 3 , Figure 4 and Figure 5 The dummy structure shown is more suitable for connecting the gaps between two grid lines. Figure 6 The dummy structure shown is more suitable for connecting gaps in a single grid line.

[0135] It should be noted that in other embodiments, the dummy structure may also take other forms to wrap the ends of the grid line gaps, and this should not unduly limit the scope of protection of the present invention.

[0136] Specifically, the gate sacrificial layer can be removed to obtain a lateral groove, and a gate layer can be deposited in the lateral groove.

[0137] In the fabrication method of the three-dimensional memory in this embodiment, the interface area between the dummy structure and the gate line gap is very small, and the mutual influence is small. This can expand the process window for etching the gate line gap at the interface between the dummy structure and the gate line gap, effectively reduce / eliminate the weak points at the interface between the dummy structure and the gate line gap, and help improve the reliability of the device.

[0138] In summary, in the three-dimensional memory of the present invention, the dummy structure includes a first dummy portion and a second dummy portion, with a gap between the first dummy portion and the second dummy portion. One end of the gate line slot extends into the gap, and at least one of the first dummy portion and the second dummy portion overlaps with the projection portion of the gate line slot on the horizontal plane, thereby achieving the connection between the dummy structure and the gate line slot. This dummy structure design, which wraps around the end of the gate line slot but does not completely overlap, can effectively improve the process window problem of gate line slot etching at the junction of the dummy structure and the gate line slot, effectively reduce / eliminate the weak points at the junction of the dummy structure and the gate line slot, and help improve device reliability. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0139] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A three-dimensional memory, characterized in that, include: A stacked structure comprising alternating gate layers and dielectric layers stacked in the vertical direction; A dummy structure extends vertically through the stacked structure, the dummy structure comprising a first dummy part and a second dummy part; A grid line slot extends vertically through the stacked structure, with one end of the grid line slot extending into the gap formed by the first dummy portion and / or the second dummy portion. At least one of the first dummy portion and the second dummy portion overlaps with the projection portion of the grid line slot on the horizontal plane.

2. The three-dimensional memory according to claim 1, characterized in that: In the direction perpendicular to the extension of the grid line slot, the width of the overlapping portion of the projection of the dummy structure and the grid line slot onto the horizontal plane is M, and the width of the grid line slot is N, where M < 0.1N.

3. The three-dimensional memory according to claim 1, characterized in that: The first dummy part and the second dummy part are independently provided, and the gap is located between the first dummy part and the second dummy part.

4. The three-dimensional memory according to claim 3, characterized in that: The first dummy part and the second dummy part are arranged parallel to each other along the extension direction of the grid line gap.

5. The three-dimensional memory according to claim 1, characterized in that: The gap is located between the first dummy part and the second dummy part. The dummy structure also includes a third dummy part, which is located in the gap and connected to the first dummy part and the second dummy part. The third dummy part is spaced at a preset distance from the gate line gap.

6. The three-dimensional memory according to claim 1, characterized in that: The gaps are located in the areas enclosed by the first dummy part and the areas enclosed by the second dummy part, respectively. The dummy structure also includes a third dummy part, which is located between the first dummy part and the second dummy part and is connected to the first dummy part and the second dummy part, respectively. The third dummy part is spaced at a preset distance from the gap of the grid line.

7. The three-dimensional memory according to claim 1, characterized in that: The gap is located between the first dummy part and the second dummy part. The dummy structure also includes a third dummy part, which is connected to the end of the first dummy part away from the grid line gap and the end of the second dummy part away from the grid line gap. The third dummy part is spaced at a preset distance from the grid line gap.

8. The three-dimensional memory according to any one of claims 1-7, characterized in that: The three-dimensional memory includes a core region and a stepped region arranged sequentially in a second horizontal direction. The grid line gap includes a first grid line gap located in the core region, and a dummy structure is connected to one end of the first grid line gap facing the stepped region.

9. The three-dimensional memory according to any one of claims 1-7, characterized in that: The three-dimensional memory includes multiple blocks in a first horizontal direction, which are divided by the grid gaps of the stacked structure. The blocks include a first core area, a step area, and a second core area arranged sequentially in a second horizontal direction. The first horizontal direction and the second horizontal direction are perpendicular to each other.

10. The three-dimensional memory according to claim 9, characterized in that: The multiple blocks include an adjacent first block and a second block. The grid line gap includes a first grid line gap located between the first block and the second block and located in the first core area. The grid line gap includes a second grid line gap located between the first block and the second block and located in the second core area. One end of the first grid line gap facing the step area is connected to a dummy structure. One end of the second grid line gap facing the step area is connected to a dummy structure.

11. The three-dimensional memory according to claim 10, characterized in that: The gap is located between the first dummy part and the second dummy part. The dummy structure also includes a third dummy part, which is connected to the end of the first dummy part away from the grid line gap and the end of the second dummy part away from the grid line gap. The third dummy part is spaced at a preset distance from the grid line gap.

12. The three-dimensional memory according to claim 10, characterized in that: The grid line gaps include multiple spaced third grid line gaps located on the side of the first block away from the second block and multiple spaced fourth grid line gaps located on the side of the second block away from the first block. The third grid line gaps and the fourth grid line gaps are located in the stepped area. Adjacent third grid line gaps are connected by the dummy structure. Adjacent fourth grid line gaps are also connected by the dummy structure.

13. The three-dimensional memory according to claim 12, characterized in that: The first dummy part and the second dummy part are independently disposed, and the gap is located between the first dummy part and the second dummy part; or the gap is located between the first dummy part and the second dummy part, and the dummy structure further includes a third dummy part, which is located in the gap and connected to the first dummy part and the second dummy part, and the third dummy part is spaced apart from the gate line gap by a preset distance; or the gap is located in the area enclosed by the first dummy part and the area enclosed by the second dummy part respectively, and the dummy structure further includes a third dummy part, which is located between the first dummy part and the second dummy part and connected to the first dummy part and the second dummy part respectively, and the third dummy part is spaced apart from the gate line gap by a preset distance.

14. The three-dimensional memory according to claim 12, characterized in that: The first block has a first retaining wall structure located in the stepped area in the edge region away from the second block, and the second block has a second retaining wall structure located in the stepped area in the edge region away from the first block. The third grid line gap is located on the side of the first retaining wall structure away from the second retaining wall structure, and the fourth grid line gap is located on the side of the second retaining wall structure away from the first retaining wall structure. Both the first retaining wall structure and the second retaining wall structure include conductive layers and insulating layers that are alternately stacked in the vertical direction.

15. The three-dimensional memory according to any one of claims 1-7, characterized in that: The virtual structure is made of insulating material.

16. The three-dimensional memory according to any one of claims 1-7, characterized in that: The bottom surface of the dummy structure is lower than the bottom surface of the grid line gap.

17. The three-dimensional memory according to any one of claims 1-7, characterized in that: It also includes a polysilicon layer, the stacked structure being disposed on the polysilicon, and the bottom of the gate gap extending at least to the surface of the polysilicon layer.

18. A method for fabricating a three-dimensional memory, characterized in that, Includes the following steps: A substrate is provided, and a stacked structure is formed on the substrate, the stacked structure including gate sacrificial layers and dielectric layers that are alternately stacked in a vertical direction; A dummy structure is formed, which penetrates the stacked structure in a vertical direction, and the dummy structure includes a first dummy part and a second dummy part; A grid line gap is formed, which penetrates the stacked structure in a vertical direction. One end of the grid line gap extends into the gap formed by the first dummy part and / or the second dummy part. At least one of the first dummy part and the second dummy part overlaps with the projection portion of the grid line gap on the horizontal plane.

19. The method for manufacturing a three-dimensional memory according to claim 18, characterized in that: In the direction perpendicular to the extension of the grid line slot, the width of the overlapping portion of the projection of the dummy structure and the grid line slot onto the horizontal plane is M, and the width of the grid line slot is N, where M < 0.1N.

20. The method for manufacturing a three-dimensional memory according to claim 18, characterized in that: The first dummy part and the second dummy part are independently provided, and the gap is located between the first dummy part and the second dummy part.

21. The method for manufacturing a three-dimensional memory according to claim 18, characterized in that: The gap is located between the first dummy part and the second dummy part. The dummy structure further includes a third dummy part, which is located in the gap and connected to both the first dummy part and the second dummy part, and the third dummy part is spaced at a preset distance from the gate line gap. Alternatively, the gap is located in the area enclosed by the first dummy part and the area enclosed by the second dummy part, respectively. The dummy structure further includes a third dummy part, which is located between the first dummy part and the second dummy part and connected to both the first dummy part and the second dummy part, and the third dummy part is spaced at a preset distance from the gate line gap. Alternatively, the gap is located between the first dummy part and the second dummy part, and the dummy structure further includes a third dummy part, which is connected to the end of the first dummy part away from the gate line gap and the end of the second dummy part away from the gate line gap, and the third dummy part is spaced at a preset distance from the gate line gap.

22. The method for manufacturing a three-dimensional memory according to any one of claims 18-21, characterized in that: The three-dimensional memory includes a core region and a stepped region arranged sequentially in a second horizontal direction. The grid line gap includes a first grid line gap located in the core region, and a dummy structure is connected to one end of the first grid line gap facing the stepped region.

23. The method for manufacturing a three-dimensional memory according to any one of claims 18-21, characterized in that: The three-dimensional memory includes multiple blocks in a first horizontal direction, which are divided by the grid gaps of the stacked structure. The blocks include a first core area, a step area, and a second core area arranged sequentially in a second horizontal direction. The first horizontal direction and the second horizontal direction are perpendicular to each other.

24. The method for manufacturing a three-dimensional memory according to claim 23, characterized in that: The multiple blocks include an adjacent first block and a second block. The grid line gap includes a first grid line gap located between the first block and the second block and located in the first core area. The grid line gap includes a second grid line gap located between the first block and the second block and located in the second core area. One end of the first grid line gap facing the step area is connected to a dummy structure. One end of the second grid line gap facing the step area is connected to a dummy structure.

25. The method for manufacturing a three-dimensional memory according to claim 24, characterized in that: The gap is located between the first dummy part and the second dummy part. The dummy structure also includes a third dummy part, which is connected to the end of the first dummy part away from the grid line gap and the end of the second dummy part away from the grid line gap. The third dummy part is spaced at a preset distance from the grid line gap.

26. The method for manufacturing a three-dimensional memory according to claim 24, characterized in that: The grid line gaps include multiple spaced third grid line gaps located on the side of the first block away from the second block and multiple spaced fourth grid line gaps located on the side of the second block away from the first block. Adjacent third grid line gaps are connected by the dummy structure; adjacent fourth grid line gaps are connected by the dummy structure.

27. The method for manufacturing a three-dimensional memory according to claim 26, characterized in that: The first dummy part and the second dummy part are independently disposed, and the gap is located between the first dummy part and the second dummy part; or the gap is located between the first dummy part and the second dummy part, and the dummy structure further includes a third dummy part, which is located in the gap and connected to the first dummy part and the second dummy part, and the third dummy part is spaced apart from the gate line gap by a preset distance; or the gap is located in the area enclosed by the first dummy part and the area enclosed by the second dummy part respectively, and the dummy structure further includes a third dummy part, which is located between the first dummy part and the second dummy part and connected to the first dummy part and the second dummy part respectively, and the third dummy part is spaced apart from the gate line gap by a preset distance.

28. The method for manufacturing a three-dimensional memory according to claim 26, characterized in that: The first block has a first retaining wall structure located in the stepped area in the edge region away from the second block, and the second block has a second retaining wall structure located in the stepped area in the edge region away from the first block. The third grid line gap is located on the side of the first retaining wall structure away from the second retaining wall structure, and the fourth grid line gap is located on the side of the second retaining wall structure away from the first retaining wall structure. Both the first retaining wall structure and the second retaining wall structure include the grid line sacrificial layer and the dielectric layer that are alternately stacked in the vertical direction.

29. The method for manufacturing a three-dimensional memory according to claim 18, characterized in that: The substrate comprises, from bottom to top, a bottom polysilicon layer, a first spacer layer, a middle polysilicon layer, a second spacer layer, and a top polysilicon layer. The bottom of the dummy structure extends at least to the surface of the second spacer layer, and the bottom of the gate gap extends at least to the surface of the top polysilicon layer.

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