Resistive random access memory and manufacturing method thereof

Abstract

The present invention provides a resistance random access memory, comprising: a dielectric layer, a lower electrode, a data storage layer, an isolation structure, a first oxygen storage layer, a second oxygen storage layer and an upper electrode. The lower electrode protrudes from the top surface of the dielectric layer. The data storage layer conformally covers the lower electrode and the dielectric layer. The isolation structure is configured on the lower electrode. The first oxygen storage layer is configured on the data storage layer at the first side of the isolation structure. The second oxygen storage layer is configured on the data storage layer at the second side of the isolation structure. The isolation structure separates the first oxygen storage layer and the second oxygen storage layer. The upper electrode is configured on the first oxygen storage layer and the second oxygen storage layer and is shared by the first oxygen storage layer and the second oxygen storage layer. A manufacturing method of a resistance random access memory is also provided.

Description

Technical Field

[0001] The invention relates to a resistance random access memory and a manufacturing method thereof. Background Art

[0002] In recent years, the development of Resistive Random Access Memory (RRAM) has been extremely rapid and is currently the most anticipated future memory structure. RRAM is very suitable as the next generation of non-volatile memory components due to its potential advantages of low power consumption, high-speed operation, high density and compatibility with complementary metal oxide semiconductor (CMOS) process technology.

[0003] Current RRAM requires a thicker transition metal oxide (TMO) layer to improve high-temperature data retention (HTDR). However, when patterning a TMO layer that is too thick, the sidewalls of the TMO layer will be damaged, causing subsequent RRAM operation to fail. In addition, a TMO layer that is too thick will also cause additional reliability issues during the formation operation. Summary of the invention

[0004] The present invention provides a resistance random access memory and a manufacturing method thereof, which can increase current gain by maintaining a data storage layer at a certain thickness, thereby improving memory performance.

[0005] The present invention provides a resistance random access memory including: a dielectric layer, a lower electrode, a data storage layer, an isolation structure, a first oxygen storage layer, a second oxygen storage layer and an upper electrode. The lower electrode protrudes from the top surface of the dielectric layer. The data storage layer conformally covers the lower electrode and the dielectric layer. The isolation structure is configured on the lower electrode. The data storage layer is sandwiched between the isolation structure and the lower electrode. The first oxygen storage layer is configured on the data storage layer at a first side of the isolation structure. The second oxygen storage layer is configured on the data storage layer at a second side of the isolation structure. The isolation structure separates the first oxygen storage layer and the second oxygen storage layer. The upper electrode is configured on the first oxygen storage layer and the second oxygen storage layer and is shared by the first oxygen storage layer and the second oxygen storage layer.

[0006] The present invention provides a method for manufacturing a resistive random access memory, comprising: forming a lower electrode protruding from a top surface of a dielectric layer; conformally forming a data storage layer on the lower electrode and the dielectric layer; forming an oxygen storage material layer on the data storage layer; forming an opening in the oxygen storage material layer to expose the data storage layer on the lower electrode; forming an isolation structure in the opening, wherein the isolation structure separates the oxygen storage material layer into a first oxygen storage layer and a second oxygen storage layer; and forming an upper electrode on the first oxygen storage layer and the second oxygen storage layer, wherein the first oxygen storage layer and the second oxygen storage layer share the upper electrode.

[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1G is a cross-sectional schematic diagram of a manufacturing process of a resistance random access memory according to a first embodiment of the present invention;

[0009] Figure 2A and Figure 2B They are Figure 1E A top view of a

[0010] Figure 3 is a cross-sectional schematic diagram of a resistance random access memory according to a second embodiment of the present invention;

[0011] Figure 4 FIG. 4 is a cross-sectional diagram of a resistance random access memory according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0012] The present invention is more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the accompanying drawings are exaggerated for clarity. The same or similar component symbols represent the same or similar components, and the following paragraphs will not be repeated one by one.

[0013] Figures 1A to 1G FIG. 4 is a cross-sectional schematic diagram of a manufacturing process of a resistance random access memory according to a first embodiment of the present invention.

[0014] A first embodiment of the present invention provides a resistance random access memory 100 (eg Figure 1G The manufacturing method of the invention comprises the following steps. First, please refer to Figure 1A, providing a substrate 102. In one embodiment, the substrate 102 includes a semiconductor substrate, such as a silicon substrate. Then, a dielectric layer 104 and a lower electrode 106 are formed on the substrate 102. The lower electrode 106 is buried in the dielectric layer 104. In one embodiment, the material of the dielectric layer 104 includes silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. The material of the lower electrode 106 includes a conductive material, which may be, for example, a metal material, a metal nitride or other suitable conductive material. For example, the lower electrode 106 may be a TiN layer. In this embodiment, the dielectric layer 104 may be regarded as an intermetallic dielectric (IMD) layer. In this case, the lower electrode 106 may be electrically connected to a component layer (not shown) between the substrate 102 and the lower electrode 106. The component layer includes active components, such as transistors, diodes and the like.

[0015] Please refer to Figure 1A and Figure 1B , an etch-back process is performed to remove a portion of the dielectric layer 104, so that the lower electrode 106 protrudes from the top surface 104t of the dielectric layer 104a. In other words, the top surface 104t of the dielectric layer 104a is lower than the top surface 106t of the lower electrode 106. In one embodiment, the height 106h of the lower electrode 106 protruding from the dielectric layer 104a can be 10nm to 100nm. The above-mentioned etch-back process can be a wet etching process or an isotropic etching process.

[0016] Please refer to Figure 1C , a data storage layer 108 is conformally formed on the lower electrode 106 and the dielectric layer 104a. In one embodiment, the material of the data storage layer 108 includes at least one oxide material selected from the group consisting of TiO2, NiO, HfO, HfO2, ZrO, ZrO2, Ta2O5, ZnO, WO3, CoO and Nb2O5, and the data storage layer 108 is formed by atomic layer deposition (ALD), chemical vapor deposition (CVD) or similar deposition methods. For example, the data storage layer 108 may be a HfO2 layer, and the thickness 108t of the data storage layer 108 may be 3nm to 15nm. However, the present invention is not limited thereto. In other embodiments, the material of the data storage layer 108 is a variable resistance material that can change its own resistance through the application of voltage.

[0017] Please refer to Figure 1D, an oxygen reservoir material layer 110 is formed on the data storage layer 108. In one embodiment, the material of the oxygen reservoir material layer 110 may include a suitable metal material such as Ti, Ta, Hf, Zr, Al or a combination thereof, and the method of forming the oxygen reservoir material layer 110 may be physical vapor deposition (PVD). For example, the oxygen reservoir material layer 110 may be a Ti layer, and the thickness 110t of the oxygen reservoir material layer 110 may be 100nm to 300nm. The thickness of the oxygen reservoir material layer 110 may be greater than the height 106h of the lower electrode 106 protruding from the dielectric layer 104a, so as to cover the top surface 106t of the lower electrode 106. In an alternative embodiment, the oxygen reservoir material layer 110 may have a greater adsorption or binding capacity for oxygen ions than the data storage layer 108, so as to quickly adsorb or bind oxygen ions when the memory cell is operated, thereby generating a filament in the data storage layer 108.

[0018] Please refer to Figure 1D and Figure 1E , a patterning process is performed to form an opening 112 in the oxygen storage material layer 110. The opening 112 exposes the data storage layer 108 directly above the lower electrode 106. Specifically, Figure 1E As shown, the opening 112 not only exposes the data storage layer 108 on the top surface 106t of the lower electrode 106, but also exposes the data storage layer 108 on the upper sidewall 106s of the lower electrode 106. Figure 2A From the perspective of FIG. 1 , the lower electrode 106 may be circular, and the opening 112 may also be circular. The area of ​​the opening 112 is larger than the area of ​​the lower electrode 106, and the opening 112 completely covers the lower electrode 106. However, the present invention is not limited thereto. Figure 2B As shown, the lower electrode 106 may be rectangular or in other shapes, and the opening 112 may also be rectangular or in other shapes.

[0019] After the opening 112 is formed, the continuous oxygen storage material layer 110 is separated into a first oxygen storage layer 110a and a second oxygen storage layer 110b by the opening 112. The first oxygen storage layer 110a is located on the data storage layer 108 at the first side 112s1 of the opening 112, and the second oxygen storage layer 110b is located on the data storage layer 108 at the second side 112s2 of the opening 112. It is worth noting that in one embodiment, the data storage layer 108 can be regarded as an etching stop layer of the above-mentioned patterning process. In this case, the data storage layer 108 exposed to the opening 112 will be consumed in the above-mentioned patterning process, so that the data storage layer 108 exposed to the opening 112 has a first thickness 108t1, and the data storage layer 108 not exposed to the opening 112 has a second thickness 108t2. In this embodiment, the first thickness 108t1 is less than the second thickness 108t2.

[0020] Please refer to Figure 1F , forming an isolation structure 114 in the opening 112. Specifically, the method for forming the isolation structure 114 includes: forming a barrier material conformally in the opening 112; forming an insulating material on the barrier material to fill the opening 112 and extend to cover the first oxygen storage layer 110a and the second oxygen storage layer 110b; and performing a planarization process (such as a CMP process) to remove part of the insulating material and part of the barrier material to expose the top surface 110t1 of the first oxygen storage layer 110a and the top surface 110t2 of the second oxygen storage layer 110b. After the planarization process, the isolation structure 114 includes a first barrier layer 116 and an insulating layer 118. The first barrier layer 116 conformally covers the opening 112. The insulating layer 118 is located on the first barrier layer 116 and fills the opening 112. In the present embodiment, the first barrier layer 116 may be used as an oxygen diffusion barrier layer to prevent oxygen ions from moving between the insulating layer 118 and the first oxygen storage layer 110a or between the insulating layer 118 and the second oxygen storage layer 110b. In one embodiment, the material of the first barrier layer 116 includes a suitable dielectric material such as aluminum oxide (Al2O3), silicon nitride, silicon carbide, silicon carbonitride, or a combination thereof, and the thickness of the first barrier layer 116 may be 1 nm to 15 nm. The material of the insulating layer 118 includes a suitable insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In addition, after the planarization process is performed, the top surface 114t of the isolation structure 114 may be coplanar with the top surface 110t1 of the first oxygen storage layer 110a and the top surface 110t2 of the second oxygen storage layer 110b.

[0021] From another perspective, Figure 1D and Figure 1F As shown, the isolation structure 114 separates the continuous oxygen storage material layer 110 into a first oxygen storage layer 110a and a second oxygen storage layer 110b. The first oxygen storage layer 110a is located on the data storage layer 108 at the first side 114s1 of the isolation structure 114, and the second oxygen storage layer 110b is located on the data storage layer 108 at the second side 114s2 of the isolation structure 114. The isolation structure 114 covers the data storage layer 108 on the top surface 106t of the lower electrode 106, and extends to cover the data storage layer 108 on the upper sidewall 106s of the lower electrode 106, as shown in FIG. Figure 1F In this embodiment, the data storage layer 108 covering the top surface 106t of the lower electrode 106 has a first thickness 108t1, and the top surface 104t covering the dielectric layer 104a has a second thickness 108t2, and the first thickness 108t1 is smaller than the second thickness 108t2.

[0022] Please refer to Figure 1G, a second barrier layer 120 is formed on the isolation structure 114, the first oxygen storage layer 110a and the second oxygen storage layer 110b. In one embodiment, the material of the second barrier layer 120 includes a suitable dielectric material such as aluminum oxide, silicon nitride, silicon carbide, silicon carbonitride, or a combination thereof. The thickness of the second barrier layer 120 can be 1 nm to 10 nm. The second barrier layer 120 and the first barrier layer 116 can have the same material or different materials. In this embodiment, the second barrier layer 120 can be used as an oxygen diffusion barrier layer to prevent oxygen ions from diffusing from the first oxygen storage layer 110a (or the second oxygen storage layer 110b) to the upper electrode 122, and prevent them from returning to the data storage layer 108 again, thereby avoiding the problem of component failure.

[0023] Then, an upper electrode 122 is formed on the second barrier layer 120 so that the second barrier layer 120 is located between the upper electrode 122 and the isolation structure 114, between the upper electrode 122 and the first oxygen storage layer 110a, and between the upper electrode 122 and the second oxygen storage layer 110b. In one embodiment, the material of the upper electrode 122 includes a conductive material, which may be, for example, a metal material, a metal nitride, or other suitable conductive materials. For example, the upper electrode 122 may be a TiN layer. In one embodiment, the upper electrode 122 and the lower electrode 106 may have the same material or different materials. After the upper electrode 122 is formed, the resistance random access memory 100 of the first embodiment is completed. The resistance random access memory 100 can be configured between any two metal layers in the interconnect structure, such as between the first metal layer (M1) and the second metal layer (M2).

[0024] It is worth noting that Figure 1G As shown, the isolation structure 114 separates the continuous oxygen storage material layer into a first oxygen storage layer 110a and a second oxygen storage layer 110b to form a dual-channel memory cell. The first oxygen storage layer 110a and the second oxygen storage layer 110b share a continuous upper electrode 122. While maintaining the data storage layer 108 at the original design thickness, the dual-channel memory cell has a larger current gain to improve the performance of the resistance random access memory 100. In other words, the resistance random access memory 100 of the embodiment of the present invention does not need to increase the thickness of the data storage layer to obtain better high-temperature data retention capability. On the other hand, during the formation operation, the formation voltage of the data storage layer 108 with a thinner thickness is lower, which is conducive to mass production and can improve the reliability of the resistance random access memory 100.

[0025] In addition, the first oxygen storage layer 110a directly contacts the data storage layer 108 on the first side wall S1 of the lower electrode 106, so a filament is formed in the data storage layer 108 on the first side wall S1 of the lower electrode 106 to serve as a current transmission path P1. The current transmission path P1 has a lower resistance value due to the thinner data storage layer 108, thereby improving the performance of the resistance random access memory 100. Similarly, the second oxygen storage layer 110b directly contacts the data storage layer 108 on the second side wall S2 of the lower electrode 106, so a filament is formed in the data storage layer 108 on the second side wall S2 of the lower electrode 106 to serve as another current transmission path P2. The current transmission path P2 also has a lower resistance value due to the thinner data storage layer 108, thereby improving the performance of the resistance random access memory 100.

[0026] Figure 3 FIG. 4 is a cross-sectional diagram of a resistance random access memory according to a second embodiment of the present invention.

[0027] Please refer to Figure 3 The resistance random access memory 200 of the second embodiment of the present invention is similar to the resistance random access memory 100 of the first embodiment of the present invention, and the main difference is that the resistance random access memory 200 of the second embodiment has a third oxygen storage layer 210, which is buried in the isolation structure 114. In one embodiment, the method for forming the third oxygen storage layer 210 includes: Figure 1F After forming the isolation structure 114, the isolation structure 114 is patterned to form an opening 115 in the isolation structure 114; then, the third oxygen storage layer 210 is formed in the opening 115. In this case, the third oxygen storage layer 210 passes through the first barrier layer 116 to contact the data storage layer 108. The isolation structure 114 separates the first oxygen storage layer 110a, the second oxygen storage layer 110b, and the third oxygen storage layer 210. The top surface of the isolation structure 114 is coplanar with the top surfaces of the first oxygen storage layer 110a, the second oxygen storage layer 110b, and the third oxygen storage layer 210.

[0028] It is worth noting that in this embodiment, the isolation structure 114 separates the continuous oxygen storage material layer into the first oxygen storage layer 110a, the second oxygen storage layer 110b and the third oxygen storage layer 210 to form a three-channel memory cell. In this case, the three-channel memory cell can have a larger current gain to further improve the performance of the resistance random access memory 200. In addition, while maintaining the data storage layer 108 at the original design thickness, this embodiment can further separate the continuous oxygen storage material layer into a multi-channel structure to effectively reduce the chip usage area, thereby meeting the requirements of miniaturization.

[0029] Figure 4FIG. 4 is a cross-sectional diagram of a resistance random access memory according to a third embodiment of the present invention.

[0030] Please refer to Figure 4 The resistance random access memory 300 of the third embodiment of the present invention is similar to the resistance random access memory 200 of the second embodiment, and the main difference is that the first barrier layer 316 of the resistance random access memory 300 of the third embodiment further extends to cover the sidewall of the third oxygen storage layer 310. In one embodiment, the method for forming the third oxygen storage layer 310 includes: Figure 1D After forming the oxygen storage material layer 110, a patterning process is performed to form two openings 109 and 111 in the oxygen storage material layer 110; then, an isolation structure 314 is formed in the two openings 109 and 111. Specifically, as Figure 4 As shown, the isolation structure 314 includes a first barrier layer 316 and an insulating layer 318. The first barrier layer 316 conformally covers the openings 109 and 111. The insulating layer 318 is located on the first barrier layer 316 and fills the openings 109 and 111. In this embodiment, the first oxygen storage layer 110a, the second oxygen storage layer 110b, and the third oxygen storage layer 310 are formed at the same time. The isolation structure 314 separates the first oxygen storage layer 110a, the second oxygen storage layer 110b, and the third oxygen storage layer 310.

[0031] In summary, the embodiment of the present invention can separate the continuous oxygen storage material layer into a multi-channel structure and the multi-channel structure shares the upper electrode to increase the current gain, thereby improving the performance of the resistance random access memory. In addition, when performing the formation operation, the formation voltage of the data storage layer with a thinner thickness is lower, which is conducive to mass production and can improve the reliability of the resistance random access memory. In addition, the multi-channel structure of the embodiment of the present invention can effectively reduce the chip usage area, thereby meeting the needs of miniaturization.

[0032] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A resistance random access memory, comprising: a lower electrode protruding from a top surface of the dielectric layer; a data storage layer conformally covering the lower electrode and the dielectric layer; an isolation structure disposed on the lower electrode, wherein the data storage layer is sandwiched between the isolation structure and the lower electrode; A first oxygen storage layer, disposed on the data storage layer at a first side of the isolation structure; a second oxygen storage layer disposed on the data storage layer at a second side of the isolation structure, wherein the isolation structure separates the first oxygen storage layer from the second oxygen storage layer; as well as The upper electrode is disposed on the first oxygen storage layer and the second oxygen storage layer and is shared by the first oxygen storage layer and the second oxygen storage layer. 2 . The resistance random access memory according to claim 1 , wherein the isolation structure covers a top surface of the lower electrode and extends to cover an upper sidewall of the lower electrode.

3. The resistance random access memory according to claim 1, wherein the data storage layer covering the top surface of the lower electrode has a first thickness, and the data storage layer covering the top surface of the dielectric layer has a second thickness, wherein the first thickness is smaller than the second thickness. 4 . The resistance random access memory according to claim 1 , wherein the isolation structure comprises a first barrier layer and an insulating layer, the first barrier layer is located between the insulating layer and the first oxygen storage layer and between the insulating layer and the second oxygen storage layer. 5 . The resistance random access memory according to claim 1 , further comprising a second barrier layer between the upper electrode and the isolation structure, between the upper electrode and the first oxygen storage layer, and between the upper electrode and the second oxygen storage layer. 6 . The resistance random access memory according to claim 1 , wherein a top surface of the isolation structure is coplanar with a top surface of the first oxygen storage layer and a top surface of the second oxygen storage layer. 7 . The resistance random access memory according to claim 1 , further comprising a third oxygen storage layer buried in the isolation structure to contact the data storage layer. 8 . The resistance random access memory according to claim 7 , wherein the isolation structure separates the first oxygen storage layer, the second oxygen storage layer, and the third oxygen storage layer.

9. A method for manufacturing a resistance random access memory, comprising: forming a lower electrode protruding from a top surface of the dielectric layer; forming a data storage layer conformally on the lower electrode and the dielectric layer; forming an oxygen storage material layer on the data storage layer; forming an opening in the oxygen storage material layer to expose the data storage layer on the lower electrode; forming an isolation structure in the opening, wherein the isolation structure separates the oxygen storage material layer into a first oxygen storage layer and a second oxygen storage layer; as well as An upper electrode is formed on the first oxygen storage layer and the second oxygen storage layer, wherein the first oxygen storage layer and the second oxygen storage layer share the upper electrode.

10. The method for manufacturing a resistance random access memory according to claim 9, wherein forming the isolation structure in the opening comprises: conformally forming a first barrier layer in the opening; forming an insulating material on the first barrier layer to fill the opening; as well as A planarization process is performed to expose a top surface of the first oxygen storage layer and a top surface of the second oxygen storage layer. 11 . The method for manufacturing a resistance random access memory according to claim 9 , before forming the upper electrode, further comprising forming a second barrier layer on the isolation structure, the first oxygen storage layer and the second oxygen storage layer. 12 . The method for manufacturing a resistance random access memory according to claim 9 , further comprising forming a third oxygen storage layer in the isolation structure, wherein the isolation structure separates the first oxygen storage layer, the second oxygen storage layer, and the third oxygen storage layer.

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