A high performance phase change memory and its preparation method

Abstract

The present invention relates to a high-performance phase change memory and a preparation method thereof. The phase change memory comprises: a substrate layer, an electrode layer, a dielectric isolation layer, a bottom electrode layer, a phase change material layer, and a top electrode layer, wherein a dielectric buffer material layer is provided between the dielectric isolation layer and the bottom electrode layer. The phase change memory can effectively avoid the performance degradation of the bottom electrode due to oxidation, thereby ensuring the service life of the electrode; and increases the heat dissipation area, improves the heat dissipation efficiency during the operation of the device, thereby reducing the thermal stress in the phase change storage medium, reducing the resistance drift coefficient, and improving the reliability of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic integrated circuits, and in particular relates to a high-performance phase change memory and a preparation method thereof. Background Art

[0002] Among the next generation of emerging non-volatile storage technologies, phase change memory (PCM), resistive random access memory (RRAM), magnetic random access memory (MRAM) and ferroelectric random access memory (FeRAM) are the new storage technologies with the most promising market prospects. Among them, the main advantages of phase change memory are low latency, balanced read and write time, long life, low power consumption, good radiation resistance, good miniaturization, compatibility with traditional CMOS processes, multi-level storage, etc. It is considered to be the most promising next generation non-volatile storage technology. Especially in the application of storage-class memory (SCM), phase change memory is expected to fill the gap between memory and hard disk storage in access speed and capacity, and ultimately achieve the purpose of replacing them and forming a unified new storage architecture.

[0003] Phase change memory (PCM) uses the resistance difference of more than two orders of magnitude between the crystalline and amorphous structures of sulfur-based compound materials to store information. Phase change materials exhibit high resistance in amorphous structures and low resistance in crystalline structures, and their structural phase change is mainly completed by Joule heat generated by current pulses. The storage performance of phase change memory is mainly determined by the phase change material as the storage medium and the structure of the storage unit. In the research and development of high-performance phase change memory with low resistance drift and long cycle erase and write life, in addition to the core storage medium material, the electrode material and dielectric material in the phase change memory unit also play a vital role. Especially in the application of storage and computing integrated memory chips, higher requirements are placed on the stability and cycle life of multi-level resistance states. Therefore, it is becoming increasingly important to develop a high-performance phase change memory to realize a neuromorphic chip with stable and long-life multi-level storage performance. Most of the existing phase change memories have only two resistance states with different resistance values, and their device structure is in the form of bottom electrode-phase change material-top electrode without any buffer layer material. [1] .

[0004] References are as follows:

[0005] [1]Xilin Zhou et al. Understanding Phase-Change Behaviors ofCarbon-Doped Ge2Sb2Te5 for Phase-Change MemoryApplication,ACS AppliedMaterials&Interfaces 2014,6,14207-14214. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a high-performance phase change memory and a preparation method thereof, so as to overcome the defects of the phase change memory in the prior art, such as high resistance drift coefficient and limited cycle erase and write life due to electrode aging.

[0007] The present invention provides a phase change memory, which comprises: a substrate layer, an electrode layer, a dielectric isolation layer, a bottom electrode layer, a phase change material layer, and a top electrode layer. A dielectric buffer material layer is provided between the dielectric isolation layer and the bottom electrode layer. The dielectric buffer material layer is made of nitride. The resistivity of the nitride should be higher than 1000Ωcm, the thermal conductivity should be higher than 200W / mK, and the thermal expansion coefficient should be less than 3×10 -6 / K.

[0008] The phase change memory structure is not limited. Preferably, the phase change memory structure is a "mushroom type (T type)" structure or a three-dimensional "restricted type" structure.

[0009] Preferably, the base layer material is a semiconductor substrate material, and the semiconductor substrate material includes silicon material (Si) or silicon-on-insulator material (SOI).

[0010] Preferably, the dielectric isolation layer material is a nitride dielectric material or an oxide dielectric material.

[0011] More preferably, the nitride dielectric material is Si3N4; and the oxide dielectric material is SiO2.

[0012] Preferably, the electrode material of the electrode layer and the bottom electrode layer includes: one of W, WN, Ta, TaW, TiW, TiN, TiSiN, and C.

[0013] Preferably, the phase change material layer has a thickness of 2-100 nanometers.

[0014] Preferably, the phase change material of the phase change material layer is a sulfur-based compound phase change material, and the sulfur-based compound phase change material includes one of Sb2Te3, Sb2Te, GeTe and Ge2Sb2Te5, or a compound obtained by modifying one or two elements of Sb2Te3, Sb2Te, GeTe and Ge2Sb2Te5 by doping with Ti, Ta, Sc, Er, In, Rh, Ga and C.

[0015] More preferably, the sulfur-based compound phase change material includes one of Ti-Sb-Te, Ta-Sb-Te, In-Sb-Te, Sc-Sb-Te, Ti-Ge-Te, In-Ge-Te, In-Ge-Sb-Te, In-Sc-Sb-Te, Rh-Ge-Sb-Te, Ga-Ge-Sb-Te, C-Ge-Sb-Te, Rh-Sb-Te, and Ta-Ge-Sb-Te.

[0016] Preferably, the dielectric buffer material layer has a thickness of 2-110 nanometers; and the nitride includes one of AlN and BN.

[0017] The present invention also provides a method for preparing a phase change memory, comprising: before depositing the phase change material, implanting a dielectric buffer material layer around the bottom electrode layer.

[0018] Preferably, the method comprises the following steps:

[0019] (1) Cleaning the substrate;

[0020] (2) forming an electrode layer and a dielectric isolation layer in sequence on the cleaned substrate;

[0021] (3) making a through hole in the dielectric isolation layer, and filling the through hole with a dielectric buffer material layer to form a dielectric buffer material layer;

[0022] (4) making a through hole in the dielectric buffer material layer, and filling the through hole with a bottom electrode material to form a bottom electrode layer;

[0023] (5) forming a phase change material layer on the upper surface of the dielectric isolation material layer in contact with the bottom electrode layer in the through hole;

[0024] (6) forming a top electrode layer on the upper surface of the phase change material layer.

[0025] Preferably, the electrode layer, dielectric isolation layer, bottom electrode layer, phase change material layer and top electrode layer are all formed by adopting one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and pulsed laser deposition.

[0026] The present invention also provides an application of a phase change memory, such as a data storage module for a handheld mobile device.

[0027] The present invention deposits a dielectric buffer material with high resistivity, high thermal conductivity and low thermal expansion coefficient on the periphery of the bottom electrode to avoid oxidation aging of the bottom electrode, improve the heat dissipation efficiency during device operation, thereby inhibiting performance aging of the electrode material and reducing thermal stress in the phase change storage medium, which helps to improve the thermal field distribution inside the structure during device operation, thereby reducing the resistance drift coefficient of the storage unit and increasing the cyclic erase and write operation life of the memory.

[0028] Beneficial Effects

[0029] The present invention adopts nitride with high resistivity, high thermal conductivity and low thermal expansion coefficient as the bottom electrode dielectric buffer material, which can effectively avoid the performance degradation of the bottom electrode caused by oxidation and ensure the service life of the electrode; and increases the heat dissipation area, improves the heat dissipation efficiency during the operation of the device, thereby improving the temperature field distribution during the operation of the device, which helps to reduce the thermal stress in the phase change storage medium, reduce the resistance drift coefficient, improve the device reliability, and overcome the problems of limited cyclic erase and write life, low resistance stability and high resistance drift coefficient of the phase change memory in the prior art.

[0030] The present invention does not increase the difficulty of the preparation process and is fully compatible with the traditional integrated circuit SS industrial CMOS process. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG. 1( a ) to FIG. 1( i ) are schematic flow diagrams of a method for preparing a high-performance phase-change memory cell with a “mushroom-type” structure according to the present invention;

[0032] FIG. 1( a ) is a schematic diagram of the steps of forming an electrode layer on a substrate;

[0033] FIG1( b ) is a schematic diagram of the steps of forming a dielectric isolation layer on an electrode layer;

[0034] FIG1(c) is a schematic diagram of the steps of forming a through hole on a dielectric isolation layer;

[0035] FIG1(d) is a schematic diagram of the step of filling the bottom electrode dielectric buffer material in the through hole to form a dielectric buffer material layer;

[0036] FIG. 1( e ) is a schematic diagram of the steps of forming a through hole on the dielectric buffer material layer;

[0037] FIG1(f) is a schematic diagram of the step of filling the bottom electrode material in the through hole to form a bottom electrode layer;

[0038] FIG1(g) is a schematic diagram of the steps of forming a sulfur compound phase change material layer on the surface of the dielectric isolation layer and the bottom electrode layer;

[0039] FIG1(h) is a schematic diagram of the steps of forming a top electrode material on a chalcogenide compound phase change material layer;

[0040] FIG. 1( i ) is a schematic diagram of the steps of forming a top electrode structure.

[0041] FIG. 2( a ) to FIG. 2( i ) are schematic flow diagrams of a method for preparing a high-performance phase-change memory cell having a “restricted” structure according to the present invention;

[0042] FIG. 2( a ) is a schematic diagram of the steps of forming an electrode layer on a substrate;

[0043] FIG2( b ) is a schematic diagram of the steps of forming a dielectric isolation layer on the electrode layer;

[0044] FIG2(c) is a schematic diagram of the steps of forming a through hole on the dielectric isolation layer;

[0045] FIG2(d) is a schematic diagram of the step of filling the bottom electrode dielectric buffer material in the through hole to form a dielectric buffer material layer;

[0046] FIG2(e) is a schematic diagram of the steps of forming a through hole on the dielectric buffer material layer;

[0047] FIG2( f ) is a schematic diagram of the step of filling the bottom electrode material in the through hole to form a bottom electrode layer;

[0048] FIG2(g) is a schematic diagram of the steps of forming a dielectric isolation layer on the surfaces of a dielectric material and an electrode material;

[0049] FIG2(h) is a schematic diagram of the steps of forming a through hole on the dielectric isolation layer;

[0050] FIG2(i) is a schematic diagram of the steps of forming a sulfur compound phase change material layer on the surface of the dielectric buffer material layer and the bottom electrode layer;

[0051] FIG2(j) is a schematic diagram of the step of forming a top electrode material on the sulfide compound phase change material layer;

[0052] FIG. 2( k ) is a schematic diagram of the steps of forming a top electrode structure.

[0053] Figure 3 The temperature field distribution simulation diagram of the traditional phase change memory unit (a) and the temperature field distribution simulation diagram of the phase change memory unit after adding high resistivity and high thermal conductivity nitride to the periphery of the bottom electrode according to Example 1 of the present invention (b). DETAILED DESCRIPTION

[0054] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0055] Example 1

[0056] This embodiment provides a method for preparing a "mushroom-type" structure phase change memory, comprising:

[0057] (1) The substrate silicon wafer was cleaned in acetone and alcohol solution under ultrasonic wave for 10 minutes respectively; then baked in 120℃ environment for 20 minutes. Then, a 50-nanometer thick TiN electrode material was deposited on the substrate by magnetron sputtering; the background vacuum during sputtering was better than 5×10 -5 Pa, the sputtering gas pressure is 0.4 Pa, and the sputtering power is 80 W; (as shown in Figure 1(a))

[0058] (2) In the same sputtering environment, magnetron sputtering was used to deposit 100 nm thick Si3N4 dielectric isolation material on the TiN electrode; the background vacuum during sputtering was better than 5×10 -5 Pa, the sputtering gas pressure is 0.4 Pa, and the sputtering power is 150 W; (as shown in Figure 1(b))

[0059] (3) Using ultraviolet exposure to form a through-hole pattern on the Si3N4 dielectric isolation material, using reactive ion etching to etch through-holes in the Si3N4 dielectric isolation material, the etching depth being such as to reach the top of the TiN; (as shown in FIG. 1(c))

[0060] (4) A 110-nanometer-thick AlN bottom electrode dielectric isolation material is then deposited in the through hole using a magnetron sputtering method, and excess AlN material is removed using a chemical mechanical planarization method, with the polishing depth reaching the top of the Si3N4; (as shown in FIG1(d))

[0061] (5) Using ultraviolet exposure to form a through-hole pattern on the AlN dielectric isolation material, and using reactive ion etching to etch through-holes in the AlN dielectric isolation material, the etching depth is based on reaching the top of the TiN; (as shown in FIG. 1(e))

[0062] (6) Deposit a 120-nanometer-thick W bottom electrode material in the through hole by magnetron sputtering, and remove the excess W material by chemical mechanical planarization. The polishing depth is based on reaching the top of Si3N4; (as shown in FIG1(f))

[0063] (7) Then, a 100-nanometer-thick Ge2Sb2Te5 sulfur compound phase change material is deposited on the surface of the dielectric isolation layer and the bottom electrode layer by magnetron sputtering; the background vacuum during sputtering is better than 5×10 -5 Pa, the sputtering gas pressure is 0.4 Pa, and the sputtering power is 50 W; (as shown in Figure 1(g))

[0064] (8) A 300-nanometer-thick Al top electrode material is then deposited on the surface of the phase-change material layer by magnetron sputtering to ensure that the Al and phase-change material layers are in perfect contact; the background vacuum during sputtering is better than 5×10 -5 Pa, the sputtering gas pressure is 0.4 Pa, and the sputtering power is 100 W; (as shown in Figure 1(h))

[0065] (9) forming a top electrode pattern on the Al top electrode layer by ultraviolet exposure, and after post-baking and heating, wet etching the Al top electrode material by phosphoric acid solution at 60° C., and extracting the electrode for electrical storage performance test characterization, thereby obtaining a phase change memory device unit; (as shown in FIG. 1(i))

[0066] (10) Connecting the prepared phase change memory unit to an electrical test system through a probe or a wire, loading an electrical pulse signal, performing read, write, and erase operations on the phase change memory unit, and studying the storage performance of the phase change memory unit under this structure.

[0067] Figure 3 It shows that the high resistivity of nitride materials will not significantly affect the heating efficiency of the bottom electrode. The high thermal conductivity of nitride materials effectively improves the heat dissipation efficiency of the device after power-on, and moves the molten area of ​​the phase change material to the phase change material layer, away from the interface in contact with the electrode, which will effectively avoid the formation of vacancies at the interface during the cyclic erase and write operation, causing device failure, and improve the device life and resistance stability. At the same time, nitride can also protect the electrode from oxidation and improve the reliability of the electrode itself.

[0068] Example 2

[0069] This embodiment provides a method for preparing a "restricted" structure phase change memory, comprising:

[0070] (1) The substrate silicon wafer was cleaned in acetone and alcohol solution under ultrasonic wave for 10 minutes respectively; then baked in 120℃ environment for 20 minutes. Then, a 50-nanometer thick TiN electrode material was deposited on the substrate by magnetron sputtering; the background vacuum during sputtering was better than 5×10 -5 Pa, the sputtering gas pressure is 0.4 Pa, and the sputtering power is 80 W; (as shown in Figure 2(a))

[0071] (2) In the same sputtering environment, magnetron sputtering was used to deposit 100 nm thick Si3N4 dielectric isolation material on the TiN electrode; the background vacuum during sputtering was better than 5×10 -5 Pa, the sputtering gas pressure is 0.4 Pa, and the sputtering power is 150 W; (as shown in Figure 2(b))

[0072] (3) Using ultraviolet exposure to form a through-hole pattern on the Si3N4 dielectric isolation material, using reactive ion etching to etch through-holes in the Si3N4 dielectric isolation material, the etching depth being such as to reach the top of the TiN; (as shown in FIG. 2(c))

[0073] (4) Depositing a 110 nm thick AlN bottom electrode dielectric isolation material in the through hole by magnetron sputtering, and removing the excess AlN material by chemical mechanical planarization, with the polishing depth reaching the top of Si3N4; (as shown in FIG2(d))

[0074] (5) Using ultraviolet exposure to form a through-hole pattern on the AlN dielectric isolation material, and using reactive ion etching to etch through-holes in the AlN dielectric isolation material, the etching depth is set to reach the top of the TiN; (as shown in FIG. 2(e))

[0075] (6) Deposit a 120-nanometer-thick W bottom electrode material in the through hole by magnetron sputtering, and remove the excess W material by chemical mechanical planarization. The polishing depth is based on reaching the top of Si3N4; (as shown in FIG2(f))

[0076] (7) Then deposit 100 nanometers thick Si3N4 dielectric isolation material on the surface of the dielectric isolation layer and the bottom electrode layer; the background vacuum during sputtering is better than 5×10 -5 Pa, the sputtering gas pressure is 0.4 Pa, and the sputtering power is 150 W; (as shown in Figure 2(g))

[0077] (8) Using ultraviolet exposure to form a through-hole pattern on the Si3N4 dielectric isolation material, using reactive ion etching to etch a through-hole in the Si3N4 dielectric isolation material, the etching depth being such as to reach the top of the bottom electrode; (as shown in FIG. 2(h))

[0078] (9) Then, a 110 nm thick Ge2Sb2Te5 sulfide phase change material is deposited in the through hole by magnetron sputtering; the background vacuum during sputtering is better than 5×10 -5 Pa, the sputtering pressure is 0.4 Pa, and the sputtering power is 50 W; and the excess Ge2Sb2Te5 material is removed by chemical mechanical planarization, and the polishing depth is based on reaching the top of Si3N4; (as shown in Figure 2(i))

[0079] (10) A 300-nanometer-thick Al top electrode material is then deposited on the surface of the phase change material and the dielectric isolation layer by magnetron sputtering to ensure that the Al and phase change material layers are in perfect contact; the background vacuum during sputtering is better than 5×10 -5 Pa, the sputtering gas pressure is 0.4 Pa, and the sputtering power is 100 W; (as shown in Figure 2(j))

[0080] (11) forming a top electrode pattern on the Al top electrode layer by ultraviolet exposure, and after post-baking and heating, wet etching the Al top electrode material by phosphoric acid solution at 60° C., and extracting the electrode for electrical storage performance test characterization, thereby obtaining a phase change memory device unit; (as shown in FIG. 2(k))

[0081] (12) Connecting the prepared phase change memory unit to an electrical test system through a probe or a wire, loading an electrical pulse signal, performing read, write, and erase operations on the phase change memory unit, and studying the storage performance of the phase change memory unit under this structure.

[0082] It can be seen from the above embodiments that the core feature of the present invention is that compared with the traditional phase change memory cell structure, a high resistivity, high thermal conductivity nitride dielectric buffer material is implanted around the bottom electrode material. This improvement does not increase the difficulty of the device unit preparation process and is fully compatible with the CMOS process of traditional integrated circuit manufacturing. The implanted high resistivity, high thermal conductivity nitride dielectric buffer material can effectively protect the electrode material from oxidation, improve the heat dissipation efficiency during device operation, reduce thermal stress in the phase change material, and improve resistance stability; it can fully meet the storage performance requirements of the storage and computing integrated neuromorphic device, and has a high industrial development value.

[0083] The above embodiments are only illustrative of the principles and functions of the present invention, and are not intended to limit the applicable scenarios of the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A phase change memory, comprising: The invention comprises a substrate layer, an electrode layer, a dielectric isolation layer, a bottom electrode layer, a phase change material layer, and a top electrode layer, wherein a dielectric buffer material layer is provided between the dielectric isolation layer and the bottom electrode layer, and the dielectric buffer material layer is made of nitride, and the resistivity of the nitride should be higher than 1000 Ω·cm, the thermal conductivity should be higher than 200 W / mK, and the thermal expansion coefficient should be less than 3×10 -6 / K; The preparation method of the phase change memory comprises the following steps: (1) Cleaning the substrate; (2) forming an electrode layer and a dielectric isolation layer in sequence on the cleaned substrate; (3) making a through hole in the dielectric isolation layer, and filling the through hole with a dielectric buffer material layer to form a dielectric buffer material layer; (4) making a through hole in the dielectric buffer material layer, and filling the through hole with a bottom electrode material to form a bottom electrode layer; (5) forming a phase change material layer on the upper surface of the dielectric isolation layer so as to contact the bottom electrode layer in the through hole; (6) Forming a top electrode layer on the upper surface of the phase change material layer.

2. The phase change memory according to claim 1, characterized in that: The phase change memory structure is a "mushroom type" structure or a three-dimensional "confinement type" structure.

3. The phase change memory according to claim 1, characterized in that: The dielectric isolation layer material is a nitride dielectric material or an oxide dielectric material.

4. The phase change memory according to claim 3, characterized in that: The nitride dielectric material is Si3N4; the oxide dielectric material is SiO2.

5. The phase change memory according to claim 1, characterized in that: The electrode material of the electrode layer and the bottom electrode layer includes one of W, WN, Ta, TaW, TiW, TiN, TiSiN, and C.

6. The phase change memory according to claim 1, characterized in that: The thickness of the phase change material layer is 2-100 nanometers; the phase change material of the phase change material layer is a sulfur compound phase change material, and the sulfur compound phase change material includes: one of Ge-Sb-Te, Ti-Sb-Te, Ta-Sb-Te, In-Sb-Te, Sc-Sb-Te, Ti-Ge-Te, In-Ge-Te, In-Ge-Sb-Te, In-Sc-Sb-Te, Rh-Ge-Sb-Te, Ga-Ge-Sb-Te, C-Ge-Sb-Te, Rh-Sb-Te, and Ta-Ge-Sb-Te.

7. The phase change memory according to claim 1, characterized in that: The dielectric buffer material layer has a thickness of 2-110 nanometers; the nitride includes one of AlN and BN.

8. A method for preparing a phase change memory as claimed in claim 1, characterized in that: Before depositing the phase change material, a dielectric buffer material layer is implanted around the bottom electrode layer.

9. The preparation method according to claim 8, characterized in that: The electrode layer, dielectric isolation layer, bottom electrode layer, phase change material layer and top electrode layer are all formed by adopting one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and pulse laser deposition.

10. Use of the phase change memory as claimed in claim 1 in a microelectronic integrated circuit.

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