MIM capacitors and their formation methods

Abstract

Various embodiments of this application relate to metal-insulator-metal (MIM) capacitors. The MIM capacitor includes a bottom electrode disposed above a semiconductor substrate. A top electrode is disposed above and on top of the bottom electrode. A capacitor insulator structure is disposed between the bottom and top electrodes. The capacitor insulator structure includes at least three dielectric structures stacked perpendicularly to each other. With respect to the dielectric material of the dielectric structures, the lower half of the capacitor insulator structure is a mirror image of its upper half. Embodiments of this application also relate to methods for forming metal-insulator-metal (MIM) capacitors.

Description

Technical Field

[0001] Embodiments of this application relate to MIM capacitors and methods of forming the same. Background Technology

[0002] Integrated circuits (ICs) are formed on a semiconductor die containing millions or billions of transistors. These transistors are configured to function as switches and / or generate power gain to achieve logic functionality. ICs also include passive devices for controlling gain, time constants, and other IC characteristics. One type of passive device is the metal-insulator-metal (MIM) capacitor. MIM capacitors are particularly suitable for decoupling in high-performance computing (HPC). Summary of the Invention

[0003] Some embodiments of this application provide a metal-insulator-metal (MIM) capacitor, comprising: a bottom electrode disposed above a semiconductor substrate; a top electrode disposed above the bottom electrode; and a capacitor insulator structure disposed between the bottom electrode and the top electrode, wherein: the capacitor insulator structure includes a first plurality of dielectric structures, the first plurality of dielectric structures including a first dielectric material; the capacitor insulator structure includes a second plurality of dielectric structures, the second plurality of dielectric structures including a second dielectric material different from the first dielectric material; the capacitor insulator structure periodically alternates between the first dielectric material and the second dielectric material from the bottom electrode to the top electrode; the first plurality of dielectric structures includes a first dielectric structure, a second dielectric structure, and a third dielectric structure; a second dielectric structure is disposed between the first dielectric structure and the third dielectric structure; and the second dielectric structure has a tetragonal crystal with a lower weight percentage (wt%) than the first dielectric structure and the third dielectric structure.

[0004] Other embodiments of this application provide a metal-insulator-metal (MIM) capacitor, comprising: a lower electrode disposed above a semiconductor substrate; an upper electrode disposed above the lower electrode; and a capacitor insulator structure disposed between the lower electrode and the upper electrode, wherein: the capacitor insulator structure includes a dielectric structure stack, the dielectric structure stack comprising at least five individual dielectric structures stacked perpendicularly to each other; each individual dielectric structure includes: a first individual dielectric structure comprising a first dielectric material; and a second individual dielectric structure comprising the first dielectric material; the first individual dielectric structure is the uppermost individual dielectric structure in the dielectric structure stack; The second single dielectric structure is the lowest single dielectric structure in the dielectric structure stack; the single dielectric structure disposed between the first single dielectric structure and the second single dielectric structure includes a first dielectric material, a second dielectric material, or a third dielectric material; the second dielectric material is different from the first dielectric material; the third dielectric material is different from both the first and second dielectric materials; and the single dielectric structure disposed between the first single dielectric structure and the second single dielectric structure periodically alternates between the first dielectric material, the second dielectric material, and the third dielectric material from the second single dielectric structure to the first single dielectric structure.

[0005] Further embodiments of this application provide a method for forming a metal-insulator-metal (MIM) capacitor, the method comprising: forming a bottom electrode layer over a semiconductor substrate; forming a first dielectric layer over the bottom electrode layer comprising a first dielectric material, wherein the first dielectric layer is formed with a first weight percentage (wt%) of tetragonal crystal; forming a second dielectric layer over the first dielectric layer comprising a second dielectric material different from the first dielectric material, wherein the second dielectric layer is formed as an amorphous solid; forming a third dielectric layer over the second dielectric layer comprising the first dielectric material, wherein the third dielectric layer is formed with a second weight percentage of tetragonal crystal; and forming a third dielectric layer over the second dielectric layer comprising the first dielectric material. A fourth dielectric layer comprising the second dielectric material is formed above the first dielectric layer, wherein the fourth dielectric layer is formed as an amorphous solid; a fifth dielectric layer comprising the first dielectric material is formed above the fourth dielectric layer, wherein the fifth dielectric layer is formed with a third weight percentage of tetragonal crystal, wherein the second weight percentage of tetragonal crystal is less than the first weight percentage of tetragonal crystal and the third weight percentage of tetragonal crystal; a top electrode layer is formed above the fifth dielectric layer; and the top electrode layer, the fifth dielectric layer, the fourth dielectric layer, the third dielectric layer, the second dielectric layer, the first dielectric layer and the bottom electrode layer are patterned to form the metal-insulator-metal capacitor. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 Cross-sectional views of some embodiments of metal-insulator-metal (MIM) capacitors with symmetrical capacitor insulator structures are shown.

[0008] Figure 2 Illustrations based on some embodiments Figure 1 The energy band diagram of a MIM capacitor.

[0009] Figures 3A to 3B Illustrations based on some embodiments Figure 1 Various band diagrams of MIM capacitors.

[0010] Figure 4 Show Figure 1 Cross-sectional views of some embodiments of MIM capacitors.

[0011] Figure 5 Show Figure 1 Cross-sectional views of some embodiments of MIM capacitors.

[0012] Figure 6 Show Figure 1 Cross-sectional views of some embodiments of MIM capacitors.

[0013] Figures 7A to 7B Illustrations based on some embodiments Figure 6 Various band diagrams of MIM capacitors.

[0014] Figure 8 Show Figure 1 Cross-sectional views of some embodiments of MIM capacitors.

[0015] Figure 9 Show Figure 1 Cross-sectional views of some embodiments of MIM capacitors.

[0016] Figure 10 Show Figure 1 Cross-sectional views of some embodiments of MIM capacitors.

[0017] Figure 11 The diagram shows that it includes embedded elements. Figure 1 Cross-sectional views of some embodiments of the interconnect structure of the MIM capacitor and some embodiments of the integrated chip (IC).

[0018] Figure 12 Show Figure 11 Cross-sectional views of some other embodiments of the IC.

[0019] Figure 13 Show Figure 11 Cross-sectional views of some other embodiments of the IC.

[0020] Figure 14 Show Figure 11 Cross-sectional views of some other embodiments of the IC.

[0021] Figure 15 Show Figure 11 Cross-sectional views of some other embodiments of the IC.

[0022] Figure 16 Show Figure 11 Cross-sectional views of some more detailed embodiments of the IC.

[0023] Figure 17 Show Figure 11 Cross-sectional views of some more detailed embodiments of the IC.

[0024] Figures 18 to 26 A series of cross-sectional views are shown of some embodiments of a method for forming an IC including a MIM capacitor having a symmetrical capacitor insulator structure.

[0025] Figure 27 Flowcharts illustrating some embodiments of a method for forming an IC including a MIM capacitor having a symmetrical capacitor insulator structure are shown. Detailed Implementation

[0026] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0028] A metal-insulator-metal (MIM) capacitor includes a bottom electrode, a top electrode above the bottom electrode, and a capacitor insulator structure between the bottom and top electrodes. A method for forming an MIM capacitor may include, for example: 1) depositing a bottom electrode layer; 2) depositing one or more multilayer high-k dielectric films above the bottom electrode layer; 3) depositing a top electrode layer on one or more instances of the multilayer high-k dielectric film; and 4) patterning the top and bottom electrode layers and the instances of the multilayer high-k dielectric film into a MIM capacitor. The top and bottom electrode layers are patterned into top and bottom electrodes, and the instances of the multilayer high-k dielectric film are patterned into a capacitor insulator structure. The top electrode and the bottom electrode share a common metal and therefore have the same work function. The multilayer high-k dielectric film includes a bottom high-k dielectric structure and a top high-k dielectric structure located above the bottom high-k dielectric structure.

[0029] The bottom high-k dielectric structure is configured to improve the leakage performance of the MIM capacitor (e.g., reduce leakage current). Since the bottom high-k dielectric structure is an amorphous solid, it can improve leakage current (e.g., the amorphous solid prevents leakage current from passing through the grain boundaries of the top high-k dielectric structure). Thus, the bottom high-k dielectric structure comprises a different high-k dielectric material than the top high-k dielectric structure (e.g., to ensure the bottom high-k dielectric structure is an amorphous solid). Because the bottom and top high-k dielectric structures comprise different high-k dielectric materials, they have different electron affinities. Typically, the difference between the electron affinities of the bottom and top high-k dielectric structures is large (e.g., greater than or equal to about 1.4 volts (V)).

[0030] The challenge of MIM capacitors lies in the asymmetry of their insulator structure. The bottom high-k dielectric structure is located at the bottom electrode, and the top high-k dielectric structure is located at the top electrode, making the lower half of the capacitor's insulator structure not a mirror image of the dielectric material structure of the upper half. Because of this asymmetry, the breakdown voltage of a MIM capacitor differs when forward and reverse biased. In other words, when forward biased, the MIM capacitor has a forward bias breakdown voltage, while when reverse biased, it has a reverse bias breakdown voltage that differs from the forward bias breakdown voltage. Furthermore, due to the asymmetry of the insulator structure and the significant difference in electron affinity between the bottom and top high-k dielectric structures, the difference between the forward and reverse bias breakdown voltages of the MIM capacitor is substantial.

[0031] For example, when forward biased, a MIM capacitor may break down if the electric field is strong enough for electrons to overcome the energy barrier from the Fermi level of the bottom electrode to the conductive band edge of the bottom high-k dielectric structure. Similarly, when reverse biased, a MIM capacitor may break down if the electric field is strong enough for electrons to overcome the energy barrier from the Fermi level of the top electrode to the conductive band edge of the top high-k dielectric structure. Since the top and bottom electrodes have the same work function, and the bottom and top high-k dielectric structures have different electron affinities, the energy barrier from the Fermi level of the bottom electrode to the conductive band edge of the bottom high-k dielectric is different from the energy barrier from the Fermi level of the top electrode to the conductive band edge of the top high-k dielectric structure. Thus, when the MIM capacitor is forward biased, the bottom high-k dielectric structure can at least partially define the breakdown voltage, while when the MIM capacitor is reverse biased, the top high-k dielectric structure can at least partially define the breakdown voltage. Therefore, the forward bias breakdown voltage of a MIM capacitor differs from its reverse bias breakdown voltage. Furthermore, due to the large difference in electron affinity between the bottom high-k dielectric structure and the top high-k dielectric structure, the difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of the MIM capacitor is also large.

[0032] Because the forward bias breakdown voltage of a MIM capacitor differs from its reverse bias breakdown voltage, its effectiveness may be limited in certain applications. More specifically, the significant difference between the forward and reverse bias breakdown voltages of a MIM capacitor can limit its effectiveness in bipolar applications. For example, when used as a decoupling capacitor in high-performance computing (HPC), the MIM capacitor may be limited by the smaller of the two breakdown voltages (e.g., if the forward bias breakdown voltage is less than the reverse bias breakdown voltage, the MIM capacitor may be limited by its smaller forward bias breakdown voltage).

[0033] Various embodiments of this application relate to a MIM capacitor comprising a symmetrical capacitor insulator structure. The capacitor insulator structure is disposed between a top electrode and a bottom electrode. The capacitor insulator structure includes at least three dielectric structures stacked perpendicularly to each other. With respect to the dielectric material of the dielectric structures, the lower half of the capacitor insulator structure is a mirror image of the upper half of the capacitor insulator structure. Because the lower half of the capacitor insulator structure is a mirror image of the upper half of the capacitor insulator structure with respect to the dielectric material of the dielectric structures, the capacitor insulator structure is symmetrical. Because the capacitor insulator structure is symmetrical, the difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of the MIM capacitor is relatively small (e.g., smaller than the larger difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of a MIM capacitor with an asymmetrical capacitor insulator structure). Therefore, the symmetrical capacitor insulator structure can improve (e.g., increase) the utility of the MIM capacitor. More specifically, when used in bipolar applications (e.g., as decoupling capacitors for HPC), symmetrical capacitor insulator structures can improve (e.g., increase) the utility of MIM capacitors.

[0034] Figure 1 Cross-sectional view 100 shows some embodiments of a metal-insulator-metal (MIM) capacitor 102 having a symmetrical capacitor insulator structure.

[0035] like Figure 1As shown in cross-sectional view 100, the MIM capacitor 102 includes a capacitor insulator structure 104 disposed between a bottom electrode 106 and a top electrode 108. The top electrode 108 is located above the bottom electrode 106. The capacitor insulator structure 104 is located above the bottom electrode 106, and the top electrode 108 is located above the capacitor insulator structure 104. The top electrode 108 defines or otherwise electrically couples to a first terminal T1 of the MIM capacitor 102, and the bottom electrode 106 defines or otherwise electrically couples to a second terminal T2 of the MIM capacitor 102.

[0036] The bottom electrode 106 and the top electrode 108 are conductive and may be, for example, or include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), certain other conductive materials, or combinations thereof. In some embodiments, the bottom electrode 106 and the top electrode 108 are or include the same material. For example, in some embodiments, both the top electrode 108 and the bottom electrode 106 are or include titanium nitride (TiN).

[0037] The capacitor insulator structure 104 includes a first plurality of dielectric structures 110. For example, the capacitor insulator structure 104 includes a first dielectric structure 110a and a second dielectric structure 110b. The capacitor insulator structure 104 also includes a third dielectric structure 112. The third dielectric structure 112 is located between the first dielectric structure 110a and the second dielectric structure 110b. The third dielectric structure 112 is configured to improve the leakage performance of the MIM capacitor 102 (e.g., reduce leakage current). The first dielectric structure 110a is located on the bottom electrode 106, the third dielectric structure 112 is located on the first dielectric structure 110a, and the second dielectric structure 110b is located on the third dielectric structure 112.

[0038] The first dielectric structure 110a is closer to the bottom electrode 106 than both the second dielectric structure 110b and the third dielectric structure 112. The second dielectric structure 110b is closer to the top electrode 108 than both the first dielectric structure 110a and the third dielectric structure 112. In some embodiments, the third dielectric structure 112 contacts (e.g., directly contacts) the first dielectric structure 110a and the second dielectric structure 110b. In other embodiments, the first dielectric structure 110a contacts (e.g., directly contacts) the bottom electrode 106. In yet another embodiment, the second dielectric structure 110b contacts (e.g., directly contacts) the top electrode 108.

[0039] The first plurality of dielectric structures 110 may be, for example, or include zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), silicon oxide (SiO2), some other dielectric material, or any combination thereof. In some embodiments, the first plurality of dielectric structures 110 are or include metal oxides (e.g., ZrO2, Al2O3, HfO2, Ta2O5, etc.) and / or include high-k dielectrics. High-k dielectrics may be, for example, dielectric materials with a dielectric constant greater than about 3.9 or some other suitable value.

[0040] The third plurality of dielectric structures 112 may be, for example, or include zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), silicon oxide (SiO2), another dielectric material, or any combination thereof. In some embodiments, the third plurality of dielectric structures 112 are or include metal oxides (e.g., ZrO2, Al2O3, HfO2, Ta2O5, etc.) and / or include high-k dielectrics. In some embodiments, the third dielectric structure 112 is an amorphous solid (e.g., amorphous ZrO2, Al2O3, HfO2, Ta2O5, etc.).

[0041] The first plurality of dielectric structures 110 are or comprise the same dielectric material. For example, both the first dielectric structure 110a and the second dielectric structure 110b are or comprise the first dielectric material. The third dielectric structure 112 is or comprises a second dielectric material different from the first dielectric material. For example, in some embodiments, both the first dielectric structure 110a and the second dielectric structure 110b are or comprise zirconium oxide (ZrO2), and the third dielectric structure 112 is or comprises aluminum oxide (Al2O3). In such embodiments, the capacitor insulator structure 104 may be said to have a ZAZ dielectric structure stack, wherein “Z” corresponds to the first letter of the first dielectric material (e.g., ZrO2), and “A” corresponds to the first letter of the second dielectric material (e.g., Al2O3). It should be understood that the capacitor insulator structure 104 may have other configurations of dielectric structure stacks, such as AZA, HZH, ZHZ, ZTZ, TZT, etc.

[0042] The capacitor insulator structure 104 is symmetrical. The capacitor insulator structure 104 is symmetrical because, in terms of the dielectric material of the dielectric structure of the capacitor insulator structure 104, the lower half of the capacitor insulator structure 104 is a mirror image of the upper half of the capacitor insulator structure 104. For example, the axis of symmetry 114 extends laterally through the third dielectric structure 112. Therefore, the lower half of the capacitor insulator structure 104 includes the first dielectric structure 110a and a first portion (e.g., the lower half) of the third dielectric structure 112, and the upper half of the capacitor insulator structure 104 includes the second dielectric structure 110b and a second portion (e.g., the upper half) of the third dielectric structure 112. The first dielectric structure 110a and the second dielectric structure 110b are or include the first dielectric material, while the third dielectric structure 112 is or includes the second dielectric material. Therefore, in terms of the dielectric material of the dielectric structure of the capacitor insulator structure 104, the lower half of the capacitor insulator structure 104 is a mirror image of the upper half of the capacitor insulator structure 104 on the axis of symmetry 114.

[0043] Because the capacitor insulator structure 104 is symmetrical, the difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of the MIM capacitor 102 is small (e.g., less than or equal to about 0.9 volts (V)). Therefore, the capacitor insulator structure 104 can improve (e.g., increase) the utility of the MIM capacitor 102. More specifically, when used in bipolar applications (e.g., as a decoupling capacitor for HPC), the capacitor insulator structure 104 can improve (e.g., increase) the utility of the MIM capacitor 102. In some embodiments, the difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of the MIM capacitor 102 is improved by about 35% (e.g., reduced by 35%) compared to the difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of a typical MIM capacitor used in bipolar applications (e.g., a MIM capacitor with an asymmetrical capacitor insulator structure).

[0044] Figure 2 Illustrations based on some embodiments Figure 1 The band structure of the MIM capacitor 102 is shown in Figure 200. Figure 2 The band structure diagram 200 shows the situation when the MIM capacitor 102 is in equilibrium (e.g., neither forward bias nor reverse bias).

[0045] like Figure 2 As shown in the band structure diagram 200, the band structure diagram 200 is configured such that the band structures of the bottom electrode 106, the top electrode 108, the first dielectric structure 110a, the second dielectric structure 110b, and the third dielectric structure 112 are aligned along the vacuum energy level E. vac Alignment (e.g., at the same energy level).

[0046] The bottom electrode 106 has a work function 202, which depends at least in part on the material of the bottom electrode 106. The work function 202 of the bottom electrode 106 is the ratio of the Fermi level to the vacuum level E of the bottom electrode 106. vac The energy difference between them. The top electrode 108 has a work function 204, which depends at least in part on the material of the top electrode 108. The work function 204 of the top electrode 108 is the energy difference between the Fermi level and the vacuum level E of the top electrode 108. vac The energy difference between them. In some embodiments, the work function 202 of the bottom electrode 106 is substantially the same as the work function 204 of the top electrode 108. For example, in some embodiments, the top electrode 108 and the bottom electrode 106 are or comprise the same material (e.g., TiN), so the work function 202 of the bottom electrode 106 is substantially the same as the work function 204 of the top electrode 108.

[0047] The first dielectric structure 110a has an electron affinity 206, which depends at least in part on the material of the first dielectric structure 110a. The electron affinity 206 of the first dielectric structure 110a is the relationship between the conducting band edge of the first dielectric structure 110a and the vacuum level E. vac The energy difference between them. The second dielectric structure 110b has an electron affinity 208, which depends at least in part on the material of the second dielectric structure 110b. The electron affinity 208 of the second dielectric structure 110b is the energy difference between the conducting band edge of the second dielectric structure 110b and the vacuum energy level E. vac The energy difference between them. The electron affinity 206 of the first dielectric structure 110a is substantially the same as the electron affinity 208 of the second dielectric structure 110b. In some embodiments, the electron affinity 206 of the first dielectric structure 110a is substantially the same as the electron affinity 208 of the second dielectric structure 110b, at least in part because the first dielectric structure 110a and the second dielectric structure 110b are or comprise the same dielectric material (e.g., ZrO2).

[0048] Figures 3A to 3B Illustrations based on some embodiments Figure 1 Various band diagrams of the MIM capacitor 102.

[0049] Figure 3A Energy band diagram 300a shows some embodiments of the MIM capacitor 102 when it is forward biased (e.g., the second terminal T2 is the injection site).

[0050] like Figure 3A As shown in band structure diagram 300a, when the MIM capacitor 102 is forward biased, there is a first band offset Φ between the bottom electrode 106 and the first dielectric structure 110a. B1 The first band offset Φ B1This is the energy difference between the Fermi level of the bottom electrode 106 and the conductive band edge of the first dielectric structure 110a when the MIM capacitor 102 is forward biased. In other words, when the MIM capacitor 102 is reverse biased, the first band shifts by Φ. B1 It is the energy difference between the work function 202 of the bottom electrode 106 and the electron affinity 206 of the first dielectric structure 110a.

[0051] When the MIM capacitor 102 is forward biased, it has a forward bias breakdown voltage (e.g., the minimum voltage required to make a portion of the capacitor insulator structure 104 conductive). If a voltage applied to the MIM capacitor 102 forward biases it and exceeds (or approaches) the forward bias breakdown voltage, the MIM capacitor 102 may fail (e.g., due to electrical breakdown of the capacitor insulator structure 104). The forward bias breakdown voltage depends at least in part on the first band offset Φ. B1 For example, if a voltage is applied to the MIM capacitor 102 that causes it to be forward biased and exceeds (or approaches) the forward bias breakdown voltage, then one or more electrons (in) Figure 3A and Figure 3B (Represented by black dots) can have enough energy to overcome the first band offset Φ B1 (and / or the conductive band edge near the first dielectric structure 110a), thereby causing electrical breakdown of the capacitor insulator structure 104 (e.g., due to one or more breakdown mechanisms, such as electron hopping, electron tunneling, etc.).

[0052] Figure 3B Energy band diagram 300b shows some embodiments of the MIM capacitor 102 when reverse biased (e.g., the first terminal T1 is the injection site).

[0053] like Figure 3B As shown in band structure diagram 300b, when the MIM capacitor 102 is reverse biased, a second band offset Φ exists between the top electrode 108 and the second dielectric structure 110b. B2 The second band offset Φ B2 This is the energy difference between the Fermi level of the top electrode 108 of the MIM capacitor 102 when it is reverse biased and the conduction band edge of the second dielectric structure 110b. In other words, when the MIM capacitor 102 is reverse biased, the second band shifts by Φ. B2 It is the energy difference between the work function 204 of the top electrode 108 and the electron affinity 208 of the second dielectric structure 110b.

[0054] When the MIM capacitor 102 is reverse biased, it has a reverse bias breakdown voltage (e.g., the minimum voltage required to make a portion of the capacitor insulator structure 104 conductive). If a voltage applied to the MIM capacitor 102 reverse biases it and exceeds (or approaches) the reverse bias breakdown voltage, the MIM capacitor 102 may fail (e.g., due to electrical breakdown of the capacitor insulator structure 104). The reverse bias breakdown voltage depends at least in part on the second band offset Φ. B2 For example, if a voltage is applied to the MIM capacitor 102 that causes it to be reverse biased and exceeds (or approaches) the forward bias breakdown voltage, one or more electrons may have sufficient energy to overcome the second band offset Φ. B2 (and / or the conductive band edge near the second dielectric structure 110b), thereby causing electrical breakdown of the capacitor insulator structure 104 (e.g., due to one or more breakdown mechanisms, such as electron hopping, electron tunneling, etc.).

[0055] Because the capacitor insulator structure 104 is symmetrical, the first band offset Φ B1 offset Φ from the second zone B2 The difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of the MIM capacitor 102 is relatively small. Therefore, when used in bipolar applications (e.g., as a decoupling capacitor for HPC), the capacitor insulator structure 104 can improve (e.g., increase) the utility of the MIM capacitor 102. For example, when used in bipolar applications, because the smaller of the forward bias breakdown voltage and the reverse bias breakdown voltage of the MIM capacitor 102 limits its utility in bipolar applications, the smaller difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of the MIM capacitor 102 can improve (e.g., increase) the utility of the MIM capacitor 102 compared to a typical MIM capacitor (e.g., a MIM capacitor with an asymmetric capacitor insulator structure). More specifically, the small difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of the MIM capacitor 102 can increase the effective barrier height of the capacitor insulator structure 104 (e.g., from about 1.6 electron volts (eV) to about 3.0 eV) compared to a typical MIM capacitor.

[0056] The third dielectric structure 112 has an electron affinity 210, which depends at least in part on the material of the third dielectric structure 112. The electron affinity 210 of the third dielectric structure 112 is the relationship between the conducting band edge of the third dielectric structure 112 and the vacuum level E. vacThe energy difference between them. In some embodiments, the electron affinity 210 of the third dielectric structure 112 is different from the electron affinity 206 of the first dielectric structure 110a and the electron affinity 208 of the second dielectric structure 110b. In some embodiments, the electron affinity 210 of the third dielectric structure 112 is different from the electron affinity 206 of the first dielectric structure 110a and the electron affinity 208 of the second dielectric structure 110b, at least in part because the third dielectric structure 112 is or includes a dielectric material (e.g., Al2O3) different from the dielectric material (e.g., ZrO2) of the first dielectric structure 110a and the second dielectric structure 110b. In yet another embodiment, the electron affinity 210 of the third dielectric structure 112 is less than the electron affinity 206 of the first dielectric structure 110a and the electron affinity 208 of the second dielectric structure 110b. In some embodiments, because the electron affinity 210 of the third dielectric structure 112 is less than the electron affinity 206 of the first dielectric structure 110a and the electron affinity 208 of the second dielectric structure 110b, the third dielectric structure 112 can improve the leakage performance of the MIM capacitor 102 (e.g., reduce leakage current) (e.g., by reducing the likelihood of one or more electron tunneling through the capacitor insulator structure 104).

[0057] In some embodiments, the electron affinity 210 of the third dielectric structure 112 may also depend at least in part on the internal atomic structure of the third dielectric structure 112. For example, the third dielectric structure 112 may be an amorphous solid (e.g., amorphous Al2O3), and therefore the third dielectric structure 112 has an electron affinity 210. Thus, in some embodiments, the third dielectric structure 112 may improve the leakage performance of the MIM capacitor 102, at least in part because it is an amorphous solid.

[0058] Figure 4 Show Figure 1 Cross-sectional view 400 of some embodiments of the MIM capacitor 102.

[0059] like Figure 4 As shown in cross-sectional view 400, both the first dielectric structure 110a and the second dielectric structure 110b have a first thickness 402. The first thickness 402 can be between approximately 10 angstroms. With the agreement Between. If the first thickness 402 is less than approximately The capacitance density of MIM capacitor 102 may be too small to be reliably used as a decoupling capacitor for HPC. If the first thickness 402 is greater than approximately... The leakage performance of MIM capacitor 102 may be too poor (e.g., too high leakage) to be reliably used as a decoupling capacitor for HPC.

[0060] The third dielectric structure 112 has a second thickness 404 that is less than or equal to the first thickness 402. The second thickness 404 is greater than approximately If the second thickness 404 is less than approximately The leakage performance of the MIM capacitor 102 may be too poor to be reliably used as a decoupling capacitor for HPC. If the second thickness 404 is greater than the first thickness 402, it may increase manufacturing costs without any noticeable performance benefit. In some embodiments, the first thickness 402 is approximately... And the second thickness is approximately The first thickness is approximately 402. And the second thickness is approximately The first thickness is approximately 402. And the second thickness is approximately Or the first thickness is approximately 402. And the second thickness is approximately In some embodiments, the total thickness of the capacitor insulator structure 104 (e.g., the sum of the thicknesses of all dielectric structures of the capacitor insulator structure 104) is between approximately and between.

[0061] In some embodiments, the capacitor insulator structure 104 is symmetrical because, in terms of the thickness of the dielectric structure of the capacitor insulator structure 104, the lower half of the capacitor insulator structure 104 is a mirror image of the upper half of the capacitor insulator structure 104. For example, the axis of symmetry 114 extends laterally through the third dielectric structure 112. Therefore, the lower half of the capacitor insulator structure 104 includes a first portion (e.g., the lower half) of the first dielectric structure 110a and the third dielectric structure 112, and the upper half of the capacitor insulator structure 104 includes a second portion (e.g., the upper half) of the second dielectric structure 110b and the third dielectric structure 112. The first dielectric structure 110a and the second dielectric structure 110b have a first thickness 402, and the third dielectric structure 112 has a second thickness 404. Therefore, in terms of the thickness of the dielectric structure of the capacitor insulator structure 104, the lower half of the capacitor insulator structure 104 is a mirror image of the upper half of the capacitor insulator structure 104 on the axis of symmetry 114.

[0062] In some embodiments, the electron affinity 206 of the first dielectric structure 110a, the electron affinity 208 of the second dielectric structure 110b, and the electron affinity 210 of the third dielectric structure 112 depend at least in part on the thicknesses of the first dielectric structure 110a, the second dielectric structure 110b, and the third dielectric structure 112. Therefore, the first band offset Φ B1 Second band offset Φ B2The thickness of the first dielectric structure 110a and the second dielectric structure 110b depends at least in part on their respective thicknesses. Therefore, since the capacitor insulator structure 104 is also symmetrical in terms of the thickness of its dielectric structure, the utility of the MIM capacitor 102 can be further improved when used in bipolar applications (e.g., due to even the first band offset Φ). B1 offset Φ from the second zone B2 (the smaller difference between them).

[0063] Figure 5 Show Figure 1 Cross-sectional view 500 of some embodiments of the MIM capacitor 102.

[0064] like Figure 5 As shown in cross-sectional view 500, the first plurality of dielectric structures 110 include one or more crystals 502 (e.g., the first plurality of dielectric structures 110 are monocrystalline and / or polycrystalline solids). Each of the one or more crystals 502 (e.g., microcrystals) has a crystal lattice. The crystal lattice of the one or more crystals 502 can be, for example, monoclinic, tetragonal, cubic, etc. In some embodiments, because the first plurality of dielectric structures 110 include one or more crystals 502, the MIM capacitor 102 can have a better (e.g., higher) capacitance density. In some embodiments, the first plurality of dielectric structures 110 includes one or more crystals 502, while the third dielectric structure 112 is an amorphous solid. In other embodiments, because the first plurality of dielectric structures 110 includes one or more crystals 502, and because the third dielectric structure 112 is an amorphous solid, the MIM capacitor 102 can have a high capacitance density and good leakage performance (e.g., low leakage).

[0065] In some embodiments, one or more crystals 502 of the first dielectric structure 110a have different crystal lattices. For example, one or more crystals 502 of the first dielectric structure 110a are less than or equal to about 20 wt% monoclinic crystal, less than or equal to about 20 wt% cubic crystal, and between about 40 wt% and 80 wt% tetragonal crystal. In other embodiments, the crystal lattices of one or more crystals 502 of the first dielectric structure 110a may be identical (e.g., tetragonal crystal). In some embodiments, because one or more crystals 502 of the first dielectric structure 110a are less than or equal to about 20 wt% monoclinic crystal, less than or equal to about 20 wt% cubic crystal, and between about 40 wt% and 80 wt% tetragonal crystal, the MIM capacitor 102 may have better (e.g., even higher) capacitance density and better (e.g., even higher) leakage performance (e.g., even lower leakage).

[0066] In some embodiments, one or more crystals 502 of the second dielectric structure 110b have different crystal lattices. For example, one or more crystals 502 of the second dielectric structure 110b are less than or equal to about 20 wt% monoclinic crystal, less than or equal to about 20 wt% cubic crystal, and tetragonal crystal between about 40 wt% and 80 wt%. In other embodiments, the crystal lattice of one or more crystals 502 of the second dielectric structure 110b may be the same (e.g., tetragonal crystal). In some embodiments, because one or more crystals 502 of the second dielectric structure 110b are less than or equal to about 20 wt% monoclinic crystal, less than or equal to about 20 wt% cubic crystal, and tetragonal crystal between about 40 wt% and 80 wt%, the MIM capacitor 102 can have better (e.g., even higher) capacitance density and better (e.g., even higher) leakage performance (e.g., even lower leakage).

[0067] In some embodiments, the lattice of one or more crystals 502 of the second dielectric structure 110b may be substantially the same as the lattice of one or more crystals 502 of the first dielectric structure 110a. For example, one or more crystals 502 of the second dielectric structure 110b may include monoclinic, cubic, and tetragonal crystals in substantially the same percentage as the first dielectric structure 110a. In such embodiments, the MIM capacitor 102 may have good capacitance density when forward and reverse biased (e.g., having the same capacitance density value when forward and reverse biased at a predetermined corresponding voltage).

[0068] Figure 6 Show Figure 1 Cross-sectional view 600 of some embodiments of the MIM capacitor 102.

[0069] like Figure 6 As shown in cross-sectional view 600, a first capacitor interface layer 602 is disposed between the capacitor insulator structure 104 and the bottom electrode 106. In some embodiments, the first capacitor interface layer 602 contacts (e.g., directly contacts) the bottom electrode 106. In other embodiments, the first capacitor interface layer 602 contacts (e.g., directly contacts) the capacitor insulator structure 104. In still other embodiments, the first capacitor interface layer 602 contacts (e.g., directly contacts) the first dielectric structure 110a.

[0070] The first capacitor interface layer 602 comprises metallic elements (e.g., titanium (Ti), tantalum (Ta), etc.) and non-metallic elements (e.g., nitrogen (N), oxygen (O), etc.). The bottom electrode 106 comprises metallic elements of the first capacitor interface layer 602. In some embodiments, the first capacitor interface layer 602 comprises metallic elements, non-metallic elements, and oxygen (O). For example, the bottom electrode 106 is or comprises titanium nitride (TiN), and the first capacitor interface layer 602 is or comprises titanium oxynitride (TiON). The first capacitor interface layer 602 has an electron affinity that is different from (e.g., less than) the electron affinity 206 of the first dielectric structure 110a.

[0071] Figures 7A to 7B Illustrations based on some embodiments Figure 6 Various band diagrams of the MIM capacitor 102.

[0072] Figure 7A Energy band diagram 700a shows some embodiments of the MIM capacitor 102 when it is forward biased.

[0073] like Figure 7A As shown in band structure diagram 700a, when the MIM capacitor 102 is reverse biased, a third band offset Φ exists between the bottom electrode 106 and the first capacitor interface layer 602. B3 The third zone offset Φ B3 This is the energy difference between the Fermi level of the bottom electrode 106 of the MIM capacitor 102 when it is forward biased and the conductive band edge of the first capacitor interface layer 602. In other words, when the MIM capacitor 102 is forward biased, the third band offset Φ B3 It is the energy difference between the work function 202 of the bottom electrode 106 and the electron affinity of the first capacitor interface layer 602. The forward bias breakdown voltage of the MIM capacitor 102 can depend on the third band offset Φ. B3 .

[0074] Figure 7B Energy band diagram 700b shows some embodiments of the MIM capacitor 102 when it is forward biased.

[0075] like Figure 7B As shown in band structure diagram 700b, when the MIM capacitor 102 is reverse biased, a second band offset Φ exists between the top electrode 108 and the second dielectric structure 110b. B2 In some embodiments, the third band is offset by Φ B3 It can be less than the second offset Φ B2 The reverse bias breakdown voltage depends at least in part on the second band offset Φ. B2 .

[0076] Although the third zone offset ΦB3 It can be less than the second offset Φ B2 However, the third zone is offset by Φ B3 offset Φ from the second zone B2 The difference between them is still relatively smaller than that of a corresponding MIM capacitor with an asymmetric capacitor insulator structure (e.g., a capacitor MIM with an asymmetric capacitor insulator structure, wherein the interface layer is disposed between the asymmetric capacitor insulator structure and the bottom electrode). Therefore, by having a small difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of the MIM capacitor 102, the capacitor insulator structure 104 can improve (e.g., increase) the utility of the MIM capacitor 102 in bipolar applications (e.g., as a decoupling capacitor for HPC).

[0077] Figure 8 Show Figure 1 Cross-sectional view 800 of some embodiments of the MIM capacitor 102.

[0078] like Figure 8 As shown in cross-sectional view 800, a second capacitor interface layer 802 is disposed between the capacitor insulator structure 104 and the top electrode 108, and a first capacitor interface layer 602 is disposed between the capacitor insulator structure 104 and the bottom electrode 106. In some embodiments, the second capacitor interface layer 802 contacts (e.g., directly contacts) the top electrode 108. In other embodiments, the second capacitor interface layer 802 contacts (e.g., directly contacts) the capacitor insulator structure 104. In yet another embodiment, the second capacitor interface layer 802 contacts (e.g., directly contacts) the second dielectric structure 110b.

[0079] The second capacitor interface layer 802 comprises metallic elements (e.g., titanium (Ti), tantalum (Ta), etc.) and non-metallic elements (e.g., nitrogen (N), oxygen (O), etc.). The top electrode 108 comprises metallic elements of the second capacitor interface layer 802. In some embodiments, the second capacitor interface layer 802 comprises metallic elements, non-metallic elements, and oxygen (O). For example, the top electrode 108 is or comprises titanium nitride (TiN), and the second capacitor interface layer 802 is or comprises titanium oxynitride (TiON). The second capacitor interface layer 802 has an electron affinity different from (e.g., less than) the electron affinity 208 of the second dielectric structure 110b.

[0080] In some embodiments, the second capacitor interface layer 802 and the first capacitor interface layer 602 are made of the same material (e.g., TiON). In other embodiments, the electron affinity of the second capacitor interface layer 802 may be substantially the same as that of the first capacitor interface layer 602. Therefore, by having a smaller difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of the MIM capacitor 102, the capacitor insulator structure 104 can improve (e.g., increase) the utility of the MIM capacitor 102 in bipolar applications. In other embodiments, the thickness of the second capacitor interface layer 802 is substantially the same as that of the first capacitor interface layer 602. In such embodiments, the electron affinity of the second capacitor interface layer 802 may be even closer to that of the first capacitor interface layer 602. Therefore, by having an even smaller difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of the MIM capacitor 102, the capacitor insulator structure 104 can improve the utility of the MIM capacitor 102 in bipolar applications.

[0081] Figure 9 Show Figure 1 Cross-sectional view 900 of some embodiments of the MIM capacitor 102.

[0082] like Figure 9 As shown in cross-sectional view 900, the capacitor insulator structure 104 includes a first plurality of dielectric structures 110 and a second plurality of dielectric structures 902. The first plurality of dielectric structures 110 and the second plurality of dielectric structures 902 are stacked perpendicularly to each other. Each of the first plurality of dielectric structures 110 is separate from one of the second plurality of dielectric structures 902, and vice versa.

[0083] In some embodiments, the first plurality of dielectric structures 110 includes a first dielectric structure 110a, a second dielectric structure 110b, and a fourth dielectric structure 110c. In some embodiments, the fourth dielectric structure 110c is an intermediate dielectric structure among the first plurality of dielectric structures 110. For example, the fourth dielectric structure 110c is vertically disposed between the first dielectric structure 110a and the second dielectric structure 110b. In some embodiments, the second plurality of dielectric structures 902 includes a fifth dielectric structure 902a and a sixth dielectric structure 902b. In other embodiments, the second plurality of dielectric structures 902 is an amorphous solid.

[0084] The first plurality of dielectric structures 110 includes N dielectric structures, where N is greater than or equal to two (2). The second plurality of dielectric structures 902 includes M dielectric structures, where M is equal to N minus one (1). For example, as Figure 9 As shown in the cross-sectional diagram 900, N is three (3) and M is two (2). It should be understood that N can be any integer greater than or equal to 2.

[0085] The first plurality of dielectric structures 110 may be, for example, or include zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), silicon oxide (SiO2), another dielectric material, or any combination thereof. In some embodiments, the first plurality of dielectric structures 110 are or include metal oxides (e.g., ZrO2, Al2O3, HfO2, Ta2O5, etc.) and / or include high-k dielectrics. The second plurality of dielectric structures 902 may be, for example, or include zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), silicon oxide (SiO2), another dielectric material, or any combination thereof. In some embodiments, the second plurality of dielectric structures 902 are or include metal oxides (e.g., ZrO2, Al2O3, HfO2, Ta2O5, etc.) and / or include high-k dielectrics.

[0086] The first plurality of dielectric structures 110 are or comprise the same dielectric material. For example, the first dielectric structure 110a, the second dielectric structure 110b, and the fourth dielectric structure 110c are or comprise the first dielectric material. The second plurality of dielectric structures 902 are or comprise the same dielectric material. For example, the fifth dielectric structure 902a and the sixth dielectric structure 902b are or comprise a second dielectric material different from the first dielectric material. More specifically, in some embodiments, the first dielectric structure 110a, the second dielectric structure 110b, and the fourth dielectric structure 110c are or comprise zirconium oxide (ZrO2), and the fifth dielectric structure 902a and the sixth dielectric structure 902b are or comprise aluminum oxide (Al2O3).

[0087] The capacitor insulator structure 104 alternates periodically between a first dielectric material and a second dielectric material from the bottom electrode 106 to the top electrode 108. For example, as... Figure 9 As shown in cross-sectional view 900, the capacitor insulator structure 104 alternates between a first dielectric material (e.g., ZrO2) and a second dielectric material (e.g., Al2O3). In such embodiments, the capacitor insulator structure 104 may be described as having a ZAZAZ dielectric structure stack, where "Z" corresponds to the first letter of the first dielectric material (e.g., ZrO2) and "A" corresponds to the first letter of the second dielectric material (e.g., Al2O3). It should be understood that the capacitor insulator structure 104 may have other configurations of dielectric structure stacks, such as AZAZA, HZHZH, ZHZHZ, TATAT, ATATA, ZTZTZ, TZTZT, etc.

[0088] The capacitor insulator structure 104 is symmetrical. The capacitor insulator structure 104 is symmetrical because, with respect to the dielectric material of its dielectric structure, the lower half of the capacitor insulator structure 104 is a mirror image of the upper half. For example, the axis of symmetry 114 extends laterally through the fourth dielectric structure 110c, and, with respect to the dielectric material of its dielectric structure, the lower half of the capacitor insulator structure 104 is a mirror image of the upper half. In some embodiments, the lower half of the capacitor insulator structure 104 is a mirror image of the upper half with respect to the dielectric material of its dielectric structure because the capacitor insulator structure 104 periodically alternates between the first and second dielectric materials from the bottom electrode 106 to the top electrode 108.

[0089] Because the capacitor insulator structure 104 is symmetrical, the difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of the MIM capacitor 102 is small. Therefore, the capacitor insulator structure 104 can improve (e.g., increase) the effectiveness of the MIM capacitor 102. More specifically, when used in bipolar applications (e.g., as a decoupling capacitor for HPC), the capacitor insulator structure 104 can improve (e.g., increase) the effectiveness of the MIM capacitor 102.

[0090] In some embodiments, each of the second plurality of dielectric structures 902 has a second thickness 404. In other embodiments, the first dielectric structure 110a and the second dielectric structure 110b both have a first thickness 402, and the fourth dielectric structure 110c has a third thickness 904. The third thickness 904 may be between approximately With the agreement Between. If the third thickness 904 is less than approximately If the capacitance density of the MIM capacitor 102 is too small to be reliably used as a decoupling capacitor for HPC, then the capacitance density of the MIM capacitor 102 may be too small to be reliably used as a decoupling capacitor for HPC. If the third thickness 904 is greater than approximately... The leakage performance of MIM capacitor 102 may be too poor (e.g., too high leakage) to be reliably used as a decoupling capacitor for HPC.

[0091] In some embodiments, the third thickness 904 is substantially the same as the first thickness 402. In other embodiments, the third thickness 904 differs from the first thickness 402. For example, in some embodiments, the third thickness 904 is less than the first thickness 402. In other embodiments, the third thickness 904 is between approximately With the agreement Between, and the first thickness is between approximately With the agreement Between. In some embodiments, because the thickness of the third thickness 904 (e.g., between approximately With the agreement (between) less than the first thickness 402 (e.g., between approximately) With the agreement (between), so the MIM capacitor 102 can have improved leakage performance.

[0092] In some embodiments, the first plurality of dielectric structures 110 include one or more crystals 502 (see, for example...) Figure 5 In some embodiments, the first plurality of dielectric structures 110 includes one or more crystals 502, while the second plurality of dielectric structures 902 is an amorphous solid. In some embodiments, the crystal lattices of the one or more crystals 502 of the first plurality of dielectric structures 110 are identical. For example, the one or more crystals 502 of the first dielectric structure 110a may include monoclinic, cubic, and tetragonal crystals in substantially the same percentage as those of the second dielectric structure 110b and the fourth dielectric structure 110c.

[0093] In other embodiments, the crystal lattices of one or more crystals 502 in the first dielectric structure 110a and the second dielectric structure 110b are substantially identical, while the crystal lattices of one or more crystals 502 in the fourth dielectric structure 110c are different. For example, the first dielectric structure 110a and the second dielectric structure 110b have substantially similar percentages of monoclinic, cubic, and / or tetragonal crystals, while the fourth dielectric structure 110c has different percentages of monoclinic, cubic, and / or tetragonal crystals. More specifically, in some embodiments, the fourth dielectric structure 110c has a lower percentage of tetragonal crystals than both the first dielectric structure 110a and / or the second dielectric structure 110b. For example, one or more crystals 502 of the fourth dielectric structure 110c are less than or equal to about 20 wt% monoclinic crystal, less than or equal to about 20 wt% cubic crystal, and tetragonal crystal between about 40 wt% and 80 wt%, and one or more crystals 502 of both the first dielectric structure 110a and the second dielectric structure 110b are tetragonal crystals with a content greater than 80 wt%. In such embodiments, the MIM capacitor 102 can have high capacitance density and good leakage performance. In other embodiments, because the thickness of the third thickness 904 (e.g., between about 20 wt% and 80 wt%)... With the agreement (between) different from the first thickness 402 (e.g., between approximately) With the agreement (between), and because one or more crystals 502 of the fourth dielectric structure 110c are different from the crystals of the first dielectric structure 110a and the second dielectric structure 110b, the MIM capacitor 102 can have even better leakage performance.

[0094] Figure 10 Show Figure 1 Cross-sectional view 1000 of some embodiments of the MIM capacitor 102.

[0095] like Figure 10 As shown in cross-sectional view 1000, the capacitor insulator structure 104 includes a first plurality of dielectric structures 110, a second plurality of dielectric structures 902, and a third plurality of dielectric structures 1002. The first plurality of dielectric structures 110, the second plurality of dielectric structures 902, and the third plurality of dielectric structures 1002 are stacked perpendicularly to each other. Each of the first plurality of dielectric structures 110 is separated from each other by at least one of the third plurality of dielectric structures 1002 and one of the second plurality of dielectric structures 902. Each of the second plurality of dielectric structures 902 is separated from each other by at least one of the first plurality of dielectric structures 110 and one of the third plurality of dielectric structures 1002. Each of the third plurality of dielectric structures 1002 is separated from each other by at least one of the first plurality of dielectric structures 110. In some embodiments, one or more of the third plurality of dielectric structures 1002 are separated from the other of the third plurality of dielectric structures 1002 by at least one of the first plurality of dielectric structures 110 and one of the second plurality of dielectric structures 902. In other embodiments, the third plurality of dielectric structures 1002 includes a seventh dielectric structure 1002a and an eighth dielectric structure 1002b.

[0096] The first plurality of dielectric structures 110 includes N dielectric structures, where N is greater than or equal to two (2). The second plurality of dielectric structures 902 includes M dielectric structures, where M is equal to N minus one (1). The third plurality of dielectric structures 1002 includes X dielectric structures, where X is equal to M. For example, as Figure 9 As shown in the cross-sectional diagram 900, N is trigonometric (3), M is digonometric (2), and X is digonometric (2). It should be understood that N can be any integer greater than or equal to 2.

[0097] The third plurality of dielectric structures 1002 may be, for example, or include zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), silicon oxide (SiO2), one other dielectric material, or any combination thereof. In some embodiments, the third plurality of dielectric structures 1002 is or includes metal oxides (e.g., ZrO2, Al2O3, HfO2, Ta2O5, etc.) and / or includes high-k dielectrics. In other embodiments, the third plurality of dielectric structures 1002 is an amorphous solid or has one or more crystals (e.g., a crystalline or polycrystalline solid).

[0098] The third plurality of dielectric structures 1002 is or includes the same dielectric material. For example, the seventh dielectric structure 1002a and the eighth dielectric structure 1002b include a third dielectric material that is different from the first dielectric material (e.g., the dielectric material of the first plurality of dielectric structures 110) and the second dielectric material (e.g., the dielectric material of the second plurality of dielectric structures 902). More specifically, in some embodiments, the first plurality of dielectric structures 110 is or includes zirconium oxide (ZrO2), the second plurality of dielectric structures 902 is or includes aluminum oxide (Al2O3), and the third plurality of dielectric structures 1002 is or includes hafnium oxide (HfO2). The capacitor insulator structure 104 alternates periodically between the first dielectric material, the second dielectric material, and the third dielectric material from the bottom electrode 106 to the top electrode 108. For example, as Figure 10 As shown in cross-sectional view 1000, the capacitor insulator structure 104 alternates in the following pattern: first dielectric material, second dielectric material, third dielectric material, first dielectric material, third dielectric material, second dielectric material, and first dielectric material. In such embodiments, the capacitor insulator structure 104 can be described as having a ZAHZHAZ dielectric structure stack, where "Z" corresponds to the first letter of the first dielectric material (e.g., ZrO2), "A" corresponds to the first letter of the second dielectric material (e.g., Al2O3), and "H" corresponds to the first letter of the third dielectric material (e.g., HfO2). It should be understood that the capacitor insulator structure 104 may have other configurations of dielectric structure stacks, such as AZHAHZA, ZHAZAHZ, HZAHAZH, ZHTZTHZ, HZTHZTH, TZHTHZT, ZAHZAHZHAZ, AZHAZHAHZA, etc.

[0099] The capacitor insulator structure 104 is symmetrical. The capacitor insulator structure 104 is symmetrical because, in terms of the dielectric material of its dielectric structure, the lower half of the capacitor insulator structure 104 is a mirror image of the upper half. For example, the axis of symmetry 114 extends laterally through the fourth dielectric structure 110c, and, in terms of the dielectric material of its dielectric structure, the lower half of the capacitor insulator structure 104 is a mirror image of the upper half. In some embodiments, the lower half of the capacitor insulator structure 104 is a mirror image of the upper half in terms of the dielectric material of its dielectric structure because the capacitor insulator structure 104 periodically alternates between the first, second, and third dielectric materials from the bottom electrode 106 to the top electrode 108.

[0100] Because the capacitor insulator structure 104 is symmetrical, the difference between the forward bias breakdown voltage and the reverse bias breakdown voltage of the MIM capacitor 102 is small. Therefore, the capacitor insulator structure 104 can improve (e.g., increase) the effectiveness of the MIM capacitor 102. More specifically, when used in bipolar applications (e.g., as a decoupling capacitor for HPC), the capacitor insulator structure 104 can improve (e.g., increase) the effectiveness of the MIM capacitor 102.

[0101] In some embodiments, each of the third plurality of dielectric structures 1002 has a fourth thickness 1004. The fourth thickness 1004 may be less than or equal to the first thickness 402. The second thickness 404 is greater than approximately If the second thickness 404 is less than approximately The leakage performance of the MIM capacitor 102 may be too poor to be reliably used as a decoupling capacitor for HPC. In some embodiments, the fourth thickness 1004 is substantially the same as the second thickness 404. In other embodiments, the fourth thickness 1004 differs from the second thickness 404. In some embodiments, the total thickness of the capacitor insulator structure 104 (e.g., the sum of the thicknesses of all dielectric structures of the capacitor insulator structure 104) is between approximately and between.

[0102] Figure 11 The diagram shows that it includes embedded with Figure 1 Cross-sectional view 1100 of some embodiments of the interconnect structure 1102 of the MIM capacitor and some embodiments of the integrated chip (IC).

[0103] like Figure 11 As shown in cross-sectional view 1100, the MIM capacitor 102 is located above the lower capacitor wiring 1104l and has a downward protrusion defining a bottom electrode via (BEVA) 1106. The upper capacitor wiring 1104u is located above the MIM capacitor 102, and the top electrode via (TEVA) 1108tv extends from the upper capacitor wiring 1104u to the MIM capacitor 102. The lower capacitor wiring 1104l, the upper capacitor wiring 1104u, and the TEVA 1108tv are conductive and may be, or include, for example, copper (Cu), aluminum (Al), aluminum-copper (AlCu), gold (Au), silver (Ag), tungsten (W), some other conductive material, or a combination of the foregoing.

[0104] The MIM capacitor 102, lower capacitor wiring 1104l, upper capacitor wiring 1104u, and TEVA 1108tv are surrounded by multiple interlayer dielectric (ILD) layers 1110. The ILD layers 1110 are stacked on top of each other, and in some embodiments, multiple etch stop layers 1112 separate the ILD layers 1110 from each other. In other embodiments, the etch stop layers 1112 are omitted. The ILD layers 1110 are made of a different material than the etch stop layers 1112. The ILD layers 1110 can be or include, for example, oxides (e.g., silicon dioxide (SiO2)), oxynitrides (e.g., silicon oxynitride (SiON)), doped silicon dioxide (e.g., carbon-doped silicon dioxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k dielectric materials, etc. The etch stop layer 1112 may be or include, for example, nitrides (e.g., SiN), oxide oxynitrides (e.g., silicon oxynitride (SiON)), carbides (e.g., silicon carbide (SiC)), etc. It should be understood that in some embodiments, the first capacitor interface layer 602 may line the substrate electrode 106 between the first dielectric structure 110a and the bottom electrode 106, and / or the second capacitor interface layer 802 may line the second dielectric structure 110b between the second dielectric structure 110b and the top electrode 108.

[0105] Figure 12 Show Figure 11 Cross-sectional view 1200 of some other embodiments of the IC.

[0106] like Figure 12 As shown in cross-sectional view 1200, a top electrode hard mask 1202 and a bottom electrode hard mask 1204 cover the MIM capacitor 102. The top electrode hard mask 1202 covers the top electrode 108 and has the same or substantially the same top layout as the top electrode 108. The bottom electrode hard mask 1204 is disposed above and covers the top electrode hard mask 1202. The bottom electrode hard mask 1204 covers and has the same or substantially the same top layout as the bottom electrode 106, the capacitor insulator structure 104, and the first capacitor interface layer 602. In some embodiments, the bottom electrode hard mask 1204 also covers and has the same or substantially the same top layout as the second capacitor interface layer 802. In other embodiments, the capacitor insulator structure 104 alternatively has the same or substantially the same top layout as the top electrode hard mask 1202. The top electrode hard mask 1202 and the bottom electrode hard mask 1204 may be or include, for example, nitrides (e.g., SiN), oxide oxynitrides (e.g., SiON), carbides (e.g., SiC), etc.

[0107] In some embodiments, the hard mask liner 1206 is independent of the top electrode hard mask 1202 and the bottom electrode hard mask 1204, and separates the top electrode hard mask 1202 and the bottom electrode hard mask 1204 from the capacitor insulator structure 104 and the top electrode 108. The hard mask liner 1206 is a different material from the top electrode hard mask 1202 and the bottom electrode hard mask 1204, and may be or include, for example, an oxide (e.g., SiO2) and / or some other suitable dielectric. In other embodiments, the hard mask liner 1206 is omitted. It should be understood that in some embodiments, the first capacitor interface layer 602 and / or the second capacitor interface layer 802 may be omitted.

[0108] Figure 13 Show Figure 11 Cross-sectional view 1300 of some other embodiments of the IC.

[0109] like Figure 13 As shown in cross-sectional view 1300, the top electrode 108 is recessed at BEVA 1106. Furthermore, the bottom electrode 106, the first capacitor interface layer 602, the capacitor insulator structure 104, the second capacitor interface layer 802, and the top electrode 108 have curved edges. Additionally, the bottom electrode hard mask 1204 and its corresponding hard mask pad in the hard mask pad 1206 also have curved surfaces. In some embodiments, the top electrode hard mask 1202 and its corresponding hard mask pad of the hard mask pad 1206 are omitted. In other embodiments, the top electrode hard mask 1202 and its corresponding hard mask pad of the hard mask pad 1206 remain on the top electrode 108, separating the top electrode 108 from the bottom electrode hard mask 1204 and its corresponding hard mask pad 1206. It should be understood that in some embodiments, the first capacitor interface layer 602 and / or the second capacitor interface layer 802 may be omitted.

[0110] Figure 14 Show Figure 11 Cross-sectional view 1400 of some other embodiments of the IC.

[0111] like Figure 14As shown in cross-sectional view 1400, the MIM capacitor 102 is situated above multiple additional conductors 1104. Furthermore, the TEVA 1108tv and the upper capacitor wiring 1104u are integrated into the conductive structure 1402. Additionally, the conductive structure 1402, the lower capacitor wiring 1104l, and the multiple additional conductors 1104 are lined by an interconnect barrier layer 1404. The interconnect barrier layer 1404 is configured to prevent material from diffusing from the conductive structure 1402, the lower capacitor wiring 1104l, and the multiple additional conductors 1104 into the underlying structure. In some embodiments, the conductive structure 1402, the lower capacitor wiring 1104l, and the multiple additional conductors 1104 are or include, for example, copper (Cu), aluminum (Al), aluminum-copper (AlCu), gold (Au), silver (Ag), tungsten (W), some other conductive material, or a combination of the foregoing. In some embodiments, the interconnect barrier layer 1404 is or includes, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), some other suitable conductive material, or a combination of the foregoing. It should be understood that in some embodiments, the first capacitor interface layer 602 and / or the second capacitor interface layer 802 may be omitted.

[0112] Figure 15 Show Figure 11 Cross-sectional view 1500 of some other embodiments of the IC.

[0113] like Figure 15 The cross-sectional view 1500 is shown, BEVA 1106 is omitted. Furthermore, the second capacitor interface layer 802 covers the lower side of the top electrode 108, the capacitor insulator structure 104 covers the lower side of the second capacitor interface layer 802, the first capacitor interface layer 602 covers the lower side of the capacitor insulator structure 104, and the bottom electrode 106 covers the lower side of the first capacitor interface layer 602. In some embodiments, the bottom electrode 106, the first capacitor interface layer 602, the capacitor insulator structure 104, and the second capacitor interface layer 802 have U-shaped or V-shaped profiles. However, it should be understood that the bottom electrode 106, the first capacitor interface layer 602, the capacitor insulator structure 104, and the second capacitor interface layer 802 are not limited to these profiles, and other profiles are modifiable. It should also be understood that in some embodiments, the first capacitor interface layer 602 and / or the second capacitor interface layer 802 may be omitted.

[0114] Figure 16 Show Figure 11 Cross-sectional view 1600 of some more detailed embodiments of the IC.

[0115] like Figure 16 As shown in the cross-sectional view 1600, the IC includes a single transistor single capacitor (1T1C) unit 1602. The 1T1C unit 1602 includes a MIM capacitor 102. Figure 16The cross-sectional view 1600 shows Figure 11 The MIM capacitor. However, it should be understood that the MIM capacitor 102 can be configured as Figure 1 , Figures 4 to 6 and Figures 8 to 15 The MIM capacitor 102 is located on the substrate 1604 and within the interconnect structure 1102. The substrate 1604 comprises any type of semiconductor substrate (e.g., single-crystal silicon / CMOS block, germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), silicon-on-insulator (SOI), etc.).

[0116] The interconnect structure 1102 includes one or more ILD layers 1110. The one or more ILD layers 1110 may, for example, be related to... Figure 11 As described. In some embodiments, the interconnect structure 1102 may include one or more etch stop layers 1112 (not shown) (see, for example...) Figure 11 One or more etch stop layers 1112 may be, for example, about Figure 11 As described. In some embodiments, the interconnect structure 1102 includes a passivation layer 1606 located on one or more ILD layers 1110. The passivation layer 1606 is a different material from the one or more ILD layers 1110 and may be or include, for example, a nitride (e.g., SiN), an oxide oxynitride (e.g., SiON), etc.

[0117] The interconnect structure 1102 also includes multiple wires 1104 and multiple vias 1108 stacked in one or more ILD layers 1110 and passivation layers 1606. The multiple wires 1104 and multiple vias 1108 are conductive and define conductive paths extending from the MIM capacitor 102 and the underlying access transistor 1608. A first conductive path extends from the MIM capacitor 102 to a bit line 1104bl above the MIM capacitor 102. A second conductive path extends from the MIM capacitor 102 to the drain region 1610d of the access transistor 1608. A third conductive path extends from the source region 1610s of the access transistor 1608 to a source line 1104sl above the source region 1610s. A fourth conductive path extends from the gate electrode 1612 of the access transistor 1608 to a word line 1104wl above the gate electrode 1610. Note that although word line 1104wl is shown as having two separate segments on opposite sides of drain region 1610d, word line 1104wl can... Figure 16 The external continuity of the cross-section diagram 1600.

[0118] Access transistor 1608 includes a drain region 1610d and a source region 1610s, and further includes a gate electrode 1612 and a gate dielectric layer 1614. The drain region 1610d and the source region 1610s are in a substrate 1604 and correspond to doped regions of the substrate 1604. The gate electrode 1612 is located on the gate dielectric layer 1614 and sandwiched between the drain region 1610d and the source region 1610s. In some embodiments, a sidewall spacer structure 1616 is on the sidewall of the gate electrode 1612, and / or access transistor 1608 is surrounded by a trench isolation structure 1618 (e.g., a shallow trench isolation structure). The sidewall spacer structure 1616 and the trench isolation structure 1618 are or include a dielectric material. Access transistor 1608 may be, for example, an insulated-gate field-effect transistor (IGFET) or some other suitable transistor.

[0119] Figure 17 Show Figure 11 Cross-sectional view 1700 of some more detailed embodiments of the IC.

[0120] like Figure 17 As shown in cross-sectional view 1700, interconnect structure 1102 is located on substrate 1604. Interconnect structure 1102 and / or substrate 1604 may, for example, be about... Figure 16 As described, the interconnect structure 1102 includes one or more ILD layers 1110 and a passivation layer 1606 located on the one or more ILD layers 1110.

[0121] Multiple MIM capacitors 1702 are disposed in the interconnect structure 1102 and above the substrate 1604. Each of the multiple MIM capacitors 1702 is configured as follows: Figure 1 , 4 to Figure 6 and Figures 8 to 15 Any of the MIM capacitors 102 or certain other suitable MIM capacitors. For example, such as Figure 17 As shown in the cross-sectional view 1700, multiple MIM capacitors 1702 are respectively configured as Figure 11 The MIM capacitor 102. However, it should be understood that the MIM capacitor 1702 can be configured as Figure 1 , Figures 4 to 6 and Figures 8 to 15 The MIM capacitors 102 or other suitable MIM capacitors may be included. One or more of the MIM capacitors 1702 are located in logic region 1704l of the IC, and one or more of the MIM capacitors 1702 are located in decoupling capacitor region 1704dc of the IC. It should be understood that in some embodiments, the MIM capacitors 1702 may only include one or more MIM capacitors located in decoupling capacitor region 1704dc of the IC.

[0122] Interconnect structure 1102 includes multiple conductors 1104 and multiple vias 1108 stacked in one or more ILD layers 1110 and passivation layers 1606. The conductors 1104 and vias 1108 are conductive and define conductive paths leading from the MIM capacitor 1702 and from multiple transistors 1706 beneath the MIM capacitor 1702. In some embodiments, apart from the conductors 1104 shown, there are no conductors or vias directly beneath one of the MIM capacitors 1702 in the decoupling capacitor region 1704dc of the IC.

[0123] Transistor 1706 can, for example, each be configured as Figure 16 The access transistors 1608 and / or each may be, for example, an IGFET or some other suitable transistor. Transistor 1706 includes a single source / drain region 1708i, a single gate electrode 1612, and a single gate dielectric layer 1614. Furthermore, two adjacent transistors 1706 share a shared source / drain region 1708s. A single gate electrode 1612 is located on top of a single gate dielectric layer 1614, and each is sandwiched between two of the single and / or shared source / drain regions 1708i, 1708s. In some embodiments, the sidewall spacer structure 1616 is independent for the single gate electrode 1612 and the line sidewalls of the single gate electrode 1612. In some embodiments, transistors 1706 are surrounded and separated by a trench isolation structure 1618 (e.g., a shallow trench isolation structure). In some embodiments, there are no transistors and / or other semiconductor devices directly beneath one or more MIM capacitors in the decoupling capacitor region 1704dc of the IC on substrate 1604.

[0124] Figures 18 to 26 A series of cross-sectional views 1800 to 2600 illustrate some embodiments of a method for forming an IC including a MIM capacitor 102 having a symmetrical capacitor insulator structure. Although referenced... Figures 18 to 26 The method is described, but it should be understood that... Figures 18 to 26 The structure shown is not limited to this method, but can exist independently of this method.

[0125] like Figure 18As shown in cross-sectional view 1800, a trench isolation structure 1618 and an access transistor 1608 are formed on a substrate 1604. The trench isolation structure 1618 is formed to extend into the top of the substrate 1604 and has a pair of laterally spaced segments. The trench isolation structure 1618 can be, for example, a shallow trench isolation (STI) structure or some other suitable trench isolation structure. After forming the trench isolation structure 1618, the access transistor 1608 is formed between the segments of the trench isolation structure 1618. The access transistor 1608 includes a gate dielectric layer 1614, a gate electrode 1612 located on the gate dielectric layer 1614, and a sidewall spacer structure 1616 along the sidewall of the gate electrode 1612. Furthermore, the access transistor 1608 includes a source region 1610s and a drain region 1610d sandwiched between the gate electrode 1612. The access transistor 1608 can be, for example, an IGFET or some other suitable transistor.

[0126] exist Figure 18 Cross-sectional view 1800 also shows an interconnect structure 1102, which is partially formed above and electrically coupled to the access transistor 1608. The interconnect structure 1102 includes a first ILD layer 1110a and a second ILD layer 1110b located above the first ILD layer 1110a. Furthermore, the interconnect structure 1102 includes multiple conductors 1104 and multiple vias 1108 stacked in the first ILD layer 1110a and the second ILD layer 1110b. The multiple conductors 1104 and the multiple vias 1108 define conductive paths leading from the access transistor 1608 to a lower capacitor wiring 1104l in the multiple conductors 1104. The lower capacitor wiring 1104l is located on top of the second ILD layer 1110b and provides a substrate for forming a MIM capacitor on the lower capacitor wiring 1104l, the details of which will be described in more detail below.

[0127] like Figure 19 As shown in the cross-sectional view 1900, the upper third ILD layer 1110c is deposited with the second ILD layer 1110b and the lower capacitor wiring 1104l. For compactness, here (e.g., in...) Figure 19 (in) and thereafter (for example, in) Figures 20 to 26 (Not shown) A portion of the interconnect structure 1102 beneath the lower capacitor wiring 204l and substrate 1604. The third ILD layer 1110c can be deposited, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other deposition process, or a combination of the foregoing. In some embodiments, an etch stop layer (e.g., ...) is first etched using, for example, CVD, PVD, ALD, some other deposition process, or a combination of the foregoing. Figure 11The third ILD layer 1110c is deposited on the second ILD layer 1110b and the lower capacitor wiring 1104l. In this embodiment, the third ILD layer 1110c is deposited on the etch stop layer.

[0128] like Figure 20 As shown in cross-sectional view 2000, the third ILD layer 1110c is patterned to form an opening 2002 located on and exposing the lower capacitor wiring 1104l. In some embodiments, the process for patterning the third ILD layer 1110c includes forming a patterned mask layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) on the upper surface of the third ILD layer 1110c. A patterned mask layer can be formed by forming a mask layer (not shown) (e.g., via spin coating) on ​​the upper surface of the third ILD layer 1110c, exposing the mask layer to a pattern (e.g., via a photolithography process, such as photolithography, extreme ultraviolet lithography, etc.) and developing the mask layer to form a patterned mask layer. Subsequently, with the patterned mask layer in place, an etching process is performed on the third ILD layer 1110c to selectively etch the third ILD layer 1110c according to the patterned mask layer. The etching process removes the unmasked portion of the third ILD layer 1110c to form an opening 2002. In some embodiments, the etching process may be, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, certain other etching processes, or a combination of the foregoing.

[0129] like Figure 21 As shown in cross-sectional view 2100, the bottom electrode layer 2102 is deposited on the third ILD layer 1110c and lined with opening 2002. In some embodiments, the bottom electrode layer 2102 is deposited by, for example, ALD, CVD, PVD, electrochemical plating, electroless plating, sputtering, certain other deposition processes, or combinations thereof. The bottom electrode layer 2102 is conductive and may be, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), some other conductive material, or combinations thereof.

[0130] like Figure 22 As shown in cross-sectional view 2200, a first interface layer 2202 is formed on the bottom electrode layer 2102. The first interface layer 2202 includes metallic elements (e.g., titanium (Ti), tantalum (Ta), etc.) and non-metallic elements (e.g., nitrogen (N), oxygen (O), etc.). The bottom electrode layer 2102 includes the metallic elements of the first interface layer 2202. In some embodiments, the first interface layer 2202 includes metallic elements, non-metallic elements, and oxygen (O). For example, the bottom electrode layer 2102 is or includes titanium nitride (TiN), and the first interface layer 2202 is or includes titanium oxynitride (TiON).

[0131] The first interface layer 2202 can be formed by an oxidation process. For example, in some embodiments, the bottom electrode layer 2102 is formed in a processing chamber. After the bottom electrode layer 2102 is formed, it can be exposed to air (e.g., by removing the bottom electrode layer 2102 and the structure below it from the processing chamber). By exposing the bottom electrode layer 2102 to air, it is oxidized, thereby causing the first interface layer 2202 to grow from the top surface of the bottom electrode layer 2102. In some embodiments, after the first interface layer 2202 is formed on the bottom electrode layer 2102 by an oxidation process, one or more plasma processing processes can be performed on the first interface layer 2202. In other embodiments, the first interface layer 2202 can be formed by a deposition process, such as CVD, PVD, ALD, certain other deposition processes, or a combination of the foregoing.

[0132] like Figure 23 As shown in cross-sectional view 2300, a first plurality of dielectric layers 2302 and a second plurality of dielectric layers 2304 are formed over a first interface layer 2202 and a bottom electrode layer 2102. In some embodiments, the first interface layer 2202 is omitted. The first plurality of dielectric layers 2302 and the second plurality of dielectric layers 2304 are formed to be stacked perpendicularly to each other. Each of the first plurality of dielectric layers 2302 is formed to be separate from one of the second plurality of dielectric layers 2304, and vice versa. For example, a first dielectric layer 2302a is formed on the first interface layer 2202, a second dielectric layer 2304a is formed on the first dielectric layer 2302a, a third dielectric layer 2302b is formed on the second dielectric layer 2304a, a fourth dielectric layer 2304b is formed on the third dielectric layer 2302b, and a fifth dielectric layer 2302c is formed on the fourth dielectric layer 2304b. In some embodiments, the first plurality of dielectric layers 2302 and the second plurality of dielectric layers 2304 are referred to as a dielectric layer stack. It should be understood that in some embodiments, a third plurality of dielectric layers (see, for example...) Figure 10 It can also be formed above the first interface layer 2202.

[0133] The first plurality of dielectric layers 2302 may be, for example, or include zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), silicon oxide (SiO2), another dielectric material, or any combination thereof. In some embodiments, the first plurality of dielectric layers 2302 are or include metal oxides (e.g., ZrO2, Al2O3, HfO2, Ta2O5, etc.) and / or include high-k dielectrics. The second plurality of dielectric layers 2304 may be, for example, or include zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), silicon oxide (SiO2), another dielectric material, or any combination thereof. In some embodiments, the second plurality of dielectric layers 2304 are or include metal oxides (e.g., ZrO2, Al2O3, HfO2, Ta2O5, etc.) and / or include high-k dielectrics. In some embodiments, the second plurality of dielectric layers 2304 are amorphous solids.

[0134] In some embodiments, the first plurality of dielectric layers 2302 include one or more crystals (e.g., Figure 5 (502). In some embodiments, the first plurality of dielectric layers 2302 comprises one or more crystals, while the second plurality of dielectric layers 2304 is an amorphous solid. In some embodiments, the crystal lattices of one or more crystals of the first plurality of dielectric layers 2302 are identical. For example, one or more crystals of the first dielectric layer 2302a may comprise monoclinic, cubic, and tetragonal crystals in substantially the same percentage as those of the third dielectric layer 2302b and the fifth dielectric layer 2302c.

[0135] In other embodiments, one or more crystals in the first dielectric layer 2302a and the fifth dielectric layer 2302c have substantially the same crystal lattice, while one or more crystals in the third dielectric layer 2302b have a different crystal lattice. For example, the first dielectric layer 2302a and the fifth dielectric layer 2302c have substantially similar percentages of monoclinic, cubic, and / or tetragonal crystals, while the third dielectric structure 2302b has a different percentage of monoclinic, cubic, and / or tetragonal crystals. More specifically, in some embodiments, the third dielectric layer 2302b has a lower percentage of tetragonal crystals than both the first dielectric layer 2302a and / or the fifth dielectric layer 2302c. For example, one or more crystals of the third dielectric layer 2302b are less than or equal to about 20 wt% monoclinic crystal, less than or equal to about 20 wt% cubic crystal, and between about 40 wt% and 80 wt% tetragonal crystal, and one or more crystals of both the first dielectric layer 2302a and the fifth dielectric layer 2302c are greater than 80 wt% tetragonal crystal.

[0136] In some embodiments, the first dielectric layer 2302a and the fifth dielectric layer 2302c are formed to have a first thickness (e.g., Figure 9 402). In other embodiments, the second dielectric layer 2304a and the fourth dielectric layer 2304b are formed to have a second thickness (e.g., Figure 9 404). In yet another embodiment, the third dielectric layer 2302b is formed to have a third thickness (e.g., ). Figure 9 (904). The first thickness can be between approximately 10 angstroms. With the agreement Between. The second thickness is less than the first thickness. The second thickness is greater than approximately The third thickness can be approximately... With the agreement In some embodiments, the third thickness is substantially the same as the first thickness. In other embodiments, the third thickness differs from the first thickness. For example, in some embodiments, the third thickness is less than the first thickness.

[0137] In some embodiments, the first plurality of dielectric layers 2302 and the second plurality of dielectric layers 2304 are formed by one or more deposition processes (e.g., CVD, PVD, ALD, etc.). For example, in some embodiments, the first plurality of dielectric layers 2302 and the second plurality of dielectric layers 2304 are formed in a processing chamber 2306 by an ALD process. The ALD process forms the first plurality of dielectric layers 2302 and the second plurality of dielectric layers 2304 in situ (e.g., without disrupting the vacuum of the processing chamber 2306). For example, by... Figure 22 The structure shown (and the components below it, see example) Figure 18 The material is loaded into processing chamber 2306 and then evacuated downwards into processing chamber 2306 (e.g., to create a vacuum in processing chamber 2306), whereby the ALD process forms a first plurality of dielectric layers 2302 and a second plurality of dielectric layers 2304 in situ. Subsequently, a first set of precursors for depositing the first plurality of dielectric layers 2302 and a second set of precursors for depositing the second plurality of dielectric layers 2304 are circulated into processing chamber 2306, thereby forming the first plurality of dielectric layers 2302 and the second plurality of dielectric layers 2304. It should be understood that in some embodiments, one or more purge / evacuation steps may be performed between the deposition of the first plurality of dielectric layers 2302 and the second plurality of dielectric layers 2304 (e.g., purging processing chamber 2306 between the formation of the first plurality of dielectric layers 2304 and the second plurality of dielectric layers 2302a, between the formation of the second plurality of dielectric layers 2304a and the third dielectric layer 2302b, and so on).

[0138] like Figure 24As shown in cross-sectional view 2400, a second interface layer 2402 is formed over a fifth dielectric layer 2302c. In some embodiments, the process for forming the second interface layer 2402 includes depositing the second interface layer 2402 on the fifth dielectric layer 2302c. The second interface layer 2402 can be deposited by, for example, CVD, PVD, ALD, sputtering, some other deposition process, or a combination of the foregoing.

[0139] Also in Figure 24 As shown in cross-sectional view 2400, a top electrode layer 2404 is formed over the second interface layer 2402 and the fifth dielectric layer 2302c. In some embodiments, the process for forming the top electrode layer 2404 includes depositing the top electrode layer 2404 on the second interface layer 2402. The top electrode layer 2404 can be deposited by, for example, CVD, PVD, ALD, electroplating, electroless plating, sputtering, certain other deposition processes, or combinations thereof. In some embodiments, the second interface layer 2402 is omitted. In such embodiments, the top electrode layer 2404 may be deposited on the fifth dielectric layer 2302c. In some embodiments, the second interface layer 2402 and / or the top electrode layer 2404 may be formed in a processing chamber 2306. In other embodiments, the second interface layer 2402 and / or the top electrode layer 2404 may also be formed in situ with the first plurality of dielectric layers 2302 and the second plurality of dielectric layers 2304. In other embodiments, the second interface layer 2402 and / or the top electrode layer 2404 may be formed in a different processing chamber than the processing chamber 2306.

[0140] The top electrode layer 2404 is conductive and may be, for example, or include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), some other conductive material, or a combination of the foregoing. The top electrode layer 2404 and the bottom electrode layer 2102 may be made of the same material. The second interface layer 2402 includes metallic elements (e.g., titanium (Ti), tantalum (Ta), etc.) and non-metallic elements (e.g., nitrogen (N), oxygen (O), etc.). The top electrode layer 2404 includes the metallic elements of the second interface layer 2402. In some embodiments, the second interface layer 2402 includes metallic elements, non-metallic elements, and oxygen (O). For example, the top electrode layer 2404 is or includes titanium nitride (TiN), and the second interface layer 2402 is or includes titanium oxynitride (TiON).

[0141] In some embodiments, the second interface layer 2402 and the first interface layer 2202 have the same electron affinity. In other embodiments, the bottom electrode layer 2102 and the top electrode layer 2404 have the same work function. In other embodiments, the second dielectric layer 2304a and the fourth dielectric layer 2304b have the same electron affinity. In other embodiments, the first dielectric layer 2302a and the fifth dielectric layer 2302c have the same electron affinity. In yet another embodiment, the first dielectric layer 2302a, the third dielectric layer 2302b, and the fifth dielectric layer 2302c have the same electron affinity. In other embodiments, the third dielectric layer 2302b has a different electron affinity than the first dielectric layer 2302a and / or the fifth dielectric layer 2302c.

[0142] like Figure 25 As shown in the cross-sectional view 2500, the top electrode layer 2404 (see example) Figure 24 ), second interface layer 2402 (see example) Figure 24 ), the first plurality of dielectric layers 2302 (see example) Figure 24 ), and a second plurality of dielectric layers 2304 (see example) Figure 24 ), First interface layer 2202 (see example) Figure 24 ) and bottom electrode layer 2102 (see example) Figure 24 Patterning is used to form a MIM capacitor 102 located above the lower capacitor wiring 1104l. In some embodiments, the MIM capacitor 102 includes a vertically stacked bottom electrode 106, a first capacitor interface layer 602, a capacitor insulator structure 104, a second capacitor interface layer 802, and a top electrode 108. The capacitor insulator structure 104 is symmetrical. In some embodiments, the capacitor insulator structure 104 includes a vertically stacked first dielectric structure 110a, a fifth dielectric structure 902a, a fourth dielectric structure 110c, a sixth dielectric structure 902b, and a second dielectric structure 110b.

[0143] In some embodiments, the patterning process for forming the MIM capacitor 102 includes forming a patterned mask layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) on the upper surface of the top electrode layer 2404. Then, with the patterned mask layer in place, an etching process is performed on the top electrode layer 2404, the second interface layer 2402, the first plurality of dielectric layers 2302, the second plurality of dielectric layers 2304, the first interface layer 2202, and the bottom electrode layer 2102 to selectively etch such layers according to the patterned mask layer. The etching process removes the unmasked portion of the top electrode layer 2404 to form the top electrode 108, removes the unmasked portion of the second interface layer 2402 to form the second capacitor interface layer 802, removes the unmasked portion of the second dielectric structure 110b to form the fifth dielectric layer 2302c, removes the unmasked portion of the fourth dielectric layer 2304b to form the sixth dielectric structure 902b, removes the unmasked portion of the third dielectric layer 2302b to form the fourth dielectric structure 110c, removes the unmasked portion of the second dielectric layer 2304a to form the fifth dielectric structure 902a, removes the unmasked portion of the first dielectric layer 2302a to form the first dielectric structure 110a, removes the unmasked portion of the first interface layer 2202 to form the first capacitor interface layer 602, and removes the unmasked portion of the bottom electrode layer 2102 to form the bottom electrode 106. In some embodiments, the etching process may be, for example, a wet etching process, a dry etching process, a RIE process, certain other etching processes, or a combination of the foregoing.

[0144] like Figure 26 As shown in cross-sectional view 2600, the interconnect structure 1102 is completed around the MIM capacitor 102. Upon completion, the interconnect structure 1102 includes a fourth ILD layer 1110d located above the MIM capacitor 102, and also includes a passivation layer 1606 located above the fourth ILD layer 1110d. Furthermore, the interconnect structure 1102 includes multiple additional conductors 1104 and multiple additional vias 1108 in the fourth ILD layer 1110d and the passivation layer 1606. The multiple additional conductors 1104 include upper capacitor wiring 1104u, and the multiple additional vias 1108 include TEVA 1108tv extending from the upper capacitor wiring 1104u to the top electrode 108.

[0145] Figure 27 Flowchart 2700 illustrates some embodiments of a method for forming an IC including a MIM capacitor having a symmetrical capacitor insulator structure. Although herein... Figure 27Flowchart 2700 illustrates and describes a series of steps or events, but it should be understood that the order in which such steps or events are shown should not be interpreted in a limiting sense. For example, some operations may occur in a different order and / or simultaneously with other operations or events, in addition to some operations shown and / or described herein. Furthermore, not all operations shown are required to implement one or more aspects or embodiments described herein, and one or more operations described herein may be performed in one or more separate operations and / or phases.

[0146] At step 2702, a first interlayer dielectric (ILD) layer is formed on the second ILD layer and the lower capacitor wiring, wherein the second ILD layer and the lower capacitor wiring are arranged above the substrate. Figures 18 to 19 A series of cross-sectional views 1800 to 1900 are shown corresponding to some embodiments of step 2702.

[0147] At step 2704, an opening is formed in the first ILD layer to expose the lower capacitor wiring. Figure 20 Cross-sectional view 2000 is shown, corresponding to some embodiments of step 2704.

[0148] At step 2706, a bottom electrode layer is formed above the first ILD layer, and the bottom electrode layer has an inner liner opening. Figure 21 Cross-sectional view 2100 is shown, corresponding to some embodiments of step 2706.

[0149] At step 2708, a dielectric layer stack is formed above the bottom electrode layer, wherein the lower half of the dielectric layer stack is a mirror image of the upper half of the dielectric layer stack in terms of material and / or material thickness. Figures 22 to 23 A series of cross-sectional views 2200 to 2300 are shown corresponding to some embodiments of step 2708.

[0150] At step 2710, a top electrode layer is formed over the dielectric layer stack. Figure 24 Cross-sectional view 2400 is shown, corresponding to some embodiments of step 2710.

[0151] At step 2712, the top electrode layer, dielectric layer stack, and bottom electrode layer are patterned into a metal-insulator-metal (MIM) capacitor. Figure 25 Cross-sectional view 2500 is shown, corresponding to some embodiments of step 2712.

[0152] In some embodiments, the present invention provides a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a bottom electrode disposed above a semiconductor substrate. A top electrode is located above the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure includes a first plurality of dielectric structures, the first plurality of dielectric structures including a first dielectric material. The capacitor insulator structure includes a second plurality of dielectric structures, the second plurality of dielectric structures including a second dielectric material different from the first dielectric material. The capacitor insulator structure alternates periodically between the first dielectric material and the second dielectric material from the bottom electrode to the top electrode. The first plurality of dielectric structures includes a first dielectric structure, a second dielectric structure, and a third dielectric structure. A second dielectric structure is disposed between the first dielectric structure and the third dielectric structure. The second dielectric structure has a lower weight percentage (wt%) of tetragonal crystal than the first dielectric structure and the third dielectric structure.

[0153] In some embodiments, the first dielectric structure is arranged closer to the bottom electrode than any other dielectric structure in the first plurality of dielectric structures, and closer to the bottom electrode than any of the second plurality of dielectric structures; and the third dielectric structure is arranged closer to the top electrode than any other dielectric structure in the first plurality of dielectric structures, and closer to the top electrode than any of the second plurality of dielectric structures. In some embodiments, the first dielectric material has a greater electron affinity than the second dielectric material. In some embodiments, the second dielectric structure has 40 wt% to 80 wt% tetragonal crystal, less than or equal to 20 wt% monoclinic crystal, and less than or equal to 20 wt% cubic crystal. In some embodiments, the first dielectric material comprises zirconium oxide; and the second dielectric material comprises aluminum oxide. In some embodiments, each of the first plurality of dielectric structures has a first thickness greater than or equal to about 6 angstroms; and each of the second plurality of dielectric structures has a second thickness greater than or equal to about 6 angstroms. In some embodiments, the first thickness is greater than the second thickness. In some embodiments, each of the first dielectric structure and the third dielectric structure has a first thickness. The second dielectric structure has a second thickness; and the second thickness is less than the first thickness. In some embodiments, each of the second plurality of dielectric structures has a third thickness less than the second thickness. In some embodiments, the second dielectric structure has 40 wt% to 80 wt% tetragonal crystal, less than or equal to 20 wt% monoclinic crystal, and less than or equal to 20 wt% cubic crystal. In some embodiments, the second plurality of dielectric structures are amorphous solids. In some embodiments, the first thickness is between 21 angstroms and 35 angstroms; the second thickness is between 10 angstroms and 20 angstroms; and the third thickness is greater than 6 angstroms. In some embodiments, the bottom electrode comprises metallic and non-metallic elements; the metal-insulator-metal capacitor includes a first capacitor interface layer disposed between the capacitor insulator structure and the bottom electrode and in direct contact with the capacitor insulator structure and the bottom electrode; and the first capacitor interface layer comprises metallic, non-metallic, and oxygen. In some embodiments, the top electrode includes the metal element and the non-metal element; the metal-insulator-metal capacitor includes a second capacitor interface layer, the first capacitor interface layer is disposed between the capacitor insulator structure and the top electrode and is in direct contact with the capacitor insulator structure and the top electrode; and the second capacitor interface layer includes the metal element, the non-metal element and oxygen.

[0154] In some embodiments, the present invention provides another metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a lower electrode disposed above a semiconductor substrate. An upper electrode is located above the lower electrode. A capacitor insulator structure is disposed between the lower electrode and the upper electrode. The capacitor insulator structure includes a dielectric structure stack comprising at least five individual dielectric structures stacked perpendicularly to each other. Each individual dielectric structure includes: a first individual dielectric structure comprising a first dielectric material; and a second individual dielectric structure comprising the first dielectric material. The first individual dielectric structure is the uppermost individual dielectric structure in the dielectric structure stack. The second individual dielectric structure is the lowermost individual dielectric structure in the dielectric structure stack. A single dielectric structure disposed between the first individual dielectric structure and the second individual dielectric structure includes a first dielectric material, a second dielectric material, or a third dielectric material. The second dielectric material is different from the first dielectric material. The third dielectric material is different from both the first and second dielectric materials. The single dielectric structure arranged between the first single dielectric structure and the second single dielectric structure alternates periodically between the second single dielectric structure and the first single dielectric structure between the first, second and third dielectric materials.

[0155] In some embodiments, the total number of individual dielectric structures comprising the first dielectric material is X; the total number of individual dielectric structures constituting the second dielectric material is Y; the total number of individual dielectric structures constituting the third dielectric material is Z; Y equals Z; and Y equals X minus 1. In some embodiments, individual dielectric structures comprising the first dielectric material are perpendicularly separated from each other by at least one of the individual dielectric structures comprising the second dielectric material and at least one of the individual dielectric structures comprising the third dielectric material; and individual dielectric structures comprising the third dielectric material are perpendicularly separated from each other by at least one of the individual dielectric structures comprising the first dielectric material. In some embodiments, the upper electrode and the lower electrode are titanium nitride; and the work function of the upper electrode is substantially the same as the work function of the lower electrode. In some embodiments, the metal-insulator-metal capacitor includes a first capacitor interface layer disposed between the capacitor insulator structure and the lower electrode and in direct contact with the capacitor insulator structure and the lower electrode; and the metal-insulator-metal capacitor includes a second capacitor interface layer disposed between the capacitor insulator structure and the upper electrode and in direct contact with the capacitor insulator structure and the upper electrode; and the first capacitor interface layer and the second capacitor interface layer are titanium oxynitride; and the electron affinity of the first capacitor interface layer is substantially the same as the electron affinity of the second capacitor interface layer.

[0156] In some embodiments, the present invention provides a method for forming a metal-insulator-metal (MIM) capacitor. The method includes forming a bottom electrode layer over a semiconductor substrate. The method includes forming a first dielectric layer comprising a first dielectric material over the bottom electrode layer, wherein the first dielectric layer is formed with a first weight percentage (wt%) of tetragonal crystal. A second dielectric layer comprising a second dielectric material different from the first dielectric material is formed over the first dielectric layer, wherein the second dielectric layer is formed as an amorphous solid. A third dielectric layer comprising the first dielectric material is formed over the second dielectric layer, wherein the third dielectric layer is formed with a second wt% of tetragonal crystal. A fourth dielectric layer comprising the second dielectric material is formed over the third dielectric layer, wherein the fourth dielectric layer is formed as an amorphous solid. A fifth dielectric layer comprising the first dielectric material is formed over the fourth dielectric layer, wherein the fifth dielectric layer is formed with a third wt% of tetragonal crystal, wherein the second wt% of tetragonal crystal is less than the first wt% of tetragonal crystal and the third wt% of tetragonal crystal. A top electrode layer is formed over the fifth dielectric layer. The top electrode layer, the fifth dielectric layer, the fourth dielectric layer, the third dielectric layer, the second dielectric layer, the first dielectric layer, and the bottom electrode layer are patterned to form the MIM capacitor.

[0157] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A metal-insulator-metal capacitor, comprising: The bottom electrode is positioned above the semiconductor substrate; The top electrode is located above the bottom electrode; as well as A capacitor insulator structure is arranged between the bottom electrode and the top electrode and has an axis of symmetry, wherein: The capacitor insulator structure includes a first plurality of dielectric structures, and the first plurality of dielectric structures include a first dielectric material; The capacitor insulator structure includes a second plurality of dielectric structures, the second plurality of dielectric structures including a second dielectric material different from the first dielectric material; The capacitor insulator structure includes a third plurality of dielectric structures, the third plurality of dielectric structures including a third dielectric material different from the first dielectric material and the second dielectric material, each of the first plurality of dielectric structures being separated from each other by at least one of the third plurality of dielectric structures and one of the second plurality of dielectric structures, and the second plurality of dielectric structures being an amorphous solid; The capacitor insulator structure alternates periodically between the first dielectric material, the second dielectric material, and the third dielectric material in a symmetrical manner on both sides of the axis of symmetry from the bottom electrode to the top electrode, and the dielectric structure including the first dielectric material is disposed on the axis of symmetry; The first plurality of dielectric structures includes a first dielectric structure, a second dielectric structure, and a third dielectric structure; The second dielectric structure is disposed between the first dielectric structure and the third dielectric structure; and The second dielectric structure has a lower weight percentage (wt%) of tetragonal crystal than the first and third dielectric structures. Each of the first plurality of dielectric structures has a first thickness, each of the second plurality of dielectric structures has a second thickness, and each of the third plurality of dielectric structures has a third thickness, the third thickness being less than the first thickness and the same as the second thickness, and the second thickness being greater than 5 Å.

2. The metal-insulator-metal capacitor according to claim 1, wherein: The first dielectric structure is arranged closer to the bottom electrode than any other dielectric structure in the first plurality of dielectric structures, and closer to the bottom electrode than any of the second plurality of dielectric structures; as well as The third dielectric structure is arranged closer to the top electrode than any other dielectric structure in the first plurality of dielectric structures, and closer to the top electrode than any of the second plurality of dielectric structures.

3. The metal-insulator-metal capacitor of claim 2, wherein, The first dielectric material has a greater electron affinity than the second dielectric material.

4. The metal-insulator-metal capacitor according to claim 1, wherein: The bottom electrode comprises titanium (Ti).

5. The metal-insulator-metal capacitor according to claim 4, wherein: The first dielectric material includes zirconium oxide; and The second dielectric material includes aluminum oxide.

6. The metal-insulator-metal capacitor according to claim 1, wherein: The first thickness is greater than or equal to 6 angstroms; as well as The second thickness is greater than or equal to 6 angstroms.

7. The metal-insulator-metal capacitor of claim 1, wherein, The top electrode comprises titanium (Ti).

8. The metal-insulator-metal capacitor of claim 1, wherein: The first dielectric material includes zirconium oxide.

9. The metal-insulator-metal capacitor of claim 1, wherein, The top electrode and the bottom electrode have the same work function.

10. The metal-insulator-metal capacitor according to claim 1, wherein: The top electrode is electrically coupled to the first terminal of the metal-insulator-metal capacitor.

11. The metal-insulator-metal capacitor of claim 1, wherein, The bottom electrode is electrically coupled to the second terminal of the metal-insulator-metal capacitor.

12. The metal-insulator-metal capacitor of claim 11, wherein: The second dielectric material includes aluminum oxide.

13. The metal-insulator-metal capacitor according to claim 1, wherein: The bottom electrode comprises metallic and non-metallic elements; The metal-insulator-metal capacitor includes a first capacitor interface layer, which is disposed between the capacitor insulator structure and the bottom electrode and is in direct contact with the capacitor insulator structure and the bottom electrode. as well as The first capacitor interface layer comprises metallic elements, non-metallic elements, and oxygen.

14. The metal-insulator-metal capacitor according to claim 13, wherein: The top electrode comprises metallic and non-metallic elements; The metal-insulator-metal capacitor includes a second capacitor interface layer, which is disposed between the capacitor insulator structure and the top electrode and is in direct contact with the capacitor insulator structure and the top electrode. as well as The second capacitor interface layer comprises metallic elements, non-metallic elements, and oxygen.

15. A metal-insulator-metal capacitor, comprising: The lower electrode is positioned above the semiconductor substrate; The upper electrode is located above the lower electrode; as well as A capacitor insulator structure is arranged between the lower electrode and the upper electrode and has an axis of symmetry, wherein: The capacitor insulator structure includes a dielectric structure stack, which comprises at least five individual dielectric structures stacked perpendicularly to each other. The single dielectric structure includes: a first single dielectric structure comprising a first dielectric material; and a second single dielectric structure comprising the first dielectric material; The first single dielectric structure is the uppermost single dielectric structure in the dielectric structure stack; The second single dielectric structure is the lowest single dielectric structure in the dielectric structure stack; The single dielectric structure disposed between the first single dielectric structure and the second single dielectric structure includes a first dielectric material, a second dielectric material, or a third dielectric material; The second dielectric material is different from the first dielectric material; The third dielectric material is different from the first dielectric material and the second dielectric material; and A single dielectric structure arranged between the first and second single dielectric structures periodically alternates between the first, second, and third dielectric materials in a symmetrical manner on both sides of the axis of symmetry. The dielectric structure comprising the first dielectric material is disposed on the axis of symmetry. Each dielectric structure comprising the first dielectric material has a first thickness, each dielectric structure comprising the second dielectric material has a second thickness, and each dielectric structure comprising the third dielectric material has a third thickness, the third thickness being less than the first thickness and the same as the second thickness, wherein the second thickness is greater than 5 Å. The second dielectric material has a tetragonal crystal with a lower weight percentage (wt%) than the first dielectric material and the third dielectric material.

16. The metal-insulator-metal capacitor according to claim 15, wherein: The total number of individual dielectric structures, including the first dielectric material, is X; The total number of individual dielectric structures, including the second dielectric material, is Y; The total number of individual dielectric structures, including the third dielectric material, is Z; Y equals Z; and Y equals X minus 1.

17. The metal-insulator-metal capacitor according to claim 16, wherein: A single dielectric structure comprising the first dielectric material is perpendicularly separated from each other by at least one of a single dielectric structure comprising the second dielectric material and at least one of a single dielectric structure comprising the third dielectric material; A single dielectric structure comprising the second dielectric material is perpendicularly separated from each other by at least one of a single dielectric structure comprising the first dielectric material and at least one of a single dielectric structure comprising the third dielectric material; and A single dielectric structure containing the third dielectric material is perpendicularly separated from each other by at least one of a single dielectric structure containing the first dielectric material.

18. The metal-insulator-metal capacitor according to claim 16, wherein: The upper electrode and the lower electrode are titanium nitride; and The work function of the upper electrode is the same as that of the lower electrode.

19. The metal-insulator-metal capacitor according to claim 18, wherein: The metal-insulator-metal capacitor includes a first capacitor interface layer, which is disposed between the capacitor insulator structure and the lower electrode and is in direct contact with the capacitor insulator structure and the lower electrode. as well as The metal-insulator-metal capacitor includes a second capacitor interface layer, which is disposed between the capacitor insulator structure and the upper electrode and is in direct contact with the capacitor insulator structure and the upper electrode. as well as The first capacitor interface layer and the second capacitor interface layer are titanium oxynitride; as well as The electron affinity of the first capacitor interface layer is the same as that of the second capacitor interface layer.

20. A method for forming a metal-insulator-metal capacitor, the method comprising: A bottom electrode layer is formed above the semiconductor substrate; A first dielectric layer comprising a first dielectric material is formed above the bottom electrode layer, wherein the first dielectric layer is formed with a first weight percentage (wt%) of tetragonal crystal; A second dielectric layer comprising a second dielectric material different from the first dielectric material is formed above the first dielectric layer, wherein the second dielectric layer is formed as an amorphous solid; A sixth dielectric layer comprising a third dielectric material is formed above the second dielectric layer, wherein the sixth dielectric layer is formed as an amorphous solid; A third dielectric layer comprising the first dielectric material is formed above the sixth dielectric layer, wherein the third dielectric layer is formed with a second weight percentage of tetragonal crystal. A seventh dielectric layer comprising the third dielectric material is formed above the third dielectric layer, wherein the seventh dielectric layer is formed as an amorphous solid; A fourth dielectric layer comprising the second dielectric material is formed above the third dielectric layer, wherein the fourth dielectric layer is formed as an amorphous solid; A fifth dielectric layer comprising the first dielectric material is formed above the fourth dielectric layer, wherein the fifth dielectric layer is formed with a third weight percentage of tetragonal crystal, wherein the second weight percentage of tetragonal crystal is less than the first weight percentage of tetragonal crystal and the third weight percentage of tetragonal crystal. A top electrode layer is formed above the fifth dielectric layer; and The top electrode layer, the fifth dielectric layer, the fourth dielectric layer, the seventh dielectric layer, the third dielectric layer, the sixth dielectric layer, the second dielectric layer, the first dielectric layer, and the bottom electrode layer are patterned to form the metal-insulator-metal capacitor. Each of the first dielectric layer, the third dielectric layer, and the fifth dielectric layer has a first thickness, each of the second dielectric layer and the fourth dielectric layer has a second thickness, and each of the sixth dielectric layer and the seventh dielectric layer has a third thickness, the third thickness being less than the first thickness and the same as the second thickness, and the second thickness being greater than 5 Å.

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