Contact structure and method of forming the same

Abstract

A semiconductor device includes a first die including a first stack in a first region on a backside of the first die and a second stack in a second region on the backside of the first die. The first stack has fewer distinct layers than the second stack. A contact structure is formed in the first region on the backside of the first die. The contact structure extends through the first stack and is configured to electrically connect a first conductive structure on a frontside of the first die with a second conductive structure on the backside of the first die. The frontside is opposite the backside.

Description

Technical Field

[0001] This application describes embodiments relating generally to semiconductor devices and processes for manufacturing semiconductor devices. Background Technology

[0002] Memory devices typically include an array of memory cells and peripheral circuitry. In some examples, the memory cell array may be formed on a first die, referred to as the array die, and the peripheral circuitry may be formed on a second die, referred to as the peripheral die. The array die and the peripheral die can be bonded to connect the peripheral circuitry to the memory cell array. Summary of the Invention

[0003] This disclosure provides a semiconductor device with a contact structure and a method for forming the same.

[0004] According to a first aspect, a semiconductor device is provided. The semiconductor device includes a first die. The first die includes a first stack in a first region on the back side of the first die and a second stack in a second region on the back side of the first die. The first stack has fewer distinct layers than the second stack. A contact structure is formed in the first region on the back side of the first die. The contact structure extends through the first stack and is configured to electrically connect a first conductive structure on the front side of the first die to a second conductive structure on the back side of the first die. The front and back sides are opposite each other.

[0005] In some embodiments, the first stack comprises, in sequence, a first layer, a replacement layer, and a first insulating layer. The second stack comprises, in sequence, a first layer, a second layer, a conductive layer, a replacement layer, and a first insulating layer.

[0006] In some embodiments, the first layer and the replacement layer have equivalent etching properties. The second layer and the first layer have different etching properties. The conductive layer and the second layer have different etching properties. In some embodiments, the first layer and the replacement layer comprise the same conductive material. In some embodiments, the first layer comprises doped silicon, and the replacement layer comprises doped silicon.

[0007] In some embodiments, the contact structure includes a conductive portion and a sidewall portion. The conductive portion is configured to be conductively connected to a first conductive structure. The sidewall portion is configured to insulate the conductive portion from the first stack.

[0008] In some embodiments, the conductive portion comprises at least one of tungsten or aluminum. In some embodiments, the sidewall portion comprises at least one of silicon oxide, silicon nitride, zirconium oxide, hafnium oxide, aluminum oxide, or tantalum oxide.

[0009] In some embodiments, the semiconductor device further includes a memory cell on the front side of a first die and a second die bonded face-to-face with the first die. The second die includes a substrate and peripheral circuitry for the memory cell formed on the front side of the substrate. In some embodiments, the memory cell includes a third stack of alternating gate layers and second insulating layers on the front side of the first die and a plurality of channel structures extending through the third stack.

[0010] In some embodiments, the semiconductor device further includes a second die bonded face-to-face with the first die. The second die includes memory cells formed on the front side of the second die. Peripheral circuitry is formed on the front side of the first die for use with the memory cells.

[0011] According to a second aspect of this disclosure, a method for manufacturing a semiconductor device is provided. The method includes replacing a plurality of layers in a stack formed on the back side of a first die with a replacement layer in a first region and from the back side of the first die. A buffer layer is formed on the back side above the replacement layer. A contact hole is formed in the first region by etching the buffer layer and the replacement layer. The contact hole exposes a first conductive structure formed on the front side of the first die. The front side is opposite to the back side.

[0012] In some embodiments, replacing multiple layers in a stack formed on the back side of the first die with a replacement layer further includes forming a groove in the stack in a first region, wherein a first etch stop layer is the bottom of the groove. A replacement layer is deposited, filling the groove in the stack and covering the stack from the back side of the first die.

[0013] In some embodiments, multiple layers in the stack are replaced with replacement layers having etch properties equivalent to the first etch stop layer in the stack. In some embodiments, the replacement layer and the first etch stop layer have the same material.

[0014] In some embodiments, an insulating portion of the contact structure is formed on the sidewall of the contact hole. A conductive portion of the contact structure is formed, which fills the contact hole and is connected to the first conductive structure.

[0015] In some embodiments, the insulating portion forming the contact structure on the sidewall of the contact hole further includes depositing insulating material on the sidewall and bottom of the contact hole. The insulating material is then removed from the bottom of the contact hole.

[0016] In some embodiments, a second conductive structure is formed on the back side of the contact structure. The second conductive structure is electrically coupled to the first conductive structure via the contact structure.

[0017] In some embodiments, memory cells are formed on the front side of a first die. Peripheral circuitry for the memory cells is formed on the front side of a second die. The first die and the second die are bonded face-to-face.

[0018] According to a third aspect, a memory system is provided. The memory system includes a semiconductor device and a controller configured to control operation of the semiconductor device. The controller is connected to the semiconductor device. The semiconductor device includes a die including a contact structure disposed on a back side of the die. A first conductive structure is disposed on a front side of the die and connected to the contact structure from the front side of the die. The front side and the back side are opposite to each other. A second conductive structure is disposed on the back side of the die and connected to the contact structure from the back side of the die. The contact structure is configured to electrically connect the first conductive structure and the second conductive structure. Attached Figure Description

[0019] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings, and in accordance with the following specific description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In practice, the dimensions of the various features may be increased or decreased for clarity of discussion.

[0020] Figure 1 This is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0021] Figure 2A , 2B 2C, 2D, 2E and 2F are cross-sectional views of a semiconductor device at various intermediate manufacturing steps according to exemplary embodiments of the present disclosure.

[0022] Figure 3 This is a flowchart of a process for manufacturing an exemplary semiconductor device according to embodiments of the present disclosure.

[0023] Figure 4 A block diagram of a memory system apparatus according to some examples of this disclosure is shown. Detailed Implementation

[0024] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not, in itself, specify a relationship between the various embodiments and / or configurations discussed.

[0025] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “down,” “above,” and “above” are used herein to describe the relationship of one element or feature to another element or feature shown in the figure. Spatially related terms are intended to encompass different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptive terms used herein may be interpreted accordingly.

[0026] Semiconductor devices may include multiple dies bonded together. In some manufacturing techniques, the dies may be bonded at the wafer level before forming pad structures. For example, a first wafer including multiple first dies (e.g., an array die) and a second wafer including multiple second dies (peripheral dies) may be bonded face-to-face. The bonded wafers are then further processed, for example, to form a pad structure on the back side of one of the wafers for interfacing with external circuitry. In some examples, after forming the pad structure, the bonded wafers may be sawn into chips, and each chip may include two dies bonded together (e.g., an array die and a peripheral die), with the pad structure formed on the back side of one of the two dies.

[0027] When a pad structure is formed on the back side of one of the two dies, the pad structure can be connected to circuitry formed on the front side of the two dies via conductive structures. Some conductive structures are formed through processing steps performed on the front side of the die prior to bonding, and some conductive structures are formed through processing steps performed on the back side of one of the two dies.

[0028] According to some aspects of this disclosure, a contact structure can be formed from the back side of one of two dies. The contact structure extends through the layers on the back side of the die and is electrically connected to a conductive structure disposed on the front side of the die (e.g., the conductive structure is formed by a processing step operating on the front side of the die). In some examples, the layers are silicon layers, and the contact structure extending through the layers is referred to as a through-silicon contact (TSC) structure. In the following description, the TSC structure is used as an example to illustrate a technique for forming a contact structure, and the technique can be used to form contact structures extending through layers that do not include silicon layers.

[0029] It should be noted that, typically, circuitry such as memory cell arrays and peripheral circuitry is located on the front side of the die (also referred to as the front side in some examples), and the opposite side of the die is called the back side. The front and back sides are the opposite sides of the die.

[0030] For ease of description, the end of the TSC structure that connects to the pad structure on the back of the die is called the back side of the TSC structure, and the end of the TSC structure that connects to the conductive structure on the front side of the die is called the front side of the TSC structure. The TSC structure can therefore be used as a connection structure.

[0031] To form a TSH structure, in some examples, the TSH is typically formed by etching through a stack from the back side of the die before depositing conductive metal material into the through-silicon hole (TSH). The stack can include different materials with different etching properties (e.g., different etch rates, etch orientations, etc.). During the etching process that forms the TSH, the TSH may have uneven sidewalls due to the differences in etching properties, for example, at the interface of two materials with different etching properties.

[0032] In some examples, TSHs typically have high aspect ratios and may require relatively smooth sidewalls. Uneven sidewalls of the TSH can pose a problem for further processing. In some examples, the stack can have considerably different etch characteristics due to other processing requirements. In one example, the stack includes an insulating layer (first layer), a conductive layer (second layer), a second etch stop layer (third layer) for etching the conductive layer, a first etch stop layer (fourth layer) for etching the second etch stop layer, and so on. Typically, the etch stop layers are chosen to have relatively large differences in etch characteristics compared to the layers being etched. Therefore, the stack includes three interfaces with relatively large differences in etch characteristics. Specifically, the first and second layers have relatively large differences in etch characteristics, the second and third layers have relatively large differences in etch characteristics, and the third and fourth layers have large differences in etch characteristics. Forming a TSH with a smooth etch profile around the three interfaces on the sidewalls of the TSH is challenging due to the differences in the etch characteristics of the four different materials.

[0033] Various aspects of this disclosure provide techniques for reducing the number of different materials in a stack through which the TSC structure extends, and thus the TSC structure can be formed with a relatively smooth sidewall profile. In examples, the stack through which the TSC structure extends comprises two layers of different materials and involves an interface. Therefore, in some examples, the etching process for forming the TSH is simplified, and more importantly, a smooth etch profile of the TSH is more easily obtained.

[0034] Figure 1This is a cross-sectional view of a semiconductor device 100 according to an exemplary embodiment of the present disclosure. As shown, the semiconductor device 100 may include a first die (or wafer) D1. The first die D1 has a back side and a front side opposite to the back side. The first die D1 may include a first stack 101 in a first region 108 on the back side of the first die D1. The first die D1 may also include a second stack 102 in a second region 109 on the back side of the first die D1. In some examples, the second stack 102 is adjacent to the first stack 101, and the second stack 102 includes more layers with different material properties than the first stack 101. The first die D1 may also include at least one through-silicon contact (TSC) structure 120 formed in the first region 108 on the back side of the first die D1 and extending through the first stack 101. At least one TSC structure 120 is configured to electrically connect a first conductive structure 131 on the front side of the first die D1 to a second conductive structure 133 on the back side of the first die D1.

[0035] In some embodiments, the first stack 101 sequentially includes a first layer 111 (shown as 111a, also referred to as a first etch stop layer), a replacement layer 116 (shown as 116a), and a first insulating layer 117 (shown as 117a). The second stack 102 sequentially includes a first layer 111 (shown as 111b), a second layer 112 (also referred to as a second etch stop layer), a conductive layer 113, a replacement layer 116 (shown as 116b), and a first insulating layer 117 (shown as 117b). In some embodiments, the first layer 111 and the replacement layer 116 have equivalent (e.g., similar or identical) etch characteristics. The second layer 112 and the first layer 111 have different etch characteristics. The conductive layer 113 and the second layer 112 have different etch characteristics.

[0036] Still referencing Figure 1 The TSC structure 120 may include a conductive portion 121 and a sidewall portion 123 (also referred to as an insulating portion). The conductive portion 121 is configured to be electrically connected to a first conductive structure 131 on the front side and a second conductive structure 133 on the back side. As a result, the second conductive structure 133 may be electrically coupled to the first conductive structure 131 via the TSC structure 120. In one example, the second conductive structure 133 is configured as a pad output structure, and the conductive portion 121 includes a conductive metallic material, such as tungsten, aluminum, etc. Note that in some examples, the first conductive structure 131 may extend into the conductive portion 121 to increase the contact area between the first conductive structure 131 and the conductive portion 121.

[0037] The sidewall portion 123 of the TSC structure 120 is configured to isolate the conductive portion 121 from the first stack 101. In this example, the sidewall portion 123 is disposed between the conductive portion 121 and the first stack 101. The sidewall portion 123 can therefore be used to electrically isolate the conductive portion 121 from the first stack 101. Therefore, the sidewall portion 123 may include an insulating material such as silicon oxide, silicon nitride, zirconium oxide, hafnium oxide, aluminum oxide, tantalum oxide, etc.

[0038] like Figure 1 As shown, the TSC structure 120 extends through the first stack 101, including a first insulating layer 117, a replacement layer 116, and a first layer 111. In one embodiment, the replacement layer 116 and the first layer 111 comprise different materials and have an interface therebetween. Thus, the TSC structure 120 extends through three different materials and two interfaces. In another embodiment, the replacement layer 116 and the first layer 111 comprise the same conductive material without etch differences, thus avoiding uneven interfaces due to etching. Therefore, the TSC structure 120 extends through two different materials and one interface. For example, the same conductive material can be silicon (e.g., doped polycrystalline silicon, doped amorphous silicon, or doped nanocrystalline silicon) or a conductive metal material.

[0039] Furthermore, in some embodiments, the semiconductor device 100 may include a shielding structure 125 formed on the back side of the first die D1. The shielding structure 125 extends through at least one of the first stack 101 or the second stack 102. Figure 1 In the example, shielding structure 125 is arranged at the boundary of the first region 108 and the second region 109. As shown, shielding structure 125 may have a high aspect ratio. Specifically, in one example, TSC structure 120 is wider than shielding structure 125 in the XY plane. Furthermore, shielding structure 125 may include insulating material to electrically isolate the second stack 102. In one example, the sidewall portions 123 of shielding structure 125 and TSC structure 120 may include the same insulating material.

[0040] Still referencing Figure 1The semiconductor device 100 may further include memory cells formed on the front side of the first die D1. In some embodiments, the memory cells include 3D NAND memory cells. In a non-limiting example, a third stack 103 of alternating word line layers 141 (also referred to as gate layers) and a second insulating layer 143 is disposed on the front side of the first die D1. The third stack 103 may include an array region in which at least one channel structure 150 is formed and extends through the third stack 103. The alternating word line layers 141 and the second insulating layer 143 and the channel structure 150 may form a transistor stack, such as a vertical memory cell string. An array of alternating word line layers 141 and the second insulating layer 143 and the channel structure 150 may form an array of vertical memory cell strings. In some examples, the transistor stack may include memory cells and select transistors, such as one or more bottom select transistors, one or more top select transistors, etc. In some examples, the transistor stack may also include one or more dummy select transistors.

[0041] The second insulating layer 143 may include one or more insulating materials, such as silicon nitride, silicon oxide, etc. The word line layer 141 may include a gate stack of materials, such as a high-k gate insulator layer, a metal gate electrode, etc. The channel structure 150 may include a channel layer 153 (e.g., polysilicon) surrounded by one or more third insulating layers 155, such as a tunneling layer (e.g., silicon oxide), a charge trapping layer (e.g., silicon nitride), and a barrier layer (e.g., silicon oxide), which may together form an oxide-nitride-oxide (ONO) structure surrounding the channel layer 153. The channel structure 150 may also include a space 151 within the channel layer 153. The space 151 may be empty or filled with insulating material.

[0042] In one embodiment, the first layer 111 (shown by 111b) in the second region 109 is configured as a source interconnect layer that serves as a common source line or electrically connects the channel layer 153 to the source region of the semiconductor device 100. Therefore, a portion of one or more third insulating layers 155 is removed, such that the first layer 111 is in direct contact with the channel layer 153. This can be achieved, for example, by the SWS technique disclosed in the applicant's co-pending patent application 17 / 113,662, filed December 7, 2020, entitled "TWO-STEP L-SHAPED SELECTIVE EPITAXIAL GROWTH," the entire contents of which are incorporated herein by reference.

[0043] Furthermore, the third stack 103 may have a stepped region where a plurality of gate contact structures 145 are formed. The gate contact structures 145 are connected to the word line layer 141.

[0044] Still referencing Figure 1 The semiconductor device 100 may include a second die (or wafer) D2 bonded to the first die D1 via a bonding interface 180 in a face-to-face manner (circuit side is the front side, and substrate side is the back side). Therefore, the second die D2 also has a front side and a back side opposite the front side. The second die D2 includes a substrate 188 and peripheral circuitry (e.g., address decoder, driver circuitry, sense amplifier, etc.) for the memory cells formed on the front side of the substrate 188. Note that the first die D1 initially includes a substrate over which the memory cells are formed. In some examples, the substrate of the first die D1 is removed before the TSC structure 120 is formed.

[0045] The structure in the first die D1 can be electrically coupled to the structure in the second die D2 via the contact structure in the first die D1, the metal layers in the first die D1 (e.g., 171 and 172, shown as 171a, 171n, 172a, 172n, etc.), the bonding structure 181 at the bonding interface 180 (shown as 181a, 181n, etc.), the metal layer in the second die D2 (e.g., 191, shown as 191a, 191n, etc.), and the contact structure in the second die D2 (not shown). For example, the channel structure 150 can be electrically connected to the structure of the peripheral circuit in the second die D2 via the metal layers 171n and 172n, the bonding structure 181n, and the metal layer 191n. Similarly, the first conductive structure 131 may be electrically connected to another structure of the peripheral circuitry (e.g., input / output circuitry) in the second die D2 via metal layers 171a and 172a, bonding structure 181a, and metal layer 191a. Thus, in some examples, the second conductive structure 133 may be electrically connected to the input / output circuitry via TSC structure 120 and the first conductive structure 131.

[0046] exist Figure 1 In the example, the first die D1 includes a memory cell, and the second die D2 includes peripheral circuitry. Typically, the peripheral circuitry of the second die D2 enables the memory cell to interface with external circuitry. For example, the peripheral circuitry receives instructions from external circuitry via the second conductive structure 133, provides control signals to the memory cell, receives data from the memory cell, and outputs the data to external circuitry via the second conductive structure 133.

[0047] In some embodiments, the semiconductor device 100 may include a plurality of array dies (e.g., a first die D1) and CMOS dies (e.g., a second die D2). The plurality of array dies and CMOS dies may be stacked and bonded together. Each array die is coupled to a CMOS die, and the CMOS dies may drive the array dies individually or together in a similar manner. Furthermore, in some embodiments, the semiconductor device 100 includes at least a first wafer and a second wafer bonded face-to-face. The first die D1 is disposed on the first wafer along with other array dies such as D1, while the second die D2 is disposed on the second wafer along with other CMOS dies such as D2. The first wafer and the second wafer are bonded together such that the array dies on the first wafer are bonded to their corresponding CMOS dies on the second wafer.

[0048] In an alternative embodiment, the second die D2 may include a memory cell, and the first die D1 may include peripheral circuitry (not shown) for the memory cell. Similarly, the peripheral circuitry is coupled to the memory cell via contact structures in the first die, a bonding interface between the first and second dies, and contact structures in the second die. Specifically, the second conductive structure 133 may still be disposed on the back side of the first die D1 and coupled to the input / output circuitry of the peripheral circuitry via the first conductive structure 131.

[0049] Figure 2A , 2B 2C, 2D, 2E, and 2F are cross-sectional views of a semiconductor device 100' at various intermediate manufacturing steps according to exemplary embodiments of the present disclosure. In some embodiments, the semiconductor device 100' may ultimately become semiconductor device 100.

[0050] As shown in the figure Figure 2A The embodiment of the semiconductor device 100' is similar to Figure 1 An embodiment of the semiconductor device 100 is described above, and this document will focus on explaining the differences. For example, the semiconductor device 100' may include a fourth stack 104 formed on the back side of the first die D1. The fourth stack 104 includes a first etch stop layer 111, a second etch stop layer 112, and a conductive layer 113. A first conductive structure 131 may extend into the fourth stack 104 to a certain penetration depth. Specifically, in Figure 2A In the example, the first conductive structure 131 extends through the first etch stop layer 111 and the second etch stop layer 112 and extends into the conductive layer 113. Note that the penetration depth of the first conductive structure 131 is related to the future TSC structure (e.g., Figure 1 The contact area of ​​the TSC structure 120 in the example is related to the contact area, and therefore can be varied in other examples.

[0051] In some embodiments, a hard mask layer 114 may be formed on the back side of the fourth stack 104. A photoresist layer 115 may be formed on the back side of the hard mask layer 114. The photoresist layer 115 is patterned such that a portion of the hard mask layer 114 is exposed in the first region 108. In one example, the hard mask layer 114 comprises at least one of silicon oxide, silicon nitride, or carbon.

[0052] Figure 2B The diagram illustrates a semiconductor device 100' after a pattern has been transferred from a photoresist layer 115 to a hard mask layer 114. This pattern transfer can be achieved by etching the portion of the hard mask layer 114 exposed in a first region 108 using the photoresist layer 115 as an etch mask. The photoresist layer 115 is then removed. As a result, a portion of the conductive layer 113 is exposed in the first region 108.

[0053] Figure 2C The semiconductor device 100' after the portion of conductive layer 113 exposed in the first region 108 has been removed is shown. This can be achieved by etching a portion of conductive layer 113 using a hard mask layer 114 as an etch mask and using a second etch stop layer 112 to determine the endpoint of the etch. As a result, a portion of the second etch stop layer 112 is exposed in the first region 108, and a recess 107 is formed within the fourth stack 104. Figure 2C In the example, the first conductive structure 131 is also exposed from the back side. For example, regarding... Figure 2A As discussed, in other examples, the penetration depth of the first conductive structure 131 can vary. Therefore, in other examples, the first conductive structure 131 may be exposed or not.

[0054] exist Figure 2D In this process, a hard mask layer 114 is used as an etch mask to etch away the portion of the second etch stop layer 112 exposed in the first region 108, and the hard mask layer 114 is also removed. Note that the hard mask layer 114 can be etched simultaneously with or after etching a portion of the second etch stop layer 112. For example, the second etch stop layer 112 may comprise silicon oxide, silicon nitride, and / or similar materials. The hard mask layer 114 may comprise at least one of silicon oxide, silicon nitride, or carbon. In one embodiment, both the hard mask layer 114 and the second etch stop layer 112 are made of silicon oxide, such that portions of both the hard mask layer 114 and the second etch stop layer 112 can be etched in the same etch process. In another embodiment, the hard mask layer 114 comprises silicon oxide, and the second etch stop layer 112 comprises silicon nitride. In this example, a portion of the second etch stop layer 112 is etched before the hard mask layer 114 is etched.

[0055] Notice, Figure 2A-2DAn example of forming a groove 107 in a fourth stack 104 in the first region 108 is shown. It should be understood that other patterning and / or etching processes can be designed and performed to form the groove 107 in the first region 108.

[0056] exist Figure 2E In this process, a replacement layer 116 is formed from the back side of the first die D1. The replacement layer 116 fills the recess 107 and covers the fourth stack 104 from the back side of the first die D1. In this example, the replacement layer 116 can be planarized from the back side of the first die D1 by chemical mechanical polishing (CMP). In some embodiments, the replacement layer 116 comprises a conductive material. For example, the conductive material can be selected such that the replacement layer 116 and the first etch stop layer 111 have equivalent (e.g., similar or identical) etch properties. During a future etching process, a smooth etch profile can be obtained around the interface between the replacement layer 116 and the first etch stop layer 111. In some embodiments, the replacement layer 116 and the first etch stop layer 111 comprise the same conductive material and no interface is formed therebetween. For example, the replacement layer 116 and the first etch stop layer 111 may comprise a silicon material (e.g., doped polycrystalline silicon, doped amorphous silicon, or doped nanocrystalline silicon) or a conductive metal material.

[0057] Still referencing Figure 2E A first insulating layer 117 (also referred to as a buffer layer) is formed on the back side of the replacement layer 116. The first insulating layer 117 may include an insulating material, such as silicon oxide. The first insulating layer 117 can serve as a buffer layer and stabilize etching conditions during future etching processes.

[0058] exist Figure 2F In the first region 108, at least one through-silicon via (TSH) 126 (also referred to as a contact via) is formed. The at least one TSH 126 extends through the first insulating layer 117, replacement layer 116, and first etch stop layer 111 of the fourth stack 104. The TSH 126 exposes the first conductive structure 131 from the back side of the first die D1. In some embodiments, an opening 127 may also be formed in the first region 108. The TSH 126 and the opening 127 have a depth H. The TSH 126 has a width D1, and the opening 127 has a width D2. In some examples, D1 may be greater than D2. The TSH 126 and the opening 127 may be formed in the same patterning process using a photoresist layer 118 as a mask. Furthermore, the opening 127 may have a high aspect ratio in its cross-section in the xz plane. The opening 127 may be a trench extending in the y-direction.

[0059] Although not shown, in some embodiments, forms such as in TSH 126 may be formed. Figure 1The TSC structure 120 has a through-silicon contact (TSC) structure, and this TSC structure contacts the first conductive structure 131. In some embodiments, a sidewall portion 123 of the TSC structure 120 is formed on the sidewall 126' of the TSH 126, and a conductive portion 121 of the TSC structure 120 is formed to fill the TSH 126. For example, an insulating material can be deposited on the sidewall 126' and the bottom 126" of the TSH 126. Then, the insulating material is removed from the bottom 126" of the TSH 126, such that the insulating material on the sidewall 126' of the TSH 126 forms the sidewall portion 123 of the TSC structure 120. Note that the insulating material may also cover a portion of the first conductive structure 131 and then be removed. Subsequently, conductive material is deposited to fill the TSH 126 and form the conductive portion 121 of the TSC structure 120. The conductive material may overfill the TSH 126, and the overfilled portion of the conductive material can be removed using a CMP process.

[0060] Furthermore, in some embodiments, a shielding structure may be formed in the opening 127, such as Figure 1 The shielding structure 125 is described above. In one embodiment, the shielding structure 125 and the sidewall portion 123 of the TSC structure 120 comprise the same insulating material and are formed in the same deposition process (note that D1 may be greater than D2). In another embodiment, the shielding structure 125 and the sidewall portion 123 of the TSC structure 120 are formed in separate processes and may or may not include the same material.

[0061] Note that in Figure 2F In one example, opening 127 is formed in the first region 108, or more precisely, on the boundary between the first region 108 and the second region 109. In another example, opening 127 may be formed in the first region 108 but not on the boundary. In yet another example, opening 127 may be formed in the second region 109, on or off the boundary. Therefore, TSH 126 and opening 127 can be formed in separate etching processes.

[0062] Figure 3 It is an embodiment of the present disclosure for manufacturing such as Figure 1 A flowchart of the process 300 of an exemplary semiconductor device 100.

[0063] Process 300 begins at step S310, wherein multiple layers in a stack formed on the back side of the first die are replaced with replacement layers in a first region and from the back side of the first die. In some embodiments, in order to replace the multiple layers with replacement layers, grooves are formed in the first region of the stack (e.g., Figure 2A-2DThe first etch stop layer of the stack can be the bottom of the groove. Then, a replacement layer is deposited to fill the groove in the stack and cover the stack from the back side of the first die (e.g., Figure 2E ).

[0064] In some embodiments, the stack includes a first etch stop layer, a second etch stop layer, and a conductive layer. In some embodiments, forming the groove includes etching a portion of the conductive layer and a portion of the second etch stop layer from the back side of the first die based on a mask, such that the first etch stop layer is exposed. In some embodiments, the back side of the replacement layer may be planarized, for example, by CMP. In some embodiments, multiple layers in the stack are replaced with replacement layers having etch characteristics equivalent to (e.g., similar to or the same as) the first layer in the stack. In the example, the replacement layer and the first etch stop layer have the same material (e.g., doped silicon).

[0065] Then, process 300 proceeds to step S320: forming a buffer layer on the back side above the replacement layer (e.g., Figure 2E The buffer layer may include an insulating material. The buffer layer can be used as a buffer layer and to stabilize etching conditions during future etching processes.

[0066] In step S330, a contact hole is formed in the first region by etching a buffer layer and a replacement layer. The contact hole exposes a first conductive structure formed on the front side of the first die. The front side is opposite to the back side. For example, a TSH may be formed in the first region (e.g., Figure 2F ).

[0067] In some embodiments, a contact structure (e.g., a TSC structure) is formed in the contact hole. Specifically, an insulating portion (also referred to as a sidewall portion) of the contact structure is formed on the sidewall of the TSH, and a conductive portion of the contact structure is formed to fill the TSH and contact the first conductive structure.

[0068] In some embodiments, an insulating material is deposited on the sidewalls and bottom of the TSH. The insulating material is then removed from the bottom of the TSH, leaving the insulating material on the sidewalls of the TSH forming the sidewall portion of the TSC structure. Subsequently, a conductive material is deposited to fill the TSH and form the conductive portion of the TSC structure.

[0069] In some embodiments, a second conductive structure is formed on the back side of the TSC structure. The second conductive structure is electrically coupled to the first conductive structure via the TSC structure. The second conductive structure may, for example, be configured to include a pad output structure.

[0070] In some embodiments, a shielding structure is formed that extends through a buffer layer, a replacement layer, and a first etch stop layer. The shielding structure may include an insulating material.

[0071] In some embodiments, memory cells are formed on the front side of a first die. Peripheral circuitry for the memory cells is formed on the front side of a second die. In an example, the first die and the second die are bonded face-to-face such that a first bonding structure connected to a first conductive structure in the first die is bonded to a second bonding structure connected to an input / output circuitry of the peripheral circuitry in the second die.

[0072] Note that the semiconductor device 100 can be suitably used in a memory system.

[0073] Figure 4 Block diagrams of memory system device 400 according to some examples of this disclosure are shown. Memory system device 400 includes one or more semiconductor memory devices, such as semiconductor memory devices 411, 412, 413, and 414 shown, which are configured similarly to semiconductor device 100. In some examples, memory system device 400 is a solid-state drive (SSD).

[0074] The memory system device 400 may include other suitable components. For example, the memory system device 400 includes, for instance, components such as... Figure 4 The interface 401 and main controller 402 are shown coupled together. The memory system device 400 may include a bus 420 that couples the main controller 402 to semiconductor memory devices 411-414. Furthermore, the main controller 402 is connected to the semiconductor memory devices 411-414, for example, by corresponding control lines 421, 422, 423, and 424.

[0075] Interface 401 is appropriately mechanically and electrically configured to connect between memory system device 400 and host device, and can be used to transfer data between memory system device 400 and host device.

[0076] The main controller 402 is configured to connect the individual semiconductor memory devices 411-414 to the interface 401 for data transfer. For example, the main controller 402 is configured to provide enable / disable signals to the semiconductor memory devices 411-414 respectively to enable one or more semiconductor memory devices 411-414 for data transfer.

[0077] The main controller 402 is responsible for executing various instructions within the memory system device 400. For example, the main controller 402 can perform bad block management, error checking and correction, garbage collection, etc.

[0078] In some embodiments, a processor chip is used to implement the main controller 402. In some examples, multiple microcontroller units (MCUs) are used to implement the main controller 402.

[0079] As used herein, “device” or “semiconductor device” generally refers to any suitable device, such as a memory circuit, a semiconductor chip (or die) having memory circuitry formed on a semiconductor chip, a semiconductor wafer having a plurality of semiconductor dies formed on a semiconductor wafer, a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips assembled on a packaging substrate, and so on.

[0080] As used herein, “substrate” generally refers to an object processed according to the present invention. A substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a substrate structure such as a semiconductor wafer, an intermediate mask, or a layer such as a thin film on or covering a substrate structure. Therefore, a substrate is not limited to any particular basic structure, patterned or unpatterned lower or upper layer, but should be understood to include any such layer or basic structure and any combination of layers and / or basic structures. This specification may refer to specific types of substrates, but this is for illustrative purposes only.

[0081] The substrate can be any suitable substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. The substrate can include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI oxide semiconductors. Group IV semiconductors can include Si, Ge, or SiGe. The substrate can be a bulk wafer or an epitaxial layer.

[0082] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: A first die, the first die comprising: A first stack in a first region on the back side of the first die and a second stack in a second region on the back side of the first die, wherein the first stack has fewer distinct layers than the second stack; and A contact structure is formed in a first region on the back side of the first die, the contact structure extending through the first stack and configured to electrically connect a first conductive structure on the front side of the first die to a second conductive structure on the back side of the first die, the front side and the back side being opposite each other. Wherein, the first stack and the second stack include the same first layer on the back side of the first die, and the contact structure extends through the first layer of the first stack, and In the direction away from the back of the first die, the first stack sequentially includes the first layer, a layer having the same or different conductive material as the first layer, and a first insulating layer.

2. The semiconductor device according to claim 1, wherein: In the direction away from the back side of the first die, the second stack sequentially includes the first layer, the second layer, the conductive layer, the layer having the same or different conductive material as the first layer, and the first insulating layer.

3. The semiconductor device according to claim 2, wherein: The second layer and the first layer have different etching characteristics, and The conductive layer and the second layer have different etching characteristics.

4. The semiconductor device according to any one of claims 1-3, wherein: The first layer comprises doped silicon.

5. The semiconductor device according to claim 1, wherein: The contact structure includes a conductive portion and a sidewall portion. The conductive portion is configured to be conductively connected to the first conductive structure, and The sidewall portion is configured to isolate the conductive portion from the first stack.

6. The semiconductor device according to claim 5, wherein: The conductive portion includes at least one of tungsten or aluminum.

7. The semiconductor device according to claim 5, wherein: The sidewall portion includes at least one of silicon oxide, silicon nitride, zirconium oxide, hafnium oxide, aluminum oxide, or tantalum oxide.

8. The semiconductor device according to claim 1, further comprising: Memory cells on the front side of the first die; as well as A second die bonded face-to-face with the first die, the second die including a substrate and peripheral circuitry for the memory cell formed on the front side of the substrate.

9. The semiconductor device according to claim 8, wherein, The memory unit includes: A third stack of alternating gate layers and second insulating layers on the front side of the first die; and Multiple channel structures extending through the third stack.

10. The semiconductor device of claim 1, further comprising: A second die bonded face-to-face with the first die, the second die including a memory cell formed on the front side of the second die; as well as Peripheral circuitry for the memory cell is formed on the front side of the first die.

11. A method of manufacturing a semiconductor device, the method comprising: In a first region and from the back of the first die, a plurality of layers in the stack formed on the back of the first die are replaced with replacement layers, such that the number of layers in the stack in the first region is less than the number of layers in the stack in the second region on the back of the first die. A buffer layer is formed on the back side, above the replacement layer; as well as Contact holes are formed in the first region by etching the buffer layer and the replacement layer, the contact holes exposing a first conductive structure formed on the front side of the first die, the front side being opposite to the back side. Wherein, the stack in the first region and the stack in the second region include the same first layer on the back side of the first die, and In the direction away from the back of the first die, the stack in the first region sequentially includes the first layer, the replacement layer, and the buffer layer.

12. The method according to claim 11, wherein, Replacing the plurality of layers in the stack formed on the back side of the first die with the replacement layer further includes: A groove is formed in the first region within the stack, wherein a first etch stop layer, which is the first layer, is the bottom of the groove; and The replacement layer is deposited, which fills the grooves in the stack and covers the stack from the back side of the first die.

13. The method of claim 12, further comprising: The plurality of layers in the stack are replaced with the replacement layer having etch characteristics equivalent to the first etch stop layer in the stack.

14. The method of claim 13, wherein: The replacement layer and the first etch stop layer have the same material.

15. The method of claim 11, further comprising: An insulating portion of a contact structure is formed on the sidewall of the contact hole; as well as A conductive portion forms the contact structure, the conductive portion fills the contact hole and is connected to the first conductive structure.

16. The method according to claim 15, wherein, The insulating portion forming the contact structure on the sidewall of the contact hole further includes: An insulating material is deposited on the sidewalls and bottom of the contact hole; and Remove the insulating material from the bottom of the contact hole.

17. The method of claim 15, further comprising: A second conductive structure is formed on the back side of the contact structure, and the second conductive structure is electrically coupled to the first conductive structure via the contact structure.

18. The method of claim 11, further comprising: A memory cell is formed on the front side of the first die; Peripheral circuitry for the memory cell is formed on the front side of the second die; as well as The first die and the second die are bonded face to face.

19. A memory system comprising: The semiconductor device according to any one of claims 1-10; as well as A controller configured to control the operation of the semiconductor device, the controller being connected to the semiconductor device.

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