Three-dimensional memory devices and methods for forming the same

Abstract

Three-dimensional (3D) memory devices and methods of forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including alternating conductive layers and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer including a slab and a plug extending from the slab into the channel structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, and a portion of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. The doped portion of the semiconductor channel circumscribes the plug of the doped semiconductor layer.

Description

Background Technology

[0001] This disclosure relates to three-dimensional (3D) memory devices and methods for manufacturing the same.

[0002] Planar memory cells have been scaled down to smaller sizes through improvements in process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the memory density for planar memory cells is approaching its upper limit.

[0003] 3D memory architecture can address the density limitations of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention

[0004] In one aspect, a 3D memory device includes: a stacked layer structure comprising alternating conductive and dielectric layers; a channel structure extending through the stacked layer structure; and a doped semiconductor layer comprising a plate and a plug extending from the plate into the channel structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, and a portion of the doped portion of the semiconductor channel extends beyond the stacked layer structure in a first direction. The doped portion of the semiconductor channel is externally connected to the plug of the doped semiconductor layer.

[0005] In another aspect, a 3D memory device includes: a stacked layer structure comprising alternating conductive and dielectric layers; a doped semiconductor layer; and a channel structure extending through the stacked layer structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion. The channel structure extends beyond the stacked layer structure in a first direction and contacts the doped semiconductor layer. The semiconductor channel includes a doped portion that extends beyond one of the conductive layers in a second direction opposite to the first direction.

[0006] In another aspect, a method for forming a 3D memory device is provided. A fill layer is formed over a substrate. A stacked layer structure is formed over the fill layer. A channel structure is formed, extending through the stacked layer structure and the fill layer. The channel structure includes a memory film and a semiconductor channel. The substrate and portions of the channel structure extending beyond the fill layer are sequentially removed to expose portions of the semiconductor channel. A doped semiconductor layer is formed, contacting the exposed portions of the semiconductor channel. The doped semiconductor layer and portions of the semiconductor channel in contact with the doped semiconductor layer are locally activated.

[0007] In another aspect, a system includes a 3D memory device configured to store data and a memory controller coupled to and configured to control the 3D memory device. The 3D memory device includes: a stacked layer structure comprising alternating conductive and dielectric layers; a channel structure extending through the stacked layer structure; and a doped semiconductor layer comprising a plate and a plug extending from the plate into the channel structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, and a portion of the doped portion of the semiconductor channel extends beyond the stacked layer structure in a first direction. The doped portion of the semiconductor channel is externally coupled to the plug of the doped semiconductor layer. Attached Figure Description

[0008] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0009] Figure 1A A side view of a cross section of an exemplary 3D memory device according to some aspects of this disclosure is shown.

[0010] Figure 1B A side view of a cross section of another exemplary 3D memory device according to some aspects of this disclosure is shown.

[0011] Figure 2 Some aspects of this disclosure are shown. Figure 1A An enlarged side view of a cross-section of an exemplary channel structure in a 3D memory device.

[0012] Figures 3A-3O A manufacturing process for forming an exemplary 3D memory device is illustrated according to some aspects of this disclosure.

[0013] Figures 4A-4C A manufacturing process for forming another exemplary 3D memory device is shown according to some aspects of this disclosure.

[0014] Figure 5 A flowchart illustrating an exemplary method for forming a 3D memory device according to some aspects of this disclosure is shown.

[0015] Figure 6 A flowchart is shown of another exemplary method for forming a 3D memory device according to some aspects of this disclosure.

[0016] Figure 7 A block diagram of an exemplary system having a 3D memory device according to some aspects of this disclosure is shown.

[0017] Figure 8AAn illustration of an exemplary memory card having a 3D memory device according to some aspects of this disclosure is shown.

[0018] Figure 8B An illustration of an exemplary solid-state drive (SSD) with a 3D memory device is shown according to some aspects of this disclosure.

[0019] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0020] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other constructions and arrangements may be used without departing from the scope of this disclosure. Furthermore, it is apparent that this disclosure can also be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other, as well as in ways not specifically depicted in the drawings, such combinations, adjustments, and modifications are within the scope of this disclosure.

[0021] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a” or “described” can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0022] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with an intermediate feature or layer therebetween, and that “above” or “on top of” means not only “above” or “on top of” something, but also includes “above” or “on top of” something without an intermediate feature or layer therebetween (i.e., directly on) something.

[0023] Furthermore, spatial relative terms, such as “below,” “under,” “lower,” “above,” and “upper,” are used herein for ease of description to describe the relationship between one element or feature and another element (or features) as shown in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0024] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or left unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0025] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entire upper or lower structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0026] In some 3D NAND memory devices, semiconductor layers are selectively grown to surround the sidewalls of the channel structure, a process known as sidewall selective epitaxial growth (SEG). Compared to another type of semiconductor layer epitaxially grown at the source end of the channel structure (e.g., bottom SEG), the formation of sidewall SEG avoids etching of the semiconductor channel at the bottom surface of the memory film and channel vias (also known as SONO vias), thereby increasing the process window, especially when fabricating 3D NAND memory devices using advanced techniques (e.g., with 90 or more layers having a multi-layered architecture).

[0027] However, because intrinsic (pure, undoped) semiconductor materials (e.g., intrinsic polysilicon) are used to form the semiconductor channel, a relatively high barrier exists between the semiconductor channel and the sidewall SEG or conductive layer in contact with the semiconductor channel, thereby introducing high contact resistance. The electrical performance of 3D memory devices can be affected by high contact resistance.

[0028] To address the aforementioned problems, this disclosure introduces a solution in which the contact resistance between the semiconductor channel and the sidewall SEG or conductive layer can be reduced. In some embodiments, the semiconductor channel is partially doped such that the portion of the semiconductor channel forming the source contact is highly doped to lower the barrier, while leaving another portion of the semiconductor channel forming the memory cell undoped or lightly doped. In some embodiments, one end of each channel structure is open from the back side to expose the doped portion of the corresponding semiconductor channel, and the 3D memory device further includes a doped semiconductor layer electrically connecting the exposed doped portion of the semiconductor channel to further reduce contact resistance and sheet resistance. For example, the doped semiconductor layer may include plugs that extend the channel structure by replacing a portion of the cap layer of the channel structure to increase the contact area and further reduce contact resistance. As a result, the electrical performance of the 3D memory device can be improved.

[0029] Consistent with the scope of this disclosure, the doped portions of a semiconductor channel and the doped semiconductor layer can be locally activated, for example, by local annealing, to activate the dopant therein without damaging other heat-sensitive portions of the device chip, such as bonding interfaces and copper interconnects. For example, the heat used to activate the dopant can be confined to a region excluding heat-sensitive components on the device chip. In some embodiments, the local activation process is also used as an in-situ doping process to dope the portions of the intrinsic semiconductor channel that are in contact with the doped semiconductor layer.

[0030] Figure 1A A cross-sectional side view of an exemplary 3D memory device 100 according to some aspects of this disclosure is shown. In some embodiments, the 3D memory device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of the first semiconductor structure 102. According to some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded at a bonding interface 106 therebetween. Figure 1A As shown, the first semiconductor structure 102 may include a substrate 101, which may include silicon (e.g., single-crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0031] The first semiconductor structure 102 of the 3D memory device 100 may include peripheral circuitry 108 on the substrate 101. It should be noted that the x-axis and y-axis are included... Figure 1A The spatial relationships of components in a 3D memory device 100 having a substrate 101 are further illustrated herein. The substrate 101 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (i.e., the lateral direction). As used herein, when the substrate (e.g., substrate 101) is positioned in the lowest plane of the semiconductor device (e.g., the vertical direction), the location of one component (e.g., a layer or device) of the semiconductor device relative to the substrate of the semiconductor device in the y-direction is determined to be “on,” “above,” or “below” another component (e.g., a layer or device). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0032] In some embodiments, peripheral circuitry 108 is configured to control and sense the 3D memory device 100. Peripheral circuitry 108 can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry for facilitating the operation of the 3D memory device 100, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuitry 108 may include transistors formed on substrate 101, wherein all or part of the transistors are formed in substrate 101 (e.g., below the top surface of substrate 101) and / or directly on substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistor) may also be formed in substrate 101. According to some implementations, transistors utilizing advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.) are high-speed. It should be understood that in some implementations, the peripheral circuitry 108 may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random access memory (SRAM) and dynamic RAM (DRAM)).

[0033] In some embodiments, the first semiconductor structure 102 of the 3D memory device 100 further includes an interconnect layer (not shown) above the peripheral circuitry 108 to transmit electrical signals to and from the peripheral circuitry 108. The interconnect layer may include multiple interconnects (also referred to herein as contacts), including lateral interconnects and vertical interconnect access (VIA) contacts. As used herein, the term interconnect can broadly include any suitable type of interconnect, such as mid-process (MEOL) interconnects and back-end process (BEOL) interconnects. The interconnect layer may also include one or more interlayer dielectric (ILD) layers (also referred to as intermetallic dielectric (IMD) layers) in which interconnects and VIA contacts can be formed. That is, the interconnect layer may include interconnects and VIA contacts in multiple ILD layers. The interconnects and VIA contacts in the interconnect layer may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layer in the interconnect layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low k) dielectric, or any combination thereof.

[0034] like Figure 1A As shown, the first semiconductor structure 102 of the 3D memory device 100 may further include a bonding layer 110 at the bonding interface 106 and above the interconnect layer and peripheral circuitry 108. The bonding layer 110 may include a plurality of bonding contacts 111 and a dielectric for electrically isolating the bonding contacts 111. The bonding contacts 111 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining region of the bonding layer 110 may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 111 in the bonding layer 110 and the surrounding dielectric may be used for hybrid bonding.

[0035] Similarly, such as Figure 1A As shown, the second semiconductor structure 104 of the 3D memory device 100 may further include a bonding layer 112 at the bonding interface 106 and above the bonding layer 110 of the first semiconductor structure 102. The bonding layer 112 may include a plurality of bonding contacts 113 and a dielectric for electrically isolating the bonding contacts 113. The bonding contacts 113 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining region of the bonding layer 112 may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 113 in the bonding layer 112 and the surrounding dielectric may be used for hybrid bonding. According to some embodiments, the bonding contacts 113 contact the bonding contacts 111 at the bonding interface 106.

[0036] As described in detail below, the second semiconductor structure 104 can be bonded face-to-face to the top of the first semiconductor structure 102 at the bonding interface 106. In some embodiments, as a result of hybrid bonding (also known as “metal / dielectric hybrid bonding”), the bonding interface 106 is disposed between bonding layers 110 and 112. Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface 106 is the location where bonding layers 112 and 110 meet and bond. In practice, the bonding interface 106 can be a layer of a certain thickness, comprising the top surface of the bonding layer 110 of the first semiconductor structure 102 and the bottom surface of the bonding layer 112 of the second semiconductor structure 104.

[0037] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes an interconnect layer (not shown) above the bonding layer 112 for transmitting electrical signals. The interconnect layer may include multiple interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer may also include one or more ILD layers, wherein interconnect lines and VIA contacts may be formed. The interconnect lines and VIA contacts in the interconnect layer may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in the interconnect layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0038] In some embodiments, the 3D memory device 100 is a NAND flash memory device, wherein the memory cells are provided in the form of an array of NAND memory strings. Each NAND memory string may include a corresponding channel structure 124. Figure 1A As shown, each channel structure 124 may extend vertically through multiple pairs, each pair including a stacked conductive layer 116 and a stacked dielectric layer 118. Alternating stacked conductive layers 116 and stacked dielectric layers 118 form part of a memory stack 114. The number of pairs of stacked conductive layers 116 and stacked dielectric layers 118 in the memory stack 114 determines the number of memory cells in the 3D memory device 100. It should be understood that in some embodiments, the memory stack 114 may have a multi-layer architecture (not shown) comprising multiple memory layers stacked on top of each other. The number of pairs of stacked conductive layers 116 and stacked dielectric layers 118 in each memory layer may be the same or different.

[0039] The memory stack 114 may include a plurality of alternating stacked conductive layers 116 and stacked dielectric layers 118. The stacked conductive layers 116 and stacked dielectric layers 118 in the memory stack 114 may be staggered in the vertical direction. In other words, except for layers at the top or bottom of the memory stack 114, each stacked conductive layer 116 may be adjacent to two stacked dielectric layers 118 on both sides, and each stacked dielectric layer 118 may be adjacent to two stacked conductive layers 116 on both sides. The stacked conductive layers 116 may include a conductive material, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each stacked conductive layer 116 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the stacked conductive layer 116 may extend laterally as a word line, terminating at one or more stepped structures of the memory stack 114. The stacked dielectric layers 118 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0040] like Figure 1A As shown, the second semiconductor structure 104 of the 3D memory device 100 may further include a fill layer 120 above the memory stack layer 114. The fill layer 120 may include polysilicon, a high-k dielectric, or a metal. For example, a high-k dielectric may include any dielectric material having a dielectric constant higher than that of silicon oxide (e.g., k > 3.7). Unlike some known solutions in which the fill layer 120 (e.g., doped polysilicon) acts as a sidewall SEG surrounding the channel structure 124 and / or a conductive layer electrically connecting the channel structure 124, the fill layer 120 in the second semiconductor structure 104 of the 3D memory device 100 may not act as a sidewall SEG and / or conductive layer, and therefore may include materials other than doped polysilicon, such as dielectrics (e.g., high-k dielectrics), metals (e.g., W, Co, Cu, or Al), metal silicides, or undoped polysilicon. It should be understood that in some examples, the fill layer 120 may also include doped polysilicon.

[0041] In some embodiments, each channel structure 124 includes a channel via filled with a semiconductor layer (e.g., as semiconductor channel 128) and a composite dielectric layer (e.g., as memory film 126). In some embodiments, the semiconductor channel 128 comprises silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the memory film 126 is a composite layer comprising a tunneling layer, a storage layer (also referred to as a "charge trapping layer"), and a barrier layer. Figure 1AAs shown, the remaining space of the channel aperture may be partially filled with a capping layer 127 comprising a dielectric material (e.g., silicon oxide) and / or an air gap (not shown). The channel structure 124 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the capping layer, semiconductor channel 128, tunneling layer, storage layer, and barrier layer of the memory film 126 are arranged radially in this order from the center of the pillar toward the outer surface. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may comprise silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film 126 may comprise a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0042] In some embodiments, the channel structure 124 also includes a channel plug 129 in the bottom portion of the channel structure 124 (e.g., at the lower end). As used herein, when the substrate 101 is positioned in the lowest plane of the 3D memory device 100, the upper end of the component (e.g., the channel structure 124) is the end away from the substrate 101 in the y-direction, and the lower end of the component (e.g., the channel structure 124) is the end closer to the substrate 101 in the y-direction. The channel plug 129 may comprise a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 129 serves as the drain of the channel structure 124.

[0043] like Figure 1A As shown, each channel structure 124 can extend vertically through alternating stacked conductive layers 116 and stacked dielectric layers 118 of the memory stack 114 into the fill layer 120. That is, the channel structure 124 can extend beyond the memory stack 114 in the positive y-direction. According to some embodiments, the upper end of the memory film 126 is flush with the upper end of the semiconductor channel 128, i.e., aligned with each other in the vertical direction. In some embodiments, the upper ends of the memory film 126 and the upper ends of the semiconductor channel 128 are flush with the top surface of the fill layer 120.

[0044] Also refer to Figure 2 An enlarged side view of the channel structure 124 in the image shows that the semiconductor channel 128 may include a doped portion 128a and an undoped portion 128b. In some embodiments, at least a portion of the doped portion 128a of the semiconductor channel 128 is in a first direction (e.g., ...). Figure 2The doped portion 128a extends beyond the memory stack 114 in the positive y-direction (as shown in the first direction). That is, the upper end of the doped portion 128a may be above the interface between the fill layer 120 and the memory stack 114 (i.e., the bottom surface of the fill layer 120 and the top surface of the memory stack 114). Similarly, the upper end of the memory film 126 may also be above the interface between the fill layer 120 and the memory stack 114. In some embodiments, the doped portion 128a of the semiconductor channel 128 also extends in a second direction opposite to the first direction (e.g., in the positive y-direction). Figure 2 The doped portion 128a of the semiconductor channel 128 extends beyond one of the stacked conductive layers 116 in the negative y-direction. It should be understood that one or more of the stacked conductive layers 116 adjacent to the fill layer 120 may be source select gate lines 201 (SSG lines, sometimes referred to as bottom select gate (BSG) lines), and the remaining stacked conductive layers 116 may include word lines 203. According to some embodiments, the doped portion 128a of the semiconductor channel 128 also extends beyond the source select gate line 201 closest to the fill layer 120. It should be understood that if the second semiconductor structure 104 of the 3D memory device 100 includes more than one source select gate line 201, the doped portion 128a may extend beyond all source select gate lines 201. On the other hand, the doped portion 128a may not extend further to face the word line 203. That is, according to some embodiments, the lower end of the doped portion 128a lies between the source select gate line 201 and the word line 203 in the vertical direction. For example, as... Figure 2 As shown, the portion of the doped portion 128a of the semiconductor channel 128 extending beyond the memory stack layer 114 may face the fill layer 120, while the remaining doped portion 128a may face one or more source select gate lines 201.

[0045] In some embodiments, the doped portion 128a of the semiconductor channel 128 comprises N-type doped polysilicon. The dopant can be any suitable N-type dopant, such as phosphorus (P), arsenic (Ar), or antimony (Sb), which contribute free electrons and increase the conductivity of the intrinsic semiconductor. In some embodiments, the doping concentration of the doped portion 128a is approximately 10⁻⁶. 19 cm -3 With approximately 10 21 cm -3 Between, for example, in 10 19 cm -3 With 10 21 cm -3 Between (e.g., 10) 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 4×1019 cm -3 5×10 19 cm -3 6×10 19 cm -3 7×10 19 cm -3 8×10 19 cm -3 9×10 19 cm -3 10 20 cm -3 2×10 20 cm -3 3×10 20 cm -3 4×10 20 cm -3 5×10 20 cm -3 6×10 20 cm -3 7×10 20 cm -3 8×10 20 cm -3 9×10 20 cm -3 10 21 cm -3 (This refers to any range defined by the lower limit of any one of these values, or any range defined by any two of these values). Compared to intrinsic semiconductors, the doping concentration of the doped portion 128a disclosed herein can significantly reduce the contact resistance between the semiconductor channel 128 and the doped semiconductor layer 122. It should be understood that, in some examples, the diffusion of the dopant can be confined to the doped portion 128a of the semiconductor channel 128, such that the remainder of the semiconductor channel 128 (i.e., the portion facing word line 203) is an undoped portion 128b that still comprises intrinsic semiconductor (e.g., intrinsic polysilicon, i.e., with a nominally zero doping concentration). The aforementioned doping concentration distribution can reduce the barrier, contact resistance, and sheet resistance at the doped portion 128a of the semiconductor channel 128, which enables electrical connections for the sources of the corresponding NAND memory strings without altering the intrinsic properties of the undoped portion 128b of the semiconductor channel 128 forming the memory cells of the NAND memory strings.

[0046] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 includes a doped semiconductor layer 122. Each channel structure 124 may extend beyond the memory stack layer 114 in a first direction and contact the doped semiconductor layer 122. In some embodiments, at least a portion of the doped portion 128a of each semiconductor channel 128 extends beyond the memory stack layer 114 in the first direction and contacts the doped semiconductor layer 122, such that the doped semiconductor layer 122 can electrically connect multiple channel structures 124 through the doped portion 128a of its semiconductor channel 128. For example, the doped semiconductor layer 122 may provide an electrical connection between the sources of an array of NAND memory strings in the same block, i.e., an array common source (ACS), with or without a fill layer 120 (depending on whether the fill layer 120 is conductive). In other words, the fill layer 120 may not necessarily include a conductive material, such as metal or doped polysilicon, because the doped semiconductor layer 122 can electrically connect the sources of multiple NAND memory strings independently. As a result, the material and size limitations of the fill layer 120 can be relaxed.

[0047] like Figure 1A As shown, in some embodiments, the doped semiconductor layer 122 comprises two parts: a plate 121 in contact with the fill layer 120, and plugs 123 extending from the plate 121 into the channel structure 124. Also refer to... Figure 2 According to some embodiments, the doped portion 128a of the semiconductor channel 128 is externally connected to a plug 123 of the doped semiconductor layer 122. As described in detail below regarding the manufacture of the 3D memory device 100, a portion of the channel aperture forming the channel structure 124 can be filled with the plug 123, which replaces a portion of the cap layer 127 in the channel aperture, such that the doped portion 128a of the semiconductor channel 128 can surround and contact the plug 123 in the lateral direction. Furthermore, the plug 123 of the doped semiconductor layer 122 can contact the cap layer 127 in the vertical direction. Figure 2 As shown, in some embodiments, the plug 123 protrudes into the channel structure 124 such that the lower end of the plug 123 (and the upper end of the cap layer 127) is below the interface between the fill layer 120 and the memory stack layer 114. That is, according to some embodiments, the cap layer 127 does not extend beyond the memory stack layer 114 due to the presence of the plug 123.

[0048] Similar to the doped portion 128a of the semiconductor channel 128, the plug 123 of the doped semiconductor layer 122 is also in the second direction (e.g., Figure 1A and Figure 2The plug 123 extends beyond one of the stacked conductive layers 116 in the negative y-direction. According to some embodiments, the plug 123 also extends beyond the source select gate line 201 closest to the fill layer 120. It should be understood that if the second semiconductor structure 104 of the 3D memory device 100 includes more than one source select gate line 201, the plug 123 may extend beyond all source select gate lines 201. In some embodiments, the plug 123 is aligned vertically with the doped portion 128a of the semiconductor channel 128. That is, the upper end of the plug 123 and the upper end of the doped portion 128a of the semiconductor channel 128 may be flush with each other, and the lower end of the plug 123 and the lower end of the doped portion 128a of the semiconductor channel 128 may also be flush with each other. As described in detail below regarding the manufacture of the 3D memory device 100, the plug 123 can act as a doping source for forming the doped portion 128a of the semiconductor channel 128, such that only the portion of the semiconductor channel 128 in contact with the plug 123 is doped by the plug 123, thereby forming the doped portion 128a of the semiconductor channel 128. It should be understood that in some examples, a portion of the semiconductor channel 128 may be doped before the plug 123 is formed, such that the lower end of the plug 123 and the lower end of the doped portion 128a of the semiconductor channel 128 are not flush with each other.

[0049] like Figure 1A As shown, according to some embodiments, a plate 121 of the doped semiconductor layer 122 is above and in contact with the memory film 126 of the fill layer 120 and the channel structure 124. In other words, the memory film 126 may extend beyond the memory stack layer 114 in a first direction (e.g., the positive y-direction) and contact the plate 121 of the doped semiconductor layer 122, and the fill layer 120 may be formed between the memory stack layer 114 and the plate 121 of the doped semiconductor layer 122. By extending laterally over the plurality of channel structures 124, the plate 121 may connect a plurality of plugs 123, each of the plurality of plugs 123 protruding into a corresponding channel structure 124.

[0050] As described in detail below, the formation of the memory stack 114 and the formation of the doped portion 128a of the semiconductor channel 128 and the doped semiconductor layer 122 can occur on the opposite side of the fill layer 120, thereby avoiding any deposition or etching processes that extend through the openings of the memory stack 114, thereby reducing manufacturing complexity and cost, and increasing yield and vertical scalability.

[0051] Similar to the doped portion 128a of the semiconductor channel 128, in some embodiments, the doped semiconductor layer 122 (including plate 121 and plug 123) also comprises N-type doped polysilicon. The dopant can be any suitable N-type dopant, such as P, Ar, or Sb, which contributes free electrons and improves the conductivity of the intrinsic semiconductor. Similar to the doped portion 128a of the semiconductor channel 128, in some embodiments, the doping concentration of the doped semiconductor layer 122 is approximately 10⁻⁶. 19 cm -3 With approximately 10 21 cm -3 Between, for example, in 10 19 cm -3 With 10 21 cm -3 Between (e.g., 10) 19 cm -3 2×10 19 cm -3 3×10 19 cm -3 4×10 19 cm -3 5×10 19 cm -3 6×10 19 cm -3 7×10 19 cm -3 8×10 19 cm -3 9×10 19 cm -3 10 20 cm -3 2×10 20 cm -3 3×10 20 cm -3 4×10 20 cm -3 5×10 20 cm -3 6×10 20 cm -3 7×10 20 cm -3 8×10 20 cm -3 9×10 20 cm -3 10 21 cm -3(any range defined by the lower limit of any one of these values, or within any range defined by any two of these values). Compared to intrinsic semiconductors, the doping concentration of the doped semiconductor layer 122 disclosed herein can significantly reduce the contact resistance between the semiconductor channel 128 and the doped semiconductor layer 122, as well as the sheet resistance of the doped semiconductor layer 122. As described in detail below, in some embodiments, the doped portion 128a of the semiconductor channel 128 and the doped semiconductor layer 122 have the same material (e.g., N-type doped polysilicon) having the same dopant, and have a continuous doping distribution due to the same local activation process performed thereon. Therefore, it should be understood that the interface and boundary between the doped portion 128a of the semiconductor channel 128 and the plug 123 of the doped semiconductor layer 122 may become indistinguishable and therefore cannot be distinguished in the 3D memory device 100.

[0052] By doping and contacting the semiconductor channel 128 and the doped semiconductor layer 122, the contact resistance between NAND memory strings (i.e., at the ACS of NAND memory strings in the same block) can be reduced, thereby improving the electrical performance of the 3D memory device 100. For example... Figure 1A and Figure 2 As shown, by extending the plug 123 into the channel structure 124, the doped portion 128a of the semiconductor channel 128 can be externally connected to the plug 123 of the doped semiconductor layer 122, thereby increasing the contact area between the semiconductor channel 128 and the doped semiconductor layer 122, which further reduces the contact resistance therebetween. The plug 123 of the N-type doped semiconductor layer 122 surrounded by the doped portion 128a of the semiconductor channel 128 can realize a gate-induced drain leakage (GIDL) auxiliary body bias for the erase operation of the 3D memory device 100. The GIDL around (one or more) source select gate lines 201 can generate hole currents (i.e., source leakage currents) from the source of the corresponding NAND memory string into the semiconductor channel 128 to increase the body potential for the erase operation. That is, according to some embodiments, the plug 123 of the N-type doped semiconductor layer 122 is configured to generate a GIDL auxiliary body bias during the execution of the erase operation. In some implementations, the GIDL effect can be further enhanced by also doping portions of the semiconductor channel 128 facing one or more source select gate lines 201.

[0053] like Figure 1AAs shown, the second semiconductor structure 104 of the 3D memory device 100 may further include insulating structures 130, each of which extends perpendicularly through alternating stacked conductive layers 116 and stacked dielectric layers 118 of the memory stack 114. According to some embodiments, unlike the channel structures 124 that extend further into the fill layer 120, the insulating structures 130 terminate at the bottom surface of the fill layer 120, i.e., do not extend perpendicularly into the fill layer 120. That is, the top surface of the insulating structure 130 may be flush with the bottom surface of the fill layer 120. Each insulating structure 130 may also extend laterally to divide the channel structures 124 into multiple blocks. In other words, the memory stack 114 may be divided into multiple memory blocks by the insulating structures 130, such that the array of channel structures 124 can be divided into each memory block. Unlike the slit structures in existing 3D NAND memory devices that include front-side ACS contacts, according to some embodiments, the insulating structure 130 does not include any contacts therein (i.e., not used as source contacts), and therefore does not introduce parasitic capacitance and leakage current with respect to the stacked conductive layer 116. In some embodiments, each insulating structure 130 includes an opening (e.g., a slit) filled with one or more dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 130 may be filled with silicon oxide. It should be understood that in some examples (e.g., Figure 1A As shown in the diagram, the insulating structure 130 may be partially filled with a non-dielectric material (e.g., polysilicon) to adjust the mechanical properties of the insulating structure 130, such as hardness and / or stress.

[0054] Furthermore, as described in detail below, the openings used to form the insulating structure 130 are not used to form the doped portions 128a of the doped semiconductor layer 122 and the semiconductor channel 128, so increasing the aspect ratio of the openings (e.g., greater than 50) with the alternating stacking of the conductive layers 116 and the stacked dielectric layers 118 will not affect the formation of the doped portions 128a of the doped semiconductor layer 122 and the semiconductor channel 128.

[0055] like Figure 1AAs shown, the 3D memory device 100 may include one or more back-side source contacts 132, rather than front-side source contacts, that are located above and in contact with the doped semiconductor layer 122. The source contacts 132 and the memory stack layer 114 (and the insulating structure 130 passing through it) may be located on the opposite side of the fill layer 120 and are thus considered "back-side" source contacts. In some embodiments, the source contacts 132 are electrically connected to the semiconductor channel 128 of the channel structure 124 via the doped semiconductor layer 122. The source contacts 132 may include any suitable type of contact. In some embodiments, the source contacts 132 include VIA contacts. In some embodiments, the source contacts 132 include laterally extending wall-like contacts. The source contacts 132 may include one or more conductive layers, such as metal layers (e.g., W, Co, Cu, or Al) or silicide layers surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

[0056] like Figure 1A As shown, the 3D memory device 100 may further include a BEOL interconnect layer 133, which is above and electrically connected to the source contacts 132 for pad take-off, for example, to transmit electrical signals between the 3D memory device 100 and external circuitry. In some embodiments, the interconnect layer 133 includes one or more ILD layers 134 on the doped semiconductor layer 122 and a redistribution layer 136 on the ILD layers 134. According to some embodiments, the upper end of the source contacts 132 is flush with the top surface of the ILD layers 134 and the bottom surface of the redistribution layer 136, and the source contacts 132 extend vertically through the ILD layers 134 to contact the doped semiconductor layer 122. The ILD layers 134 in the interconnect layer 133 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The redistribution layer 136 in interconnect layer 133 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some embodiments, interconnect layer 133 also includes a passivation layer 138 as the outermost layer for passivation and protection of the 3D memory device 100. A portion of the redistribution layer 136 may be exposed from the passivation layer 138 to serve as contact pads 140. That is, interconnect layer 133 of the 3D memory device 100 may also include contact pads 140 for wire bonding and / or bonding to an interposer. As described below with respect to the manufacturing process, in some embodiments, source contact 132 and redistribution layer 136 may be formed using the same process and have the same material, such as Al. Therefore, in some examples, source contact 132 may be considered as a portion of BEOL interconnect layer 133.

[0057] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes contacts 142 and 144 extending through the doped semiconductor layer 122 and the fill layer 120. According to some embodiments, since the doped semiconductor layer 122 may comprise polysilicon, contacts 142 and 144 are through-silicon contacts (TSCs). In some embodiments, contact 142 extends through the doped semiconductor layer 122, the fill layer 120, and the ILD layer 134 to contact the redistribution layer 136, such that the doped semiconductor layer 122 is electrically connected to contact 142 via the source contact 132 and the redistribution layer 136 of the interconnect layer 133. In some embodiments, contact 144 extends through the doped semiconductor layer 122, the fill layer 120, and the ILD layer 134 to contact the contact pad 140. Both contacts 142 and 144 may comprise one or more conductive layers, such as metal layers (e.g., W, Co, Cu, or Al) or silicide layers surrounded by an adhesive layer (e.g., TiN). In some embodiments, at least contact 144 further includes spacers (e.g., dielectric layers) to electrically isolate contact 144 from doped semiconductor layer 122 and fill layer 120.

[0058] In some embodiments, the 3D memory device 100 further includes peripheral contacts 146 and 148, each peripheral contact 146 and 148 extending vertically outside the memory stack layer 114. Each peripheral contact 146 or 148 may have a depth greater than the depth of the memory stack layer 114 to extend vertically from the bonding layer 112 to the fill layer 122 in a peripheral region outside the memory stack layer 114. In some embodiments, peripheral contact 146 is below and contacts contact 142, such that the doped semiconductor layer 122 is electrically connected to peripheral circuitry 108 in the first semiconductor structure 102 via at least source contact 132, redistribution layer 136, contact 142, and peripheral contact 146. In some embodiments, peripheral contact 148 is below and contacts contact 144, such that peripheral circuitry 108 in the first semiconductor structure 102 is electrically connected to contact pads 140 for pad take-off via at least contact 144 and peripheral contact 148. Both peripheral contacts 146 and 148 may include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

[0059] like Figure 1AAs shown, the 3D memory device 100 also includes a plurality of local contacts (also referred to as "C1") as part of an interconnect structure, which directly contact structures within the memory stack 114. In some embodiments, the local contacts include channel local contacts 150, each channel local contact 150 being below and contacting the lower end of a corresponding channel structure 124. Each channel local contact 150 may be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts also include word line local contacts 152, each word line local contact 152 being below and contacting a corresponding stacked conductive layer 116 (including word lines) at a stepped structure of the memory stack 114 for word line fan-out. The local contacts (e.g., channel local contacts 150 and word line local contacts 152) may be electrically connected to peripheral circuitry 108 of the first semiconductor structure 102 via at least bonding layers 112 and 110. Local contacts (e.g., channel local contact 150 and word line local contact 152) may each include one or more conductive layers, such as metal layers (e.g., W, Co, Cu or Al) or silicide layers surrounded by adhesive layers (e.g., TiN).

[0060] although Figure 1A An exemplary 3D memory device 100 is shown, but it should be understood that any other suitable architecture of the 3D memory device may be applied to this disclosure without further detail by changing the relative positions of the first semiconductor structure 102 and the second semiconductor structure 104, the use of the back-side source contact 132 or a known front-side source contact (not shown), and / or the pad lead-out positions (e.g., by the first semiconductor structure 102 and / or the second semiconductor structure 104).

[0061] Figure 1B A side view of a cross-section of another exemplary 3D memory device 160 according to some embodiments of the present disclosure is shown. 3D memory device 160 is similar to 3D memory device 100, except for a different structure at the upper ends of the doped semiconductor layer 122 and the cap layer 127. It should be understood that, for ease of description, details of other identical structures in both 3D memory devices 160 and 100 are not repeated.

[0062] like Figure 1B As shown, according to some embodiments, the doped semiconductor layer 122 does not include any plugs extending into the channel structure 124 (e.g., Figure 1A (The plug 123 in the middle). That is, in some embodiments, the entire doped semiconductor layer 122 can be regarded as a plate 121. Without the plug 123 extending into the channel structure 124, the cap layer 127 of the channel structure 124 can completely fill the channel hole, and therefore in the first direction (e.g., Figure 1B The channel structure 124 extends beyond the memory stack layer 114 in the positive y-direction and contacts the doped semiconductor layer 122. That is, the upper ends of the memory film 126, the semiconductor channel 128, and the cap layer 127 can be flush with each other and contact the doped semiconductor layer 122. Consequently, in some embodiments, the channel structure 124 extends beyond the memory stack layer 114 in the positive y-direction and contacts the doped semiconductor layer 122. Figure 1B It extends beyond the memory stack layer 114 in the positive y direction and contacts the doped semiconductor layer 122.

[0063] Figure 7 A block diagram of an exemplary system 700 having a 3D memory device according to some aspects of this disclosure is shown. System 700 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 7 As shown, system 700 may include a host 708 and a storage system 702, the storage system 702 having one or more 3D memory devices 704 and a memory controller 706. The host 708 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 708 may be configured to send data to or receive data from the 3D memory device 704.

[0064] 3D memory device 704 can be any 3D memory device disclosed herein, for example, Figure 1A and Figure 1B The 3D memory devices 100 and 160 are shown. In some embodiments, each 3D memory device 704 includes NAND flash memory. Consistent with the scope of this disclosure, the semiconductor channel of the 3D memory device 704 may be partially doped, such that the portion of the semiconductor channel forming the source contacts is highly doped to lower the barrier, while leaving another portion of the semiconductor channel forming the memory cells undoped or lightly doped. One end of each channel structure of the 3D memory device 704 may be open from the back side to expose the doped portion of the corresponding semiconductor channel. The 3D memory device 704 may also include a doped semiconductor layer electrically connecting the exposed doped portions of the semiconductor channel to further reduce contact resistance and sheet resistance. The 3D memory device 704 may further include a doped semiconductor layer electrically connecting the exposed doped portions of the semiconductor channel to further reduce contact resistance and sheet resistance. As a result, the electrical performance of the 3D memory device 704 can be improved, which in turn improves the performance of the memory system 702 and system 700, for example, thereby achieving higher operating speeds.

[0065] According to some embodiments, a memory controller 706 is coupled to a 3D memory device 704 and a host 708, and is configured to control the 3D memory device 704. The memory controller 706 can manage data stored in the 3D memory device 704 and communicate with the host 708. In some embodiments, the memory controller 706 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 706 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which serve as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. The memory controller 706 can be configured to control the operation of the 3D memory device 704, such as read, erase, and program operations. The memory controller 706 can also be configured to manage various functions relating to data stored or to be stored in the 3D memory device 704, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 706 is also configured to process error correction codes (ECC) relating to data read from or written to the 3D memory device 704. The memory controller 706 can also perform any other suitable function, such as formatting the 3D memory device 704. The memory controller 706 can communicate with external devices (e.g., host 708) according to specific communication protocols. For example, the memory controller 706 can communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0066] The memory controller 706 and one or more 3D memory devices 704 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 702 can be implemented and packaged into different types of end electronic products. Figure 8AIn one example shown, the memory controller 706 and a single 3D memory device 704 can be integrated into the memory card 802. The memory card 802 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 802 may also include a connection between the memory card 802 and a host computer (e.g., Figure 7 The host (708) is electrically coupled to the memory card connector 804. In such a way... Figure 8B In another example shown, the memory controller 706 and multiple 3D memory devices 704 can be integrated into the SSD 806. The SSD 806 may also include components for connecting the SSD 806 to a host computer (e.g., ...). Figure 7 The host 708 is electrically coupled to the SSD connector 808. In some embodiments, the storage capacity and / or operating speed of the SSD 806 is greater than the storage capacity and / or operating speed of the memory card 802.

[0067] Figures 3A-3O A manufacturing process for forming an exemplary 3D memory device according to some embodiments of the present disclosure is shown. Figure 5 A flowchart of a method 500 for forming an exemplary 3D memory device according to some embodiments of the present disclosure is shown. Figures 3A-3O as well as Figure 5 Examples of 3D memory devices depicted include Figure 1A The 3D memory device 100 depicted herein will be described together. Figures 3A-3O as well as Figure 5 It should be understood that the operations shown in method 500 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously, or in conjunction with... Figure 5 The different execution sequences are shown.

[0068] refer to Figure 5 Method 500 begins at operation 502, wherein peripheral circuitry is formed on a first substrate. The first substrate may be a silicon substrate. Figure 3GAs shown, multiple transistors are formed on the silicon substrate 350 using multiple processes, including but not limited to photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some embodiments, doped regions (not shown) are formed in the silicon substrate 350 by ion implantation and / or thermal diffusion, and the doped regions serve, for example, as source and / or drain regions of the transistors. In some embodiments, isolation regions (e.g., STI) are also formed in the silicon substrate 350 by wet etching and / or dry etching, as well as thin film deposition. Peripheral circuitry 352 can be formed on the silicon substrate 350.

[0069] like Figure 3G As shown, a bonding layer 348 is formed over peripheral circuitry 352. The bonding layer 348 includes bonding contacts electrically connected to peripheral circuitry 352. To form the bonding layer 348, an ILD layer is deposited using one or more thin-film deposition processes (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof); wet etching and / or dry etching (e.g., reactive ion etching (RIE)) are used, followed by the formation of bonding contacts through the ILD layer using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0070] Method 500 proceeds to operation 504, such as... Figure 5 As shown, a fill layer is formed over a second substrate, and a stacked layer structure is formed over the fill layer. The fill layer and the stacked layer structure can be formed on the positive side of the second substrate, and a semiconductor device can be formed on the second substrate. The second substrate can be a silicon substrate. It should be understood that since the second substrate will be removed from the final product, the second substrate can be a portion of a dummy wafer (e.g., a carrier substrate) made of any suitable material (e.g., glass, sapphire, plastic, silicon, to name just a few) to reduce the cost of the second substrate. In some embodiments, the substrate is a carrier substrate. In some embodiments, the fill layer includes polysilicon, a high-k dielectric, or a metal, and the stacked layer structure includes a dielectric stack with alternating stacked dielectric layers and stacked sacrificial layers. It should be understood that in some examples, the stacked layer structure can include a memory stack with alternating stacked dielectric layers (e.g., silicon oxide layers) and stacked conductive layers (e.g., polysilicon layers).

[0071] To better control the measurement and surface flatness of various structures to be formed on the second substrate, various stop layers can be formed between the second substrate and the fill layer. In some embodiments, a first stop layer and a second stop layer are formed sequentially between the second substrate and the fill layer. The first stop layer may include silicon oxide or silicon nitride, and the second stop layer may include silicon oxide or polysilicon. In some embodiments, a third stop layer, such as a silicon nitride layer or a polysilicon layer, is formed between the second stop layer and the fill layer. In some embodiments, a single stop layer, such as a silicon oxide layer or a high-k dielectric layer, is formed between the second substrate and the fill layer.

[0072] like Figure 3A As shown, a first stop layer 303 is formed over a carrier substrate 302, a second stop layer 304 is formed on the first stop layer 303, and a fill layer 306 is formed on the second stop layer 304. The fill layer 306 may comprise polysilicon, a high-k dielectric, or a metal. When etching the channel via from the front side, the second stop layer 304 may act as an etch stop layer and may therefore comprise any suitable material having high etch selectivity (e.g., greater than about 5) relative to the material directly on the second stop layer 304, such as silicon oxide or polysilicon. When removing the carrier substrate 302 from the back side, the first stop layer 303 may act as a CMP / etch stop layer and may therefore comprise any suitable material other than the material of the carrier substrate 302, such as silicon nitride or silicon oxide. It should be understood that in some examples, a pad oxide layer (e.g., a silicon oxide layer) may be formed between the carrier substrate 302 and the first stop layer 303 to relax stress between the different layers and prevent peeling.

[0073] like Figure 3A As shown, a stacked layer of silicon oxide (pad oxide layer), silicon nitride (first stop layer 303), and silicon oxide (second stop layer 304) can be sequentially formed on a carrier substrate 302 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, a fill layer 306 is formed by depositing polysilicon or any other suitable material (e.g., a high-k dielectric or a metal) on the second stop layer 304 using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. For ease of description, the term "silicon oxide" is used in this disclosure. Figure 3AThe combination of stop layers shown is used to describe the manufacturing process. However, it should be understood that any other suitable combination of stop layers(s) may be used in other examples. In the example not shown, a single oxide layer or high-k dielectric layer (as the first stop layer 303 and the second stop layer 304) may be formed on the carrier substrate 302 using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0074] like Figure 3B As shown, a dielectric stack 308 comprising multiple pairs of first dielectric layers (hereinafter referred to as "stacked sacrificial layers" 312) and second dielectric layers (hereinafter referred to as "stacked dielectric layers" 310, collectively referred to as "dielectric layer pairs") is formed on a fill layer 306. According to some embodiments, the dielectric stack 308 comprises alternating stacked sacrificial layers 312 and stacked dielectric layers 310. The stacked dielectric layers 310 and stacked sacrificial layers 312 may be alternately deposited on the fill layer 306 above the carrier substrate 302 to form the dielectric stack 308. In some embodiments, each stacked dielectric layer 310 comprises a silicon oxide layer, and each stacked sacrificial layer 312 comprises a silicon nitride layer. The dielectric stack 308 can be formed by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Figure 3B As shown, a stepped structure can be formed on the edge of the dielectric stack 308. The stepped structure can be formed by performing multiple so-called “trimming-etching” cycles on the dielectric layer pairs of the dielectric stack 308 toward the carrier substrate 302. Because repeated trimming-etching cycles are applied to the dielectric layer pairs of the dielectric stack 308, the dielectric stack 308 can have one or more sloping edges and a top dielectric layer pair shorter than the bottom dielectric layer pair, such as… Figure 3B As shown in the image.

[0075] Method 500 proceeds to operation 506, such as... Figure 5 As shown, a channel structure is formed that extends vertically through a dielectric stack and a fill layer. The channel structure may include a memory film and a semiconductor channel. In some embodiments, to form the channel structure, a channel hole extending vertically through the dielectric stack and the fill layer is formed, stopping at a second stop layer, and a memory film, a semiconductor channel, and a capping layer are sequentially formed in the channel hole.

[0076] like Figure 3BAs shown, each via is an opening extending vertically through the dielectric stack layer 308 and the fill layer 306, stopping at the second stop layer 304. In some embodiments, multiple openings are formed such that each opening becomes a location for growing a separate channel structure 314 in a subsequent process. In some embodiments, the fabrication process for forming the vias of the channel structure 314 includes wet etching and / or dry etching, such as deep RIE (DRIE). According to some embodiments, etching of the vias continues until stopped by the second stop layer 304 (e.g., silicon oxide or polysilicon). In some embodiments, etching conditions (e.g., etch rate and time) can be controlled to ensure that each via has reached and been stopped by the second stop layer 304, minimizing the planing variation between the via and the channel structure 312 formed therein. It should be understood that, depending on the specific etch selectivity, one or more vias may extend to a very small extent into the second stop layer 304, which is still considered to be stopped by the second stop layer 304 in this disclosure.

[0077] like Figure 3B As shown, a memory film comprising a barrier layer 317, a storage layer 316, and a tunneling layer 315, and a semiconductor channel 318 are sequentially formed along the sidewalls and bottom surface of the channel via. In some embodiments, the barrier layer 317, storage layer 316, and tunneling layer 315 are first deposited sequentially along the sidewalls and bottom surface of the channel via using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form the memory film. Then, a semiconductor material (e.g., polysilicon, e.g., undoped polysilicon) can be deposited over the tunneling layer 315 using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to form the semiconductor channel 318. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (“SONO” structure) are sequentially deposited to form the barrier layer 317, storage layer 316, tunneling layer 315, and semiconductor channel 318 of the memory film.

[0078] like Figure 3BAs shown, a capping layer 319 is formed in the channel via and over the semiconductor channel 318 to completely or partially fill the channel via (e.g., with or without an air gap). The capping layer 319 can be formed by depositing a dielectric material (e.g., silicon oxide) using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). A channel plug can then be formed in the top portion of the channel via. In some embodiments, portions of the memory film, semiconductor channel 318, and capping layer 319 on the top surface of the dielectric stack 308 are removed and planarized by CMP, wet etching, and / or dry etching. A recess can then be formed in the top portion of the channel via by wet etching and / or dry etching of the portions of the semiconductor channel 318 and capping layer 319 in the top portion of the channel via. The channel plug can then be formed by depositing a semiconductor material (e.g., polysilicon) into the recess using one or more thin-film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof). According to some embodiments, the channel structure 314 is thus formed through the dielectric stack layer 308 and the fill layer 306, stopping at the second stop layer 304.

[0079] like Figure 3C As shown, the slot 320 is an opening that extends vertically through the dielectric stack 308 and terminates at the fill layer 306. In some embodiments, the fabrication process for forming the slot 320 includes wet etching and / or dry etching, such as DRIE. Gate replacement can then be performed through the slot 320 to replace the dielectric stack 308 (e.g., memory stack 330) with the memory stack 330. Figure 3E (as shown in the image).

[0080] like Figure 3D As shown, the stacked sacrificial layer 312 is first removed via the gap 320 (as shown). Figure 3C (as shown in the diagram) to form lateral recesses 322. In some embodiments, lateral recesses 322 are created alternately between stacked dielectric layers 310 by removing the stacked sacrificial layer 312 through an etchant applied via the gap 320. The etchant may include any suitable etchant that selectively etches the stacked sacrificial layer 312 onto the stacked dielectric layer 310.

[0081] like Figure 3E As shown, the stacked conductive layer 328 (including the gate electrode and the adhesive layer) is deposited through the gap 320 into the lateral recess 322 (as shown). Figure 3DIn some embodiments, a gate dielectric layer 332 is deposited into a lateral recess 322 prior to the stacked conductive layer 328, such that the stacked conductive layer 328 is deposited on the gate dielectric layer 332. The stacked conductive layer 328 (e.g., a metal layer) can be deposited using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some embodiments, the gate dielectric layer 332 (e.g., a high-k dielectric layer) is also formed along the sidewalls of the slot 320 and at the bottom of the slot 320. According to some embodiments, this forms a memory stack 330 comprising alternating stacked conductive layers 328 and stacked dielectric layers 310, thereby replacing the dielectric stack 308 (e.g., ...). Figure 3D (as shown in the image).

[0082] like Figure 3E As shown, an insulating structure 336 is formed that extends vertically through the memory stack layer 330 and terminates on the top surface of the fill layer 306. The insulating structure 336 can be formed by depositing one or more dielectric materials (e.g., silicon oxide) into the gap 320 to completely or partially fill the gap 320 (with or without air gaps) using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). In some embodiments, the insulating structure 336 includes a gate dielectric layer 332 (e.g., including a high-k dielectric) and a dielectric capping layer 334 (e.g., including silicon oxide). In some embodiments, the dielectric capping layer 334 may partially fill the gap 320, and a polysilicon core layer 335 may fill the remaining space of the gap 320 as part of the insulating structure 336 to adjust the mechanical properties of the insulating structure 336, such as hardness or stress.

[0083] like Figure 3F As shown, after forming the insulating structure 336, local contacts including channel local contacts 344 and word line local contacts 342, as well as peripheral contacts 338 and 340, are formed. A local dielectric layer can be formed on the memory stack 330 by depositing a dielectric material (e.g., silicon oxide or silicon nitride) on top of the memory stack 330 using one or more thin-film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof). Contact openings through the local dielectric layer (and any other ILD layer) can be formed by etching using wet etching and / or dry etching (e.g., RIE), followed by filling the contact openings with a conductive material using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0084] like Figure 3F As shown, a bonding layer 346 is formed over the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. The bonding layer 346 includes bonding contacts electrically connected to the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. To form the bonding layer 346, an ILD layer is deposited using one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof), and wet etching and / or dry etching (e.g., RIE) are used, followed by forming the bonding contacts through the ILD layer using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0085] Method 500 proceeds to operation 508, such as... Figure 5 As shown, a first substrate and a second substrate are bonded face-to-face, such that the memory stack layer is above the peripheral circuitry. Bonding includes hybrid bonding. (As shown...) Figure 3G As shown, a carrier substrate 302 and components formed thereon (e.g., a memory stack 330 and a channel structure 314 formed therethrough) are flipped upside down. According to some embodiments, a downward-facing bonding layer 346 is bonded to an upward-facing bonding layer 348, i.e., face-to-face, thereby forming a bonding interface 354 between the carrier substrate 302 and the silicon substrate 350. In some embodiments, a processing technique, such as plasma treatment, wet processing, and / or thermal treatment, is applied to the bonding surfaces prior to bonding. After bonding, the bonding contacts in the bonding layer 346 and the bonding contacts in the bonding layer 348 are aligned and contacted, such that the memory stack 330 and the channel structure 314 formed therethrough are electrically connected to and above the peripheral circuitry 352.

[0086] Method 500 proceeds to operation 510, such as Figure 5 As shown, the portion of the second substrate and the channel structure extending beyond the fill layer is removed sequentially to expose the portion of the semiconductor channel. Removal can be performed from the back side of the second substrate. Figure 6 As shown, in some embodiments, to sequentially remove portions of the second substrate and the channel structure, at 602, the second substrate is removed, stopping at the first stop layer; at 604, the first stop layer is removed, stopping at the second stop layer; and at 606, the second stop layer and portions of the channel structure are removed, stopping at the fill layer. In some embodiments, the removed portion of the channel structure extends into the second stop layer, and the second stop layer and the portion of the channel structure extending into the second stop layer are polished. Figure 6 As shown, in some embodiments, at 608, a portion of the capping layer of the channel structure is etched back to form a recess surrounded by a portion of the semiconductor channel.

[0087] like Figure 3H As shown, the carrier substrate 302 (and Figure 3G The pad oxide layer between the carrier substrate 302 and the first stop layer 303 shown is completely removed from the back side until stopped by the first stop layer 303 (e.g., a silicon nitride layer). The carrier substrate 302 can be completely removed using CMP, polishing, dry etching, and / or wet etching. In some embodiments, the carrier substrate 302 is stripped. In some embodiments where the carrier substrate 302 comprises silicon and the first stop layer 303 comprises silicon nitride, the carrier substrate 302 is removed using silicon CMP, which can automatically stop upon reaching a first stop layer 330 (e.g., acting as a back-side CMP stop layer) having a material other than silicon. In some embodiments, the carrier substrate 302 (silicon substrate) is removed using wet etching with tetramethylammonium hydroxide (TMAH), which automatically stops upon reaching a first stop layer 303 (e.g., acting as a back-side etching stop layer) having a material other than silicon. The first stop layer 303 can ensure complete removal of the carrier substrate 302 without considering thickness uniformity after thinning.

[0088] like Figure 3I As shown, the first stop layer 303 and the second stop layer 304 can then be completely removed by wet etching using a suitable etchant (e.g., phosphoric acid and hydrofluoric acid). Figure 3H As shown in the diagram, it continues until it is stopped by a filling layer 306 having a different material (e.g., polysilicon) than the second stop layer 304. Figure 3I As shown, the portion of the channel structure 314 extending beyond the filler layer 306 is removed, making the upper end of the channel structure 314 flush with the top surface of the filler layer 306. In some embodiments where a portion of the channel structure 314 extends into the second stop layer 304, the second stop layer 304 and the portion of the channel structure 314 extending into the second stop layer 304 are removed together by polishing (e.g., CMP), stopping at the filler layer 306. It should be understood that if the channel structure 314 does not extend beyond the filler layer 306 and into the second stop layer 304, the removal of the upper end of the channel structure 314 can be skipped.

[0089] like Figure 3JAs shown, a portion of the capping layer 319 is removed to form a recess 321 surrounded by the top portion of the semiconductor channel 318. For example, a portion of the capping layer 319 of the channel structure 314 can be etched back using, for example, dry etching and / or wet etching to form the recess 321. In some examples, while the upper end of the capping layer 319 is still covered by the semiconductor channel 318, a portion of the semiconductor channel 318 can be etched first to expose the capping layer 319. The etching of the capping layer 319 can be controlled by controlling the etching time and / or etching rate such that the etching does not continue beyond one or more source-select gate lines (e.g., one or more stacked conductive layers 328 closest to the fill layer 306). The formation of the recess 321 can expose the portion of the semiconductor channel 318 surrounding the recess 321. In some embodiments, the top portion of the semiconductor channel 318 exposed by the recess 321 is doped to increase its conductivity. For example, a tilted ion implantation process can be performed to dope the top portion of the semiconductor channel 318 (e.g., including polysilicon) exposed by the recess 321 with any suitable dopant (e.g., an N-type dopant (e.g., P, As, or Sb)) to the desired doping concentration.

[0090] Using an opening through the dielectric stack 308 / memory stack 330 with a high aspect ratio (e.g., greater than 50) (e.g., Figure 3D Compared to known solutions for wet etching of the front side of the slot 320, removing a portion of the channel structure 314 from the back side is significantly less challenging and yields higher production volumes. By avoiding the problems introduced by the high aspect ratio of the slot 320, manufacturing complexity and cost can be reduced, and production volume can be increased. Furthermore, vertical scalability can be improved (e.g., with increased layers in the dielectric stack 308 / memory stack 330).

[0091] Method 500 proceeds to operation 512, such as Figure 5 As shown, a doped semiconductor layer is formed in contact with the exposed portion of the semiconductor channel. In some embodiments, the dopant includes an N-type dopant. Figure 6 As shown, in some embodiments, in order to form a doped semiconductor layer, a polysilicon layer is deposited on the recess and fill layer at 610; and at 612, the doped polysilicon layer is deposited.

[0092] like Figure 3K As shown, a doped semiconductor layer 360 is formed in the recess 321 (e.g., Figure 3JAs shown in the diagram, the recess 321 on the fill layer 306 is surrounded by and in contact with the exposed portion of the semiconductor channel 318. In some embodiments, to form the doped semiconductor layer 360, a semiconductor layer (e.g., polysilicon) is deposited in the recess 321 in contact with the exposed portion of the semiconductor channel 318 and the cap layer 319, and on the outside of the recess 321 in contact with the fill layer 306, using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process or any combination thereof). The deposited semiconductor layer can be doped with one or more N-type dopants (e.g., P, As, or Sb) using ion implantation and / or thermal diffusion. In some embodiments, to form the doped semiconductor layer 360, in-situ doping with an N-type dopant (e.g., P, As, or Sb) is performed when the semiconductor layer is deposited into the recess 321 and onto the fill layer 306. In some implementations, a CMP process can be performed to remove any excess doped semiconductor layer 360 as needed.

[0093] Method 500 proceeds to operation 514, such as... Figure 5 As shown, the doped semiconductor layer and the portion of the semiconductor channel in contact with the doped semiconductor layer are locally activated. In some embodiments, for localized activation, heat is applied to a confined region of the portion having the doped semiconductor layer and the semiconductor channel to activate the dopant in the portion of the doped semiconductor layer and the semiconductor channel. The confined region may be between the stacked layer structure and the doped semiconductor layer. In some embodiments, after activation, the doping concentration of both the doped semiconductor layer and the portion of the semiconductor channel in contact with the doped semiconductor layer is 10. 19 cm -3 With 10 21 cm -3 between.

[0094] like Figure 3LAs shown, the portions of the doped semiconductor layer 360 and the semiconductor channel 318 that are in contact with the doped semiconductor layer 360 are locally activated. In some embodiments, heat is applied to a confined region having the portions of the doped semiconductor layer 360 and the semiconductor channel 318 to activate one or more dopants therein, such as N-type dopants (e.g., P, As, or Sb). For example, the confined region may be located vertically between the memory stack layer 330 and the doped semiconductor layer 360. Heat can be applied and focused by any suitable technique, such as annealing, laser, ultrasonic, or any other suitable thermal process. In some embodiments, the confined region affected by heat during the local activation process may not extend to and not exceed the bonding interface 354 to avoid heating the bonding interface 354 and the Cu interconnects used to connect the peripheral circuitry 352. The local activation process can activate the dopants doped into the doped semiconductor layer 360 (and, if it is already doped, in the exposed portions of the semiconductor channel 318). As a result, after activation, the doping concentration of both the doped semiconductor layer 360 and the exposed portions of the semiconductor channel 318 are above 10%. 19 cm -3 With 10 21 cm -3 In some embodiments, the local activation process is controlled such that dopants in the doped semiconductor layer 360 (and, if it is already doped, in the exposed portion of the semiconductor channel 318) diffuse from the source of the channel structure 314 toward the drain of the channel structure 314, up to and including the source-select gate line(s) (e.g., the one or more stacked conductive layers 328 closest to the fill layer 306), but not facing the word line, as described above regarding Figure 2 As described. When the exposed portion of the semiconductor channel 318 is not yet doped, the doped semiconductor layer 360 can act as a dopant source during the local activation process to diffuse dopant from the doped semiconductor layer 360 into the semiconductor channel 318, such that the portion of the semiconductor channel layer 318 in contact with the doped semiconductor layer 360 can become a doped portion, and the doped portion of the doped semiconductor layer 360 and the doped portion of the semiconductor channel 318 can have the same dopant and doping concentration.

[0095] Local activation processes can activate dopants, allowing them to occupy the silicon lattice, thereby reducing the contact resistance between the doped semiconductor layer 360 and the semiconductor channel 318, and reducing the sheet resistance of the doped semiconductor layer 360. On the other hand, by confining the heat during the local activation process to a region without heat-sensitive structures, any potential damage to heat-sensitive structures (e.g., bonding interface 354 and Cu interconnects for connecting peripheral circuitry 352) can be reduced or avoided.

[0096] Method 500 proceeds to operation 516, such as... Figure 5 As shown, a source contact is formed that contacts the doped semiconductor layer. Figure 3M As shown, one or more ILD layers 356 are formed on the doped semiconductor layer 360. The ILD layer 356 can be formed by depositing a dielectric material on the top surface of the doped semiconductor layer 360 using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). Figure 3N As shown, the source contact opening 358 can be formed through the ILD layer 356 to expose a portion of the doped semiconductor layer 360. In some embodiments, the source contact opening 358 is formed using wet etching and / or dry etching (e.g., RIE).

[0097] like Figure 3O As shown, source contacts, which are part of the conductive layer 370, are formed in each source contact opening 358 on the back side of the fill layer 306 (e.g., Figure 3N As shown in the diagram. According to some embodiments, the source contact is above and in contact with the doped semiconductor layer 360. In some embodiments, a conductive layer 370 (e.g., Al) is deposited into the source contact opening 358 using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to fill the source contact opening 358. A planarization process (e.g., CMP) can then be performed to remove excess conductive layer 370.

[0098] like Figure 3O As shown, in some embodiments, the conductive layer 370 further includes a redistribution layer above and in contact with the source contacts. That is, according to some embodiments, the conductive layer 370 is deposited not only into the source contact opening 358 as the source contacts, but also deposited outside the source contact opening 358 onto the ILD layer 356 as a redistribution layer electrically connecting the multiple source contacts.

[0099] like Figure 3O As shown, in some embodiments, the conductive layer 370 further includes contacts extending through the ILD layer 356, the doped semiconductor layer 360, and the fill layer 306. That is, the conductive layer 370 is deposited not only in the source contact opening 358 as a source contact, but also in contact openings 363 and 361 (…). Figure 3N (As shown) are contacts that are electrically connected to peripheral contacts 338 and 340. Figure 3M and Figure 3NAs shown, contact openings 363 and 361, both extending through the spacer layer 371, ILD layer 356, doped semiconductor layer 360, and filler layer 306, are formed using wet etching and / or dry etching (e.g., RIE). In some embodiments, photolithography is used to pattern the contact openings 363 and 361 to align them with peripheral contacts 338 and 340, respectively. Etching of the contact openings 363 and 361 may stop at the upper ends of the peripheral contacts 338 and 340 to expose the peripheral contacts 338 and 340. Figure 3N As shown, spacer 362 is formed by spacer layer 371 along the sidewalls of contact openings 363 and 361 to electrically separate doped semiconductor layer 360.

[0100] Figures 4A-4C A manufacturing process for forming another exemplary 3D memory device according to some embodiments of the present disclosure is illustrated. Figures 4A-4C Examples of 3D memory devices depicted include Figure 1B The 3D memory device 160 depicted herein has a recess 321 formed therein by an etch-back capping layer 319. Figure 3J Different, such as Figure 4A As shown, the top portion of the semiconductor channel 318 is doped to increase its conductivity without first etching back the capping layer 319 to expose a portion of the semiconductor channel 318. For example, a tilted ion implantation process can be performed to dope the top portion of the semiconductor channel 318 (e.g., including polysilicon) to the desired doping concentration with any suitable dopant (e.g., N-type dopant (e.g., P, As, or Sb)).

[0101] In some embodiments, to form a doped semiconductor layer, a polysilicon layer is deposited onto a filler layer, and the deposited polysilicon layer is doped. For example... Figure 4B As shown, a doped semiconductor layer 360 is formed on the fill layer 306 and the upper end of the channel structure 314. In some embodiments, to form the doped semiconductor layer 360, a semiconductor layer (e.g., polysilicon) is deposited on the fill layer 306 using one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). The deposited semiconductor layer can be doped with one or more N-type dopants (e.g., P, As, or Sb) using ion implantation and / or thermal diffusion. In some embodiments, to form the doped semiconductor layer 360, in-situ doping with an N-type dopant (e.g., P, As, or Sb) is performed when the semiconductor layer is deposited on the fill layer 306. In some embodiments, a CMP process can be performed to remove any excess doped semiconductor layer 360 as needed.

[0102] like Figure 4CAs shown, the doped portions of the doped semiconductor layer 360 and the semiconductor channel 318 are locally activated. In some embodiments, heat is applied to a confined region having the doped portions of the doped semiconductor layer 360 and the semiconductor channel 318 to activate one or more dopants therein, such as N-type dopants (e.g., P, As, or Sb). This local activation process can activate the dopants doped into the doped portions of the doped semiconductor layer 360 and the semiconductor channel 318. As a result, after activation, the doping concentration of both the doped semiconductor layer 360 and the doped portions of the semiconductor channel 318 are within 10%. 19 cm -3 With 10 21 cm -3 In some embodiments, the local activation process is controlled such that dopants in the doped portions of the doped semiconductor layer 360 and the semiconductor channel 318 diffuse from the source of the channel structure 314 toward the drain of the channel structure 314, up to and including one or more source-select gate lines (e.g., one or more stacked conductive layers 328 closest to the fill layer 306), but not toward the word lines, as described above regarding... Figure 2 As described.

[0103] According to one aspect of this disclosure, a 3D memory device includes: a stacked layer structure comprising alternating conductive and dielectric layers; a channel structure extending through the stacked layer structure; and a doped semiconductor layer comprising a plate and a plug extending from the plate into the channel structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, and a portion of the doped portion of the semiconductor channel extends beyond the stacked layer structure in a first direction. The doped portion of the semiconductor channel is externally connected to the plug of the doped semiconductor layer.

[0104] In some embodiments, the doping concentration of the doped portion of the semiconductor channel and the doping concentration of the doped semiconductor layer are both above 10. 19 cm -3 With 10 21 cm -3 between.

[0105] In some implementations, both the doped portion of the semiconductor channel and the doped semiconductor layer comprise N-type doped polysilicon.

[0106] In some embodiments, the doped portion of the semiconductor channel and the plug of the doped semiconductor layer both extend beyond one of the conductive layers in a second direction opposite to the first direction.

[0107] In some implementations, one of the conductive layers includes a source-select gate line.

[0108] In some implementations, the 3D memory device further includes a fill layer between the stacked layer structure and the plate of the doped semiconductor layer.

[0109] In some implementations, the filler layer includes polysilicon, a high-k dielectric, or a metal.

[0110] In some implementations, a source contact that contacts the doped semiconductor layer is also included.

[0111] In some implementations, the memory film extends beyond the stacked layer structure in a first direction and contacts the plate of the doped semiconductor layer.

[0112] In some implementations, the plug of the doped semiconductor layer is configured to generate a GIDL auxiliary body bias when an erase operation is performed.

[0113] According to another aspect of this disclosure, a 3D memory device includes: a stacked layer structure comprising alternating conductive and dielectric layers; a doped semiconductor layer; and a channel structure extending through the stacked layer structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion. The channel structure extends beyond the stacked layer structure in a first direction and contacts the doped semiconductor layer. The semiconductor channel includes a doped portion that extends beyond one of the conductive layers in a second direction opposite to the first direction.

[0114] In some embodiments, the doping concentration of the doped portion of the semiconductor channel and the doping concentration of the doped semiconductor layer are both above 10. 19 cm -3 With 10 21 cm -3 between.

[0115] In some implementations, both the doped portion of the semiconductor channel and the doped semiconductor layer comprise N-type doped polysilicon.

[0116] In some implementations, one of the conductive layers includes a source-select gate line.

[0117] In some implementations, a portion of the doped portion of the semiconductor channel extends beyond the stacked layer structure in a first direction and contacts the doped semiconductor layer.

[0118] In some implementations, the 3D memory device further includes a fill layer between the stacked layer structure and the doped semiconductor layer.

[0119] In some implementations, the filler layer includes polysilicon, a high-k dielectric, or a metal.

[0120] In some implementations, the 3D memory device also includes source contacts that are in contact with the doped semiconductor layer.

[0121] In some embodiments, the channel structure further includes a capping layer that extends beyond the stacked layer structure in a first direction and contacts the doped semiconductor layer.

[0122] In some implementations, the doped semiconductor layer is configured to generate a GIDL auxiliary body bias when an erase operation is performed.

[0123] According to another aspect of this disclosure, a method for forming a 3D memory device is provided. A fill layer is formed over a substrate. A stacked layer structure is formed over the fill layer. A channel structure is formed, extending through the stacked layer structure and the fill layer. The channel structure includes a memory film and a semiconductor channel. The substrate and portions of the channel structure extending beyond the fill layer are sequentially removed to expose portions of the semiconductor channel. A doped semiconductor layer is formed, contacting the exposed portions of the semiconductor channel. The doped semiconductor layer and portions of the semiconductor channel in contact with the doped semiconductor layer are locally activated.

[0124] In some implementations, heat is applied to a confined region of the portion having a doped semiconductor layer and a semiconductor channel for localized activation, thereby activating the dopant in the portion of the doped semiconductor layer and semiconductor channel.

[0125] In some implementations, the confined region is between the stacked layer structure and the doped semiconductor layer.

[0126] In some embodiments, the dopant includes an N-type dopant, and after activation, the doping concentration of both the doped semiconductor layer and the doping concentration of the portion of the semiconductor channel in contact with the doped semiconductor layer are within 10. 19 cm -3 With 10 21 cm -3 between.

[0127] In some implementations, the exposed portion of the doped semiconductor channel is formed before the doped semiconductor layer is formed.

[0128] In some embodiments, a first stop layer and a second stop layer are formed sequentially between the substrate and the fill layer.

[0129] In some embodiments, the first stop layer comprises silicon oxide or silicon nitride, the second stop layer comprises silicon oxide or polysilicon, and the fill layer comprises polysilicon, a high-k dielectric, or a metal.

[0130] In some embodiments, in order to form a channel structure, a channel hole is formed, the channel hole extends through the stacked layer structure and the fill layer, stops at a second stop layer, and a memory film, a semiconductor channel and a capping layer are sequentially formed in the channel hole.

[0131] In some embodiments, in order to sequentially remove portions of the substrate memory film, the substrate is removed, the removal stops at a first stop layer, the first stop layer is removed, the removal stops at a second stop layer, and the removal of the second stop layer and portions of the channel structure stops at a fill layer.

[0132] In some embodiments, the removed portion of the channel structure extends into the second stop layer. In some embodiments, to remove the second stop layer and portions of the channel structure, the second stop layer and the portions of the channel structure extending into the second stop layer are polished.

[0133] In some implementations, in order to sequentially remove portions of the substrate and the channel structure, portions of the capping layer of the channel structure are etched back to form a recess surrounded by portions of the semiconductor channel.

[0134] In some implementations, in order to form a doped semiconductor layer, a polysilicon layer is deposited onto the recess and filler layer, and the deposited polysilicon layer is doped.

[0135] In some implementations, in order to form a doped semiconductor layer, a polysilicon layer is deposited onto a filler layer, and the deposited polysilicon layer is doped.

[0136] In some implementations, source contacts are formed in contact with the doped semiconductor layer after the doped semiconductor layer is locally activated.

[0137] According to another aspect of this disclosure, a system includes a 3D memory device configured to store data and a memory controller coupled to the 3D memory device and configured to control the 3D memory device. The 3D memory device includes: a stacked layer structure comprising alternating conductive and dielectric layers; a channel structure extending through the stacked layer structure; and a doped semiconductor layer comprising a plate and a plug extending from the plate into the channel structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, and a portion of the doped portion of the semiconductor channel extends beyond the stacked layer structure in a first direction. The doped portion of the semiconductor channel is externally coupled to the plug of the doped semiconductor layer.

[0138] In some implementations, the system also includes a host coupled to the memory controller and configured to send or receive data.

[0139] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0140] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A three-dimensional (3D) memory device, comprising: A stacked layer structure comprising alternating conductive layers and dielectric layers; A channel structure extending through the stacked layer structure, the channel structure including a memory film and a semiconductor channel, wherein the semiconductor channel includes a doped portion, and a portion of the doped portion of the semiconductor channel extends beyond the stacked layer structure in a first direction; and A doped semiconductor layer, the doped semiconductor layer including a plate and a plug extending from the plate into the channel structure, wherein the doped portion of the semiconductor channel is external to the plug of the doped semiconductor layer, and both the doped portion of the semiconductor channel and the plug of the doped semiconductor layer extend beyond one of the conductive layers in a second direction opposite to the first direction.

2. The three-dimensional memory device according to claim 1, wherein, The doping concentration of the doped portion of the semiconductor channel and the doped semiconductor layer are both above 10. 19 cm -3 With 10 21 cm -3 between.

3. The three-dimensional memory device according to claim 1 or 2, wherein, Both the doped portion of the semiconductor channel and the doped semiconductor layer comprise N-type doped polysilicon.

4. The three-dimensional memory device according to claim 1 or 2, wherein, One of the conductive layers includes a source-select gate line.

5. The three-dimensional memory device according to claim 1 or 2, further comprising a fill layer between the plate of the stacked layer structure and the doped semiconductor layer.

6. The three-dimensional memory device according to claim 5, wherein, The filling layer includes polysilicon, a high dielectric constant (high k) dielectric, or a metal.

7. The three-dimensional memory device according to claim 1 or 2 further includes a source contact in contact with the doped semiconductor layer.

8. The three-dimensional memory device according to claim 1 or 2, wherein, The memory film extends beyond the stacked layer structure in the first direction and contacts the plate of the doped semiconductor layer.

9. The three-dimensional memory device according to claim 1 or 2, wherein, The plug of the doped semiconductor layer is configured to generate a gate-induced drain leakage (GIDL) auxiliary bias during an erase operation.

10. A three-dimensional (3D) memory device, comprising: A stacked layer structure comprising alternating conductive layers and dielectric layers; A channel structure extending through the stacked layer structure, the channel structure including a memory film and a semiconductor channel; as well as Doped semiconductor layer, The channel structure extends beyond the stacked layer structure in a first direction and contacts the doped semiconductor layer; and The semiconductor channel includes a doped portion that extends beyond one of the conductive layers in a second direction opposite to the first direction.

11. The three-dimensional memory device according to claim 10, wherein, The doping concentration of the doped portion of the semiconductor channel and the doped semiconductor layer are both above 10. 19 cm -3 With 10 21 cm -3 between.

12. The three-dimensional memory device according to claim 10 or 11, wherein, Both the doped portion of the semiconductor channel and the doped semiconductor layer comprise N-type doped polysilicon.

13. The three-dimensional memory device according to claim 10 or 11, wherein, One of the conductive layers includes a source-select gate line.

14. The three-dimensional memory device according to claim 10 or 11, wherein, A portion of the doped portion of the semiconductor channel extends beyond the stacked layer structure in the first direction and contacts the doped semiconductor layer.

15. The three-dimensional memory device of claim 10 or 11, further comprising a fill layer between the stacked layer structure and the doped semiconductor layer.

16. The three-dimensional memory device according to claim 15, wherein, The filling layer includes polysilicon, a high dielectric constant (high k) dielectric, or a metal.

17. The three-dimensional memory device according to claim 10 or 11, further comprising a source contact in contact with the doped semiconductor layer.

18. The three-dimensional memory device according to claim 10 or 11, wherein, The channel structure further includes a capping layer that extends beyond the stacked layer structure in the first direction and contacts the doped semiconductor layer.

19. The three-dimensional memory device according to claim 10 or 11, wherein, The doped semiconductor layer is configured to generate a gate-induced drain leakage (GIDL) auxiliary bias during an erase operation.

20. A method for forming a three-dimensional (3D) memory device, comprising: A filler layer is formed over the substrate; A stacked layer structure is formed above the filler layer; A channel structure is formed, the channel structure extending through the stacked layer structure and the fill layer, the channel structure extending beyond the stacked layer structure in a first direction, and the channel structure including a memory film and a semiconductor channel; The substrate and the portion of the channel structure extending beyond the fill layer are removed sequentially to expose a portion of the semiconductor channel; A doped semiconductor layer is formed, the doped semiconductor layer being in contact with an exposed portion of the semiconductor channel, the portion of the semiconductor channel in contact with the doped semiconductor layer including a doped portion, and the doped portion extending beyond one of the conductive layers in the stacked layer structure in a second direction opposite to the first direction. as well as The portion of the doped semiconductor layer and the semiconductor channel in contact with the doped semiconductor layer is locally activated.

21. The method according to claim 20, wherein, Local activation includes applying heat to a confined region having the portion of the doped semiconductor layer and the semiconductor channel to activate the dopant in the portion of the doped semiconductor layer and the semiconductor channel.

22. The method according to claim 21, wherein, The confined region is between the stacked layer structure and the doped semiconductor layer.

23. The method according to claim 21 or 22, wherein, The dopant includes an N-type dopant, and after activation, the doping concentration of the doped semiconductor layer and the doping concentration of the portion of the semiconductor channel in contact with the doped semiconductor layer are both above 10. 19 cm -3 With 10 21 cm -3 between.

24. The method according to any one of claims 20-22, further comprising, prior to forming the doped semiconductor layer, doping the exposed portion of the semiconductor channel.

25. The method according to any one of claims 20-22, further comprising forming a first stop layer and a second stop layer sequentially between the substrate and the fill layer.

26. The method of claim 25, wherein, The first stop layer comprises silicon oxide or silicon nitride, the second stop layer comprises silicon oxide or polysilicon, and the fill layer comprises polysilicon, a high dielectric constant (high k) dielectric, or a metal.

27. The method according to claim 25, wherein, The formation of the channel structure includes: Forming channel holes that extend through the stacked layer structure and the fill layer, stopping at the second stop layer; and The memory film, the semiconductor channel, and the capping layer are sequentially formed in the channel hole.

28. The method according to claim 27, wherein, Sequentially removing the portion of the substrate and the channel structure includes: Remove the substrate, stopping at the first stop layer; Remove the first stop layer, and stop at the second stop layer; and Remove the second stop layer and the portion of the channel structure, stopping at the fill layer.

29. The method of claim 28, wherein The removed portion of the channel structure extends into the second stop layer; and Removing the second stop layer and the portion of the channel structure includes polishing the second stop layer and the portion of the channel structure that extends into the second stop layer.

30. The method according to any one of claims 27-29, wherein, Sequentially removing the substrate and the portion of the channel structure also includes etching back a portion of the capping layer of the channel structure to form a recess surrounded by the portion of the semiconductor channel.

31. The method according to claim 30, wherein, Forming the doped semiconductor layer includes: A polycrystalline silicon layer is deposited into the recess and onto the filler layer; and The polycrystalline silicon layer deposited by doping.

32. The method according to any one of claims 20-22, wherein, Forming the doped semiconductor layer includes: Depositing a polycrystalline silicon layer onto the filler layer; and The polycrystalline silicon layer deposited by doping.

33. The method according to any one of claims 20-22, further comprising forming a source contact in contact with the doped semiconductor layer after locally activating the doped semiconductor layer.

34. A memory system, comprising: A three-dimensional (3D) memory device configured to store data, the three-dimensional memory device comprising: A stacked layer structure comprising alternating conductive layers and dielectric layers; A channel structure extending through the stacked layer structure, the channel structure including a memory film and a semiconductor channel, wherein the semiconductor channel includes a doped portion, and a portion of the doped portion of the semiconductor channel extends beyond the stacked layer structure in a first direction; and A doped semiconductor layer, the doped semiconductor layer including a plate and a plug extending from the plate into the channel structure, wherein the doped portion of the semiconductor channel is external to the plug of the doped semiconductor layer, and both the doped portion of the semiconductor channel and the plug of the doped semiconductor layer extend beyond one of the conductive layers in a second direction opposite to the first direction; and A memory controller coupled to the three-dimensional memory device and configured to control the three-dimensional memory device.

35. The memory system of claim 34, further comprising a host coupled to the memory controller and configured to transmit or receive the data.

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