Apparatus for controlling latency on an input signal path

Abstract

Apparatuses for controlling latency on an input signal path are disclosed. An example apparatus includes a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal, a command decoder that latches a command signal with the system clock signal and further provides a signal based on the command signal, and a command delay adjustment circuit that includes a clock synchronization circuit that receives the signal, latches the signal with the system clock signal, and provides a clocked read signal in response to a shift cycle parameter.

Description

[0001] Divisional application information

[0002] This application is a divisional application of the invention patent application filed on March 22, 2017, with application number 201780026103.7 and invention title "Device for Controlling Waiting Time on Input Signal Path". Technical Field

[0003] Embodiments of this disclosure generally relate to semiconductor memories, and more specifically to devices for controlling latency on input signal paths. Background Technology

[0004] High data reliability, high memory access speed, and low power consumption are the characteristics required for semiconductor memories. In recent years, efforts have been made to further increase memory access speed. Many synchronous integrated circuits in semiconductor devices operate based on clock signals to meet critical timing requirements.

[0005] To evaluate the performance of a pulse signal transmitting system, a window, or "data eye," pattern can be assessed. The data eye, for each data signal, defines the actual effective duration of each signal after considering various factors affecting the signal, such as timing skew, voltage, and current drive capability. In the case of signal timing skew, it is typically caused by various timing errors, such as loads on the lines of the bus and the physical length of such lines. For example, a rank margin test (RMT) can be used to evaluate the window to assess the performance tolerance of the input buffer in a semiconductor device. In the RMT, the reference voltage (VREF) level is varied from the midpoint between the input high voltage (VIH) and the input low voltage (VIL) to test the margin of the RMT as the performance tolerance. As long as the reference voltage is within a predetermined range, the input buffer must still operate without any error, even if the reference voltage is shifted.

[0006] Figure 1 is a block diagram of a device 100 including a command delay adjustment circuit 130. The device 100 may include a clock input buffer 110, a command input buffer 111, a command decoder circuit 120, a command delay adjustment circuit 130, signal trees 190 and 191 for the command signal and the clock signal, and an output buffer 195.

[0007] Command delay adjustment circuitry 130 may include a DLL clock path and a command path. The DLL clock path may include a command copy 121 and a delay line 141 for the clock signal. Command copy 121 replicates the delay of command decoder circuitry 120 to provide an RdClk signal in response to the command signal CMD and the system clock signal SCLK_CMD. Command copy 121 may delay the SCLK_DLL signal and provide the delayed system clock signal SCLKD to delay line 141. The command path includes delay line 140 for the command signal and dQ-enable-delay (QED) circuitry 160. Command delay adjustment circuitry 130 further includes a DLL clock path copy 151, a phase detector 170, and DLL control circuitry 180, which together with delay line 141 for the clock signal form a DLL circuit.

[0008] Command delay adjustment circuit 130 synchronizes the output signal of dQ-enable-delay circuit 160 with the DLL clock signal DllClk from delay line 141, while providing a latency on the output signal of dQ-enable-delay circuit 160. The latency here is (for example) a column address strobe (CAS) latency (CL) that can be set based on the clock frequency of clock signal CK. The CL value can take into account the delay between when the memory receives a READ command and when the output buffer 195 provides the read data to the output bus (e.g., via the DQ pad after output buffer 195) in response to the READ command. The CL value can be expressed as the number of clock cycles. One clock cycle can be represented by T.

[0009] However, the following side effects exist: increased jitter in the SCLKD signal from command copy 121 and increased effective standby current (e.g., IDD3N). The jitter in the SCLKD signal further increases the jitter in the DLL clock signal DllClk, leading to a reduced RMT margin. Therefore, the higher memory access speed achieved by adding command copy 121 results in a reduced RMT margin, accompanied by higher power consumption. Summary of the Invention

[0010] An exemplary device according to an embodiment of the present invention may include: a first circuit configured to respond to a first clock signal to latch a first signal, the first circuit being configured to provide a second signal; and a second circuit coupled to the first circuit to latch the second signal, the second circuit being configured to provide a third signal based on the second signal in response to a first output timing signal substantially in phase with the first clock signal.

[0011] Another exemplary device according to an embodiment of the present invention may include: a clock input buffer configured to provide a reference clock signal and a system clock signal based on an external clock signal; a command decoder configured to latch a command signal in response to the system clock signal and further configured to provide a signal based on the command signal; and a command delay adjustment circuit. The command delay adjustment circuit may include: a clock synchronization circuit configured to receive the signal from the command decoder, configured to latch the signal in response to the system clock signal, and further configured to provide a clock-synchronized read signal in response to a shift loop parameter.

[0012] An exemplary method according to an embodiment of the present invention may include: providing a reference clock signal and a system clock signal in a clock input buffer based on an external clock signal; latching a command signal in response to the system clock signal; providing a signal based on the command signal; latching the signal in response to the system clock signal; and providing a clock-synchronized read signal in response to a shift loop parameter and in response to waiting time information. Attached Figure Description

[0013] Figure 1 is a block diagram of a device containing command delay adjustment circuitry during a read operation.

[0014] Figure 2 This is a block diagram of a device including a command delay adjustment circuit according to an embodiment of the present invention.

[0015] Figure 3 This is a block diagram of a clock synchronization circuit according to an embodiment of the present invention.

[0016] Figure 4A This is a diagram of a cell in an input pointer register in a clock synchronization circuit according to an embodiment of the present invention.

[0017] Figure 4B This is according to an embodiment of the present invention. Figure 4A Timing diagram of the signals in the cell of the input pointer register.

[0018] Figure 5 This is a circuit diagram of a command decoder circuit in a device including a command delay adjustment circuit according to an embodiment of the present invention.

[0019] Figure 6 This is a timing diagram of signals in a device including a command delay adjustment circuit according to an embodiment of the present invention. Detailed Implementation

[0020] Various embodiments of the invention will be described in more detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0021] Figure 2 This is a block diagram of a device 200 including a command delay adjustment circuit 230 according to an embodiment of the present invention. Device 200 may include a clock input buffer 210, a command input buffer 211, a first circuit 220 (which may also be referred to herein as a command decoder circuit), the command delay adjustment circuit 230, signal trees 290 and 291 for the command signal and the clock signal, and an output buffer 295. Clock input buffer 210 receives a clock signal CK, a complementary clock signal CKB (both of which are external clock signals), and further receives a complementary reset signal RESETB. Clock input buffer 210 further receives an enable signal Rdi based on a READ command from the command decoder circuit 220. Clock input buffer 210 may provide a system clock signal SCLK_CMD and a reference clock signal SCLK_DLL, at least partially in response to the clock signal CK and the complementary clock signal CKB. The system clock signal SCLK_CMD and the reference clock signal SCLK_DLL may be synchronized with each other or in phase with each other. Clock input buffer 210 can at least partially enable or disable the provision of the reference clock signal SCLK_DLL in response to the enable signal Rdi. Command input buffer 211 receives a first signal (which may also be referred to herein as the command signal CMD), a reference voltage VREF, and a complementary signal RESETB or a clock enable signal CKE. Command input buffer 211 provides the command signal CMD to command decoder circuit 220. Command decoder circuit 220 receives the system clock signal SCLK_CMD and the command signal CMD. Command decoder circuit 220 decodes the command on the command signal CMD in response to the system clock signal SCLK_CMD to provide a pulse on a second signal (which may also be referred to herein as the command delay line input signal RdClk). As described earlier, command decoder circuit 220 can provide the enable signal Rdi in response to a command signal for a READ operation.

[0022] Command delay adjustment circuit 230 may include a DLL clock path and a command path. The DLL clock path may include a delay line circuit 241 for the clock signal. The command path includes a second circuit 231 (which may also be referred to herein as a clock synchronization circuit), a delay line circuit 240 for the command signal, and a third circuit 260 (which may also be referred to herein as a QED circuit). Command delay adjustment circuit 230 further includes a selector control signal generator circuit 232, a copy of the DLL clock path 251, a phase detector 270, and a delay control circuit 280 (which may also be referred to herein as a DLL control circuit). The copy of the DLL clock path 251, the phase detector 270, and the DLL control circuit 280 together with the delay line 241 for the clock signal form the DLL circuit. Clock synchronization circuit 231 receives the command delay line input signal RdClk from command decoder circuit 220, the system clock signal SCLK_CMD from clock input buffer 210, and shift loop parameters X (X[3:0]) from selector control signal generator circuit 232. A clock synchronization circuit 231 is provided to absorb the time delay tDec caused by command decoding and latching in the command decoder circuit 220. The clock synchronization circuit 231 synchronizes the rising edge of the command delay line input signal RdClk with the rising edge of the system clock signal SCLK_CMD and provides a third signal (which may also be referred to herein as the clock-synchronized read signal RdClk_shift). A selector control signal generator circuit 232 can provide shift cycle parameters X (X[3:0]) to the clock synchronization circuit 231 and the QED circuit 260. The shift cycle parameter X represents the number of clock cycles to be shifted to absorb the time delay tDec (e.g., up to three clock cycles in this embodiment). In some embodiments, the shift cycle parameter X may represent more than three clock cycles. The selector control signal generator circuit 232 receives the N value (which will be described in detail later) and the predetermined CL value (which may be a frequency-dependent value) from the DLL control circuit 280, and provides X in the DLL reset sequence or DLL update sequence by assigning an extra period “CL-N” to the shift cycle parameter X (X[3:0]) using a subtractor.

[0023] Delay lines 240 and 241 include adjustable delay circuitry. Delay line 240 receives a clock-synchronized read signal RdClk_shift and a tap signal (dTap[x:0]) from DLL control circuitry 280 and provides a fourth signal (which may also be referred to herein as the delayed read signal RdDll). DLL control circuitry 280 further provides an N value, which represents the timing relationship between the reference clock signal SCLK_DLL and the feedback clock signal SCLK_DLL_fb. The N value may be the number of clock cycles used to achieve a lock condition in which the reference clock signal SCLK_DLL and the feedback clock signal SCLK_DLL_fb are in phase. After the lock condition is achieved, the N value can be provided to selector control signal generator circuitry 232 and QED circuitry 260. QED circuitry 260 synchronizes the delayed read signal RdDll from delay line 240 with the DLL clock signal DllClk from delay line 241. QED circuit 260 uses the values ​​of N and CL, as well as the shift cycle parameter X, to adjust the waiting time of the delayed read signal RdDll. QED circuit 260 provides a fifth signal (which may also be referred to herein as the read activation signal).

[0024] Phase detector 270 detects the phase difference between the feedback clock signal SCLK_DLL_fb and the reference signal SCLK_DLL through model delay and provides the detected phase difference to DLL control circuit 280. Based on the phase difference between the reference signal SCLK_DLL and the feedback clock signal SCLK_DLL_fb, DLL control circuit 280 can adjust the delays of delay lines 240 and 241 so that the rising edge of the feedback clock signal SCLK_DLL_fb is synchronized with the rising edge of the reference clock signal SCLK_DLL. DLL control circuit 280 controls delay lines 240 and 241 to have substantially the same delay. To provide latch margin between the DLL clock signal DllClk from delay line 241 and the delayed read signal RdDll in QED circuit 260, the rising edge of the reference clock SCLK_DLL and the rising edge of the clock synchronization read signal RdClk_shift are controlled to be synchronized before delay line 240. By including clock synchronization circuit 231, the two delay lines 240 and 241 can use the same tap signal dTap[x:0] to have the same delay. Therefore, the rising edge timing of the reference clock signal SCLK_DLL can be synchronized with the rising edge of the clock-synchronized read signal RdClk_shift by adding clock synchronization circuit 231 to the command path used for data transmission.

[0025] Figure 3 This is a block diagram of a clock synchronization circuit according to an embodiment of the present invention. For example, the clock synchronization circuit 30 may be... Figure 2The clock synchronization circuit 231 is located on the command path. The clock synchronization circuit 30 is a first-in-first-out (FIFO) circuit that receives the command delay line input signal RdClk, the system clock signal SCLK_CMD, and the shift loop parameters X (X[3:0]). The clock synchronization circuit 30 includes a counter circuit 310, multiple decoder circuits 320 and 321, an input pointer register 330 containing multiple units, and an output pointer register 331 containing multiple units. The multiple decoders 320 and 321 may be four-bit decoders. The FIFO clock signal can be generated by using the counter circuit 310. In some embodiments, the counter circuit 310 may be a Gray code counter; however, in other embodiments, other types of counters may be used as the counter circuit 310. In this embodiment, the counter circuit 310 may be a two-bit counter circuit and is shared between the input pointer register 330 and the output pointer register 331. The clock synchronization circuit 30 may further include a delay circuit 340 located at the output node of the counter circuit 310. This delay circuit, in response to the output signal of the counter circuit 310, provides a delayed counter signal to the decoder circuit 320. The delay circuit 340 compensates for the waiting time between the system clock signal SCLK_CMD and the command delay line input signal RdClk, which is equivalent to the sum of "tDec + tSU", where tSU is the setting time of the command delay line input signal RdClk and tDec is the time delay caused by command decoding and latching in the command decoder circuit 220. The delay circuit 340 is located on the command path, not on the DLL clock path; therefore, the delay circuit 340 does not increase the jitter in the reference clock signal SCLK_DLL, thus improving the margin of the RMT.

[0026] Each cell of the input pointer register 330 may contain two latches to achieve lower power consumption, as will be described in more detail later. In other embodiments, the cells of the input pointer register 330 may be flip-flops. For example, each of cells [0] to [3] of the input pointer register 330 receives a corresponding pointer input signal PI from the decoder circuit 320. <0> arrive <3> And the command delay line input signal RdClk. For example, each of the cells [0] to [3] of the input pointer register 330 can respond to the corresponding pointer input signal PI. <0> arrive <3> The activation of the command delay line input signal RdClk is received. The input pointer register 330's cells [0] to [3] will output the signal (e.g., the pointer signal RdClk_Out). <0> arrive <3> The shift cycle parameter X (X[3:0]) is provided to selector 350. Selector 350 receives the shift cycle parameter X (X[3:0]) as a selector control signal and selects a path in response to the shift cycle parameter X (X[3:0]). The cells of output pointer register 331 can be flip-flops. Decoder circuit 321 receives the system clock signal SCLK_CMD and the output signal from counter circuit 310, and outputs multiple corresponding pointer signals PO. <0> arrive <3> Units [0] to [3] of the output pointer register 331 are provided. Units [0] to [3] of the output pointer register 331 respond to the shift loop parameter X and the pointer output signal PO. <0> arrive <3> Signals are received from selector 350 by selectively coupling a cell of input pointer register 330 to a corresponding cell of output pointer register 331. Output pointer register 331 responds to signals from selector 350 and pointer output signal PO. <0> arrive <3> The clock-synchronized read signal RdClk_shift is provided via the OR circuit 360. For example, each of the cells [0] to [3] of the output pointer register 331 can respond to the corresponding pointer output signal PO. <0> arrive <3> The activation of the clock-synchronized read signal RdClk_shift is provided. The clock-synchronized read signal RdClk_shift can be provided to the delay line, for example, provided to... Figure 2 The delay line is 240. The clock-synchronized read signal RdClk_shift can be synchronized with the SCLK_CMD signal.

[0027] Figure 4A This is a diagram of the input pointer register units in a clock synchronization circuit according to an embodiment of the present invention. Units [0] 530a, [1] 530b, [2] 530c and [3] 530d can be Figure 3Cells [0] to [3] of the input pointer register 330 in the clock synchronization circuit 30. Cells 530a, 530b, 530c and 530d can receive the command delay line input signal RdClk and can respond to the pointer input signal PI respectively. <0> To PI <3> Furthermore, a pointer signal RdClk_Out is provided. <0> arrive <3> Each of units 530a, 530b, 530c, and 530d contains two latches. For example, unit [0] 530a contains an AND gate 51a and latches 52a and 52b. Latch 52a may contain two NAND gates 521 and 522, and latch 52b may contain two NAND gates 523 and 524. Similarly, unit [1] 530b contains an AND gate 51b and latches 52c and 52d. Latch 52c may contain two NAND gates 525 and 526, and latch 52d may contain two NAND gates 527 and 528.

[0028] Figure 4B This is according to an embodiment of the present invention. Figure 4A Timing diagram of the signals in the input pointer register. Pointer input signal PI <0> To PI <3> This is a pulse signal with a pulse width of 1T, having a command delay line input signal RdClk, where T is one clock cycle. The pointer input signal PI... <0> To PI <3> By PI <0> PI <1> PI <2> PI <3> The order is activated alternately, and determined by the decoder circuitry (e.g., Figure 3 The decoder circuit 320 in the middle is provided.

[0029] For example, unit [0]530a receives the pointer input signal PI. <0> The NAND gate 522 in latch 52a provides signal En1. <0> The signal En1 <0> Responding to the pointer input signal PI at time T1 and time T3 respectively <0> The NAND gate 521 outputs a signal EnF1, which has both rising and falling edges. <0> Invalid (e.g., at logic low). NAND gate 521 provides signal EnF1. <0> The signal EnF1 <0> Responding to signal En1 at time T3 <0> It has a rising edge and a falling edge, and at time T4 it has a rising edge in response to the falling edge of the command delay line input signal RdClk.

[0030] Signal En2 <0> and pointer input signal PI <0> NAND gate 524 is provided to latch 52b. NAND gate 524 in latch 52b provides signal EnF2. <0> The signal EnF2 <0> The output signal En2 of NAND gate 523 before time T3. <0> The logic level is low and further responds to the pointer input signal PI from time T3. <0> The signal is valid when the logic level is low (e.g., when the logic level is high). The NAND gate 523 in latch 52b provides the signal En2. <0> The signal En2 <0> The response to signal EnF1 is at time T3 and time T4 respectively. <0> The signal EnF2 has both rising and falling edges. <0> It is valid (e.g., at logic high level "high"). AND gate 51a receives the pointer input signal PI. <0> and signal En2 <0> And provide an invalid pointer signal RdClk_Out (e.g., at logic low "low"). <0> .

[0031] At the same time, unit [1]530b receives pointer input signal PI <1> The NAND gate 526 in latch 52c provides signal En1. <1> The signal En1 <1> It has a falling edge at time T4 in response to the falling edge of the command delay line input signal RdClk, and at time T5 in response to the pointer input signal PI. <1> It has a rising edge and a falling edge. NAND gate 525 provides signal EnF1. <1> The signal EnF1 <1> At times T2 and T4 respectively, it responds to the rising and falling edges of the command delay line input signal RdClk, thus having a falling edge and a rising edge, while signal En1... <1> Valid before time T4 (e.g., at logic high). Signal En2 <1> and pointer input signal PI <1> The NAND gate 528 in latch 52d is provided. The NAND gate 528 in latch 52d provides the signal EnF2. <1> The signal EnF2 <1> Responding to the pointer input signal PI at time T3 and time T5 respectively <1> The latch 52d has both rising and falling edges, and thus has falling and rising edges. The NAND gate 527 in latch 52d provides signal En2. <1> The signal En2 <1> In response to signal EnF1 <1> It has a falling edge and a rising edge and responds to the signal EnF2 <1> It has a rising edge and a falling edge. The AND gate 51b receives the pointer input signal PI. <1> and signal En2 <1> And provide the pointer signal RdClk_Out <1> The pointer signal RdClk_Out <1> It has a rising edge at time T3 and a falling edge at time T5.

[0032] Therefore, in Figure 4BIn this example, the command delay line input signal RdClk can be generated by the pointer input signal PI. <1> Capture. As described above, latches 52a and 52c are captured via pointer input signal PI. <0> and <1> The rising edge of the command delay line input signal RdClk is captured, and latches 52b and 52d provide a pulse width of 1T.

[0033] Figure 5 This is a circuit diagram of a command decoder circuit in a device including a command delay adjustment circuit according to an embodiment of the present invention. The command decoder circuit 70 can latch the command on the command signal CMD using a clock signal GCLK based on the system clock signal SCLK_CMD before and after command decoding. In the command decoder circuit 70, the command signal CMD is provided to a buffer gate 73 having a delay d1. The system clock signal SCLK_CMD is provided to a delay unit 71 to provide a delay d2, which is approximately equal to the delay d1 of the buffer gate 73, and the delay unit 71 provides the clock signal GCLK. A flip-flop 74 latches the delayed command signal from the buffer gate 73 using the clock signal GCLK. The output signal from the flip-flop 74 is provided to the decoder circuit 75. The decoder circuit 75 can decode the command based on the output signal from the flip-flop 74 and provide a signal (for example, a read signal) in response to the output signal. A flip-flop 76 latches the signal from the decoder circuit 75 using the clock signal GCLK' and provides an internal read signal Rd. Delay unit 72, with a delay of d3, receives the clock signal GCLK and provides the clock signal GCLK'. The delay d3 of delay unit 72 is equivalent to the delay caused by flip-flop 74, decoder circuit 75, and flip-flop 76. Flip-flop 77 latches the internal read signal Rd using the clock signal GCLK' and provides the enable signal Rdi to the clock input buffer 210. Buffer gate 78, with a delay of d4, receives the internal read signal Rd and provides the command delay line input signal RdClk to... Figure 2 The clock synchronization circuit 231 of the command delay adjustment circuit 230 is used. Therefore, a time delay tDec, approximately the sum of delays d1, d3, and d4, is provided to the command delay line input signal RdClk. The clock synchronization circuit 231 is configured to absorb the time delay provided to the command delay line input signal RdClk.

[0034] Figure 6 This is a timing diagram of signals in a device including a command delay adjustment circuit according to an embodiment of the present invention. After the DLL is reset or updated, the clock signal CK is provided to... Figure 2The device 200 has a clock input buffer 210. The clock signal CK is a clock pulse signal containing a rising edge at T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, ... T16, T17, etc. The clock input buffer 210 provides a system clock signal SCLK_CMD with a delay tIB at its clock input buffer 210 in response to the clock signal CK. When a READ command is issued at T0, the command input buffer 211 receives the READ command on the command signal CMD and provides the command signal CMD to the command decoder circuit 220. The system clock signal SCLK_CMD has a rising edge with a delay tIB in response to the rising edge of the clock signal CK at T0. The rising edge of the clock signal GCLK has a delay d2 relative to the rising edge of the system clock signal SCLK_CMD due to the delay unit 71, the delay being equivalent to... Figure 5 The delay d1 is at buffer gate 73. The enable signal Rdi has a rising edge with a delay d3 relative to the rising edge of the clock signal GCLK. The command delay line input signal RdClk has a delay d4 relative to the enable signal Rdi caused by buffer gate 78. Therefore, the command delay line input signal RdClk has a delay "tDec(=d2+d3+d4)". After the read operation, the enable signal Rdi can be reset by the burst end signal (not illustrated). In the clock synchronization circuit 30, the delay circuit 340 provides the delay "tDec+tSU" from the system clock signal SCLK_CMD to the pointer input signal PI<3:0>. Figure 6 In the timing diagram, the pointer input signal PI <0> At T0, there is a delay of "tDec+tSU" relative to the rising edge of the system clock signal SCLK_CMD. Therefore, the pointer input signal PI <0> It has a delay tSU relative to the command delay line input signal RdClk, the delay being the setting time of the command delay line input signal RdClk.

[0035] For example, in Figure 6In the timing diagram, the shift cycle parameter X in this example is three, which means that the RdClk_shift signal has a three-cycle delay relative to the corresponding pulse of the system clock signal SCLK_CMD. This delay only occurs when the pointer input signal PI is activated. <0> Then activate the pointer output signal PO <3> Pointer output signal PO <2> To PO <0> It can remain in an invalid state (e.g., at a logic low level). Therefore, in response to the pointer output signal PO... <3> The RdClk_shift signal is activated. The feedback clock signal SCLK_DLL_fb has a delay relative to DllClk, which is the sum of the delays at clock input buffer 210 (tIB), tree 290 (tTREE), and output buffer 295 (tOB). In this example, N is five, meaning that the feedback clock signal SCLK_DLL_fb has a five-cycle delay relative to the corresponding pulse of the system clock signal SCLK_CMD. For example, after the delay line 240 with delay tDL, the delayed read signal RdDll is latched using the falling edge of the DLL clock signal DllClk in QED circuit 260. To ensure the latch margin "tlat" between the DLL clock signal DllClk in QED circuit 260 and the delayed read signal RdDll, the rising edge of the reference clock signal SCLK_DLL can be synchronized with the rising edge of the clock-synchronized read signal RdClk_shift via clock synchronization circuit 231, as described earlier. The QED circuit 260 synchronizes the delayed read signal RdDll with the DLL clock signal DllClk by shifting the delayed read signal RdDll for a total of (CL-NX) cycles. Therefore, the output data on the DQ signal has a total delay of “tTree+tOB+(CL-NX)*T” relative to the DLL clock signal DllClk.

[0036] Those skilled in the art will further appreciate that the various illustrative logic blocks, configurations, modules, circuits, and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software executed by a processor, or a combination of both. The various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in accordance with their functionality. While those skilled in the art may implement the described functionality in varying ways for each particular application, such implementation decisions should not be construed as departing from the scope of the invention.

[0037] The foregoing description of the disclosed embodiments is provided to enable those skilled in the art to make or use the disclosed embodiments. Various modifications to these embodiments will readily become apparent to those skilled in the art, and the principles defined herein can be applied to other embodiments without departing from the scope of the invention. Therefore, the invention is not intended to be limited to the embodiments shown herein, but is to be endowed with the widest possible scope consistent with the principles and novel features as defined by the appended claims.

Claims

1. A semiconductor device comprising: A first circuit is configured to respond to a first clock signal to latch a first signal, and the first circuit is configured to provide a second signal; A second circuit coupled to the first circuit to latch the second signal, the second circuit being configured to provide a third signal based on the second signal in response to a first output timing signal that is substantially in phase with the first clock signal; and A clock input buffer circuit, configured to generate the first clock signal in response to an enable signal. The first circuit is coupled to the clock input buffer circuit and further configured to provide the enable signal to the clock input buffer, wherein the first circuit is configured to decode the first signal to provide the second signal.

2. The semiconductor device of claim 1, wherein the first circuit is a command decoder circuit and the first signal includes a command signal.

3. The semiconductor device according to claim 1, further comprising: A first delay circuit is configured to receive a second clock signal that is substantially in phase with the first clock signal, and is further configured to provide a third clock signal by delaying the second clock signal through an adjustable first delay. A second delay circuit, coupled to the second circuit and configured to provide a fourth signal by delaying the third signal through an adjustable second delay; and A delay control circuit configured to adjust the first delay of the first circuit and the second delay of the second delay circuit to make them substantially equal.

4. The semiconductor device according to claim 3, further comprising: A third circuit, coupled to the second delay circuit, is configured to provide a fifth signal by delaying the fourth signal in response to the third clock signal and wait time information; and An output buffer, coupled to the third circuit, is configured to be activated in response to the fifth signal and further configured to operate in response to the third clock signal.

5. The semiconductor device of claim 1, wherein the second circuit is further configured to latch the second signal in response to a first input signal that is phase-delayed from the first clock signal.

6. The semiconductor device according to claim 5, The second circuit further includes: A counter circuit configured to receive the first clock signal and further configured to provide a plurality of timing control signals in response to the first clock signal; A third delay circuit is coupled to the counter circuit and configured to provide a plurality of second input timing signals by delaying the plurality of timing control signals; A first decoder, coupled to the third delay circuit and configured to provide a first input timing signal by decoding the plurality of second input timing signals; and A second decoder is coupled to the counter circuit and configured to provide the first output timing signal by decoding the plurality of timing control signals.

7. The semiconductor device of claim 6, wherein the third delay circuit is configured to represent a substantially constant first delay.

8. The semiconductor device according to claim 6, wherein The first decoder is further configured to provide a third input timing signal by decoding the plurality of second input timing signals. The second decoder is further configured to provide a second output timing signal by decoding the plurality of timing control signals, and The second circuit further includes: A first input latch circuit and a second input latch circuit are coupled together to the first circuit and configured to latch the second signal in response to the first input timing signal and the second input timing signal, respectively. A first output latch circuit and a second output latch circuit are respectively coupled to a first input latch circuit and a second input latch circuit and configured to output the third signal in response to the first output timing signal and the second output timing signal, respectively. and A selector circuit includes a first input node and a second input node respectively coupled to the first input latch circuit and the second input latch circuit, and a first output node and a second output node respectively coupled to the first output latch circuit and the second output latch circuit. The selector circuit is configured to couple the first input latch circuit and the second input latch circuit to the first output latch circuit and the second output latch circuit in response to a selector control signal.

9. The semiconductor device according to claim 8, further comprising: A third circuit, coupled to the second circuit and configured to provide the selector control signal in response to waiting time information.

10. A method for memory operations, comprising: Provides the system clock signal; The command signal is latched in response to the system clock signal; The signal is provided based on decoding the command signal; The signal is latched in response to the system clock signal; and A clock synchronization read signal is provided in response to wait time information. The waiting time information used to provide the clock synchronization read signal is the waiting time between the system clock signal and the clock synchronization read signal, and the clock synchronization read signal is provided based on the command signal and the signal latched in response to the system clock signal.

11. The method of claim 10, wherein the system clock signal is based on an external clock signal.

12. The method of claim 10, wherein the clock synchronization read signal is responsive to a shift loop parameter in response to the waiting time information.

13. The method of claim 10, wherein latching the command signal in response to the system clock signal comprises: The command signal is latched in response to a first clock signal that is in response to the system clock signal; In response to a read command or write command on the command signal, a read signal or write signal is provided as an output signal; The read signal or the write signal is latched in response to a second clock signal that is in response to the first clock signal; Provide the latched read signal or the latched write signal as an internal signal; The internal signal is latched in response to the second clock signal; and An enable signal is provided in response to the latched internal signal.

14. The method of claim 13, wherein providing the system clock signal comprises: A reference clock signal is provided in response to the enable signal.

15. The method of claim 14, wherein providing the system clock signal comprises: The reference clock signal and the system clock signal are provided based on an external clock signal.

16. The method of claim 10, wherein latching the signal in response to the system clock signal comprises: Receive the system clock signal; A plurality of first timing control signals are provided in response to the system clock signal; Provide a plurality of second timing control signals having a predetermined delay with the system clock signal; and A pointer input signal is provided by decoding the plurality of second timing control signals, and The clock synchronization read signal provided in response to the waiting time information includes: Receive the system clock signal and the plurality of first timing control signals, and A pointer output signal is provided in response to the system clock signal by decoding the plurality of first timing control signals.

Images