Dram having dual-layer capacitor structure, semiconductor device and method of manufacturing the same

Abstract

The present application relates to a memory cell structure, a memory and a semiconductor device including the memory, the memory cell comprising: a semiconductor substrate; a trench capacitor on the semiconductor substrate; and a stacked capacitor above the trench capacitor. With the memory of the dual-layer capacitor structure in the present application, a substantial increase in storage capacity is achieved under the condition of a smaller unit size area (4F 2 ).

Description

Technical Field

[0001] This application relates to DRAM with a double-layer capacitor structure and a method for manufacturing the same, as well as semiconductor devices, electronic devices and methods for manufacturing the same including the DRAM. Background Technology

[0002] A typical semiconductor device includes multiple memory cell arrays and multiple sense amplifier arrays. The multiple memory cell arrays have multiple unit cells for storing and outputting data according to an address, and the multiple sense amplifier arrays are used to amplify and output the data signal output from the cell array.

[0003] To rapidly improve the integration and scalability of memory, the integration density of semiconductor devices is constantly increasing, while the design size of semiconductor devices is continuously shrinking. To address the challenges of increasing integration density, increasing net die size, improving memory performance, and reducing manufacturing costs, a vertical-type gate-around transistor (SGT) has been proposed. This SGT features a pillar-shaped semiconductor layer formed on a semiconductor substrate, with gates formed around the sidewalls of the pillar-shaped semiconductor layer. Specifically, a gate-around transistor memory cell is as follows: Figure 1 As shown, the drain 11 is disposed between the word line (WL) and the bit line (BL). A channel 12 and a gate insulator 13 surrounding the channel 12 are disposed within the word line WL above the drain 11. The source 14 is disposed above the channel 12 and the gate insulator 13, and a capacitor 15 is disposed above the source 14, with its upper part grounded. Here, the drain 11, the gate insulator 13, and the source 14 form a transistor, and the transistor and the capacitor 15 form a memory cell 10, which is vertically formed at the intersection of the bit line BL and the word line WL.

[0004] When using the aforementioned SGT-type memory cells to form DRAM (Dynamic Random Access Memory), because the drain, gate, and source are arranged vertically in the SGT, a cross-point type memory cell array can be formed, so theoretically, 4F can be achieved. 2 (F is the minimum distance between fine patterns, representing the minimum critical dimension) cell size. Therefore, compared to using a cell with 6F... 2 Or 8F 2Compared to existing planar transistor DRAM, the cell size can be significantly reduced.

[0005] The aforementioned memory cell is a typical 1T / 1C embedded DRAM cell, where one T (Transistor) corresponds to one C (Capacitor). Each bit line BT has a gate structure and a capacitor structure. Although this technology can reduce the area occupied by the memory cell, it does not increase the effective area of ​​the capacitor, i.e., increase the data storage capacity. Summary of the Invention

[0006] The objective of this application is achieved through the following technical solution:

[0007] According to one or more embodiments, this application discloses a storage cell structure, including:

[0008] Semiconductor substrate;

[0009] A trench capacitor located within the semiconductor substrate;

[0010] A first gate word line extending along a first direction;

[0011] A bit line extending in a second direction above the first gate word line;

[0012] A second gate word line extending above the bit line along the first direction;

[0013] Stacked capacitors located above the second gate word line;

[0014] The vertical active region is embedded in the substrate and electrically connected to the trench capacitor, the first gate word line, the bit line, the second gate word line, and the stacked capacitor, respectively.

[0015] According to one or more embodiments, this application also discloses a memory structure including a plurality of memory modules, wherein the memory modules are composed of the memory cell structure described above.

[0016] According to one or more embodiments, this application also discloses a method for manufacturing a memory cell structure, which includes the following process steps:

[0017] A semiconductor substrate is provided, and a trench capacitor is formed within the semiconductor substrate;

[0018] A first gate word line is formed above the substrate along a first direction;

[0019] A bit line is formed above the first gate word line along the second direction;

[0020] A second gate word line is formed above the bit line along a first direction;

[0021] A vertical active region is formed at the intersection of the first gate word line, the second gate word line, and the bit line;

[0022] A stacked capacitor is formed above the active region.

[0023] According to one or more embodiments, this application also discloses semiconductor devices, electronic devices, etc., that include the memory structure described above or that include the memory structure prepared by the manufacturing method described above.

[0024] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description, or some features and advantages may be inferred from the description or determined without question, or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0025] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0026] Figure 1 It has 4F 2 A schematic diagram of a 1T / 1C storage cell structure;

[0027] Figure 2 This is a planar schematic diagram of a storage cell structure with a double-layer capacitor structure in an embodiment of this application;

[0028] Figure 3 This is a three-dimensional schematic diagram of a storage cell structure with a double-layer capacitor structure according to an embodiment of this application;

[0029] Figure 4 This is a schematic diagram of a storage module composed of multiple storage cell structures with double-layer capacitor structures according to an embodiment of this application;

[0030] Figure 5 This is a schematic diagram of the connection structure between storage modules in an embodiment of this application. Detailed Implementation

[0031] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are shown. However, the present application is not limited to the embodiments set forth herein. Rather, these embodiments are provided to thoroughly and completely illustrate and fully convey the scope of the present application to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. The same numerals throughout the text identify the same elements. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0032] The terminology used herein is for the purpose of detailed description of embodiments only and is not intended to limit the application. As used herein, unless explicitly stated otherwise, the singular forms “a,” “the,” and “the” also include the plural forms. It should also be understood that the term “comprising” as used in the specification indicates the presence of the stated feature, integral, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0033] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extends to another element," it can be directly on the other element, directly extended to the other element, or there may be intermediate elements. Conversely, when an element is referred to as "directly on another element" or "directly extended to another element," there are no intermediate elements. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0034] It should be understood that although the terms first, second, etc., may be used herein to describe different elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts are not limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the spirit of this application, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0035] Furthermore, relative terms, such as “below” or “bottom” and “above” or “top”, are used here to describe the relationship between one element and another as shown in the accompanying drawings. It should be understood that relative terms include not only the orientations described in the drawings but also different orientations of the device. For example, if a device in the drawing is flipped, an element described as being below another element becomes above another element. Therefore, the exemplary term “below” includes both the “below” and “above” orientations depending on the specific orientation of the drawing. Similarly, if a device in the drawing is flipped, an element described as “below other elements” or “under other elements” is oriented above other elements. Therefore, the exemplary term “below” or “under…” includes both the above and below orientations.

[0036] Embodiments of this application are described herein with reference to illustrative cross-sectional views (and / or plan views) illustrating idealized embodiments. Similarly, deviations from the schematic shapes are expected due to factors such as manufacturing processes and / or tolerances. Therefore, the embodiments of this application are not to be construed as limitations on the specific shapes of the areas illustrated herein, but rather to include shape deviations caused, for example, by manufacturing processes. For instance, etched areas illustrated as or described as rectangular typically have circular or curved features. Thus, the areas illustrated are schematic in nature, and their shapes do not represent the precise shapes of the device areas nor limit the scope of this application.

[0037] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms, such as those defined in common dictionaries, should be interpreted as consistent with their meaning in relevant art literature and, unless expressly defined herein, not as idealized or overly formal. Those skilled in the art will understand that references to structural or functional components configured adjacent to another component may have overlapping or subordinate parts.

[0038] This application discloses a memory cell structure with double-layer capacitors and its manufacturing method. The double-layer capacitors can be vertically arranged on the same vertical line. The lower capacitor can be a trench capacitor, and the upper capacitor can be a stacked capacitor. This is just one example, and the application is not limited to this. One embodiment of this application, with its specific memory cell structure and manufacturing process detailed below:

[0039] This application embodiment illustrates a semiconductor device for a memory composed of memory cells with double-layer capacitors. This semiconductor device can be used in, for example, some electronic device, such as a smartphone, computer, tablet computer, wearable smart device, artificial intelligence device, power bank, etc. Figure 2As shown, the memory cell comprising the memory with a double-layer capacitor can first be provided with a semiconductor substrate (not shown). The substrate may include, within the memory cell substrate, a plurality of trench type capacitors 100, such as pillar type capacitors, and above the memory cell, a plurality of stack type capacitors 200, such as cylindrical type capacitors, and a first gate word line 300 (1 st Word line), second gate word line 400 (2 nd The active region 600 includes a gate word line 300, a bit line 500 located between the two gate word lines, and a vertical active region 600. The vertical active region 600 can be partially buried in the substrate and can be electrically connected to the trench capacitor 100, the first gate word line 300, the bit line 500, the second gate word line 400, and the stacked capacitor 200, respectively. The gate of the first gate word line 300 can be a vertical 3D gate. The first gate word line 300 can extend along a first direction, and the vertical 3D gate of the first gate word line 300 can be perpendicular to the active region 600 at its channel, thereby forming a vertical active region 600. Figure 1 The example shown is a gate-all-around transistor; similarly, the gate of the second gate word line 400 can also be a vertical 3D gate. The second gate word line 400 can also extend along the first direction, and the vertical 3D gate of the second gate word line 400 can be perpendicular to the active region 600 at its channel, thereby forming a structure similar to... Figure 1The diagram shows a gate-all-around transistor. The entire semiconductor device can be partially buried in the substrate and partially located in a dielectric layer above the substrate. In some embodiments of the invention, the trench capacitor 100 is buried in the substrate, while the first gate word line 300, bit line 500, second gate word line 400, and stacked capacitor 200 are all located above the substrate and surrounded by a dielectric layer. The structure of the first gate word line 300 and the second gate word line 400 may include a gate dielectric layer and a gate conductor layer. The gate dielectric layer may extend along the sidewalls of the active region, and in some embodiments, it may also extend along the dielectric layer at a height substantially level with the bottom of each word line. The gate conductor layer extends above the sidewalls and bottom walls of the respective gate dielectric layer. Of course, the vertical 3D gate is not limited to the above structure and can be any other suitable structure; in this embodiment, for cost savings and ease of fabrication, the first and second gate word lines 400 share the active region 600. The trench capacitor 100 can be electrically connected to the active region 600 via a first landing pad (not shown), while the stacked capacitor 200 can be electrically connected to the active region 600 via a second landing pad. The middle portion of the active region 600 is electrically connected by perpendicularly intersecting the center of the bit line 500. The first gate word line 300 and the second gate word line 400 can be located in the same plane (i.e.,...). Figure 2 Parallel lines extending along the first direction (as shown in the paper orientation), and bit lines extending along the second direction can intersect the plane exactly perpendicularly (i.e., bit lines 500 are perpendicular to the plane). Figure 2 As shown in the paper orientation (where the first direction and the second direction intersect perpendicularly), the intersection point of the bit line 500 and this plane can be exactly equidistant from the first gate word line 300 and the second gate word line 400. With the above arrangement, the trench capacitor 100, the active region 600, the vertical 3D gates of the first gate word line 300 and the second gate word line 400, and the stacked capacitor 200 can be substantially located on the same straight line, which lies within the aforementioned plane and is perpendicular to the vertical 3D gate of the first gate word line 300 and the second gate word line 400. In this embodiment, the trench capacitor 100 and the stacked capacitor 200 can have the same storage capacity, but based on their different structures, they can be designed separately to obtain the same storage capacity. In addition, the memory may also include a first metal connection portion 700 and a second metal connection portion 800. The first metal connection portion 700 connects the first gate word line 300 to a metal wiring layer (not shown), while the second metal connection portion 800 connects the second gate word line 400 to a metal wiring layer (not shown). The first metal connection portion 700 and the second metal connection portion 800 may be controlled separately through the metal wiring layer.

[0040] likeFigures 4-5 As shown, this application also provides a memory composed of the above-described memory cells. Specifically, the memory may have multiple memory blocks, each of which may consist of multiple memory cell structures. In the memory, the first word lines between adjacent memory blocks are configured in the same region of the same word line driver region (SWD), and the second word lines between adjacent memory blocks are also configured in the same region of the same word line driver region. The aforementioned word line driver region includes the configured word lines and their corresponding peripheral gates. The configured word lines and their corresponding peripheral gates between adjacent memory blocks form a shared source. Simultaneously, adjacent bit lines of multiple memory cells in a memory block are respectively configured in sense amplifier regions at opposite ends, with one end of the sense amplifiers at opposite ends configured with an odd number of bit lines, and the other end configured with an even number of bit lines. The distances between bit lines, between first word lines, and between first word lines are all the same between storage modules. Furthermore, the lengths of bit lines, first word lines, and second word lines are all the same between storage modules, and the word lines and bit lines form a neat array of the same size.

[0041] Next, the manufacturing process of the above-mentioned memory, as disclosed in an embodiment of this application, will be described in further detail:

[0042] First, a semiconductor substrate can be provided, and ion implantation is performed on the substrate region corresponding to the memory cell location. Then, a trench type capacitor 100 can be formed within the semiconductor substrate, such as a common trench type pillar capacitor. Next, a first landing pad template layer can be formed above the semiconductor substrate, and first landing pads (not shown) can be formed within the first landing pad template layer at positions corresponding to the trench type capacitor 100. Then, a dielectric material can be deposited above the first landing pad template layer to form a dielectric layer, leaving space for the active region to be formed, and the dielectric layer is etched back to the height to which the word line is to be formed. A first word line material layer can then be formed on the dielectric layer, and subsequently, at the positions corresponding to the trench type capacitor 100, the first word line material layer can be etched along a first direction to form a first gate word line 300 extending along the first direction, wherein the gate can be a vertical 3D gate ring structure. The word line material layer mentioned here may include a gate dielectric material layer and a gate conductor material layer. The gate dielectric material layer may extend along the sidewalls of the active region location and the top surface of the etched-back dielectric layer, and similarly, the gate conductor material layer may extend along the sidewalls and bottom wall of the gate dielectric layer. Then, the gate dielectric material layer and the gate conductor material layer may be etched to form the first gate word line 300 by photolithography or other methods. Subsequently, a dielectric layer may be formed above the first gate word line 300. Then, a bit line material layer may be formed above the dielectric layer on the first gate word line. Subsequently, at the corresponding position of the trench capacitor 100, the bit line material layer may be etched along a second direction perpendicular to the first direction to form a bit line 500 extending along the second direction. Then, dielectric material may be deposited again to perform node separation and form a dielectric layer above the bit line 500. Subsequently, a second word line material layer can be formed above the dielectric layer on the bit line 500. Then, at the corresponding position of the trench capacitor 100, the second word line material layer can be etched along the first direction to form a second gate word line 400 extending along the first direction, wherein the gate can be a vertical 3D ring gate structure. The method for forming the second gate word line 400 can refer to the aforementioned method for forming the first gate word line 300, and will not be repeated here.Subsequently, a dielectric layer can be formed above the first gate word line 400; wherein the projections of the first gate word line 300, the second gate word line 400, and the bit line 500 onto the horizontal plane can intersect at the same point, which can correspond to the position of the trench capacitor 100, and the gates of the first gate word line and the second gate word line are both located at the intersection point; subsequently, a dielectric layer can be formed on the second gate word line at the position corresponding to the intersection point of the first gate word line 300, the second gate word line 400, and the bit line 500. Vertical etching is performed at the location to form a through active region 600, allowing the first gate word line 300, the second gate word line 400, and the bit line 500 to share the active region 600, thus saving processing steps. Subsequently, a second landing pad mold layer can be formed above the active region 600, and a second landing pad (not shown) can be formed within the second landing pad mold layer at a position corresponding to the active region 600. Subsequently, a stacked capacitor 200 can be formed above the second landing pad. The structure of the stacked capacitor 200 can, for example, adopt the common manufacturing method of a stacked cylindrical capacitor. After the stacked capacitor 200 is formed, the first word line 300 can be electrically connected to the metal wiring layer through the first metal contact 700, and the second word line 400 can be electrically connected to the metal wiring layer through the second metal contact 800, thereby realizing the communication between the memory cell and the outside.

[0043] The heat dissipation structure of the memory cell in this embodiment is similar to the existing structure, which is easy to design, and the 4F of the memory cell... 2 The word lines and bit lines of the structure are also designed with right angles, allowing the existing SWD / SA design structure to be used directly without any special changes.

[0044] The memory using the double-layer capacitor structure in the embodiments of this application achieves a smaller unit size area (4F). 2 Under these conditions, storage capacity was significantly increased, and the manufacturing process was simplified, reducing costs.

[0045] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0046] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A storage cell structure, comprising: Semiconductor substrate; A trench capacitor located within the semiconductor substrate; A first gate word line extending along a first direction; A bit line extending in a second direction above the first gate word line; A second gate word line extending above the bit line along the first direction; Stacked capacitors located above the second gate word line; The vertical active region partially embedded in the substrate penetrates the first gate word line, the bit line, and the second gate word line, and is electrically connected to the trench capacitor, the first gate word line, the bit line, the second gate word line, and the stacked capacitor, respectively.

2. The storage cell structure according to claim 1, characterized in that: The active region is perpendicular to the first gate word line at its center position, and / or the active region is perpendicular to the second gate word line at its center position.

3. The storage cell structure according to claim 1, characterized in that: The active region is located at the center of the bit line and is perpendicular to the bit line.

4. The storage cell structure according to any one of claims 1-3, characterized in that: The gates of the first gate word line and / or the second gate word line are vertical 3D gate structures.

5. The storage cell structure according to any one of claims 1-3, characterized in that: The trench capacitor and the stacked capacitor have the same storage capacity.

6. The storage cell structure according to claim 5, characterized in that: The trench capacitor is a cylindrical capacitor, and the stacked capacitor is a cylindrical capacitor.

7. The storage cell structure according to any one of claims 1-3, characterized in that: The first gate word line is electrically connected to the first metal connection portion; The second gate word line is electrically connected to the second metal connection portion.

8. A memory structure comprising a plurality of memory modules, wherein the memory modules are composed of a plurality of memory cell structures as described in any one of claims 1-6.

9. The memory structure according to claim 8, characterized in that: The first gate word lines between adjacent memory modules are configured in the same region of the same word line driving region; the second gate word lines between adjacent memory modules are configured in the same region of the same word line driving region.

10. The memory structure according to claim 9, characterized in that: The word line driving region includes the configured word lines and peripheral gates, and the configured word lines and peripheral gates share a source.

11. The memory structure according to claim 9, characterized in that: The adjacent bit lines of the plurality of memory cells of the memory module are respectively arranged in the sensing amplifier regions at opposite ends, and one end of the sensing amplifier at opposite ends is configured with an odd number of the bit lines, while the other end is configured with an even number of the bit lines.

12. The memory structure according to claim 9, characterized in that: The distances between bit lines, between first gate word lines, and between second gate word lines are all the same between the memory modules. The lengths of the bit lines between the memory modules, the lengths of the first gate word lines between the first gate word lines, and the lengths of the second gate word lines between the second gate word lines are all the same.

13. The memory structure according to claim 8, characterized in that: The memory cell structure includes a first metal connection portion and a second metal connection portion. The first gate word line is electrically connected to the first metal connection portion, and the second gate word line is electrically connected to the second metal connection portion. The first metal connection portion and the second metal connection portion are controlled respectively on the metal wiring layer.

14. A method for manufacturing a memory cell structure, comprising the following process steps: A semiconductor substrate is provided, and a trench capacitor is formed within the semiconductor substrate; A first gate word line is formed above the substrate along a first direction; A bit line is formed above the first gate word line along the second direction; A second gate word line is formed above the bit line along a first direction; A vertical active region is formed at the intersection of the first gate word line, the second gate word line, and the bit line; A stacked capacitor is formed above the active region.

15. The manufacturing method according to claim 14, comprising the following process steps: The formation of the first gate word line involves depositing a first word line material layer after depositing a dielectric layer on the substrate, followed by etching the first word line material layer along a first direction to form the first gate word line along the first direction, and then depositing a dielectric layer. The bit line formation involves forming a bit line material layer on a dielectric layer above the first gate word line, then etching the bit line material layer along a second direction to form a bit line along the second direction, followed by depositing a dielectric layer. The formation of the second gate word line involves forming a second word line material layer on a dielectric layer above the bit line, then etching the second word line material layer along a first direction to form the second gate word line along the first direction, followed by depositing a dielectric layer. The formation of the vertical active region involves forming a vertical trench at the intersection of the first gate word line, the second gate word line, and the bit line, and filling the trench to form the active region.

16. The manufacturing method according to claim 14, comprising the following process steps: Before forming the first gate word line, the process further includes forming a first landing pad so that the active region is electrically connected to the trench capacitor via the landing pad.

17. The manufacturing method according to claim 14, comprising the following process steps: Before forming the stacked capacitor, a second landing pad is also formed so that the active region is electrically connected to the stacked capacitor through the second landing pad.

18. The manufacturing method according to any one of claims 14-17, comprising the following process steps: Before forming the trench capacitor, ion implantation is performed on the substrate region at the location corresponding to the storage cell.

19. The manufacturing method according to any one of claims 14-17, comprising the following process steps: After forming the stacked capacitor, the method further includes electrically connecting the storage cell to the metal wiring layer via metal contacts.

20. A semiconductor device comprising the memory structure as described in any one of claims 8-13.

21. An electronic device comprising the semiconductor device as claimed in claim 20.

22. The electronic device of claim 21, wherein the electronic device has DRAM.

23. The electronic device according to claim 21 or 22, wherein the electronic device includes a smartphone, a computer, a wearable smart device, an artificial intelligence device, and a power bank.

24. The electronic device of claim 23, wherein the electronic device comprises a tablet computer.

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