Semiconductor memory structure and method for forming the same

Abstract

The present invention provides a semiconductor memory structure and a method for forming the same, including: forming an isolation structure to surround an active region in a substrate; forming a first trench to separate the active region into a first active region and a second active region; forming a bit line at the bottom of the first trench; forming a word line to surround the first active region and the second active region and be located above the bit line; forming a contact point on the top of the first active region and the second active region in a self-aligned manner; and forming a capacitor on the contact point. By separating the active region with a buried bit line, leakage current between word lines can be reduced.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device, and more particularly to a gate all around (GAA) structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in integrated circuit design and materials have produced generations of integrated circuits, each with smaller and more complex circuits than the previous generation. As integrated circuits have evolved, their geometry has gradually shrunk.

[0003] As integrated circuits shrink in size and DRAM density increases, sub-threshold leakage, gate-induced drain leakage (GIDL), and word line leakage may increase, resulting in a loss of retention time.

[0004] Although existing DRAMs are adequate for their original purpose, they are not satisfactory in all aspects. For example, the loss of retention time caused by leakage current still needs to be improved. Summary of the invention

[0005] Some embodiments of the present invention provide a semiconductor memory structure and a method for forming the same, the method comprising: forming an isolation structure to surround an active region in a substrate; forming a first trench to separate the active region into a first active region and a second active region; forming a bit line at the bottom of the first trench; forming a word line to surround the first active region and the second active region and be located above the bit line; self-aligningly forming contacts at the top of the first active region and the second active region; and forming a capacitor on the contact.

[0006] An embodiment of the present invention also provides a semiconductor memory structure, including: an isolation structure, surrounding a first active region and a second active region, and located on a substrate; a bit line, located under the isolation structure between the first active region and the second active region; a word line, surrounding the first active region and the second active region, and located on the bit line; a contact, located on the first active region and the second active region, and directly contacting the first active region and the second active region; and a capacitor, located on the contact.

[0007] The present application can reduce leakage current between word lines by separating active regions with buried bit lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following will be described in detail with reference to the accompanying drawings. It should be noted that the various characteristic components are not drawn to scale and are only used for illustration. In fact, the size of the components may be enlarged or reduced to clearly show the technical features of the embodiments of the present invention.

[0009] Figure 1 is a perspective view illustrating a semiconductor memory structure according to some embodiments.

[0010] Figures 2A to 2G , Figure 2H-1 , Figure 2I to Figure 2L , Figure 2M-1 The invention is a cross-sectional view showing various stages of forming a semiconductor memory structure according to some embodiments.

[0011] Figure 2H-2 and Figure 2M-2 FIG. 1 is a top view of a semiconductor memory structure according to some embodiments.

[0012] Figure 3 FIG. 5 is a top view of a semiconductor memory structure according to some other embodiments.

[0013]

Figure Number Description

[0014] 100,200,Semiconductor memory structure

[0015] 102. Substrate

[0016] 104. Active Zone

[0017] 104a, first active area

[0018] 104b, second active area

[0019] 106. Bit line

[0020] 106a, Barrier layer

[0021] 106b, conductive layer

[0022] 108. Semiconductor material layer

[0023] 110. Isolation Structure

[0024] 110a. Isolation structure

[0025] 110b. Isolation materials

[0026] 112. Word Line

[0027] 112a, gate dielectric layer

[0028] 112b, Barrier layer

[0029] 112c, conductive layer

[0030] 114. Source / Drain Region

[0031] 116. Capacitor

[0032] 118. Well Area

[0033] 120a, first doping region

[0034] 120b, second doping region

[0035] 122. Top floor

[0036] 124. Cushion

[0037] 126. Groove

[0038] 128. Photoresist

[0039] 130. Lining

[0040] 132. Groove

[0041] 134. Barrier layer

[0042] 136. Groove

[0043] 138. Channel Area

[0044] 140. Groove

[0045] 142. Contact point

[0046] 142a, Barrier layer

[0047] 142b. Conductive materials

[0048] 144. Dielectric layer

[0049] 2-2, Line

[0050] θ, angle

[0051] θ1, angle DETAILED DESCRIPTION

[0052] An embodiment of the present invention provides a dynamic random access memory having a buried bit line, which can block leakage current between word lines. The surrounding gate structure can reduce subthreshold leakage current caused by short channel effect, and the gate does not overlap with the source / drain region, which can also reduce gate-induced drain leakage current. Forming a well region below the bit line can reduce leakage current between the bit lines. In addition, forming contacts above the active area in a self-aligned manner can reduce masking and processes. The capacitors formed are arranged in a honeycomb manner to increase memory density.

[0053] Figure 1FIG. 1 is a perspective view of a semiconductor memory structure 100 according to some embodiments. Figures 2A to 2G , Figure 2H-1 , Figure 2I to Figure 2L , Figure 2M-1 1 is a cross-sectional view illustrating various stages of forming a semiconductor memory structure 100 according to some embodiments. Figure 2A-2G , Figure 2H-1 , Figure 2I to Figure 2L , Figure 2M-1 draw Figure 1 A cross-sectional view of the semiconductor memory structure 100 taken along line 2-2 in FIG. Figure 1 As shown, the semiconductor memory structure 100 includes a substrate 102, on which a first active region 104a and a second active region 104b are formed. A bit line 106 is buried between the first active region 104a and the second active region 104b, and a semiconductor material layer 108 is connected to the substrate 102 below, and an isolation material 110 is used to separate the first active region 104a and the second active region 104b above. A word line 112 surrounds the first active region 104a and the second active region 104b to form a surrounding gate structure, and a source / drain region 114 is located above and below the word line 112, respectively. A capacitor 116 is located above the first active region 104a and the second active region 104b.

[0054] like Figure 1 and Figure 2A As shown, a substrate 102 is provided. The substrate 102 may be a semiconductor substrate, which may include elemental semiconductors such as silicon (Si), germanium (Ge), etc.; compound semiconductors such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), etc.; alloy semiconductors such as silicon germanium alloy (SiGe), gallium arsenic phosphide alloy (GaAsP), aluminum indium arsenic alloy (AlInAs), aluminum gallium arsenic alloy (AlGaAs), indium gallium arsenide alloy (GaInAs), gallium indium phosphide alloy (GaInP), gallium indium arsenic phosphide alloy (GaInAsP), or a combination thereof. In addition, the substrate 102 may also be a semiconductor on insulator (SOI).

[0055] According to some embodiments, Figure 2AAs shown, the substrate 102 is blanket doped to form a well region 118 having a first conductivity type in the substrate 102, and a first doped region 120a having the first conductivity type and a second doped region 120b having a second conductivity type are formed above the well region 118, and the first conductivity type is different from the second conductivity type. In some embodiments, the second doped region 120b is located between the two first doped regions 120a. In some embodiments, the first conductivity type is N-type. In some embodiments, the first conductivity type is P-type. N-type dopants may include phosphorus, arsenic, nitrogen, antimony ions, or combinations thereof. P-type dopants may include boron, gallium, aluminum, indium, boron trifluoride ions (BF3 + ), or a combination of the foregoing.

[0056] Then, if Figure 2A As shown, a top layer 122 is formed on the substrate 102, and a pad layer 124 is formed on the top layer 122. The top layer 122 can serve as a buffer layer between the substrate 102 and the pad layer 124, and the pad layer 124 can serve as an etch stop layer for a subsequent planarization process. In some embodiments, the top layer 122 is an oxide such as silicon oxide. The pad layer 124 can be SiN, SiCN, SiOC, SiOCN, other available materials, or a combination of the above. SiN can be isolated and can serve as a stop layer for subsequent etching. The top layer 122 and the pad layer 124 can be formed by a deposition process, a spin coating process, a sputtering process, or a combination of the above.

[0057] Then, if Figure 2A As shown, a patterning process such as photolithography and etching process is used to form a trench 126 to define the active region 104. In some embodiments, the trench 126 surrounds the active region 104. The patterning process may include coating the photoresist 128 (e.g., spin coating), soft baking, mask alignment, exposing the pattern, post-exposure baking, developing the photoresist 128, cleaning and drying (e.g., hard baking), other suitable techniques, or combinations thereof.

[0058] In some embodiments, the well region 118 is located in the substrate 102 below the active region 104. In some embodiments, the bottom surface of the trench 126 protrudes below the bottom surface of the well region 118.

[0059] Then, if Figure 2B As shown, a liner 130 is conformally formed on the sidewalls and bottom surface of the trench 126. The liner 130 can be used to protect the active region 104 from being damaged in subsequent processes (such as annealing or etching processes). In some embodiments, the liner 130 is made of oxide such as silicon oxide.

[0060] Then, if Figure 2BAs shown, an isolation structure 110a is formed in the trench 126. The isolation structure 110a can be made of silicon nitride, silicon oxide, other dielectric materials, or a combination thereof. In some embodiments, the isolation structures 110a in different areas of the substrate 102 are made of different materials. For example, trenches 126 of different sizes in the substrate 102 are filled with different isolation structure materials. Thereafter, the isolation structure 110a is planarized to expose the upper surface of the pad layer 124 (not shown). The isolation structure 110a can be planarized by a chemical mechanical polishing (CMP) process.

[0061] Then, if Figure 2B As shown, the pad layer 124 is removed. In some embodiments, the pad layer 124 is removed by a wet etching process or a dry etching process. The wet etching process may include using a phosphoric acid (H3PO4) etching solution.

[0062] Then, if Figure 2C As shown, a trench 132 is formed in the active region 104 by a patterning process and an etching process. In some embodiments, the trench 132 separates the active region 104 into a first active region 104a and a second active region 104b. The bottom surface of the trench 132 is located in the well region 118. The process of forming the trench 132 is similar or the same as the process of forming the trench 126, and will not be repeated here.

[0063] Then, if Figure 2D As shown, a barrier layer 134 is conformally formed on the sidewalls and bottom surface of the trench 132, the upper surface of the top layer 122, and the upper surface of the isolation structure 110a. In some embodiments, the barrier layer 134 is made of nitride such as SiN, SiCN, SiOC, and SiOCN. SiN can be used as a barrier layer for a metal such as tungsten in a subsequently formed bit line. In some embodiments, the barrier layer 134 and the isolation structure 110a are made of the same material. Next, the barrier layer 134 on the bottom surface of the trench 132 and the barrier layer 134 on the upper surface of the top layer 122 are removed by a patterning process such as photolithography and etching process to expose the substrate 102 and a portion of the top layer 122 at the bottom of the trench 132. The etching process may include a dry etching process (e.g., reactive ion etching, anisotropic plasma etching, or a combination thereof).

[0064] Then, if Figure 2EAs shown, a semiconductor material layer 108 is deposited at the bottom of the trench 132. In some embodiments, the bottom of the semiconductor material layer 108 is located in the well region 118. In some embodiments, the semiconductor material layer 108 includes polysilicon. Polysilicon can form titanium silicide with Ti in the subsequently formed bit line to reduce resistance, or a combination thereof. Then, an etching process can be performed to etch back the semiconductor material layer 108 to a desired height.

[0065] Then, according to some embodiments, Figure 2E As shown, the bit line 106 is formed on the semiconductor material layer 108 in the trench 132. In some embodiments, the bit line 106 and the semiconductor material layer 108 are located at the bottom of the trench 132. In some embodiments, the bit line 106 includes a barrier layer 106a and a conductive layer 106b. Before forming the conductive layer 106b, the barrier layer 106a may be formed on the sidewall and the bottom of the trench 132 to prevent the conductive material from diffusing into the first active region 104a and the second active region 104b. The material of the barrier layer 106a may be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), other suitable materials, or combinations thereof. The conductive layer 106b includes a metal material (e.g., tungsten, aluminum, or copper), a metal alloy, other suitable materials, or combinations thereof.

[0066] Next, an etching process is performed to etch back the conductive layer 106b and the barrier layer 106a to a desired height to form the bit line 106. In some embodiments, the upper surface of the bit line 106 is lower than the upper surface of the lower first doped region 120a. In some embodiments, the semiconductor material layer 108 is located between the well region 118 and the bit line 106, and directly contacts the well region 118 and the bit line 106.

[0067] In some embodiments, a portion of the well region 118 is located below the bit line 106, and the bottom of the semiconductor material layer 108 below the bit line 106 is located in the well region 118. In this way, the well region 118 and the isolation structure 110a can reduce leakage current between adjacent bit lines 106.

[0068] Then, if Figure 2FAs shown, the trench 132 is filled with an isolation material 110b. Therefore, the bit line 106 is located below the isolation material 110b. In some embodiments, the isolation material 110b and the isolation structure 110a are made of the same material. Therefore, the isolation material 110b and the isolation structure 110a can be regarded as the same isolation structure 110, which surrounds the first active region 104a and the second active region 104b. In some embodiments, the isolation material 110b and the isolation structure 110a include nitrides such as SiN, SiCN, SiOC, SiOCN. SiN can be used as a barrier layer for metals such as tungsten in the bit line 106. The process of filling the isolation material 110b is similar or the same as the process of the isolation structure 110a, and will not be repeated here.

[0069] Then, if Figure 2G As shown, the word line 112 is formed by a patterning process such as photolithography and etching process. First, an etching process is performed to remove the isolation material 110b above the top layer 122 and the top layer 122. The isolation structure 110 on the sidewalls of the first active region 104a and the second active region 104b is further etched to form a trench 136 between the first active region 104a and the second active region 104b and the isolation structure 110. In some embodiments, the trench 136 surrounds the first active region 104a and the second active region 104b. In some embodiments, as shown in FIG. Figure 2G As shown, the bottom of the trench 136 is flush with the bottom of the second doped region 120b, and the isolation structure 110 protrudes above the upper surfaces of the first active region 104a and the second active region 104b. The trench 136 can be formed using an etching process such as a wet etching process, a dry etching process, other suitable techniques, or a combination thereof.

[0070] Then, if Figure 2H-1 As shown, a word line 112 is formed in the trench 136. In some embodiments, the word line 112 includes a gate dielectric layer 112a, a barrier layer 112b, and a conductive layer 112c. The gate dielectric layer 112a is located on a portion of the sidewalls of the first active region 104a and the second active region 104b, the barrier layer 112b is conformally formed on the surface of the first active region 104a, the second active region 104b, and the isolation structure 110 in the trench 136, and the conductive layer 112c fills the space between the barrier layer 112b in the trench 136. In some embodiments, as Figure 2H-1 As shown, the word line 112 is located above the buried bit line 106 .

[0071] In some embodiments, the gate dielectric layer 112a may include silicon oxide, silicon nitride, or silicon oxynitride, a high-k dielectric material (i.e., a dielectric constant greater than 3.9) such as HfO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3, BaTiO3, BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, (Ba, Sr)TiO3, Al2O3, or a combination thereof. The process of forming the barrier layer 112b and the conductive layer 112c of the word line 112 is similar or the same as the process of forming the barrier layer 106a and the conductive layer 106b of the bit line 106, and is not repeated here.

[0072] Figure 2H-2 for Figure 2H-1 FIG. 1 is a top view of the semiconductor memory structure 100. Figure 2H-2 As shown, the word line 112 surrounds the first active region 104a and the second active region 104b to form a surrounding gate structure, thereby increasing the contact area between the word line 112 and the channel region and reducing the subthreshold leakage current caused by the short channel effect.

[0073] It should be noted that, for the sake of distinction, Figure 2H-2 The first active region 104a and the second active region 104b are drawn in different styles. However, the first active region 104a and the second active region 104b have the same structure and material.

[0074] According to some embodiments, Figure 2H-1 As shown, after the conductive layer 112c is filled, an etching process is performed to etch back the gate dielectric layer 112a, the barrier layer 112b, and the conductive layer 112c to expose the top of the first active region 104a and the second active region 104b. Figure 2H-1 As shown, the upper surface and the lower surface of the word line 112 are flush with the upper surface and the lower surface of the second doped region 120b, respectively. Therefore, a channel region 138 having a second conductivity type is formed in the first active region 104a and the second active region 104b surrounded by the word line 112. A source / drain region 114 is formed above and below the channel region 138 in the first active region 104a and the second active region 104b exposed from the word line 112, and is located within the range of the first doped region 120a and has a first conductivity type. Since the word line 112 does not overlap with the source / drain region 114, the gate-induced drain leakage current can be reduced. In addition, since the bit line 106 is buried under the isolation structure 110 between the word lines 112, the adjacent word lines 112 are separated by the isolation structure 110, and therefore, the leakage current between the word lines 112 can be reduced.

[0075] Then, if Figures 2I to 2JAs shown, the trench 136 is filled with an isolation material 110 , and a planarization process such as a chemical mechanical polishing process is performed to etch the isolation material 110 to expose the upper surfaces of the first active region 104 a and the second active region 104 b .

[0076] Afterwards, if Figure 2K As shown, the tops of the first active region 104a and the second active region 104b are etched back by an etching process to form a recess 140. The etching process may include a dry etching process (eg, reactive ion etching, anisotropic plasma etching), a wet etching process, or a combination thereof.

[0077] Next, a metal semiconductor compound layer (not shown) is selectively formed on the top of the first active region 104a and the second active region 104b. The metal semiconductor compound layer can reduce the resistance between the source / drain region 114 and the subsequently formed contact. The metal semiconductor compound layer may include TiSi2, NiSi, CoSi, other suitable materials, or a combination thereof. A metal layer may be first formed on the source / drain region 114, and then an annealing process is performed to react the metal layer with the source / drain region 114 to produce a metal semiconductor compound layer. Thereafter, an etching process is performed to remove the unreacted metal layer, leaving the metal semiconductor compound layer.

[0078] Afterwards, if Figure 2L As shown, a contact 142 is formed in the groove 140. In some embodiments, the contact 142 includes a barrier layer 142a and a conductive material 142b. Figure 2L As shown, the bottom surface of the contact 142 is lower than the top surface of the isolation structure 110. In some embodiments, the contact 142 is located above the first active region 104a and the second active region 104b and directly contacts the source / drain regions 114 of the first active region 104a and the second active region 104b.

[0079] The materials and processes for forming the barrier layer 142a and the conductive material 142b of the contact 142 are similar or identical to the materials and processes for forming the barrier layer 106a and the conductive layer 106b of the bit line 106, and are not repeated here. Figure 2K to Figure 2L The method can form the contact 142 on the first active region 104a and the second active region 104b in a self-aligned manner without requiring additional photomask and patterning processes.

[0080] Then, if Figure 2M-1 As shown, a dielectric layer 144 is formed on the first active region 104a, the second active region 104b and the isolation structure 110. Then, a patterning process such as photolithography and etching is used to form a trench (not shown) in the dielectric layer 144. In some embodiments, the trench in the dielectric layer 144 is aligned with the contact 142.

[0081] Next, a capacitor 116 is formed in the trench in the dielectric layer 144. Thus, a capacitor 116 is formed on the contact 142. The capacitor 116 may include a bottom electrode, a top electrode, and a dielectric (not shown) sandwiched therebetween. The bottom electrode and the top electrode may include TiN, TaN, TiAlN, TiW, WN, Ti, Au, Ta, Ag, Cu, AlCu, Pt, W, Ru, Al, Ni, metal nitrides, other suitable electrode materials, or combinations thereof. The dielectric may include a high dielectric constant dielectric material such as HfO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3, BaTiO3, BaZrO, HfZrO, HfLaO, HfTaO, HfSiO, HfSiON, HfTiO, LaSiO, AlSiO, (Ba, Sr)TiO3, Al2O3, or combinations thereof.

[0082] Figure 2M-2 for Figure 2M-1 FIG. 1 is a top view of the semiconductor memory structure 100. Figure 2M-2 As shown, the bit line 106 separates the active region 104 into a first active region 104a and a second active region 104b, and the adjacent first active regions 104a and second active regions 104b are arranged substantially in parallel. A capacitor 116 is formed on the first active region 104a and the second active region 104b. In some embodiments, Figure 2M-1 As shown, the capacitors 116 are arranged in a honeycomb shape, so that the density of the capacitors 116 can be increased.

[0083] As described above, by separating the active area with buried bit lines, the leakage current between word lines can be reduced. The surrounding gate structure can increase the contact area between the word line and the channel area, reducing the sub-threshold leakage current caused by the short channel effect. The well area and isolation structure under the bit line can reduce the leakage current between adjacent bit lines. The word line does not overlap with the source / drain structure to reduce the gate-induced drain leakage current. Reducing the leakage current can improve the loss of residence time. In addition, the contacts above the active area can be self-aligned without the need for additional masks and processes. The capacitors formed by this method are arranged in a honeycomb shape, which can increase the density of the capacitors.

[0084] Figure 3 FIG. 2 is a top view of a semiconductor memory structure 200 according to some other embodiments. The same or similar processes or elements as those in the above embodiments will be marked with the same reference numerals, and their details will not be repeated. Figure 3As shown, the adjacent first active region 104a and the second active region 104b are substantially arranged vertically. That is, in some embodiments, the angle θ between the adjacent first active region 104a and the second active region 104b is in the range of about 80 degrees to about 100 degrees. In other words, the angle θ between the adjacent active regions 104 is in the range of about 80 degrees to about 100 degrees. In addition, in some embodiments, the angle θ1 between the connection line of the first active region 104a and the second active region 104b and the bit line is in the range of about 20 degrees to about 40 degrees.

[0085] By defining the pattern of the active region 104 by a patterning process and then dividing the active region 104 into a first active region 104a and a second active region 104b by a bit line 106, the distribution pattern of the capacitor 116 formed on the first active region 104a and the second active region 104b can be determined. Figure 3 As shown, the capacitors 116 are arranged in parallel. Therefore, different patterns of the active region 104 may be used depending on the process and design requirements.

[0086] In summary, by separating the active region with buried bit lines, leakage current between word lines can be reduced. The surrounding gate structure can reduce subthreshold leakage current caused by short channel effect. The well area and isolation structure under the bit line can reduce leakage current between adjacent bit lines. The word line does not overlap with the source / drain structure to reduce gate-induced drain leakage current. Reducing leakage current can improve the loss of residence time. In addition, self-aligned formation of contacts above the active region can reduce additional masks and processes. Different active region patterns can be used according to process and design requirements to form different capacitor arrangements.

Claims

1. A method for forming a semiconductor memory structure, characterized in that: include: Forming an isolation structure to surround an active region in a substrate; forming a first trench to separate the active region into a first active region and a second active region; forming a bit line at a bottom of the first trench; forming a word line to surround the first active region and the second active region and be located above the bit line; Self-aligning and forming a contact on the first active region and the second active region; as well as forming a capacitor on the contact point; Wherein, the bit line is located below the isolation structure between the first active region and the second active region; The word line surrounds the first active region and the second active region and is located on the bit line.

2. The method for forming a semiconductor memory structure according to claim 1, wherein: Also includes: After forming the first trench, conformally forming a barrier layer on a sidewall and a bottom surface of the first trench; removing the barrier layer on the bottom surface of the first trench; Depositing a semiconductor material layer on the bottom of the first trench; as well as The bit line is formed on the semiconductor material layer in the first trench.

3. The method for forming a semiconductor memory structure according to claim 1, wherein: Also includes: After forming the bit line, filling the first trench with an isolation material, wherein the isolation material and the isolation structure are made of the same material; Etching back the isolation material and the isolation structure to form a second trench surrounding the first active region and the second active region; forming the word line in the second trench; After forming the word line, filling the second trench with the isolation material; planarizing the isolation material to expose an upper surface of the first active region and the second active region; Etching back the first active region and the second active region to form a recess; and A conductive material is filled into the groove to form the contact.

4. The method for forming a semiconductor memory structure according to claim 3, wherein: Forming the word line includes: forming a gate dielectric layer on a sidewall of the first active region and the second active region in the second trench; Conformally forming a barrier layer in the second trench; filling the second trench with a conductive layer; and The gate dielectric layer, the barrier layer, and the conductive layer are etched back to expose a top portion of the first active region and the second active region.

5. The method for forming a semiconductor memory structure according to claim 1, wherein: Also includes: Blanket doping the first active region and a lower portion of the second active region to form a well region with a first conductivity type; The first active region and the second active region are doped so that the first active region and the second active region exposed from the word line have a first conductivity type and the first active region and the second active region surrounded by the word line have a second conductivity type, wherein the first conductivity type is different from the second conductivity type.

6. A semiconductor memory structure, characterized in that: include: An isolation structure surrounds a first active region and a second active region and is located on a substrate; a bit line located below the isolation structure between the first active region and the second active region; a word line surrounding the first active region and the second active region and located above the bit line; a contact point located on the first active region and the second active region and directly contacting the first active region and the second active region; as well as A capacitor is located on the contact point.

7. The semiconductor memory structure according to claim 6, characterized in that: The first active region and the second active region further include: a channel region surrounded by the word line; and a pair of source / drain regions, located above and below the channel region, respectively, The pair of source / drain regions has a first conductivity type, the channel region has a second conductivity type, and the first conductivity type is different from the second conductivity type, wherein the contact directly contacts the pair of source / drain regions, and the bottom surface of the contact is lower than the upper surface of the isolation structure.

8. The semiconductor memory structure according to claim 6, characterized in that: Also includes: a barrier layer located between the bit line and the first active region and the second active region, wherein the barrier layer and the isolation structure are made of the same material; a well region located at the lower part of the first active region and the second active region and partially located under the bit line; and A semiconductor material layer is located between the well region and the bit line and directly contacts the well region and the bit line.

9. The semiconductor memory structure according to claim 6, characterized in that: The word line comprises: a gate dielectric layer formed on a side wall of the first active region and the second active region; a barrier layer conformally formed on the surfaces of the first active region, the second active region, and the isolation structure; A conductive layer is located between the barrier layers.

10. The semiconductor memory structure according to claim 6, characterized in that: The first active region and the second active region are arranged vertically with the adjacent first active region and the second active region.

Images