Vertical storage devices

By using a highly conductive layer to form a common source layer in vertical memory devices and setting the ACS contact structure in the stepped region, the leakage and capacitance problems of the ACS contact structure are solved, improving the performance and reliability of the memory cell and reducing the process complexity.

CN113903749BActive Publication Date: 2026-05-26YANGTZE MEMORY TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
YANGTZE MEMORY TECH CO LTD
Filing Date
2020-05-29
Publication Date
2026-05-26

AI Technical Summary

Technical Problem

In existing vertical memory devices, the ACS contact structure has problems such as word line leakage, large capacitance and process stress in the gate wire dicing structure, which affect the performance and reliability of the memory cell.

Method used

A common source layer is formed using a highly conductive layer, and an ACS contact structure is set in the stepped region, away from the array region. The ACS is connected to the peripheral circuit through the contact structure, which reduces the number of masks and optimizes the current distribution.

Benefits of technology

It achieves ACS contacts with no word line leakage, no capacitance, and no stress, improving the utilization rate of the core area of ​​the memory cell and the current distribution efficiency, while reducing the complexity of the process.

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  • Figure CN113903749B_ABST
    Figure CN113903749B_ABST
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Abstract

This disclosure provides a vertical memory device. In an embodiment, the semiconductor device includes a stacked layer. The stacked layer includes a common source layer, a gate layer, and an insulating layer disposed on a substrate. The gate layer and the insulating layer are stacked alternately. The semiconductor device then includes an array of channel structures formed in an array region. The channel structures extend through the stacked layer and form a stack of transistors configured in series. The channel structures include a channel layer in contact with the common source layer. The common source layer extends over the array region and a stepped region. The semiconductor device includes contact structures disposed in the stepped region. The contact structures form a conductive connection with the common source layer.
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