Memory device with vertical structure

Abstract

The present disclosure relates to a memory device having a vertical structure. A memory device includes a cell wafer including a memory cell array, and a peripheral wafer including a row control circuit, a column control circuit, and a peripheral circuit to control the memory cell array, the peripheral wafer being stacked on the cell wafer in a first direction and bonded to the cell wafer. The peripheral wafer includes a first substrate having a first surface and a second surface facing away from each other in the first direction, a first logic structure disposed on the first surface of the first substrate and including the row control circuit and the column control circuit, and a second logic structure disposed on the second surface of the first substrate and including the peripheral circuit.

Description

Technical Field

[0001] The various implementations generally relate to semiconductor technology, and more specifically to memory devices with a vertical structure. Background Technology

[0002] The memory device may include an array of memory cells comprising memory cells that have different states depending on the data stored therein. Memory cells can be accessed via word lines and bit lines, and the memory device may include circuitry configured to access memory cells via control word lines and bit lines. Additionally, the memory device may include circuitry configured to perform externally requested operations such as data write operations, read operations, and erase operations. Summary of the Invention

[0003] Various implementation methods involve measures that can help improve the integration of memory devices.

[0004] In one embodiment, the vertical memory device may include: a cell wafer comprising a memory cell array; and a peripheral wafer comprising row control circuitry, column control circuitry, and peripheral circuitry, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer may include: a first substrate having a first surface and a second surface facing away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, the first logic structure including the row control circuitry and the column control circuitry; and a second logic structure disposed on the second surface of the first substrate, the second logic structure including the peripheral circuitry. The row control circuitry, column control circuitry, and peripheral circuitry control the memory cell array.

[0005] In one embodiment, the vertical memory device may include: logic circuit components including row control circuitry, column control circuitry, and peripheral circuitry; and cell components stacked on the logic circuit components in a first direction, including a memory cell array. The logic circuit components may include: a substrate having a first surface and a second surface facing away from each other in the first direction; a first logic circuit component disposed on the first surface of the substrate, including row control circuitry and column control circuitry; and a second logic circuit component disposed on the second surface of the substrate, including peripheral circuitry. The row control circuitry, column control circuitry, and peripheral circuitry control the memory cell array.

[0006] In one embodiment, the vertical memory device may include: a cell wafer including a memory cell array; a first peripheral wafer including row control circuitry and column control circuitry; and a second peripheral wafer including peripheral circuitry. The first and second peripheral wafers may be stacked on the cell wafer in a first direction. The row control circuitry, column control circuitry, and peripheral circuitry control the memory cell array. Attached Figure Description

[0007] Figure 1 This is a block diagram schematically illustrating a representation of a memory device according to an embodiment of the present disclosure.

[0008] Figure 2 It is shown Figure 1 The example of the storage block shown is represented by an equivalent circuit diagram.

[0009] Figure 3 This is a cross-sectional view showing a schematic structure of a memory device according to an embodiment of the present disclosure.

[0010] Figures 4A to 4D This is a top view showing the layout of the page buffer circuitry and the line decoder of a memory device according to an embodiment of the present disclosure.

[0011] Figure 5 yes Figure 3 Detailed diagram.

[0012] Figure 6 This is a cross-sectional view showing a schematic structure of a memory device according to an embodiment of the present disclosure.

[0013] Figure 7 yes Figure 6 Detailed diagram.

[0014] Figure 8 This is a cross-sectional view showing a schematic structure of a memory device according to an embodiment of the present disclosure.

[0015] Figure 9 yes Figure 8 Detailed diagram.

[0016] Figure 10 This is a block diagram schematically illustrating a representation of a memory system including a memory device according to an embodiment of the present disclosure.

[0017] Figure 11 This is a block diagram schematically illustrating a representation of a computing system including a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0018] The advantages and features of this disclosure, as well as methods for implementing them, will become apparent from the following description of exemplary embodiments, which are described with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. The exemplary embodiments of this disclosure convey the scope of this disclosure to those skilled in the art.

[0019] Because the figures, dimensions, ratios, angles, and quantities of elements given in the accompanying drawings describing embodiments of this disclosure are merely illustrative, this disclosure is not limited to the illustrative content. Throughout the specification, similar reference numerals refer to similar components. In describing this disclosure, detailed descriptions of related technologies will be omitted where it is determined that such detailed descriptions may obscure the gist or clarity of the disclosure. It should be understood that, unless expressly stated otherwise, the terms “comprising,” “having,” “including,” etc., as used in the specification and claims should not be construed as limited to the means listed thereafter. Where indefinite or definite articles (e.g., “a,” “one,” or “the”) are used when referring to singular nouns, the article may include the plural form of the noun unless expressly stated otherwise.

[0020] When interpreting the elements in the embodiments of this disclosure, they should be interpreted as including tolerances, even if not explicitly stated otherwise.

[0021] Furthermore, in describing the components of this disclosure, terms such as first, second, A, B, (a), and (b) may be used. These are for the purpose of distinguishing one component from another and do not limit the nature, order, sequence, or number of the components. Moreover, the components in embodiments of this disclosure are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, as used herein, within the spirit of the present disclosure, a first component may be a second component.

[0022] If a component is described as “connected,” “linked,” or “attached” to another component, this can mean that the component is not only directly “connected,” “linked,” or “attached” but also indirectly “connected,” “linked,” or “attached” via a third component. When describing positional relationships, terms such as “component A on component B,” “component A above component B,” “component A below component B,” and “component A next to component B” can indicate that one or more other components may be positioned between component A and component B, unless the terms “directly” or “immediately adjacent” are explicitly used.

[0023] Features of the various exemplary embodiments of this disclosure can be combined, integrated, or separated, in whole or in part. Technically, various interactions and operations are possible. Various exemplary embodiments can be practiced individually or in combination.

[0024] In the following, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 This is a block diagram schematically illustrating a representation of a memory device according to an embodiment of the present disclosure.

[0026] Reference Figure 1The memory device 100 according to embodiments of the present disclosure may include a memory cell array 110 and logic circuitry 120. Logic circuitry 120 may include a row decoder (X-DEC) 121, a page buffer circuitry 122, and peripheral circuitry (PERI circuitry) 123.

[0027] The memory cell array 110 may include multiple memory blocks BLK. Each of the multiple memory blocks BLK may include multiple memory cells. The memory blocks BLK can be connected to the row decoder 121 via multiple word lines WL. The memory cell array 110 can be connected to the page buffer circuit 122 via multiple bit lines BL.

[0028] In response to the row address X_A provided from the peripheral circuitry (PERI circuit) 123, the row decoder (X-DEC) 121 can select any one of the memory blocks BLK included in the memory cell array 110. The row decoder (X-DEC) 121 can transmit the operating voltage X_V provided from the peripheral circuitry (PERI circuit) 123 to the word line WL connected to the selected memory block BLK included in the memory cell array 110.

[0029] Although not shown, the line decoder (X-DEC) 121 may include a pass transistor circuit and a block switch circuit. The pass transistor circuit may include multiple pass transistor groups. The multiple pass transistor groups may be respectively connected to multiple memory blocks BLK. Each pass transistor group may be connected to a corresponding memory block BLK via multiple word lines WL. In response to a row address X_A received from the peripheral circuit (PERI circuit) 123, the block switch circuit may select one of the pass transistor groups included in the pass transistor circuit. The block switch circuit may include multiple block switches respectively connected to the pass transistor groups. When a row address X_A is received from the peripheral circuit (PERI circuit) 123, any one of the block switches may be activated in response to the received row address X_A. The activated block switch may transmit a signal provided from the peripheral circuit (PERI circuit) 123 to the corresponding pass transistor group. The pass transistor group selected by the block switch circuit (i.e., provided with a signal from the block switch circuit) may transmit an operating voltage X_V to the word line WL connected to the corresponding memory block BLK.

[0030] Page buffer circuit 122 may include multiple page buffers PB, each connected to a bit line BL. Page buffers PB can receive page buffer control signals PB_C from peripheral circuitry (PERI circuitry) 123, and can send and receive data signals DATA from peripheral circuitry (PERI circuitry) 123. Page buffers PB can control bit lines BL in response to page buffer control signals PB_C. For example, page buffers PB can detect data stored in memory cells of memory cell array 110 by sensing signals on bit lines BL in response to page buffer control signals PB_C, and can send data signals DATA to peripheral circuitry (PERI circuitry) 123 based on the detected data. Page buffers PB can apply signals to bit lines BL based on data signals DATA received from peripheral circuitry (PERI circuitry) 123 in response to page buffer control signals PB_C, thereby writing data into memory cells of memory cell array 110. Page buffers PB can write data to or read data from memory cells connected to activated word lines WL.

[0031] The peripheral circuit (PERI circuit) 123 can receive command signals CMD, address signals ADD, and control signals CTRL from a device outside the memory device 100 (e.g., a memory controller), and can send data DATA to and receive data DATA from the device outside the memory device 100. The peripheral circuit (PERI circuit) 123 can output signals for writing data to or reading data from the memory cell array 110 based on the command signal CMD, address signal ADD, and control signal CTRL, such as row address X_A, page buffer control signal PB_C, etc. The peripheral circuit (PERI circuit) 123 can generate various voltages required in the memory device 100, including the operating voltage X_V.

[0032] As the integration density and operating speed of the memory device 100 increase, it is necessary to reduce the latency caused by the transmission of the operating voltage of the self-decoder (X-DEC) 121 to the word line WL in the future. To this end, the line decoder (X-DEC) 121 can be configured to have a shape extending in the direction in which the word line WL is arranged, and can have a length in the direction in which the word line WL is arranged that is substantially the same as or similar to that of the memory cell array 110.

[0033] As the integration density and operating speed of the memory device 100 increase, it is necessary to reduce the delay time of the signals applied to or provided to the page buffer circuit 122 via the bit line BL. To this end, the page buffer circuit 122 may be configured to have a shape extending in the direction in which the bit line BL is arranged, and may have a length substantially the same as or similar to that of the memory cell array 110 in the direction in which the bit line BL is arranged.

[0034] As the size of electronic products incorporating memory devices 100 decreases, there is a growing demand to reduce the size of memory devices 100. As the number of word lines WL increases due to the need for higher capacity, the number of transistors in the line decoder 121 also increases. In this design, the transistors are arranged in multiple columns along the extension direction of the word lines WL. For these reasons, the footprint of the line decoder 121 is increasing.

[0035] As the spacing of bit lines BL decreases due to increased integration density, the page buffer PB constituting the page buffer circuit 122 is configured with multiple rows in the extension direction of bit lines BL. Therefore, the occupied area of ​​the page buffer circuit 122 increases.

[0036] Thus, as the size of the memory device 100 decreases and the area occupied by the line decoder 121 and page buffer circuit 122 increases, there may be insufficient space for the peripheral circuitry 123. Embodiments of this disclosure can provide measures to address the problem of insufficient space for the peripheral circuitry 123 caused by the reduced size, high capacity, and high integration of the memory device 100.

[0037] In the following text, and in the accompanying drawings, the direction projecting vertically from the top surface of the substrate is defined as the first direction FD, and two directions parallel to the top surface of the substrate and intersecting each other are defined as the second direction SD and the third direction TD, respectively. For example, the second direction SD may correspond to the extension direction of a word line, and the third direction TD may correspond to the extension direction of a bit line. The second direction SD and the third direction TD may intersect each other substantially perpendicularly. The first direction FD may be orthogonal to the second direction SD and the third direction TD. In the accompanying drawings, the direction indicated by the arrow and the direction opposite to it represent the same direction.

[0038] Although this specification describes memory device 100 as a flash memory device by way of example, the type of memory is not limited to this, and the spirit of this disclosure can be applied to other types of memory besides flash memory. For example, the memory may be DRAM, PCRAM, or ReRAM. Although this specification shows a case where the row control circuitry connected to the word line WL of memory cell array 110 is a row decoder and the column control circuitry connected to the bit line BL of memory cell array 110 is a page buffer circuitry, this indicates a circuit configuration where the memory is flash memory, and it should be understood that the row control circuitry and column control circuitry may vary depending on the type of memory.

[0039] Figure 2 It is shown Figure 1 The equivalent circuit diagram of the storage block BLK shown is illustrated in the figure.

[0040] Reference Figure 2 A memory block BLK may include multiple cell strings CSTRs connected between multiple bit lines BL and a common source line CSL. Bit lines BL may extend on a third direction TD and may be arranged on a second direction SD. Multiple cell strings CSTR may be connected in parallel to each bit line BL. Cell strings CSTR may be collectively connected to the common source line CSL. Multiple cell strings CSTR may be connected between multiple bit lines BL and a common source line CSL.

[0041] Each cell string CSTR may include a drain-select transistor DST connected to bit line BL, a source-select transistor SST connected to common source line CSL, and multiple memory cells MC connected between the drain-select transistor DST and the source-select transistor SST. The drain-select transistor DST, memory cells MC, and source-select transistor SST may be connected in series on the first direction FD.

[0042] Drain select line DSL, multiple word lines WL, and source select line SSL can be stacked on FD in the first direction between bit line BL and common source line CSL. Each drain select line DSL can be connected to the gate of the corresponding drain select transistor DST. Each word line WL can be connected to the gate of the corresponding memory cell MC. The source select line SSL can be connected to the gate of source select transistor SST. Memory cells MC that are all connected to a single word line WL can form a page.

[0043] Figure 3 This is a cross-sectional view illustrating a schematic structure of a memory device according to an embodiment of the present disclosure.

[0044] Reference Figure 3The memory device according to embodiments of the present disclosure may include a cell wafer CW and a peripheral wafer PW stacked and bonded to the cell wafer CW in a first direction FD. For ease of understanding, Figure 3 The unit wafer CW and the peripheral wafer PW are shown to be separated from each other, but it should be understood that the top surface of the unit wafer CW and the bottom surface of the peripheral wafer PW are in contact with each other.

[0045] The peripheral wafer (PW) may include a substrate 10, a first logic structure PS1, and a second logic structure PS2. The substrate 10 may have a first surface 11 and a second surface 12 facing away from each other in a first direction FD. The first surface 11 may be a surface closer to the cell wafer (CW) than the second surface 12. The first logic structure PS1 may be disposed on the first surface 11 of the substrate 10, and the second logic structure PS2 may be disposed on the second surface 12 of the substrate 10. The first logic structure PS1 may be bonded to the cell wafer (CW).

[0046] The first logic structure PS1 may include a row decoder X-DEC and a page buffer circuit PBC. The row decoder X-DEC may correspond to... Figure 1 The line decoder 121 shown, and the page buffer circuit PBC can correspond to Figure 1 The page buffer circuit 122 is shown. The second logic structure PS2 may include the peripheral circuit PERI. The peripheral circuit PERI may correspond to Figure 1 The peripheral circuit 123 is shown.

[0047] The row decoder X-DEC and page buffer circuit PBC are directly interfaced with the memory cell array MCA and configured in the first logic structure PS1, which is bonded to the cell wafer CW. As a result, the length of the electrical path connecting the row decoder X-DEC and page buffer circuit PBC to the memory cell array MCA can be shortened.

[0048] The cell wafer CW may include a substrate 20 and a cell structure CS defined on the substrate 20. The cell structure CS may include a memory cell array MCA. Although not shown, the memory cell array MCA may include multiple word lines extending in the second direction SD, multiple bit lines extending in the third direction TD, and multiple memory cells connected to the multiple word lines and the multiple bit lines.

[0049] Figures 4A to 4D This is a top view showing the layout of the line decoder and page buffer circuitry of a memory device according to an embodiment of the present disclosure.

[0050] Reference Figure 4AThe substrate 10 of the peripheral wafer may include a cell region CR and a slimming region SR. The cell region CR may be located on the first direction FD and adjacent to the memory cell array ( Figure 3 The thinning region SR can be adjacent to the cell region CR on the second direction SD. The thinning region SR is the area in which the wiring structure connecting the word lines of the memory cell array and the row decoder X-DEC is provided.

[0051] The line decoder X-DEC can be set in the thinned region SR. As mentioned above, in order to reduce the delay time caused by the transmission of the operating voltage of the line decoder X-DEC to the word line (WL) in the future, the line decoder X-DEC can be set to have a shape that extends on the third direction TD, which is the direction in which the word line (WL) is arranged.

[0052] Page buffer circuits (PBCs) can be disposed within cell regions (CR). As described above, to reduce the delay time of signals applied to or provided to the page buffer circuits (PBC) via bit lines (BLs), the page buffer circuits (PBC) can have a length substantially the same as or similar to the length of the cell region (CR) in the second direction (SD), which is the direction in which the bit lines (BLs) are arranged. As the spacing of the bit lines (BLs) decreases due to increased integration density, the page buffers constituting the page buffer circuits (PBCs) are arranged in multiple rows in the third direction (TD), which is the direction in which the bit lines (BLs) extend. Based on this fact, the page buffer circuits (PBCs) can be configured to have a width substantially the same as or similar to the width of the cell region (CR) in the third direction (TD).

[0053] Reference Figure 4B The thinning region SR can be disposed in the central portion of the substrate 10. The unit region CR can be divided into a first unit region CR1 and a second unit region CR2, and can be disposed on both sides of the thinning region SR in the second direction SD.

[0054] The line decoder X-DEC can be set in the thinning region SR. The page buffer circuit PBC can be divided into a first page buffer circuit PBC1 and a second page buffer circuit PBC2, and can be set in the first unit region CR1 and the second unit region CR2 respectively.

[0055] Reference Figure 4C and Figure 4D In order to increase the area of ​​overlap with the memory cell array on the first direction FD, each of the line decoder X-DEC and page buffer circuit PBC can be divided into at least two parts and set in different regions.

[0056] For example, a cell region CR may include a first cell region CR1 to a fourth cell region CR4, divided by a first line L1 and a second line L2 that intersect each other at a single intersection point. A line decoder X-DEC may be divided into a first line decoder X-DEC1 and a second line decoder X-DEC2, and may be located in the first cell region CR1 and the third cell region CR3, respectively. A page buffer circuit PBC may be divided into a first page buffer circuit PBC1 and a second page buffer circuit PBC2, and may be located in the second cell region CR2 and the fourth cell region CR4, respectively.

[0057] like Figure 4C As shown, the first row decoder X-DEC1 and the second row decoder X-DEC2, as well as the first page buffer circuit PBC1 and the second page buffer circuit PBC2, can be configured to be adjacent to the corner of the cell region CR in different cell regions. Furthermore, as... Figure 4D As shown, the first line decoder X-DEC1 and the second line decoder X-DEC2, as well as the first page buffer circuit PBC1 and the second page buffer circuit PBC2, can be set to be adjacent to the intersection between the first line L1 and the second line L2 in different cell regions.

[0058] Figure 5 yes Figure 3 Detailed diagram.

[0059] Reference Figure 5 The substrate 10 of the peripheral wafer PW can be a single-crystal semiconductor film. For example, the substrate 10 can be a bulk silicon substrate, a germanium substrate, a silicon-germanium substrate, or an epitaxial thin film formed by selective epitaxial growth.

[0060] The first logic structure PS1 may include a row decoder X-DEC and a page buffer circuit PBC. The row decoder X-DEC may be disposed in the thinned region SR common to the first surface 11 of the substrate 10, and the page buffer circuit PBC may be disposed in the cell region CR common to the first surface 11 of the substrate 10.

[0061] Each of the line decoder X-DEC and the page buffer circuit PBC may include a plurality of first horizontal transistors TR1. The first horizontal transistor TR1 may include a gate dielectric layer Gox1 disposed on a first surface 11 of the substrate 10, a gate electrode G1 disposed on the gate dielectric layer Gox1, and junctions Jn11 and Jn12 defined on both sides of the gate electrode G1 in the active region of the substrate 10. Junctions Jn11 and Jn12 are regions defined by implanting n-type or p-type impurities into the active region of the first surface 11 of the substrate 10. One junction of Jn11 and Jn12 may serve as the source region of the first horizontal transistor TR1, and the other junction may serve as the drain region of the first horizontal transistor TR1.

[0062] The dielectric layer ILD1 can be defined on the first surface 11 of the substrate 10 to cover the line decoder X-DEC and page buffer circuit PBC. The bottom surface of the dielectric layer ILD1 can form a surface for bonding the peripheral wafer PW to the cell wafer CW.

[0063] Contacts CNT1a to CNT1d and wirings M1a to M1c and M1a' can be defined in the dielectric layer ILD1. Contacts CNT1a to CNT1d and wirings M1a to M1c and M1a' can be connected to the line decoder X-DEC or the page buffer circuit PBC. Although in Figure 5 Not shown in detail, but each trace M1a' can be connected to a corresponding trace M1a, and can be connected to the row decoder X-DEC or the page buffer circuit PBC via the corresponding trace M1a and contact CNT1a. The peripheral wafer PW can include multiple bonding pads BP1 on one of its surfaces. The bonding pads BP1 can be connected to one of the page buffer circuit PBC and the row decoder X-DEC via contacts CNT1a to CNT1d and traces M1a to M1c.

[0064] The second logic structure PS2 may include a peripheral circuit PERI. The peripheral circuit PERI may include a plurality of second horizontal transistors TR2. The second horizontal transistors TR2 may include a gate dielectric layer Gox2 disposed on the second surface 12 of the substrate 10, a gate electrode G2 disposed on the gate dielectric layer Gox2, and junctions Jn21 and Jn22 defined in the active region of the substrate 10 on both sides of the gate electrode G2. Junctions Jn21 and Jn22 are regions defined by implanting n-type or p-type impurities into the active region of the second surface 12 of the substrate 10. One junction of Jn21 and Jn22 may be used as the source region of the second horizontal transistor TR2, and the other junction may be used as the drain region of the second horizontal transistor TR2.

[0065] A dielectric layer ILD2 can be defined on the second surface 12 of the substrate 10 to cover the peripheral circuit PERI. The top surface of the dielectric layer ILD2 can form another surface of the peripheral wafer PW. Contacts CNT2a and CNT2b and wirings M2a and M2b can be defined in the dielectric layer ILD2. The contacts CNT2a and CNT2b and wirings M2a and M2b can be connected to the peripheral circuit PERI.

[0066] The substrate 10 may include an isolation dielectric layer 13 passing through a first surface 11 and a second surface 12. A via TSV1 passes through the isolation dielectric layer 13 and connects wiring M2b defined in dielectric layer ILD2 and wiring M1a' defined in dielectric layer ILD1. The via TSV1 may be defined below wiring M2b. Peripheral circuitry PERI may be connected to the via TSV1 via contacts CNT2a and CNT2b and wiring M2a and M2b, and may be connected to the line decoder X-DEC and / or the page buffer circuit PBC via the via TSV1 and wiring M1a'.

[0067] The peripheral wafer (PW) may include external connection pads (PADs) exposed through the dielectric layer ILD2. These external connection pads, serving as external contacts for connection to external devices such as memory controllers, may be exposed on another surface of the peripheral wafer (PW).

[0068] A cell wafer (CW) may include a substrate 20 and a memory cell array (MCA) defined on the substrate 20. The substrate 20 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 20 may be configured as a polycrystalline layer or an epitaxial layer.

[0069] The memory cell array (MCA) may include a plurality of electrode layers 22 and a plurality of interlayer dielectric layers 24 alternately stacked on a substrate 20, and a plurality of vertical channels CH passing through the plurality of electrode layers 22 and the plurality of interlayer dielectric layers 24 in a first direction FD.

[0070] Electrode layer 22 may include a conductive material. For example, electrode layer 22 may include at least one selected from doped semiconductors (e.g., doped silicon), metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and transition metals (e.g., titanium or tantalum). In electrode layer 22, at least one electrode layer 22 starting from the bottommost electrode layer 22 may form a source select line. In electrode layer 22, at least one electrode layer 22 starting from the topmost electrode layer 22 may form a drain select line. The electrode layers 22 between the source select line and the drain select line may form word lines. Interlayer dielectric layer 24 may include silicon oxide.

[0071] Although not shown, a plurality of first slits may be defined to divide the alternately stacked electrode layers 22 and interlayer dielectric layers 24 into memory block cells. Second slits may be defined between adjacent first slits to divide at least one of the drain select line and source select line into cells (e.g., sub-block cells) smaller than the memory block. Thus, word lines can be divided into memory block cells, and at least one of the drain select line and source select line can be divided into sub-block cells.

[0072] Electrode layer 22 can extend from unit region CR to thinned region SR at different lengths, for example, in the second direction SD, thereby forming stepped steps in thinned region SR. Figure 5 As shown, in the thinning region SR, the electrode layer 22 can be configured to form steps in the second direction SD. Although not shown, in the thinning region SR, the electrode layer 22 can be configured to form steps even in the third direction TD. These steps expose a lower electrode layer 22 that extends longer than the upper electrode layer 22, and can define a contact pad region exposed upward in the first direction FD in each electrode layer 22.

[0073] Multiple vertical channels CH can pass through multiple electrode layers 22 and multiple interlayer dielectric layers 24 alternately stacked in a cell region CR in a first direction FD. Although not shown in detail, each vertical channel CH may include a channel layer and a gate dielectric layer. The channel layer may include polysilicon or monocrystalline silicon and may include p-type impurities such as boron (B) in certain regions therein. The gate dielectric layer may have a shape surrounding the outer wall of the channel layer. The gate dielectric layer may include a tunnel dielectric layer, a charge storage layer, and a barrier layer sequentially stacked from the outer wall of the channel layer. In some embodiments, the gate dielectric layer may have an ONO (oxide-nitride-oxide) stack structure in which an oxide layer, a nitride layer, and an oxide layer are sequentially stacked.

[0074] Source-select transistors can be configured in a region or area where the source-select line surrounds the vertical channel CH. Memory cells can be configured in a region or area where the word line surrounds the vertical channel CH. Drain-select transistors can be configured in a region or area where the drain-select line surrounds the vertical channel CH. Source-select transistors, multiple memory cells, and drain-select transistors arranged along a vertical channel CH can form a cell string.

[0075] Multiple bit lines BL can be disposed above multiple alternately stacked electrode layers 22, multiple interlayer dielectric layers 24, and multiple vertical channels CH. The bit lines BL can extend in the third direction TD and can be arranged in the second direction SD. The bit lines BL can be connected to the vertical channels CH through bit line contacts BLC.

[0076] A dielectric layer ILD3 can be defined on the substrate 20 to cover multiple electrode layers 22 and multiple interlayer dielectric layers 24, vertical channels CH, and bit lines BL. The top surface of the dielectric layer ILD3 can form a surface on which the unit wafer CW is bonded to the peripheral wafer PW. The unit wafer CW can include multiple bonding pads BP2 on one of its surfaces, which are bonded to multiple bonding pads BP1.

[0077] Each electrode layer 22 can be connected to one of the bonding pads BP2 via contacts CNT3a and CNT3b defined in the dielectric layer ILD3 and wiring M3a. Each bit line BL can be connected to one of the bonding pads BP2 via contacts CNT3b' defined in the dielectric layer ILD3.

[0078] Although for the sake of simplicity, in Figure 5 Only the bonding pads BP2 connected to some electrode layers 22 are shown, but it should be understood that multiple bonding pads BP2 connected to multiple electrode layers 22 are disposed on one surface of the unit wafer CW. Although for the sake of simplicity, Figure 5 The diagram only shows bonding pads BP2 connected to some bit lines BL, but it should be understood that multiple bonding pads BP2 connected to multiple bit lines BL are disposed on one surface of the cell wafer CW.

[0079] The unit wafer (CW) and peripheral wafers (PW) can be fabricated separately and then bonded together. The wiring M1a to M1c, M1a', M2a, and M2b of the peripheral wafers (PW) can be formed from a conductive material with low resistivity, but may cause process failures at the highest temperatures during the process of forming the unit wafer (CW) (hereinafter referred to as the "process critical temperature"). For example, the wiring M1a to M1c, M1a', M2a, and M2b of the peripheral wafers (PW) can be formed from copper or aluminum.

[0080] In the embodiments described herein, the peripheral wafer PW is formed separately from the unit wafer CW, and therefore, a material with a low melting point and low resistivity can be used as the conductive material for the wirings M1a to M1c, M1a', M2a and M2b forming the peripheral wafer PW.

[0081] Figure 6 This is a cross-sectional view showing a schematic structure of a memory device according to an embodiment of the present disclosure.

[0082] Reference Figure 6 The memory device according to this embodiment may include a logic circuit component LCP and a cell component CP, wherein the cell component CP is stacked on the logic circuit component LCP in a first direction FD.

[0083] The logic circuit component LCP may include a substrate 10, a first logic circuit component LCP1, and a second logic circuit component LCP2.

[0084] The substrate 10 may have a first surface 11 and a second surface 12 facing away from each other in a first direction FD. A first logic circuit component LCP1 may be disposed on the first surface 11 of the substrate 10, and a second logic circuit component LCP2 may be disposed on the second surface 12 of the substrate 10.

[0085] The first logic circuit component LCP1 may include a row decoder X-DEC and a page buffer circuit PBC. The second logic circuit component LCP2 may include peripheral circuitry PERI. The cell component CP may include a source plate 20A and a memory cell array MCA defined on the source plate 20A.

[0086] Following the first logic circuit component LCP1, a source plate 20A and a memory cell array MCA are sequentially formed on the first surface 11 of the substrate 10, and a second logic circuit component LCP2 can be formed on the second surface 12 of the substrate 10. The memory device according to this embodiment can have an integrated structure in a single wafer.

[0087] Figure 7 yes Figure 6 Detailed diagram.

[0088] Reference Figure 7 The substrate 10 of the logic circuit component LCP can be a single-crystal semiconductor film. For example, the substrate 10 can be a bulk silicon substrate, a germanium substrate, a silicon-germanium substrate, or an epitaxial thin film formed by selective epitaxial growth.

[0089] The first logic circuit component LCP1 may include a row decoder X-DEC and a page buffer circuit PBC defined on a first surface 11 of the substrate 10. The row decoder X-DEC may be disposed in a thinned region SR of the first surface 11 of the substrate 10, and the page buffer circuit PBC may be disposed in a cell region CR of the first surface 11 of the substrate 10.

[0090] A dielectric layer ILD1 can be defined on the first surface 11 of the substrate 10 to cover the line decoder X-DEC and the page buffer circuit PBC. Contacts CNT11a and CNT11b, as well as wirings M11a, M11b, and M11a', can be defined in the dielectric layer ILD1. The contacts CNT11a and CNT11b, as well as the wirings M11a, M11b, and M11a', can be connected to the line decoder X-DEC and / or the page buffer circuit PBC. Although in Figure 7 Not shown in detail, but each wire M11a' can be connected to the corresponding wire M11a, and can be connected to the line decoder X-DEC or page buffer circuit PBC through the corresponding wire M11a and contact CNT11a.

[0091] The second logic circuit component LCP2 may include a peripheral circuit PERI defined on a second surface 12 of the substrate 10. A dielectric layer ILD2 may be defined on the second surface 12 of the substrate 10 to cover the peripheral circuit PERI. Contacts CNT21a and CNT21b and wirings M21a and M21b may be defined in the dielectric layer ILD2. The contacts CNT21a and CNT21b and the wirings M21a and M21b may be connected to the peripheral circuit PERI.

[0092] The bottom surface of the dielectric layer ILD2 can form the other surface of the logic circuit component LCP, which is opposite to one surface of the LCP that contacts the cell component CP. The dielectric layer ILD2 can have openings that expose external connection pads (PADs). These external connection pads (PADs) can be exposed on the other surface of the logic circuit component LCP.

[0093] The substrate 10 may include an isolation dielectric layer 13 passing through the first surface 11 and the second surface 12. The isolation dielectric layer 13 may define a via TSV21 that connects wiring M11a' in dielectric layer ILD1 and wiring M21b in dielectric layer ILD2. The peripheral circuitry PERI may be connected to the via TSV21 via contacts CNT21a and CNT21b and wiring M21a and M21b, and may be connected to the line decoder X-DEC and / or the page buffer circuit PBC via the via TSV21 and wiring M11a'.

[0094] The source plate 20A can be formed on the dielectric layer ILD1 of the first logic circuit component LCP1. The source plate 20A can include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor can include silicon, germanium, or silicon-germanium. Because the source plate 20A can be formed on the dielectric layer ILD1, the source plate 20A can be formed as a polycrystalline layer or an epitaxial layer.

[0095] The memory cell array MCA can be constructed from multiple electrode layers 22 and multiple interlayer dielectric layers 24 alternately stacked on the source plate 20A, and vertical channels (not shown) passing through the multiple electrode layers 22 and multiple interlayer dielectric layers 24. A bit line BL connected to the vertical channel can be defined above the memory cell array MCA. Multiple vias TSV22 passing through the source plate 20A can be defined. An isolation dielectric layer 21 can be defined on the sidewall of the vias TSV22 to isolate the vias TSV22 from the source plate 20A. The bit line BL can be connected to the page buffer circuit PBC of the first logic circuit component LCP1 through one of the vias TSV22, contacts CNT11a and CNT11b, and wirings M11a and M11b. Electrode layer 22 can be connected to the row decoder X-DEC of the first logic circuit component LCP1 via another of the vias TSV22, contact CNT31a, wiring M31a and contacts CNT11a and CNT11b, and wiring M11a and M11b. A dielectric layer ILD3 can be defined on the source plate 20A to cover the memory cell array MCA.

[0096] As described above, the first logic circuit component LCP1 can be formed before the unit component CP is formed, and the second logic circuit component LCP2 can be formed after the unit component CP is formed.

[0097] The wirings M11a, M11b, and M11a' of the first logic circuit component LCP1 can be configured to not exhibit process failures (e.g., hillocks) at the process critical temperature, which is the maximum temperature during the formation of the cell component CP. In other words, the wirings M11a, M11b, and M11a' of the first logic circuit component LCP1 can be formed of a conductive material with a melting point higher than the process critical temperature, thereby exhibiting heat resistance at the process critical temperature. For example, the material used to form the wirings M11a, M11b, and M11a' of the first logic circuit component LCP1 can include tungsten (W). Furthermore, the conductive material forming the wirings M21a and M21b of the second logic circuit component LCP2 can include a material having a lower resistivity than the conductive material forming the wirings M11a, M11b, and M11a' of the first logic circuit component LCP1. For example, the conductive material used for the wirings M21a and M21b used to form the second logic circuit component LCP2 may include a material such as copper or aluminum, which may cause process failures at temperatures below the process critical temperature but has a low resistivity.

[0098] Since the wirings M21a and M21b of the second logic circuit component LCP2 are formed after the formation of the unit component CP, materials with low melting point and low resistivity can be used as conductive materials for forming the wirings M21a and M21b of the second logic circuit component LCP2.

[0099] Figure 8 This is a cross-sectional view showing a schematic structure of a memory device according to an embodiment of the present disclosure.

[0100] Reference Figure 8 The memory device according to embodiments of the present disclosure may include a cell wafer CW, a first peripheral wafer PW1 bonded to the cell wafer CW, and a second peripheral wafer PW2 bonded to the first peripheral wafer PW1.

[0101] For ease of understanding, Figure 8 The diagram shows a unit wafer CW and a first peripheral wafer PW1 separated from each other, as well as a first peripheral wafer PW1 and a second peripheral wafer PW2 separated from each other. However, it should be understood that the top surface of the unit wafer CW is in contact with the bottom surface of the first peripheral wafer PW1, and the top surface of the first peripheral wafer PW1 is in contact with the bottom surface of the second peripheral wafer PW2.

[0102] The first peripheral wafer PW1 may include a substrate 10a and a first logic structure PS1 defined on the bottom surface of the substrate 10a. The first logic structure PS1 may include a row decoder X-DEC and a page buffer circuit PBC.

[0103] The second peripheral wafer PW2 may include a substrate 10b and a second logic structure PS2 defined on the bottom surface of the substrate 10b. The second logic structure PS2 may include peripheral circuitry PERI.

[0104] The row decoder X-DEC can be connected to the memory cell array MCA of the cell wafer CW via word lines, and the page buffer circuit PBC can be connected to the memory cell array MCA via bit lines. Because the row decoder X-DEC and the page buffer circuit PBC are directly interfaced with the memory cell array MCA and configured in the first peripheral wafer PW1 bonded to the cell wafer CW, the length of the electrical path connecting the row decoder X-DEC and the page buffer circuit PBC to the memory cell array MCA can be shortened.

[0105] A cell wafer (CW) may include a substrate 20 and a cell structure (CS) defined on the substrate 20. The cell structure (CS) may include a memory cell array (MCA).

[0106] Figure 9 yes Figure 8 Detailed diagram.

[0107] Reference Figure 9 The substrate 10a of the first peripheral wafer PW1 can be a single-crystal semiconductor film. For example, the substrate 10a can be a bulk silicon substrate, a germanium substrate, a silicon-germanium substrate, or an epitaxial thin film formed by selective epitaxial growth.

[0108] The first logic structure PS1 may include a row decoder X-DEC and a page buffer circuit PBC. The row decoder X-DEC may be disposed in the thinned region SR on the bottom surface of the substrate 10a, and the page buffer circuit PBC may be disposed in the cell region CR on the bottom surface of the substrate 10a.

[0109] A dielectric layer ILD1a can be defined on the bottom surface of substrate 10a to cover the line decoder X-DEC and page buffer circuit PBC. The bottom surface of dielectric layer ILD1a can form a surface for bonding the first peripheral wafer PW1 to a cell wafer CW. Contacts CNT12a to CNT12d and wirings M12a to M12c and M12a' can be defined in dielectric layer ILD1a. Contacts CNT12a to CNT12d and wirings M12a to M12c and M12a' can be connected to the line decoder X-DEC or page buffer circuit PBC. Although in Figure 9 Not shown in detail, but each wire M12a' can be connected to the corresponding wire M12a, and can be connected to the line decoder X-DEC or page buffer circuit PBC through the corresponding wire M12a and contact CNT12a.

[0110] The first peripheral wafer PW1 may include multiple bonding pads BP11 on one of its surfaces. The bonding pads BP11 may be connected to one of the page buffer circuit PBC and the line decoder X-DEC via contacts CNT12a to CNT12d and wiring M12a to M12c.

[0111] The substrate 10a may include an isolation dielectric layer 13 extending through its top and bottom surfaces. The isolation dielectric layer 13 may define a via TSV3 that is connected to the wiring M12a' in the dielectric layer ILD1a.

[0112] The dielectric layer ILD1b can be defined on the top surface of the substrate 10a. The top surface of the dielectric layer ILD1b can form a bonding surface between the first peripheral wafer PW1 and the second peripheral wafer PW2. The first peripheral wafer PW1 can include a plurality of bonding pads BP12 on its other surface.

[0113] The bonding pad BP12 can be connected to the via TSV3 via the contact CNT12e, and can be connected to one of the line decoder X-DEC and page buffer circuit PBC via the via TSV3 and the wiring M12a'.

[0114] The second peripheral wafer PW2 may include a substrate 10b and a second logic structure PS2. The substrate 10b may be a single-crystal semiconductor film. For example, the substrate 10b may be a bulk silicon substrate, a germanium substrate, a silicon-germanium substrate, or an epitaxial thin film formed by selective epitaxial growth.

[0115] The second logic structure PS2 may include peripheral circuitry PERI defined on the bottom surface of substrate 10b. A dielectric layer ILD2a may be defined on the bottom surface of substrate 10b to cover the peripheral circuitry PERI. The bottom surface of the dielectric layer ILD2a may form a surface on which the second peripheral wafer PW2 is bonded to the first peripheral wafer PW1.

[0116] Contacts CNT22a to CNT22c and wirings M22a and M22b can be defined in the dielectric layer ILD2a. Contacts CNT22a to CNT22c and wirings M22a and M22b can be connected to the peripheral circuit PERI.

[0117] The second peripheral wafer PW2 may include a plurality of bonding pads BP13 on one of its surfaces, which are bonded to bonding pads BP12 of the first peripheral wafer PW1. The bonding pads BP13 may be connected to the peripheral circuit PERI via contacts CNT22a to CNT22c and wirings M22a and M22b.

[0118] An external connection pad (PAD) may be defined on the top surface of substrate 10b. A dielectric layer (ILD2b) may be defined on the top surface of substrate 10b and may have openings that expose the external connection pad (PAD). Although not shown, the external connection pad (PAD) may be connected to a peripheral circuit (PERI) via a through-hole through substrate 10b.

[0119] The cell wafer CW may include a substrate 20 and a memory cell array MCA defined on the substrate 20. A dielectric layer ILD3 may be defined on the substrate 20 to cover the memory cell array MCA. The top surface of the dielectric layer ILD3 may form a surface on which the cell wafer CW is bonded to the first peripheral wafer PW1.

[0120] The unit wafer CW may include multiple bonding pads BP14 on one of its surfaces. Each electrode layer 22 may be connected to one of the bonding pads BP14 via contacts CNT32a and CNT32b defined in the dielectric layer ILD3 and wiring M32a.

[0121] The unit wafer CW, the first peripheral wafer PW1, and the second peripheral wafer PW2 can be fabricated separately and then bonded together. The wirings M12a to M12c of the first peripheral wafer PW1 and the wirings M22a and M22b of the second peripheral wafer PW2 can be formed from a conductive material with low resistivity that may cause process failures at the process critical temperatures of the process forming the unit wafer CW. For example, the wirings M12a to M12c of the first peripheral wafer PW1 and the wirings M22a and M22b of the second peripheral wafer PW2 can be formed from copper or aluminum.

[0122] Because the first peripheral wafer PW1 and the second peripheral wafer PW2 are formed separately from the unit wafer CW, materials with low melting point and low resistivity can be used as conductive materials for forming the wirings M12a to M12c of the first peripheral wafer PW1 and the wirings M22a and M22b of the second peripheral wafer PW2.

[0123] As the area occupied by the line decoder X-DEC and page buffer circuit PBC increases due to high integration and high capacity, there are limitations in arranging the peripheral circuit PERI to overlap with the memory cell array MCA. Consequently, the area of ​​the memory device, i.e., the area of ​​the plane perpendicular to the first direction FD, can increase, thus limiting the increase in the integration density of the memory device. This embodiment removes the limitations on arranging the peripheral circuit PERI due to the presence of the line decoder X-DEC and page buffer circuit PBC by placing the peripheral circuit PERI on the surface of a different substrate separate from the line decoder X-DEC and page buffer circuit PBC, thereby contributing to improved integration density of the memory device.

[0124] Figure 10 This is a block diagram schematically illustrating a representation of a memory system including a memory device according to an embodiment of the present disclosure.

[0125] Reference Figure 10 The memory system 600 according to the embodiment may include a non-volatile memory device (NVM device) 610 and a memory controller 620.

[0126] The non-volatile memory device (NVM device) 610 can be constructed from the memory device described above and can operate in the manner described above. The memory controller 620 can be configured to control the non-volatile memory device (NVM device) 610. The combination of the non-volatile memory device (NVM device) 610 and the memory controller 620 can provide a memory card or solid-state drive (SSD). SRAM 621 serves as the working memory for the processing unit (CPU) 622. The host interface (host I / F) 623 includes a data exchange protocol for the host connected to the memory system 600.

[0127] Error correction code block (ECC) 624 detects and corrects errors included in data read from non-volatile memory device (NVM device) 610.

[0128] The memory interface (memory I / F) 625 is interfaced with the non-volatile memory device (NVM device) 610 of this embodiment. The processing unit (CPU) 622 performs overall control operations for data exchange with the memory controller 620.

[0129] Although not shown in the figures, it will be apparent to those skilled in the art that the memory system 600 according to the embodiment may additionally include a ROM storing code data for connection to a host interface. The non-volatile memory device (NVM device) 610 may be configured as a multi-chip package comprising multiple flash memory chips.

[0130] The memory system 600 according to the above embodiments can be provided as a highly reliable storage medium with a low probability of error occurrence. In particular, the non-volatile memory device of this embodiment can be included in memory systems such as solid-state drives (SSDs), which are currently under active research. In this case, the memory controller 620 can be configured to communicate with an external (e.g., a host) via one of various interface protocols such as USB (Universal Serial Bus), MMC (Multimedia Card), PCI-E (Rapid Peripheral Component Interconnect), SATA (Serial Advanced Technology Attached) protocol, PATA (Parallel Advanced Technology Attached) protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol, and IDE (Integrated Drive Electronic Devices) protocol.

[0131] Figure 11 This is a block diagram schematically illustrating a representation of a computing system including a memory device according to an embodiment of the present disclosure.

[0132] Reference Figure 11 The computing system 700 according to an embodiment may include a memory system 710, a microprocessor (CPU) 720, RAM 730, a user interface 740, and a modem 750, such as a baseband chipset, electrically connected to a system bus 760. In the case where the computing system 700 according to an embodiment is a mobile device, a battery (not shown) may be additionally provided to provide the operating voltage for the computing system 700. Although not shown in the figures, it will be apparent to those skilled in the art that the computing system 700 according to an embodiment may additionally include an application chipset, a camera image processor (CIS), and mobile DRAM, etc. The memory system 710 may be configured, for example, to use non-volatile memory to store data, as an SSD (solid-state drive / disk). Alternatively, the memory system 710 may be configured as converged flash memory (e.g., OneNAND flash memory).

[0133] Although exemplary embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments shown in the drawings and disclosed above should be considered descriptive only and not intended to limit the scope of the technology. The scope of this disclosure is not limited by the embodiments and drawings. The spirit and scope of this disclosure should be interpreted by the appended claims and cover all equivalents falling within the scope of the appended claims.

[0134] Cross-references to related applications

[0135] This application claims priority to Korean Patent Application No. 10-2020-0082736, filed on July 6, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A memory device comprising: A unit wafer, the unit wafer comprising a memory cell array; as well as A peripheral wafer, comprising row control circuitry, column control circuitry, and peripheral circuitry, is stacked on and bonded to the unit wafer in a first direction. The peripheral wafer includes: A first substrate, the first substrate having a first surface and a second surface facing away from each other in the first direction; A first logic structure, disposed on the first surface of the first substrate, includes the row control circuit and the column control circuit; and A second logic structure is disposed on the second surface of the first substrate, and the second logic structure includes the peripheral circuit.

2. The memory device of claim 1, wherein, The first surface is closer to the unit wafer in the first direction than the second surface.

3. The memory device according to claim 2, wherein, The cell wafer includes a plurality of first bonding pads on a surface of the cell wafer that is bonded to the peripheral wafer, which are connected to word lines and bit lines of the memory cell array. Wherein, the peripheral wafer includes a plurality of second bonding pads bonded to the plurality of first bonding pads on a surface of the peripheral wafer bonded to the unit wafer, and each of the plurality of second bonding pads is connected to the row control circuit or the column control circuit.

4. The memory device of claim 2, wherein, Each of the row control circuit and the column control circuit is connected to the peripheral circuit through a through-hole passing through the first substrate.

5. The memory device of claim 1, wherein, The memory cell array includes: Multiple word lines and multiple interlayer dielectric layers are alternately stacked on a second substrate; and Multiple vertical channels pass through the multiple word lines and the multiple interlayer dielectric layers.

6. A memory device comprising: A logic circuit component, the logic circuit component including row control circuit, column control circuit and peripheral circuit; as well as A unit component, which is stacked on the logic circuit component in a first direction, and includes a memory cell array. The logic circuit component includes: A substrate having a first surface and a second surface facing away from each other in the first direction; A first logic circuit component, disposed on the first surface of the substrate, and including the row control circuit and the column control circuit; and The second logic circuit component is disposed on the second surface of the substrate and includes the peripheral circuit.

7. The memory device of claim 6, wherein, The first surface is closer to the unit component in the first direction than the second surface.

8. The memory device of claim 7, wherein, Each of the row control circuit and the column control circuit is connected to the peripheral circuit via a through-hole passing through the substrate.

9. The memory device according to claim 7, in, The first logic circuit component further includes a first dielectric layer covering the row control circuit and the column control circuit, and a first wiring defined in the first dielectric layer. The second logic circuit component further includes a second dielectric layer covering the peripheral circuit and a second wiring defined in the second dielectric layer. The second wiring is formed of a material with a resistivity lower than that of the first wiring.

10. The memory device according to claim 6, wherein, The memory cell array includes: Source plate, which is stacked on the first logic circuit component; Multiple word lines and multiple interlayer dielectric layers are alternately stacked on the source plate; and Multiple vertical channels pass through the multiple word lines and the multiple interlayer dielectric layers.

11. The memory device according to any one of claims 1 to 10, wherein, The row control circuit is located in the thinning region and the column control circuit is located in the cell region.

12. The memory device according to any one of claims 1 to 10, wherein, When viewed in the first direction, the row control circuit is disposed in the thinning region and separates the column control circuits disposed in the separated cell regions, and The thinning region and the unit region are arranged in a second direction perpendicular to the first direction.

13. The memory device according to any one of claims 1 to 10, further comprising: When viewed in the first direction, the rectangular unit region is divided into four quadrants. Each of the four quadrants includes a portion of the row control circuit or the column control circuit.

14. The memory device according to claim 13, wherein, The portions of the row control circuit and the column control circuit are located at the corners of the rectangular cell region.

15. The memory device according to claim 13, wherein, The portions of the row control circuit and the column control circuit are located at the corners of each quadrant closest to the center of the rectangular cell region.

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