Light emitting diode and manufacturing process thereof

Abstract

The application provides a light emitting diode and a manufacturing process thereof. The light emitting diode comprises a substrate, an epitaxial structure and an insulating layer. The epitaxial structure is arranged on the substrate and comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are stacked in sequence. The epitaxial structure has four side walls, and the connecting part of two adjacent side walls forms an angle. The insulating layer covers the epitaxial structure, the side walls of the epitaxial structure and the substrate around the epitaxial structure. The insulating layer has a first gap which is located on the upper surface of the substrate and around at least one angle of the epitaxial structure. By the arrangement, the black point generated on the epitaxial structure can be reduced, and the yield and performance of the light emitting diode product are ensured.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a light-emitting diode and its manufacturing process. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor device that emits light by releasing energy when charge carriers recombine. LED chips have many advantages, such as low power consumption, pure color, long life, small size, fast response time, energy saving and environmental protection.

[0003] In the LED chip manufacturing process, cutting LED wafers into individual LED chips is a crucial step. Currently, LED chips are cut using laser stealth cutting. During the cutting process, the laser cuts along the horizontal and vertical cutting tracks to divide the LED wafer into individual chips.

[0004] However, because the laser repeatedly scans the intersection area of ​​the cutting track, the DBR structure reflects the laser, resulting in severe burns of the epitaxial layer near the intersection area, causing black spots and ultimately affecting the performance of the LED product.

[0005] Therefore, ensuring the yield and performance of light-emitting diode products has become one of the technical challenges that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] To address the aforementioned problems of low yield and poor performance of light-emitting diode (LED) products, this invention provides a manufacturing process for LEDs, comprising the following steps: forming an epitaxial layer on a substrate, the epitaxial layer comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked from bottom to top; etching the epitaxial layer to expose a portion of the upper surface of the substrate to form multiple independent epitaxial structures and forming cleaving channels around the epitaxial structures, wherein each epitaxial structure has four sidewalls, and the cleaving channels include lateral cleaving channels and longitudinal cleaving channels, the lateral cleaving channels and the longitudinal cleaving channels intersecting to form an intersection region; covering the cleaving channels, the upper surface of the epitaxial structures, and the sidewalls of the epitaxial structures with an insulating layer; etching the insulating layer to form a first notch located in the intersection region; and cutting along the lateral cleaving channels and the longitudinal cleaving channels to obtain an LED.

[0007] In one embodiment, the shape of the first notch can be cross-shaped, square, polygonal, circular, or elliptical.

[0008] In one embodiment, while forming the first gap, a second gap is also formed between the sidewalls of two adjacent extension structures. The second gap is located on the non-intersecting area of ​​the cutting channel, and the width of the first gap located in the intersecting area is greater than the width of the second gap located in the non-intersecting area.

[0009] In one embodiment, the first gap is formed only in the intersection area, and the insulating layer on the non-intersection area of ​​the cut is fully preserved.

[0010] In one embodiment, the insulating layer has a sidewall at the first notch, and the bottom of the sidewall at the first notch has a minimum horizontal distance from the sidewall of the epitaxial structure, the minimum horizontal distance being at least 4 micrometers.

[0011] In one embodiment, while forming the cutting path around the epitaxial structure, the corners of each epitaxial structure are recessed toward the center of the epitaxial structure to form a groove.

[0012] In one embodiment, after the dicing step, the edges of the substrate surrounding the four sidewalls of the epitaxial structure are aligned with the edges of the insulating layer, and the first notch is located around the junction of two adjacent sidewalls of the epitaxial structure.

[0013] The present invention also provides a light-emitting diode, comprising a substrate, an epitaxial structure, and an insulating layer. The epitaxial structure is disposed on the upper surface of the substrate and includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially. The epitaxial structure has four sidewalls, with the connection portions of adjacent two sidewalls forming an angle. The insulating layer covers the epitaxial structure, the sidewalls of the epitaxial structure, and the substrate surrounding the epitaxial structure. The insulating layer has a first notch located on the upper surface of the substrate and around at least one of the corners of the epitaxial structure.

[0014] In one embodiment, the shape of the first notch can be "L", square, triangle, concave polygon or fan.

[0015] In one embodiment, the first notch is located only around the corner of the epitaxial structure.

[0016] In one embodiment, when viewed from above the light-emitting diode toward the substrate, the minimum distance from the first notch of the insulating layer to the corner of the epitaxial structure is less than the minimum distance from the sidewall of the epitaxial structure to the edge of the substrate.

[0017] In one embodiment, the epitaxial structure has a plane that exposes a portion of the first semiconductor layer.

[0018] In one embodiment, the insulating layer has a sidewall at the first notch, and the bottom of the sidewall of the insulating layer has a minimum horizontal distance from the corner of the epitaxial structure, the minimum horizontal distance being at least 4 micrometers.

[0019] In one embodiment, viewed from above the light-emitting diode toward the substrate, the corners of the epitaxial structure are recessed toward the center of the epitaxial structure to form a groove.

[0020] In one embodiment, the projection of the groove onto the horizontal plane is L-shaped, polygonal, or arc-shaped.

[0021] In one embodiment, the edges of the substrate surrounding the four sidewalls of the epitaxial structure are aligned with the edges of the insulating layer.

[0022] In one embodiment, the insulating layer further has a second notch located around the four sidewalls of the epitaxial structure, and the minimum distance from the second notch to the epitaxial structure is greater than the minimum distance from the first notch around the corner to the epitaxial structure.

[0023] The light-emitting diode and its manufacturing process provided by this invention reduce the risk of black spots by designing a first notch in the insulating layer, thereby ensuring the yield and performance of the light-emitting diode products.

[0024] The present invention also provides a light-emitting diode and its manufacturing process. By designing the corners of the epitaxial structure to be concave, the epitaxial structure can be kept away from the burst point, thus avoiding damage to the epitaxial structure during laser cutting.

[0025] Other features and beneficial effects of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects of the invention and other beneficial effects may be realized and obtained by means of the structures particularly pointed out in the description, claims, etc. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Unless otherwise specified, the positional relationships shown in the drawings in the following description are based on the direction in which the components are drawn in the figure.

[0027] Figure 1 This is a schematic flowchart of the manufacturing process of the light-emitting diode of the present invention;

[0028] Figure 2This is a cross-sectional schematic diagram of a wafer fabrication stage provided in an embodiment of the present invention;

[0029] Figure 3 yes Figure 2 A top-view structural diagram;

[0030] Figure 4 This is a top view schematic diagram of a wafer structure provided in another embodiment of the present invention;

[0031] Figure 5 This is a top view schematic diagram of a wafer structure provided in another embodiment of the present invention;

[0032] Figure 6 This is a top view schematic diagram of a wafer structure provided in another embodiment of the present invention;

[0033] Figure 7 This is a top view schematic diagram of a wafer structure provided in another embodiment of the present invention;

[0034] Figure 8 This is a top view schematic diagram of a wafer structure provided in another embodiment of the present invention;

[0035] Figure 9 This is a top view schematic diagram of a wafer structure provided in another embodiment of the present invention;

[0036] Figure 10 This is a top view schematic diagram of a wafer structure provided in another embodiment of the present invention;

[0037] Figure 11 This is a cross-sectional schematic diagram of a light-emitting diode provided in an embodiment of the present invention;

[0038] Figure 12 yes Figure 11 A top view of a light-emitting diode;

[0039] Figure 13 This is a top view of the structure of a light-emitting diode provided in another embodiment of the present invention;

[0040] Figure 14 This is a cross-sectional schematic diagram of a light-emitting diode provided in another embodiment of the present invention;

[0041] Figure 15 yes Figure 14 A top view of a light-emitting diode.

[0042] Figure label:

[0043] 10, 11, 12, 13, 14, 15, 17, 18, 57 LEDs with 18 substrates

[0044] 51 and 52 wafers

[0045] 20, 60 Epitaxial structure 21, 61 First semiconductor layer 211 Sidewall

[0046] 212 corner 22, 62 light-emitting layer 23, 63 second semiconductor layer

[0047] 30 Horizontal cutting track 32 Vertical cutting track 34 Intersection area

[0048] 36 Insulating layer 361 First opening 362 Second opening

[0049] 363 First Notch 38 Current Extension Layer 41 First Electrode

[0050] 411 First contact electrode; 412 First pad electrode; 42 Second electrode

[0051] 421 Second contact electrode 422 Second pad electrode 611 Groove

[0052] D1 Minimum horizontal distance; D2 Second distance; W1, W2, W3 Width

[0053] 364 Second gap 368 Side wall Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The technical features designed in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0055] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof mean "at least comprising."

[0056] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integrally formed connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0058] Please see Figure 1 , Figure 2 and Figure 3 , Figure 1 This is a schematic flowchart of the manufacturing process of the light-emitting diode of the present invention. Figure 2 This is a cross-sectional schematic diagram of a wafer 10 process stage provided in an embodiment of the present invention. Figure 3 yes Figure 2 A top view structural schematic diagram. To achieve at least one or more advantages, an embodiment of the present invention provides a manufacturing process for a light-emitting diode. As shown in the figure, the manufacturing process for a light-emitting diode includes the following steps:

[0059] S100: An epitaxial layer is formed on a substrate, the epitaxial layer comprising a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked from bottom to top;

[0060] S200: Etch the epitaxial layer to expose a portion of the upper surface of the substrate to form multiple independent epitaxial structures and form cleavage around the epitaxial structures;

[0061] S300: Use an insulating layer to cover the cut path, the upper surface of the epitaxial structure, and the sidewalls of the epitaxial structure;

[0062] S400: Etch the insulating layer to form the first notch located in the intersection region;

[0063] S500: Cut along the horizontal and vertical cutting lines to obtain a light-emitting diode.

[0064] After step S100, the following step may also be performed: etching the second semiconductor layer 23 to the upper surface of the first semiconductor layer 21 to form an electrode mesa. For example... Figure 2 As shown, the electrode mesa includes a ramp extending through the second semiconductor layer 23 and the light-emitting layer 22, and a plane exposing a portion of the first semiconductor layer 21. The insulating layer 36 covers the electrode mesa, i.e., covers both the ramp and the plane.

[0065] In step S200, as Figure 3 As shown, each independent extension structure 20 has four sidewalls 211. Cutting channels are formed between the sidewalls 211 of adjacent independent extension structures 20, including transverse cutting channels 30 and longitudinal cutting channels 32. The transverse cutting channels 30 and longitudinal cutting channels 32 intersect each other to form an intersection area 34. That is, the position where the transverse cutting channels 30 and longitudinal cutting channels 32 intersect and overlap is the intersection area 34.

[0066] In step S400, as Figure 2 As shown, the first notch 363 and the edge of the first semiconductor layer 21 have a first distance D1, which ranges from 0.3 micrometers to 1.5 micrometers. By limiting the distance from the first notch 363 to the corner of the first semiconductor layer 21, the size of the first notch 363 can be maximized while ensuring that the insulating layer 36 has a certain coverage thickness, thus avoiding the generation of black spots on the epitaxial structure 20. Figure 3 As shown, the first notch 363 is the shaded area in the diagram, which can be cross-shaped, which is beneficial for the manufacturing process. However, this case is not limited to this; for example: Figure 5 The first notch 363 in the wafer 12 structure can be polygonal; Figure 6 The first notch 363 in the wafer 13 structure can be circular, near-circular, or almost circular; Figure 7 The first notch 363 in the wafer 14 structure can be square; Figure 8The epitaxial structure 20 in the wafer 15 structure can be staggered, and the first notch 363 can be polygonal. Furthermore, any notch formed by etching the insulating layer 36 in the intersection region 34 of the transverse dicing 30 and the longitudinal dicing 32 should be considered as the first notch 363 of this patent.

[0067] In step S400, when etching the insulating layer 36, a first opening 361 and a second opening 362 can also be formed. For example... Figure 2 As shown, the first opening 361 is formed by etching the insulating layer 36 onto the upper surface of the first semiconductor layer 21, and the second opening 362 is formed by etching the insulating layer 36 onto the upper surface of the second semiconductor layer 23. Furthermore, after etching the insulating layer 36, a first electrode 41 and a second electrode 42 can be provided, i.e., the first electrode 41 is electrically connected to the first semiconductor layer 21 through the first opening 361, and the second electrode 42 is electrically connected to the second semiconductor layer 23 through the second opening 362.

[0068] In one embodiment, such as Figure 2 As shown, the first electrode 41 includes a first contact electrode 411 and a first pad electrode 412, and the second electrode 42 includes a second contact electrode 421 and a second pad electrode 422. The first contact electrode 411 is located at the electrode mesa of the first semiconductor layer 21 and forms an ohmic contact with the first semiconductor layer 21. The first pad electrode 412 is located on the insulating layer 36 and is electrically connected to the first contact electrode 411 through a first opening 361. The second contact electrode 421 is located on the second semiconductor layer 23 and forms an ohmic contact with the second semiconductor layer 23. The second pad electrode 422 is located on the insulating layer 36 and is electrically connected to the second contact electrode 421 through a second opening 362.

[0069] The first electrode 41 and the second electrode 42 are metal electrodes for supplying current to the outside, such as nickel, gold, chromium, titanium, platinum, palladium, rhodium, iridium, aluminum, tin, indium, tantalum, copper, cobalt, iron, ruthenium, zirconium, tungsten, molybdenum, or one or a combination thereof.

[0070] In one embodiment, such as Figure 2 As shown, a current spreading layer 38 can be deposited on the second semiconductor layer 23, and an insulating layer 36 covers the current spreading layer 38. The material of the current spreading layer 38 can be one or a combination of ITO, GTO, GZO, and ZnO, and is not limited to the examples listed here.

[0071] In one embodiment, such as Figure 2 As shown, the insulating layer 36 has a sidewall 368 at the first notch 363, and the bottom of the sidewall 368 at the first notch 363 has a minimum horizontal distance D1 with the sidewall 211 of the extension structure 20, the minimum horizontal distance D1 being at least 4 micrometers.

[0072] In one embodiment, such as Figure 9 , Figure 10 As shown, while forming the dicing path around the epitaxial structure 20 in step S200, the following step can also be performed: the corners of each epitaxial structure are recessed towards the center of the epitaxial structure to form a groove. That is, the corners of the epitaxial structure 60 are etched inward to form a groove 611. From the top view, in this type of wafer 51, 52 structure, the corners of the epitaxial structure 60 are concave in shape, and preferably, the projection of the groove 611 on the horizontal plane is an arc shape. This setting allows the epitaxial structure 60 to be kept away from the laser cutting point (the intersection of the transverse dicing path 30 and the longitudinal dicing path 32), avoiding damage to the epitaxial structure 60 during laser cutting. Figure 9 , Figure 10 As shown, in order to match the concave extension structure 60, the shape of the first notch 363 can also be designed as a convex polygon to increase the size of the first notch 363.

[0073] The cutting operation in step S500, with Figure 3 To put it simply, cutting is performed along the horizontal cutting channel 30 and the vertical cutting channel 32, resulting in four light-emitting diodes.

[0074] Please see Figure 11 and Figure 12 , Figure 11 This is a cross-sectional schematic diagram of a light-emitting diode 17 provided in an embodiment of the present invention. Figure 12 yes Figure 11 A top view schematic diagram of a light-emitting diode 17. It should be noted that the light-emitting diode 17 is obtained by cutting in step S500 of the light-emitting diode manufacturing process. To achieve at least one or more advantages, an embodiment of the present invention provides a light-emitting diode 17. As shown in the figure, the light-emitting diode 17 includes a substrate 18, an epitaxial structure 20, and an insulating layer 36.

[0075] The substrate 18 can be a transparent substrate, a non-transparent substrate, or a semi-transparent substrate. The transparent or semi-transparent substrate allows the light radiated from the light-emitting layer 22 to pass through the substrate 18 and reach the side of the substrate 18 away from the epitaxial structure 20. For example, the substrate 18 can be any one of a sapphire flat substrate, a sapphire patterned substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, or a glass substrate.

[0076] The epitaxial structure 20 is disposed on the upper surface of the substrate 18 and includes a first semiconductor layer 21, a light-emitting layer 22 and a second semiconductor layer 23 stacked sequentially.

[0077] The first semiconductor layer 21, grown on the substrate 18, can be a gallium nitride semiconductor layer doped with n-type impurities, such as Si.

[0078] The light-emitting layer 22 can have a single quantum well structure or a multiple quantum well structure. The composition and thickness of the well layers within the light-emitting layer 22 determine the wavelength of the generated light. In particular, by adjusting the composition of the well layers, light-emitting layers 22 can be provided to generate different colors of light, such as ultraviolet light, blue light, and green light.

[0079] The second semiconductor layer 23 can be a gallium nitride semiconductor layer doped with p-type impurities, such as Mg. Although the first semiconductor layer 21 and the second semiconductor layer 23 can each be a single layer, this invention is not limited to this and can also be multiple layers, and may also include a superlattice layer. The first semiconductor layer 21, the light-emitting layer 22, and the second semiconductor layer 23 can be formed on the substrate 18 using methods such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0080] The extensional structure 20 also has multiple sidewalls 211, and the connection portion of two adjacent sidewalls 211 forms an angle 212. Taking the figure as an example, the extensional structure 20 has four sidewalls 211, and the connection portion of two adjacent sidewalls 211 forms an angle 212, forming a total of four angles 212.

[0081] An insulating layer 36 covers the epitaxial structure 20, the sidewalls 211 of the epitaxial structure 20, and the substrate 18 surrounding the epitaxial structure 20. The insulating layer 36 can be formed using techniques such as chemical vapor deposition (CVD) as an oxide film such as SiO2, a nitride film such as SiNx, or an insulating film such as MgF2. The insulating layer 36 can be formed as a single layer or as a structure of repeated stacked layers. The structure of repeated stacked layers can be formed by alternating layers of low-refractive-index and high-refractive-index materials in a distributed Bragg reflector (DBR). For example, a highly reflective insulating layer 36 can be formed by stacking SiO2 / TiO2, SiO2 / ZrO2, or MgF2 / TiO2.

[0082] The insulating layer 36 has a first notch 363 located on the upper surface of the substrate 18 and around at least one corner 212 of the epitaxial structure 20. Preferably, the first notch 363 is located around all corners 212 of the epitaxial structure 20 to avoid the formation of black spots. Preferably, the first notch 363 is only located around the corners 212 of the epitaxial structure 20; in other words, the first notch 363 is formed only in the intersection region 34 of the dicing, and the insulating layer 36 on the non-intersection region of the dicing is fully preserved to avoid the formation of black spots on the epitaxial structure 20.

[0083] From top view Figure 12 As can be seen, the shape of the first notch 363 of the light-emitting diode 17 obtained after cutting can be "L" shaped. However, this case is not limited to this, referring to... Figures 4 to 8 After being cut along the transverse cutting channel 30 and the longitudinal cutting channel 32, the first notch 363 of a single light-emitting diode 17 can also be square, triangular, concave polygonal or fan-shaped.

[0084] In one embodiment, viewed from above the light-emitting diode 17 toward the substrate 18, as shown... Figure 12 , Figure 13 As shown, the minimum distance from the first notch 363 of the insulating layer 36 to the corner 212 of the epitaxial structure 20 is less than the minimum distance from the sidewall 211 of the epitaxial structure 20 to the edge of the substrate 18.

[0085] In one embodiment, such as Figure 13 As shown, the insulating layer 36 of this light-emitting diode 18 also has a second notch 364, which is located around the four sidewalls 211 of the epitaxial structure 20. Preferably, the second notch 364 is connected to the first notch 363 and arranged to surround the epitaxial structure 20, that is, to encircle and cover the epitaxial structure 20. For example, in the illustration, the first notch 363 is around the four corners 212 of the epitaxial structure 20, and the second notch 364 is around the four sidewalls 211 of the epitaxial structure 20, so as to release more stress on the insulating layer 36, protect the epitaxial structure 20, and prevent chip warping. More preferably, the minimum distance from the second notch 364 around the sidewall 211 to the epitaxial structure (e.g., the first semiconductor layer 21) is greater than the minimum distance from the first notch 363 around the corner 212 to the epitaxial structure (e.g., the first semiconductor layer 21). The second notch 364 is preferably narrower mainly to prevent moisture from entering the epitaxial structure 20.

[0086] In one embodiment, such as Figure 11 As shown, the insulating layer 36 has a sidewall 368 at the first notch 363. The bottom of the sidewall 368 of the insulating layer 36 has a minimum horizontal distance D1 with the corner 212 of the epitaxial structure 20. The minimum horizontal distance D1 is at least 4 micrometers to avoid damaging the epitaxial structure 20 during the notch formation process.

[0087] In one embodiment, such as Figure 11 As shown, the insulating layer 36 and the sidewall 211 on the same side of the substrate 18 have a second distance D2, which is greater than or equal to 2.5 micrometers, to maximize the first notch 363 in order to avoid the generation of black spots.

[0088] like Figure 11As shown, the epitaxial structure 20 also has an electrode mesa, which includes a slope penetrating the second semiconductor layer 23 and the light-emitting layer 22, and a plane exposing a portion of the first semiconductor layer 21. The insulating layer 36 covers the slope and the plane. The light-emitting diode 17 also includes a first electrode 41 and a second electrode 42. The first electrode 41 is electrically connected to the first semiconductor layer 21 through a first opening 361, and the second electrode 42 is electrically connected to the second semiconductor layer 23 through a second opening 362. Specifically, the first electrode 41 includes a first contact electrode 411 and a first pad electrode 412, and the second electrode 42 includes a second contact electrode 421 and a second pad electrode 422. The first contact electrode 411 is located on the plane of the first semiconductor layer 21 and forms an ohmic contact with the first semiconductor layer 21. The first pad electrode 412 is located on the insulating layer 36 and is electrically connected to the first contact electrode 411 through the first opening 361. The second contact electrode 421 is located on the second semiconductor layer 23 and forms an ohmic contact with the second semiconductor layer 23. The second pad electrode 422 is located on the insulating layer 36 and is electrically connected to the second contact electrode 421 through the second opening 362. The light-emitting diode 17 also includes a current spreading layer 38, which is located between the second semiconductor layer 23 and the second contact electrode 421 and is covered by the insulating layer 36.

[0089] Please see Figure 14 and Figure 15 , Figure 14 This is a cross-sectional schematic diagram of a light-emitting diode 57 provided in another embodiment of the present invention. Figure 15 yes Figure 14 A top view schematic diagram of the light-emitting diode 57. To achieve at least one or more advantages, another embodiment of the invention further provides a light-emitting diode 57, compared to... Figure 11 Regarding the light-emitting diode 17, the epitaxial structure 60 in this embodiment includes a first semiconductor layer 61, a light-emitting layer 62, and a second semiconductor layer 63. Electrode mesa are formed on both sides of the epitaxial structure 60. Each electrode mesa includes a sloping surface penetrating the second semiconductor layer 63 and the light-emitting layer 62, and a plane exposing a portion of the first semiconductor layer 61. The four corners 212 of the first semiconductor layer 61 are recessed inward to form grooves 611. That is, the corners 212 of the epitaxial structure 60 are recessed towards the center of the epitaxial structure 60 to form grooves 611, so that the epitaxial structure 60 as a whole is far away from the laser cutting point, avoiding damage to the epitaxial structure 20 during laser cutting. Preferably, the projection of the groove 611 onto the horizontal plane is an arc shape. However, this embodiment is not limited to this; the projection of the groove 611 onto the horizontal plane can also be a right angle, etc. The effect of being far away from the cutting point can be achieved simply by recessing it into the epitaxial structure 20.

[0090] In summary, the light-emitting diode and its manufacturing process provided by this invention reduce the possibility of damage to the epitaxial structures 20 and 60 by designing a first notch 363 in the insulating layer 36, thereby reducing the proportion of black spots and ensuring the yield and performance of the light-emitting diode product. Specifically, when the laser cuts along the transverse cutting track 30 and the longitudinal cutting track 32, the insulating layer 36 in the intersection region 34 is etched away, forming the first notch 363, thus reducing the area of ​​the insulating layer 36 in the intersection region 34 and reducing the proportion of black spots. Preferably, a portion of the insulating layer 36 in the non-intersection region of the transverse cutting track 30 and the longitudinal cutting track 32 is etched away to form a second notch 364, which can release more stress on the insulating layer 36 and further improve the yield and performance of the light-emitting diode product.

[0091] The light-emitting diode and its manufacturing process can also be designed by making the corners of the epitaxial structures 20 and 60 concave, so that the epitaxial structures 20 and 60 are far away from the burst point, thus avoiding damage to the epitaxial structures 20 and 60 during laser cutting.

[0092] Furthermore, those skilled in the art should understand that although many problems exist in the prior art, each embodiment or technical solution of the present invention can be improved in only one or a few aspects, without necessarily solving all the technical problems listed in the prior art or the background art simultaneously. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as a limitation on that claim.

[0093] Although this document uses terms such as wafer, electrode, and semiconductor frequently, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of the invention; interpreting them as any additional limitation would contradict the spirit of the invention.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A manufacturing process for a light-emitting diode, characterized in that, The manufacturing process of the light-emitting diode includes the following steps: (1) An epitaxial layer is formed on a substrate, the epitaxial layer comprising a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked from bottom to top; (2) Etching the epitaxial layer to expose a portion of the upper surface of the substrate to form a plurality of independent epitaxial structures and forming cleaving channels around the epitaxial structures, wherein each epitaxial structure has four sidewalls and the cleaving channels include transverse cleaving channels and longitudinal cleaving channels, the transverse cleaving channels and the longitudinal cleaving channels intersect each other to form an intersection area; (3) Use an insulating layer to cover the cut path, the upper surface of the epitaxial structure, and the sidewalls of the epitaxial structure; (4) Etching the insulating layer to form a first notch located in the intersection region; and (5) Laser cutting is performed along the transverse and longitudinal cutting lines to obtain light-emitting diodes; The substrate is a transparent substrate, a non-transparent substrate, or a semi-transparent substrate; the insulating layer completely covers the sidewalls of the epitaxial structure.

2. The manufacturing process of the light-emitting diode according to claim 1, characterized in that: The first notch is polygonal, circular, or elliptical in shape.

3. The manufacturing process of the light-emitting diode according to claim 1, characterized in that: While forming the first gap in step (4), a second gap is also formed between the sidewalls of two adjacent extension structures. The second gap is located in the non-intersecting area of ​​the cutting channel, and the width of the first gap in the intersecting area is greater than the width of the second gap in the non-intersecting area.

4. The manufacturing process of the light-emitting diode according to claim 1, characterized in that: The first gap in step (4) is formed only in the intersection area, and the insulation layer on the non-intersection area of ​​the cut is completely preserved.

5. The manufacturing process of the light-emitting diode according to claim 1, characterized in that: The insulating layer has a sidewall at the first notch, and the bottom of the sidewall at the first notch has a minimum horizontal distance from the sidewall of the epitaxial structure, the minimum horizontal distance being at least 4 micrometers.

6. The manufacturing process of the light-emitting diode according to claim 1, characterized in that: While forming the cutting path around the epitaxial structure in step (2), the corners of each epitaxial structure are recessed toward the center of the epitaxial structure to form a groove.

7. The manufacturing process of the light-emitting diode according to claim 1, characterized in that: After cutting in step (5), the edges of the substrate around the four sidewalls of the epitaxial structure are aligned with the edges of the insulating layer, and the first notch is located around the connection between two adjacent sidewalls of the epitaxial structure.

8. A light-emitting diode, characterized in that, The light-emitting diode includes: Substrate; An epitaxial structure, disposed on a portion of the upper surface of the substrate, includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially. The epitaxial structure has four sidewalls, and the connection portions of adjacent two sidewalls form an angle. An insulating layer covers the epitaxial structure, the sidewalls of the epitaxial structure, and the substrate surrounding the epitaxial structure, the insulating layer having a first notch; The first notch is located on the upper surface of the substrate and is situated around at least one corner of the epitaxial structure; The substrate is a transparent substrate, a non-transparent substrate, or a semi-transparent substrate; the insulating layer completely covers the sidewalls of the epitaxial structure.

9. The light-emitting diode according to claim 8, characterized in that: The first notch is polygonal or arc-shaped.

10. The light-emitting diode according to claim 8, characterized in that: The first notch is located only around the corner of the epitaxial structure.

11. The light-emitting diode according to claim 8, characterized in that: Viewed from above the light-emitting diode toward the substrate, the minimum distance from the first notch of the insulating layer to the corner of the epitaxial structure is less than the minimum distance from the sidewall of the epitaxial structure to the edge of the substrate.

12. The light-emitting diode according to claim 8, characterized in that: The insulating layer has a sidewall at the first notch, and the bottom of the sidewall of the insulating layer has a minimum horizontal distance from the corner of the epitaxial structure, the minimum horizontal distance being at least 4 micrometers.

13. The light-emitting diode according to claim 8, characterized in that: Viewed from above the light-emitting diode toward the substrate, the corners of the epitaxial structure are recessed toward the center of the epitaxial structure to form a groove.

14. The light-emitting diode according to claim 13, characterized in that: The projection of the groove onto the horizontal plane is polygonal or arc-shaped.

15. The light-emitting diode according to claim 8, characterized in that: The edges of the substrate surrounding the four sidewalls of the epitaxial structure are aligned with the edges of the insulating layer.

16. The light-emitting diode according to claim 8, characterized in that: The insulating layer also has a second notch located around the four sidewalls of the epitaxial structure, and the minimum distance from the second notch to the epitaxial structure is greater than the minimum distance from the first notch around the corner to the epitaxial structure.

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