Vertical cavity surface emitting laser array with isolated cathodes and common anode

Abstract

A vertical cavity surface emitting laser (VCSEL) array can include an n-type substrate layer and an n-type metal on a bottom surface of the n-type substrate layer. The n-type metal can form a common anode for a set of VCSELs. The VCSEL array can include a bottom mirror structure on a top surface of the n-type substrate layer. The bottom mirror structure can include one or more bottom mirror sections and a tunnel junction that reverses the carrier type within the bottom mirror structure. The VCSEL array can include an active region on the bottom mirror structure, and an oxidation layer to provide optical and electrical confinement. The VCSEL array can include an n-type top mirror on the active region, a top contact layer above the n-type top mirror, and a top metal on the top contact layer. The top metal can form an isolated cathode for the VCSEL array.

Description

Technical Field

[0001] This disclosure generally relates to vertical-cavity surface-emitting laser (VCSEL) arrays, and more specifically, to VCSEL arrays having isolated cathodes and a common anode. Background Technology

[0002] A VCSEL is a semiconductor laser, more specifically, a diode laser with a monolithic laser resonator in which light is emitted in a direction perpendicular to the chip surface. Typically, the laser resonator consists of two distributed Bragg reflector (DBR) mirrors parallel to the chip surface, with the light-generating active region (composed of one or more quantum wells) between them. Typically, the upper and lower mirrors of a VCSEL are doped with p-type and n-type materials, respectively, thus forming a diode junction. Summary of the Invention

[0003] In some embodiments, a VCSEL array may include an n-type substrate layer having a top surface and a bottom surface; an n-type metal on the bottom surface of the n-type substrate layer, the n-type metal forming a common anode for a group of VCSEL arrays including the VCSEL array; a bottom mirror structure on the top surface of the n-type substrate layer, the bottom mirror structure including one or more bottom mirror portions and a tunnel junction of a carrier type within the inverted bottom mirror structure; an active region on the bottom mirror structure; an oxide layer for providing optical and electrical confinement of the VCSELs of the VCSEL array; an n-type top mirror on the active region; a top contact layer above the n-type top mirror; and a top metal on the top contact layer, the top metal forming an isolation cathode for the VCSEL array.

[0004] In some embodiments, the optical device may include a plurality of VCSEL arrays, the plurality of VCSEL arrays including an n-type metal on a first surface of an n-type substrate layer, the n-type metal forming a common anode for each of the plurality of VCSEL arrays; a bottom mirror structure on a second surface of the n-type substrate layer, the bottom mirror structure including at least one bottom mirror portion and a tunnel junction of a reverse carrier type within the bottom mirror structure; an active region on the bottom mirror structure; an oxide layer for providing optical and electrical confinement for the VCSELs included in the plurality of VCSEL arrays; an n-type top mirror on the active region; a top contact layer above the n-type top mirror; and a top metal on the top contact layer, the top metal forming an isolation cathode for each of the plurality of VCSEL arrays.

[0005] In some embodiments, a method may include forming an n-type metal on a first surface of an n-type substrate layer, the n-type metal providing a common anode for a plurality of VCSEL arrays; forming a bottom mirror structure on a second surface of the n-type substrate layer, the bottom mirror structure including one or more bottom mirror portions and a tunnel junction of a carrier type within the inverted bottom mirror structure; forming an active region on the bottom mirror structure; forming an oxide layer to provide optical and electrical confinement for VCSELs included in the plurality of VCSEL arrays; forming an n-type top mirror on the active region; forming a top contact layer above the n-type top mirror; and forming a top metal on the top contact layer, the top metal providing an isolation cathode for each of the plurality of VCSEL arrays. Attached Figure Description

[0006] Figure 1A and 1B This is a schematic diagram illustrating a traditional VCSEL example.

[0007] Figure 2A-2C This is a figure associated with a first exemplary embodiment of a VCSEL array having an isolated cathode and a common anode and a tunnel junction as described herein.

[0008] Figures 3A-3C This is a figure associated with a second exemplary embodiment of a VCSEL array having an isolated cathode and a common anode and multiple tunnel junctions as described herein.

[0009] Figure 4A and 4B This is a schematic diagram illustrating an example of a VCSEL array having isolated cathode contacts on an n-type substrate used as a common anode, as described herein.

[0010] Figures 5A-5C This is a schematic diagram illustrating an example arrangement of a VCSEL array in an optical device as described herein.

[0011] Figure 6 This is a flowchart of an example process related to the fabrication of a VCSEL array as described herein, featuring an isolated cathode and a common anode, as well as a tunnel junction. Detailed Implementation

[0012] The following detailed description of exemplary embodiments is with reference to the accompanying drawings. The same reference numerals in different drawings may identify the same or similar elements.

[0013] Two-dimensional (2D) VCSEL arrays can be used in applications such as three-dimensional sensing (3DS). In 3DS applications, there is an increasing need for VCSEL arrays (e.g., subarrays) with multiple transmitters having independent electrical connections (e.g., to allow illumination of different parts of a scene or different patterns). Typically, the system is designed so that these multiple transmitters (e.g., on the same chip) are driven independently of a single integrated circuit chip.

[0014] A current source is typically required to drive such VCSEL arrays stably because of their low differential resistance, which varies inversely with the number of emitters, which can differ by section. In practice, at the output stage of the current source, the VCSEL array is connected to transistors such as bipolar junction transistors (BJTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), or metal-semiconductor field-effect transistors (MESFETs). BJTs can be either npn or pnp. Similarly, MOSFETs can be either n-channel or p-channel, where n and p represent the carrier types in the transistor section. The carrier type of the transistor determines the relative polarity of the transistor terminals during operation. Notably, in the case of MOSFETs, n-channel transistors generally exhibit better performance characteristics than p-channel transistors (e.g., n-channel transistors have relatively higher speeds and lower resistances due to higher electron mobility over holes). Likewise, for BJTs, npn transistors generally exhibit better performance characteristics than pnp transistors. Therefore, when driving VCSEL arrays, it is preferable to use n-channel transistors (in the case of MOSFETs) or npn transistors (in the case of BJTs).

[0015] Additionally, to reduce manufacturing complexity, VCSEL arrays with multiple sections can be designed, where sections of the VCSEL array share a common anode or a common cathode. However, for such multi-section VCSEL arrays with a common contact (common anode or common cathode), the possible circuit design and transistor types in the output stage of the current driver may be limited. For example, a multi-section VCSEL array with a common cathode can be driven by a pnp transistor array (or p-channel transistor array), where each transistor drives a different section of the VCSEL array. Here, due to the circuit configuration typically used in current drivers, the pnp transistors (or p-channel transistors) supplying current to the multi-section VCSEL array require isolated anodes and a common cathode. As another example, a multi-section VCSEL array with a common anode can be driven by an npn transistor array (or n-channel transistor array), where each transistor drives a different section of the VCSEL array. Here, due to the typical circuit configuration, the npn transistors (or n-channel transistors) supplying current to the multi-section VCSEL array require isolated cathodes and a common anode.

[0016] Generally, single-part VCSEL arrays can be used with transistors of any carrier type—either n-channel or p-channel in the case of MOSFETs—with no limitations on circuit design. However, even for single-part VCSEL arrays, a substrate may be required as the anode. For example, if multiple chips are bonded relatively close to each other, it may be desirable to electrically connect the substrates to allow for the closest possible spacing without managing conductive epoxy or solder die-attach materials to short-circuit the two arrays. In this case, the chips will function electrically as a multi-part VCSEL array, and when driven with n-channel or npn transistors, the substrate is expected to act as the anode. Notably, it is possible to fabricate multi-part VCSEL arrays where each part has an isolated cathode and an isolated anode, and in this case, there are no limitations on the circuitry and transistor type of the current-driven output stage. However, such multi-part VCSEL arrays require additional processing steps and die area, resulting in higher manufacturing costs.

[0017] Furthermore, common anode designs with n-type substrates are superior to those with p-type substrates because p-type substrates have a higher defect density and are not currently mass-produced. Additionally, p-type substrates exhibit significantly higher (e.g., more than twice) optical loss compared to n-type substrates, a characteristic particularly relevant to bottom-emitting VCSELs (e.g., VCSELs that emit light through the substrate). Moreover, the low hole mobility means that the conductivity of p-type substrates can be 4 to 10 times worse than that of n-type substrates. When fabricating dense emitter arrays (e.g., hundreds of emitters per square millimeter), carrying several amperes per square millimeter, this voltage drop becomes significant. Therefore, n-type common anode VCSEL arrays are superior in terms of large-volume manufacturability, reliability, and performance.

[0018] Some embodiments described herein provide VCSEL arrays comprising one or more subarrays on a common n-type substrate, wherein the substrate serves as a common anode (rather than a common cathode) and an isolation cathode for each set of emitters on the substrate. In some embodiments, the VCSELs in the VCSEL array have tunnel junctions located in the lower DBR (e.g., the DBR closest to the substrate) to allow the n-type substrate to serve as the common anode for the subarrays, and each subarray has its own isolation cathode (e.g., formed on an epitaxial surface). Other details are as follows.

[0019] It is worth noting that while the VCSEL array described here can be used for 3DS applications, it can also be used for another type of application, such as data communication applications, where the subarray includes a single transmitter and a multi-channel driver is used to drive different communication channels.

[0020] Figure 1A and 1B This is a schematic diagram related to a conventional VCSEL array 100. Figure 1A This is a schematic diagram showing the various layers of the VCSEL array 100, and Figure 1B It shows that it has Figure 1A A schematic diagram illustrating an example cross-section of a specific VCSEL in the VCSEL array 100 of the shown layer. (See diagram for reference.) Figure 1A and 1BAs shown, the VCSEL array 100 includes an n-type substrate 102, an n-type metal 104 as a cathode on the bottom surface, and an n-type DBR 106 on the top surface. As further shown, the VCSEL array 100 includes an active region 108 on the n-type DBR 106 and a p-type DBR 112 on the active region 108. As further shown, a p-type contact 114 is disposed on the p-type DBR 112, and a p-type metal 116 serving as the anode is disposed on the p-type contact 114. As further shown, the VCSEL array 100 includes an oxide layer 110 forming oxide holes (for providing optical and electrical confinement of the VCSEL array 100). As shown, the oxide layer 110 is typically located above the active region 108 in the p-type DBR 112. It is worth noting that, as... Figure 1B As shown, the VCSEL array 100 also includes a dielectric layer 118 and an isolation implant 120.

[0021] As described above, the VCSEL array 100 is formed from an n-type substrate 102, and all VCSELs in the VCSEL array 100 share a common back cathode (e.g., n-type metal 104). In some cases, it may be formed from multiple isolated front anodes (e.g., formed in p-type metal 116), each connected to a different group (e.g., subarray) of VCSELs. In this case, the back contact of the n-type DBR 106 to the n-type substrate 102 is connected to the n-layer of the light-emitting pin diode junction in the active region 108. Because the junction must be forward biased to emit light, the p-type side of the VCSEL array 100 (i.e., the top of the epitaxial layer of the VCSEL array 100) serves as the anode, and the n-type side of the VCSEL array 100 (i.e., the n-type substrate 102) serves as the cathode.

[0022] It is worth noting that p-type substrates (e.g., p-type GaAs substrates) have been used to achieve a configuration in which the back contact of the p-type substrate is connected to the p-type side of the light-emitting pin diode junction (via the lower p-DBR), and the top of the epitaxial layer (via the upper n-DBR) is connected to the n-type side of the light-emitting pin diode junction. However, this configuration requires a p-type substrate, which, as mentioned above, has a higher defect density and absorbs more light than an n-type substrate, and is therefore undesirable.

[0023] Furthermore, it is possible to implement a common anode VCSEL array on a single substrate with a different design, such that the substrate is isolated from the bottom (lower) DBR of the VCSEL array. In this case, the p-type contact and p-DBR are on the top side of the epitaxial layer, and the n-DBR is on the bottom side of the VCSEL array (e.g., similar to VCSEL array 100), but with the substrate isolated, it can be independently connected to the cathode of the VCSEL subarray. However, this design requires more complex fabrication to contact the n-DBR compared to the single overlay metal contact of the substrate used in VCSEL array 100, and is therefore undesirable.

[0024] Furthermore, a configuration can be adopted in which the anodes and cathodes of different subarrays for the VCSEL array can be used on the same substrate. This design no longer uses a common anode but can be used with drive circuitry designed for VCSEL arrays with a common anode or common cathode (e.g., those with n-channel or p-channel FETs at the output stage of the driver). However, designs similar to the one described above, where the substrate is isolated from the bottom DBR, are more complex to manufacture and require more chip area compared to the design of VCSEL array 100, and are therefore undesirable.

[0025] Figure 2A-2C This is a figure associated with a first exemplary embodiment of a VCSEL array 200 having an isolated cathode and a common anode and a tunnel junction. Figure 2A This is a schematic diagram showing the various layers of a VCSEL array 200. In some embodiments, the VCSEL array 200 may be a group of subarrays of VCSELs formed on one or more chips (e.g., the group of subarrays may be formed on the same integrated circuit). Figure 2A As shown, the VCSEL array 200 may include an n-type substrate layer 202, an n-type metal 204, an n-type bottom mirror 206, an active region 208, a p-type layer 210, an oxide layer 212, a tunnel junction 214, an n-type top mirror 216, an n-type contact layer 218, and an n-type metal 220. Figure 2A As shown, the n-type bottom mirror 206, the tunnel junction 214, and the p-type bottom mirror can be included in the bottom mirror structure 209 of the VCSEL array 200.

[0026] The n-type substrate layer 202 includes a substrate comprising an n-type material. In some embodiments, other layers of the VCSEL array 200 are grown on the n-type substrate layer 202. In some embodiments, the n-type substrate layer 202 may be formed of a semiconductor material, such as gallium arsenide (GaAs), indium phosphide (InP), or another type of semiconductor material.

[0027] The n-type metal 204 includes an n-type metal layer on the bottom surface of the n-type substrate layer 202 (e.g., on the back side of the VCSEL array 200). The n-type metal 204 is a layer electrically in contact with the n-type substrate layer 202 and forms a common anode for a group of VCSEL arrays including the VCSEL array 200. That is, the n-type metal 204 can be used as a common anode for a group of subarrays of the VCSEL array, of which the VCSEL array 200 is one. In some embodiments, the n-type metal 204 may include an annealed metallization layer, such as a gold-germanium-nickel (AuGeNi) layer, a palladium-germanium-gold (PdGeAu) layer, etc.

[0028] The bottom mirror structure 209 includes an n-type bottom mirror 206, a tunnel junction 214, and a p-type layer 210. As shown, the bottom mirror structure can be formed on the top surface of the n-type substrate layer 202.

[0029] The n-type bottom mirror 206 is part of the bottom mirror structure 209. In some embodiments, the n-type bottom mirror 206 is part of the bottom reflector of an optical resonator and is formed of an n-type material. For example, the n-type bottom mirror 206 may include a DBR, a dielectric mirror, or other types of mirror structures. In some embodiments, the n-type bottom mirror 206 is located on the top surface of the n-type substrate layer 202, and the tunnel junction 214 is located on the n-type bottom mirror 206. In some embodiments, the n-type bottom mirror 206 may have a thickness ranging from about 3.5 micrometers (μm) to about 9 μm (e.g., 5 μm). In some embodiments, the n-type bottom mirror 206 includes a set of layers (e.g., aluminum gallium arsenide (AlGaAs) layers grown using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other techniques).

[0030] The p-type layer 210 is the mirror portion of the bottom mirror structure 209. In some embodiments, the p-type layer 210 is part of the bottom reflector of an optical resonator and is formed of a p-type material. In some embodiments, such as Figure 2A As shown, the p-type layer 210 may be located between the tunnel junction 214 and the active region 208. In some embodiments, the p-type layer 210 is on the tunnel junction 214, and the active region 208 is on the p-type layer 210. In some embodiments, the p-type layer 210 may include a DBR, a dielectric mirror, or another type of mirror structure. In some embodiments, the p-type layer 210 is a thin p-type DBR (p-DBR) (e.g., a p-DBR with fewer than six layer pairs) that forms part of the bottom reflector of the optical resonator. In some embodiments, the p-type layer 210 is a p-type spacer layer (e.g., a single layer of material, such as GaAs or AlGaAs) that supports hole injection in the active region 208 but does not serve as part of the bottom reflector of the optical resonator.

[0031] Tunnel junction 214 includes one or more layers to reverse the carrier type within bottom mirror structure 209. For example, tunnel junction 214 may include one or more layers that convert electrons from n-type bottom mirror 206 to holes in p-type layer 210. In some embodiments, tunnel junction 214 is formed by placing one or more layers of highly doped n-type and p-type materials (typically referred to as n++ and p++, respectively). Due to the high intrinsic electric field formed by the junction of the highly doped materials, tunnel junction 214 allows electrons injected from below tunnel junction 214 (through n-type bottom mirror 206) to be converted to holes above tunnel junction 214 (in p-type layer 210). In some embodiments, tunnel junction 214 may have a total thickness ranging from about 0.01 μm to about 0.12 μm. In some embodiments, the tunnel junction 214 is within the bottom mirror structure 209, which allows for a low-resistance transition from the n-type bottom mirror 206 (i.e., the n-doped portion of the bottom mirror structure 209 grown on the n-type substrate layer 202) to the p-type layer 210 (i.e., the p-doped portion of the bottom mirror structure 209 grown above the n-doped portion of the bottom mirror structure 209).

[0032] In some implementations, the tunnel junction 214 can be formed at any location on the bottom mirror structure 209. For example, the bottom mirror structure 209 can be formed at the top of the bottom mirror structure 209 (e.g., at a location on the bottom mirror structure 209 where there are no more mirror pairs above it). As another example, the bottom mirror structure 209 can be formed at the bottom of the bottom mirror structure 209 (e.g., at a location where there are no pairs below it). It is worth noting that there is a trade-off between the voltage drop across the p-type layer 210 (e.g., one or more p-DBR pairs) and the voltage drop across the tunnel junction 214. As the tunnel junction 214 is placed closer to the aperture formed by the oxide layer 212 (i.e., higher in the bottom mirror structure 209), the current is laterally confined to a narrower region, resulting in a higher current density and a higher voltage drop across the tunnel junction 214. However, in this case, fewer p-DBR pairs must pass through (higher resistance). p-DBR pairs typically have higher lateral resistance than n-DBR pairs and typically have higher vertical resistance. As the tunnel junction 214 moves closer to the n-type substrate 202, more p-DBR pairs are needed in the p-type layer 210 above the tunnel junction 214, but the current density and corresponding voltage drop through the tunnel junction 214 will be lower. Therefore, the position of the tunnel junction 214 within the bottom mirror structure 209 can be selected based on its resistance. For sufficiently low tunnel junction resistance (e.g., less than approximately 2 × 10⁻⁶), -5 Ohm square centimeter (cm) 2 Placing the tunnel junction 214 close to the oxide aperture may be beneficial for improving electro-optical power conversion efficiency (e.g., compared to common cathode designs of comparable materials without a tunnel junction).

[0033] It is worth noting that the tunnel junction 214 can increase the voltage drop across the VCSELs in the VCSEL array 200 compared to a typical common cathode design on an n-type substrate without any tunnel junction. However, a more suitable comparison is a common anode design on a p-type substrate. As mentioned above, p-type substrates have higher resistance than n-type substrates. Therefore, a properly designed tunnel junction 214 and the voltage drop across the n-type substrate layer 202 can potentially be lower than the voltage drop across the p-type substrate of a high-density VCSEL array operating at a current of a few amperes per square millimeter.

[0034] The active region 208 includes one or more layers in which electrons and holes recombine to emit light and define the emission wavelength range of the VCSEL array 200. For example, the active region 208 may include one or more quantum wells. In some embodiments, the active region 208 may include one or more cavity spacer layers between the n-type top mirror 216 and the bottom mirror structure 209. The optical thickness of the active region 208 (including the cavity spacer layers) and the optical thickness of the n-type top mirror 216 and the bottom mirror structure 209 define the resonant cavity wavelength of the VCSEL array 200, which can be designed within the emission wavelength range of the active region to achieve laser emission. In some embodiments, the active region 208 may be formed on the bottom mirror structure 209.

[0035] In some embodiments, the active region 208 may be a single pin junction with an intrinsic (i) region having a light-emitting quantum well. Alternatively, in some embodiments, the active region 208 may be a multi-junction active region—a series of pin junctions connected by tunnel junctions, having a stack of pin / n++ / p++ / pin / n++ / p++ / pin (from bottom to top), wherein each intrinsic region includes a light-emitting quantum well. In some embodiments, the thickness of the active region 208 may be in the range of approximately 0.06 μm to approximately 0.5 μm, for example, 0.15 μm or 0.30 μm. In some embodiments, the active region 208 comprises a set of layers grown using MOCVD, MBE, or another technique.

[0036] The oxide layer 212 includes an oxide layer forming oxide holes for providing optical and electrical confinement to the VCSELs of the VCSEL array 200. In some embodiments, the oxide layer 212 is formed as a result of the oxidation of one or more epitaxial layers of the VCSEL array 200. For example, the oxide layer 212 may be an alumina (Al2O3) layer formed as a result of the oxidation of an epitaxial layer (e.g., an AlGaAs layer, an aluminum arsenide (AlAs) layer, etc.). In some embodiments, the thickness of the oxide layer 212 may be in the range of about 0.007 μm to about 0.04 μm, for example, 0.02 μm. In some embodiments, oxide trenches ( Figure 2A Not shown in the image, and displayed as filled in. Figure 2B and 2C The oxide apertures (forming the oxide pores) can allow vapor to enter the epitaxial layer forming the oxide layer 212. In some embodiments, the oxide apertures have a circular shape. In some embodiments, the oxide apertures have a non-circular shape. In some embodiments, the size (e.g., diameter) of the oxide apertures formed by the oxide layer 212 is in the range of about 1 μm to about 300 μm, for example, 5 μm or 8 μm. In some embodiments, the oxide layer 212 (which forms the oxide apertures of the VCSEL) within the bottom mirror structure 209 is below the active region 208 (i.e., on the substrate side of the active region 208). In some embodiments, the oxide layer 212 may be above the active region 208 (e.g., in the n-type top mirror 216) and on or in the n-type top mirror 216.

[0037] The n-type top mirror 216 is the top reflector of an optical resonator and is formed of an n-type material. For example, the n-type top mirror 216 may include a DBR mirror, a dielectric mirror, etc. In some embodiments, the n-type top mirror 216 may have a thickness ranging from approximately 1 μm to approximately 6 μm, for example, 3 μm. In some embodiments, the n-type top mirror 216 is grown on the n-side of the active region 208.

[0038] The n-type contact layer 218 is the top contact layer of the VCSEL array 200, which makes electrical contact with the n-type top mirror 216 through which current can flow. In some embodiments, the n-type contact layer 218 includes an annealed metallization layer. For example, the n-type contact layer 218 may include a chromium-gold (Cr-Au) layer, a gold-zinc (Au-Zn) layer, a titanium-platinum-gold (TiPtAu) layer, a gold-germanium-nickel (AuGeNi) layer, a palladium-germanium-gold (PdGeAu) layer, etc. In some embodiments, the thickness of the n-type contact layer 218 is in the range of about 0.03 μm to about 0.3 μm, for example, 0.2 μm. In some embodiments, the n-type contact layer 218 has an annular, slotted annular, gear-shaped, or other circular or non-circular shape (e.g., depending on the design of the VCSELs in the VCSEL array 200).

[0039] The n-type metal 220 is a top metal layer located on the front side of the VCSEL array 200. For example, the n-type metal 220 may be a layer that is electrically in contact with the n-type contact layer 218. In some embodiments, the n-type metal 220 may form an isolation cathode of the VCSEL array 200. That is, the n-type metal 204 may be used as an isolation cathode for a specific subarray of a VCSEL array comprising a set of subarrays, of which the VCSEL array 200 is one.

[0040] Figure 2B It is shown that has Figure 2AA schematic diagram illustrating an example cross-section of the design of the top-emitting VCSEL in the VCSEL array 200 of the shown layer. Figure 2B As shown, the n-type metal 220 is insulated from the sidewalls of the trench by a dielectric layer 222, which can be, for example, silicon nitride (SiN), silicon dioxide (SiO2), a polymer dielectric, or another type of insulating material. Additionally, as... Figure 2B As shown, the VCSEL may have an isolation implant 224 to prevent free carriers from reaching the edge of the trench and / or to isolate adjacent VCSELs in the VCSEL array 200 from each other (e.g., if the trench does not completely surround the VCSELs of the VCSEL array 200).

[0041] Figure 2C It is shown that has Figure 2A This is a schematic diagram of an example cross-section of the design of a bottom-emitting VCSEL in the VCSEL array 200 shown in the diagram. The structure of the bottom-emitting VCSEL is similar to... Figure 2B The top-emitting VCSEL shown has an opening in the n-type metal 204 to allow light to be emitted from the n-type substrate layer 202. In some embodiments, such as Figure 2C As shown, the anti-reflective coating 240 can be formed in the openings of the n-type metal 204. For example... Figure 2C As further shown, in a bottom-emitting VCSEL, an n-type metal 220 covers the top surface of the VCSEL above the n-type contact layer 218. Similar to a top-emitting VCSEL, a tunnel junction 214 is located within the bottom mirror structure to allow for a low-resistance transition from the n-type bottom mirror 206 to the p-type layer 210.

[0042] It is worth noting that in a typical common cathode structure used for VCSEL arrays, the top contact has a high (e.g., greater than approximately 5 × 10⁻⁶) value at the surface. 19 cm -3 p-type doped p-type materials. This high doping allows for tunnel contacts with some materials (e.g., titanium, platinum, gold), which can be deposited prior to oxidation and do not require surface alloying to achieve low contact resistance. Furthermore, depositing ohmic contacts before trench etching is advantageous because defining dense lithographic features (through a flat surface) is simpler. However, ohmic contacts must be maintained at temperatures around 400 degrees Celsius (°C) for many minutes during oxidation. (Refer to the above...) Figure 2A-2CIn the case of the described common anode design, the top metal contact is nominally an n-type material (e.g., n-type contact layer 218). However, common alloy structures used for such n-type contacts in GaAs (e.g., gold-germanium (Au-Ge)) are sensitive to annealing conditions and typically degrade (e.g., increase resistance) if heated for too long at around 400°C. Low-temperature alloy materials (e.g., palladium, germanium) also significantly increase resistance in this process. To overcome this, in some embodiments, the topmost epitaxial layer of the VCSEL array 200 can be made with a dopant (e.g., tellurium, selenium, etc.) with a height (e.g., greater than 5 × 10⁻⁶). 18 cm -3 Doping with silicon (n) allows for high electron concentrations even in unsaturated conditions, as occurs when GaAs is doped with silicon. High-peak n-doping enables the use of non-alloy ohmic contacts (e.g., titanium, platinum, gold, etc.) – which typically form diode (Schottky) contacts (e.g., from approximately 3 × 10⁻⁶). 17 cm -3 Up to approximately 3×10 18 cm -3 Nitrogen-doped GaAs makes conventional GaAs n-type contacts (e.g., palladium, germanium, etc.) less sensitive to prolonged exposure to high temperatures. Surface n-type doping can also be achieved in lower ranges (e.g., from 5 × 10¹⁷ cm⁻³ to approximately 3 × 10¹⁸ cm⁻³), enabling adequate ohmic contact with conventional n-contact materials deposited after the oxidation process. However, as mentioned above, photolithography can be challenging due to the presence of oxide trenches, and defining narrow features can be more difficult (e.g., compared to when the surface is planar).

[0043] Figure 2A-2C The number, arrangement, thickness, order, and symmetry of the layers shown are provided as examples. In practice, the VCSEL array 200 may include additional layers, fewer layers, different layers, layers with different structures, or layers with different arrangements, or layers with... Figure 2A-2C The different arrangements of layers are shown. Additionally or alternatively, a set of layers (e.g., one or more layers) may perform one or more functions described as being performed by another set of layers of the VCSEL array 200, and any layer may include more than one layer.

[0044] In some embodiments, to simplify fabrication and follow similar steps associated with fabricating a common cathode VCSEL array, it may be desirable to insert an additional tunnel junction beneath the top surface of the VCSEL array 200, with the p++ layer extending to the surface of the VCSEL array 200. In this way, the top contact of the VCSEL array 200 is allowed to be a p-type contact and can be formed as a tunnel contact (e.g., titanium, platinum, gold, etc.), which is compatible with high-temperature oxidation. In some embodiments, the second tunnel junction may have a lower resistance than tunnel junction 214 because the amount of time exposed to the elevated growth temperature is relatively short.

[0045] Figures 3A-3C This is a figure associated with a second exemplary embodiment of a VCSEL array 300 having an isolated cathode and a common anode and multiple tunnel junctions. Figure 3A This is a schematic diagram showing the various layers of the VCSEL array 300, and Figure 3B It is shown that has Figure 3A A schematic diagram of an example cross-section of a design for a top-emitting VCSEL in a VCSEL array 300 of the shown layers. Figure 3C It is shown that has Figure 3A A schematic diagram of an example cross-section of the design of the bottom-emitting VCSEL in the VCSEL array 300 of the shown layer.

[0046] For example, through comparison Figure 2A-2C and Figures 3A-3C As shown, the structure of VCSEL array 300 is similar to that of VCSEL array 200, except that VCSEL array 300 includes a tunnel junction 226 on an n-type top mirror 216, a p-type contact layer 228 (e.g., instead of an n-type contact layer 218) above the tunnel junction 226, and a p-type metal 230 (e.g., instead of an n-type metal 220) on the p-type contact layer 228. As described above, by including the second tunnel junction 226, the top contact of VCSEL array 300 is allowed to be a p-type contact and can be formed as a tunnel contact (e.g., titanium, platinum, gold, etc.), which is compatible with high-temperature oxidation.

[0047] Figures 3A-3C The number, arrangement, thickness, order, symmetry, etc., of the layers shown are provided as examples. In practice, the VCSEL array 300 may include additional layers, fewer layers, different layers, layers with different constructions, or layers with different arrangements. Additionally or alternatively, a set of layers (e.g., one or more layers) may perform one or more functions described as being performed by another set of layers in the VCSEL array 300, and any layer may include more than one layer.

[0048] In some implementations, a series of processes can be used to fabricate the VCSEL array 200 / 300. For example, in other examples, one or more growth processes, one or more deposition processes, one or more etching processes, one or more oxidation processes, one or more implantation processes, and / or one or more metallization processes can be used to create one or more layers of the VCSEL array 200 / 300.

[0049] A specific example of the process for fabricating a VCSEL array 200 / 300 is as follows. First, a crystalline layer (e.g., a GaAs / AlGaAs layer) can be grown (e.g., laterally uniform) on an n-type substrate layer 202 (e.g., an n-type GaAs substrate) to form a bottom mirror structure 209 (e.g., an n-type bottom mirror 206, a tunnel junction 214, and a p-type layer 210), an oxide layer 212, an active region 208, an n-type top mirror 216 (and, in the case of a VCSEL array 300, a tunnel junction 226). Next, a top contact layer (e.g., an n-type contact layer 218 or a p-type contact layer 228) can be deposited. This step can also be performed after the oxide layer 212 is oxidized, as described below. Next, trenches can be etched to allow lateral oxidation (partially or completely surrounding the emitter). Next, the oxide layer 212 (e.g., a layer with a higher aluminum content) can be oxidized to form oxide holes. Next, emitters belonging to different cathodes can be isolated by ion implantation (e.g., the formation of isolation implant 224) (e.g., when the emitters were not etched and isolated in the preceding steps, or when additional isolation is required). Next, interconnects and pad metallization (e.g., n-type metal 220, p-type metal 230) are deposited as needed. Next, the n-type substrate 202 can be thinned (e.g., as required for wafer dicing). Next, n-type metal 204 can be deposited on the back side of the thinned n-type substrate 202. Finally, the wafer can be diced into individual dies. It is noteworthy that one or more additional steps, such as surface passivation, strain compensation, thermal processing, photolithography, cleaning, patterning, etc., can be performed at different points between the above steps. Furthermore, some of the above steps may require patterning of the wafer (e.g., for etching, metallization, or isolation only of specific regions across each VCSEL array 200 / 300 or within each emitter).

[0050] In some implementations, multiple VCSEL arrays 200 / 300 can be formed on a single chip and can share a common substrate anode contact while having isolated cathode contacts. Figure 4A An example of two VCSEL arrays 200 with isolated cathode contacts on an n-type substrate used as a common anode is shown. Figure 4B An example of two VCSEL arrays 300 with isolated cathode contacts on an n-type substrate used as a common anode is shown.

[0051] Figure 4A and 4B The number, arrangement, thickness, order, and symmetry of the layers shown are provided as examples. In practice, VCSEL200 can include additional layers, fewer layers, different layers, layers with different structures, or layers different from those in the example. Figure 4A and 4B The layers are arranged as shown.

[0052] Figures 5A-5C This is a schematic diagram illustrating an example arrangement of a VCSEL array 200 / 300 in an optical device. Figure 5A and 5B In this configuration, each emitter area corresponds to the emitter area of ​​a corresponding VCSEL array 200 / 300, and each emitter area is served by a single contact pad. In some implementations, such as Figure 5C As shown, VCSEL arrays 200 / 300 can be continuous. Instead, VCSELs in regions (e.g., region A and region B, such as...) Figure 5C (As shown) can be staggered, as long as VCSELs in a given region are isolated from VCSELs in another region.

[0053] As mentioned above, Figures 5A-5C Provided as an example. Other examples may differ from those provided. Figures 5A-5C As described.

[0054] Figure 6 This is a flowchart of an example process 600 involving the fabrication of a VCSEL array with an isolated cathode and a common anode and a tunnel junction.

[0055] like Figure 6 As shown, process 600 may include forming an n-type metal on a first surface of an n-type substrate layer, the n-type metal providing a common anode for a plurality of VCSEL arrays (block 610). For example, n-type metal 204 may be formed on the first surface of an n-type substrate layer 202, as described above, n-type metal 204 providing a common anode for a plurality of VCSEL arrays 200.

[0056] like Figure 6 As further shown, process 600 may include forming a bottom mirror structure on the second surface of the n-type substrate layer, the bottom mirror structure including one or more bottom mirror portions and a tunnel junction to reverse the carrier type within the bottom mirror structure (block 620). For example, bottom mirror structure 209 may be formed on the second surface of the n-type substrate layer 202, the bottom mirror structure 209 including one or more bottom mirror portions (e.g., n-type bottom mirror 206 and / or p-type layer 210) and a tunnel junction 214 to reverse the carrier type within the bottom mirror structure 209, as described above.

[0057] like Figure 6As further shown, process 600 may include forming an active region on the bottom mirror structure (box 630). For example, as described above, active region 208 may be formed on bottom mirror structure 209.

[0058] like Figure 6 As further shown, process 600 may include forming an oxide layer to provide optical and electrical confinement for VCSELs included in a plurality of VCSEL arrays (block 640). For example, as described above, oxide layer 212 may be formed to provide optical and electrical confinement for VCSELs included in a plurality of VCSEL arrays 200.

[0059] like Figure 6 As further shown, process 600 may include forming an n-type top mirror on the active region (box 650). For example, as described above, an n-type top mirror 216 may be formed on the active region 208.

[0060] like Figure 6 As further shown, process 600 may include forming a top contact layer (box 660) above the n-type top mirror. For example, the top contact layer (e.g., as described above, n-type contact layer 218, p-type contact layer 228) may be formed above the n-type top mirror 216.

[0061] like Figure 6 As further shown, process 600 may include forming a top metal on the top contact layer, which provides an isolation cathode for each of the plurality of VCSEL arrays (block 670). For example, the top metal (e.g., n-type metal 220, p-type metal 230) may be formed on the top contact layer, which provides an isolation cathode for each of the plurality of VCSEL arrays 200, as described above.

[0062] Process 600 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or elsewhere herein.

[0063] In the first embodiment, the top contact layer is an n-type contact layer 218, the top metal is another n-type metal (e.g., n-type metal 220), the n-type contact layer 218 is on the n-type top mirror 216, and the other n-type metal is on the n-type contact layer 218.

[0064] In the second embodiment, alone or in combination with the first embodiment, the oxide layer 212 is below the active region 208 and on or in the bottom mirror structure 209.

[0065] In the third embodiment, alone or in combination with one or more of the first and second embodiments, one or more bottom mirror portions include an n-type bottom mirror portion (e.g., an n-type bottom mirror 206), wherein the n-type bottom mirror portion is on the second surface of the n-type substrate layer 202, and the tunnel junction 214 is on the n-type bottom mirror portion.

[0066] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, one or more bottom mirror portions include a p-type bottom mirror portion (e.g., p-type layer 210), wherein the p-type bottom mirror portion is on the tunnel junction 214 and the active region 208 is on the p-type bottom mirror portion.

[0067] Although Figure 6 Example blocks of process 600 are shown, but in some implementations, process 600 may include additional blocks, fewer blocks, different blocks, or blocks similar to those in the example. Figure 6 The blocks are arranged differently as shown. Alternatively, two or more blocks of process 600 can be executed in parallel.

[0068] The foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations can be made based on the foregoing disclosure, or modifications and variations can be derived from practice of the embodiments. Furthermore, any embodiments described herein can be combined unless the foregoing disclosure expressly provides reasons why one or more embodiments cannot be combined.

[0069] Even though specific combinations of features are referenced in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of various embodiments. In fact, many of these features can be combined in ways not specifically stated in the claims and / or not disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of various embodiments includes combinations of each dependent claim with each other claim in the claim set.

[0070] Unless otherwise stated, the elements, actions, or instructions used herein should not be construed as critical or necessary. Furthermore, as used herein, the term “group” is intended to include one or more items (e.g., related items, unrelated items, a combination of related and unrelated items, etc.). When only one item is intended, the phrase “only one” or similar language is used. Additionally, as used herein, the terms “have,” “possess,” “with,” etc., are intended to be open-ended terms. Furthermore, the phrase “based on” is intended to mean “at least partially based on”, unless explicitly stated otherwise. Furthermore, as used herein, the term “or” is intended to be included when used in series and may be used interchangeably with “and / or”, unless explicitly stated otherwise (e.g., if used in conjunction with “any” or “only one of them”). Additionally, for ease of description, spatially relative terms such as “above,” “below,” “under,” “below,” “on,” “above,” etc., may be used herein to describe the relationship of one element or feature to another element or feature shown in the figures. In addition to the orientations described in the figures, spatially relative terms are intended to include different orientations of the equipment, apparatus, and / or elements in use or operation. The equipment may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptors used herein may be interpreted accordingly.

[0071] Cross-references to related applications

[0072] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 042,283, filed June 22, 2020, entitled "Vertical-Cavity Surface-Emitting Laser Arrays with Isolated Cathodes and a Common Anode". The disclosure of the earlier application is considered part of this patent application and is incorporated herein by reference.

Claims

1. A vertical-cavity surface-emitting laser (VCSEL) array, comprising: An n-type substrate layer has a top surface and a bottom surface; n-type metal, on the bottom surface of the n-type substrate layer, forms a common anode for a group of VCSEL arrays including a VCSEL array; A bottom mirror structure, located on the top surface of an n-type substrate layer, comprises: One or more bottom mirror portions, and Tunnel junction, to reverse the carrier type within the bottom mirror structure; The active region is located on the bottom mirror structure; The oxide layer provides optical and electrical confinement for the VCSEL array; n-type top mirror, located in the active region; Top contact layer, above the n-type top mirror; and The top metal, on the top contact layer, forms the isolation cathode of the VCSEL array.

2. The VCSEL array according to claim 1, wherein the top contact layer is an n-type contact layer, and the top metal is another n-type metal, the n-type contact layer is on the n-type top mirror, and the other n-type metal is on the n-type contact layer.

3. The VCSEL array of claim 1, wherein the oxide layer is below the active region and on or in the bottom mirror structure.

4. The VCSEL array of claim 1, wherein the oxide layer is above the active region and on or in the n-type top mirror.

5. The VCSEL array of claim 1, wherein the one or more bottom mirror portions comprise an n-type bottom mirror portion. The n-type bottom mirror portion is located on the top surface of the n-type substrate layer, and the tunnel junction is located on the n-type bottom mirror portion.

6. The VCSEL array of claim 1, wherein the one or more bottom mirror portions comprise p-type bottom mirror portions. The p-type bottom mirror portion is located on the tunnel junction, and the active region is located on the p-type bottom mirror portion.

7. The VCSEL array of claim 1 further includes another tunnel junction, said other tunnel junction being located on the n-type top mirror. The top contact layer is a p-type contact layer, the top metal is a p-type metal, the p-type contact layer is on another tunnel junction, and the p-type metal is on the p-type contact layer.

8. The VCSEL array according to claim 1, wherein the group of VCSEL arrays is on the same integrated circuit.

9. An optical device, comprising: Multiple vertical-cavity surface-emitting laser (VCSEL) arrays, wherein the multiple VCSEL arrays include: An n-type metal on the first surface of an n-type substrate layer, the n-type metal forming a common anode for each of the multiple VCSEL arrays; A bottom mirror structure on the second surface of an n-type substrate layer, the bottom mirror structure comprising: At least one bottom mirror portion, and Tunnel junction, to reverse the carrier type within the bottom mirror structure; The active region on the bottom mirror structure; An oxide layer is provided to provide optical and electrical confinement for the VCSELs included in the plurality of VCSEL arrays; An n-type top mirror in the active region; Top contact layer above the n-type top mirror; and A top metal on the top contact layer forms an isolation cathode for each of the plurality of VCSEL arrays.

10. The optical device of claim 9, wherein the top contact layer is an n-type contact layer and the top metal is another n-type metal, the n-type contact layer is on the n-type top mirror and the other n-type metal is on the n-type contact layer.

11. The optical device of claim 9, wherein the oxide layer is below the active region and on or in the bottom mirror structure.

12. The optical device of claim 9, wherein the oxide layer is above the active region and on or in the n-type top mirror.

13. The optical device of claim 9, wherein the at least one bottom mirror portion comprises an n-type bottom mirror portion. The n-type bottom mirror portion is located on the second surface of the n-type substrate layer, and the tunnel junction is located on the n-type bottom mirror portion.

14. The optical device of claim 9, wherein the at least one bottom mirror portion comprises a p-type bottom mirror portion. The p-type bottom mirror portion is located on the tunnel junction, and the active region is located on the p-type bottom mirror portion.

15. The optical device of claim 9, wherein the plurality of VCSEL arrays further comprises another tunnel junction on the n-type top mirror. The top contact layer is a p-type contact layer, the top metal is a p-type metal, the p-type contact layer is on another tunnel junction, and the p-type metal is on the p-type contact layer.

16. A method of forming an optical device, comprising: An n-type metal is formed on the first surface of an n-type substrate layer, which provides a common anode for multiple vertical cavity surface emission laser (VCSEL) arrays; A bottom mirror structure is formed on the second surface of the n-type substrate layer. The bottom mirror structure includes: One or more bottom mirror portions, and Tunnel junction, to reverse the carrier type within the bottom mirror structure; An active region is formed on the bottom mirror structure; An oxide layer is formed to provide optical and electrical confinement for the VCSELs included in the plurality of VCSEL arrays; An n-type top mirror is formed in the active region; A top contact layer is formed on the n-type top mirror; and A top metal is formed on the top contact layer, which provides an isolation cathode for each of the multiple VCSEL arrays.

17. The method of claim 16, wherein the top contact layer is an n-type contact layer and the top metal is another n-type metal, the n-type contact layer is on the n-type top mirror, and the other n-type metal is on the n-type contact layer.

18. The method of claim 16, wherein the oxide layer is below the active region and on or in the bottom mirror structure.

19. The method of claim 16, wherein the one or more bottom mirror portions comprise an n-type bottom mirror portion. The n-type bottom mirror portion is located on the second surface of the n-type substrate layer, and the tunnel junction is located on the n-type bottom mirror portion.

20. The method of claim 16, wherein the one or more bottom mirror portions include a p-type bottom mirror portion. The p-type bottom mirror portion is located on the tunnel junction, and the active region is located on the p-type bottom mirror portion.

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