Electronic component embedded substrate

Abstract

This disclosure provides an embedded substrate for electronic components, comprising a first core layer having a first through-hole; a first passive component disposed in the first through-hole; a second core layer disposed on the first core layer and having a second through-hole; a second passive component disposed in the second through-hole; an insulating material covering at least a portion of each of the first and second passive components and disposed in at least a portion of each of the first and second through-holes; and a first wiring layer disposed between the first and second passive components, wherein at least a portion of the first wiring layer is covered by the insulating material. The first and second passive components are interconnected through the first wiring layer.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0082795, filed with the Korean Intellectual Property Office on July 6, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to an embedded substrate for electronic components. Background Technology

[0003] Recently, with the development of technologies such as fifth-generation (5G) mobile communication and artificial intelligence (AI), there is a need for high-performance packages. As a result, there is a need for improved electrical characteristics (such as signal integrity (SI) and power integrity (PI), and the number of passive components that should be mounted on the substrate in the package has increased. Summary of the Invention

[0004] According to one aspect of this disclosure, an embedded substrate for an electronic component includes: a first core layer having a first through-hole; a first passive component disposed in the first through-hole; a second core layer disposed on the first core layer and having a second through-hole; a second passive component disposed in the second through-hole; an insulating material covering at least a portion of each of the first and second passive components and disposed in at least a portion of each of the first and second through-holes; and a first wiring layer disposed between the first and second passive components, wherein at least a portion of the first wiring layer is covered by the insulating material. The first passive component and the second passive component are connected to each other through the first wiring layer.

[0005] According to one aspect of this disclosure, an embedded substrate for an electronic component includes: a core structure comprising a first core layer having a first through-hole, a first passive component disposed in the first through-hole, a second core layer disposed on the first core layer and having a second through-hole, a second passive component disposed in the second through-hole, and an insulating material covering each of the first passive component and the second passive component and disposed in at least a portion of each of the first through-hole and the second through-hole; a first stacked structure comprising a first insulating layer and a first wiring layer connected to the first passive component, the first core layer being disposed between the first stacked structure and the second core layer; and a second stacked structure comprising a second insulating layer and a second wiring layer connected to the second passive component, the second core layer being disposed between the second stacked structure and the first core layer. The insulating material integrally covers the side surface of the second passive component and the surface of the second passive component facing the second stacked structure.

[0006] According to one aspect of this disclosure, an embedded substrate for an electronic component includes: a first core layer having a first through-hole; a first passive component disposed in the first through-hole; a second core layer disposed on the first core layer and having a second through-hole; a second passive component disposed in the second through-hole; an insulating material covering at least a portion of each of the first and second passive components and disposed in at least a portion of each of the first and second through-holes; and a conductive structure embedded in the insulating material and disposed between the first and second passive components. The first and second passive components are connected to each other through the conductive structure. Attached Figure Description

[0007] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0008] Figure 1 This is a schematic block diagram of an electronic device system according to exemplary embodiments of the present disclosure.

[0009] Figure 2 This is a schematic perspective view of an electronic device according to exemplary embodiments of the present disclosure.

[0010] Figure 3 This is a schematic cross-sectional view of an embedded substrate for an electronic component according to exemplary embodiments of the present disclosure.

[0011] Figures 4A to 4J This is a schematic process diagram illustrating the process of manufacturing an embedded substrate for electronic components according to exemplary embodiments of the present disclosure.

[0012] Figure 5 This is a schematic cross-sectional view of an electronic component embedded substrate according to another exemplary embodiment of the present disclosure.

[0013] Figure 6 This is a schematic cross-sectional view of an electronic component embedded substrate according to another exemplary embodiment of the present disclosure.

[0014] Figure 7 This is a schematic cross-sectional view of an electronic component embedded substrate according to another exemplary embodiment of the present disclosure.

[0015] Figure 8 This is a schematic cross-sectional view of an electronic component embedded substrate according to another exemplary embodiment of the present disclosure.

[0016] Figure 9 This is a schematic cross-sectional view illustrating an example of a semiconductor chip disposed on an embedded substrate of an electronic component according to an exemplary embodiment of the present disclosure.

[0017] Figure 10 This is a schematic cross-sectional view illustrating an example of a semiconductor package disposed on an embedded substrate of an electronic component according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0018] In the following description, this disclosure will be made with reference to the accompanying drawings. For clarity of description, the shape and size of the elements in the drawings may be exaggerated or reduced.

[0019] Electronic devices

[0020] Figure 1 This is a schematic block diagram of an electronic device system according to an exemplary embodiment.

[0021] Reference Figure 1 The electronic device 1000 may house a motherboard 1010. The motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, etc., which are physically or electrically connected thereto. These components may be connected to other components described below via various signal lines 1090.

[0022] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters, application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other. Chip-related components 1020 may be in the form of a package including the aforementioned chips or electronic components.

[0023] Network-related components 1030 may include components operating based on protocols such as: Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM+, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, and 5G protocols, as well as any other wireless and wired protocols specified after those listed above. However, network-related components 1030 are not limited to these protocols and may also include components operating based on various other wireless or wired standards or protocols. In addition, the network-related component 1030 can be combined with the aforementioned chip-related component 1020.

[0024] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) capacitors, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited to these, and may also include passive components for various other purposes. Furthermore, other components 1040 may be combined with the aforementioned chip-related components 1020 and / or network-related components 1030.

[0025] Depending on the type of electronic device 1000, it may include other components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, these other components are not limited to these and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage units (e.g., hard disk drives), optical disc (CD) drives, digital versatile optical disc (DVD) drives, etc. Furthermore, these other components may include other components for various purposes, depending on the type of electronic device 1000, etc.

[0026] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital camera, digital video camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these and can be any other electronic device that processes data.

[0027] Figure 2 This is a schematic perspective view of an electronic device according to an exemplary embodiment.

[0028] Reference Figure 2 The electronic device can be, for example, a smartphone 1100. A motherboard 1110 can be housed within the body 1101 of the smartphone 1100, and various electronic components 1120 can be physically and / or electrically connected to the motherboard 1110. Furthermore, other electronic components (such as a camera module 1130 and / or a speaker) that may or may not be physically and / or electrically connected to the motherboard 1110 can be housed within the body 1101. A portion of the electronic components 1120 can be, but are not limited to, the aforementioned chip-related components (e.g., a semiconductor package 1121). The semiconductor package 1121 can be a surface-mount type in which a semiconductor chip or passive component is located on a package substrate, but is not limited to this. The electronic device is not limited to the smartphone 1100, but can be other electronic devices as described above.

[0029] Embedded substrate for electronic components

[0030] Figure 3 This is a schematic cross-sectional view of an electronic component embedded substrate 100A according to an exemplary embodiment.

[0031] Reference Figure 3 The embedded substrate 100A for electronic components may include a core structure 110.

[0032] Additionally, the electronic component embedded substrate 100A may also include a first stacking structure 120 disposed on one side of the core structure 110 and a second stacking structure 130 disposed on the other side of the core structure 110. One side of the core structure 110 may refer to the side on which the first core layer 111a is disposed, and the other side of the core structure 110 may refer to the side on which the second core layer 111b is disposed. However, the first stacking structure 120 and the second stacking structure 130 are additional components that can be omitted depending on design requirements.

[0033] The core structure 110 may include: a first core layer 111a having a first through-hole 111ah; a first passive component 112a disposed in the first through-hole 111ah; a second core layer 111b disposed on the first core layer 111a and having a second through-hole 111bh; a second passive component 112b disposed in the second through-hole 111bh; and an insulating material 113 covering the first passive component 112a and the second passive component 112b, while filling at least a portion of each of the first through-hole 111ah and the second through-hole 111bh.

[0034] The insulating material 113 may include a first insulating material 113a, a second insulating material 113b, and a third insulating material 113c. The first insulating material 113a may cover the first passive component 112a and fill at least a portion of the first through-hole 111ah. Additionally, the first insulating material 113a may cover the surface of the first core layer 111a facing the second core layer 111b. Accordingly, the first insulating material 113a may fill the space between the first core layer 111a and the second core layer 111b. The second insulating material 113b may cover the second passive component 112b and fill at least a portion of the second through-hole 111bh. Additionally, the second insulating material 113b may cover the surface of the second core layer 111b opposite to the surface of the second core layer 111b facing the first core layer 111a. The third insulating material 113c may be disposed on the side of the first core layer 111a opposite to the side on which the second core layer 111b is disposed, to cover one side of each of the first passive component 112a and the first insulating material 113a. Additionally, the third insulating material 113c may cover the surface of the first core layer 111a opposite to the surface of the first core layer 111a facing the second core layer 111b.

[0035] In this case, the boundaries between the first insulating material 113a, the second insulating material 113b, and the third insulating material 113c may be obvious or indistinct. Therefore, the boundaries between the first insulating material 113a, the second insulating material 113b, and the third insulating material 113c are represented by dashed lines in the accompanying drawings. When the boundaries between the first insulating material 113a, the second insulating material 113b, and the third insulating material 113c are indistinct, the first insulating material 113a, the second insulating material 113b, and the third insulating material 113c may be integrated to form a single insulating material 113.

[0036] The core structure 110 may further include a first wiring layer 114a, which is disposed between the first passive component 112a and the second passive component 112b such that at least a portion of the first wiring layer 114a is covered by the insulating material 113. For example, the first wiring layer 114a may be disposed on a horizontal plane between the first passive component 112a and the second passive component 112b. The first passive component 112a and the second passive component 112b may be connected to each other via the first wiring layer 114a. According to the process described later, the first wiring layer 114a may be disposed together with the second core layer 111b on the first insulating material 113a. Therefore, the surfaces of the second core layer 111b in contact with the first insulating material 113a and the surfaces of the first wiring layer 114a in contact with the first insulating material 113a may be coplanar. Similarly, the surface of the second core layer 111b facing the first core layer 111a and the surface of the first wiring layer 114a facing the first passive component 112a may be coplanar. Additionally, the core structure 110 may further include a first via layer 115a, the first via layer 115a having first vias embedded in the insulating material 113 to connect the first passive component 112a to the first wiring layer 114a. Each via of the first via layer 115a may penetrate a portion of the first insulating material 113a.

[0037] The core structure 110 may further include: a second wiring layer 114b disposed on the second insulating material 113b and connected to the second passive component 112b; and a second via layer 115b penetrating the second insulating material 113b and connecting the second passive component 112b and the second wiring layer 114b to each other. Additionally, the core structure 110 may further include: a third wiring layer 114c disposed on the third insulating material 113c and connected to the first passive component 112a; and a third via layer 115c penetrating the third insulating material 113c and connecting the first passive component 112a and the third wiring layer 114c to each other.

[0038] The core structure 110 may also include a through-hole 116 that penetrates the first core layer 111a, the second core layer 111b and the insulating material 113 and connects the second wiring layer 114b and the third wiring layer 114c to each other.

[0039] The core structure 110 may further include a connecting conductor 117 disposed on the first wiring layer 114a, and the second passive component 112b may be connected to the first wiring layer 114a via the connecting conductor 117. One or a combination of two or more of the first wiring layer 114a, the first via layer 115a, and the connecting conductor 117 may serve as a conductive structure to connect the first passive component and the second passive component to each other.

[0040] The first stacked structure 120 may include a first insulating layer 121, a fourth wiring layer 122 disposed on the first insulating layer 121 and connected to the first passive component 112a, and a fourth via layer 123 penetrating the first insulating layer 121 to connect to the fourth wiring layer 122. Additionally, the first stacked structure 120 may also include a first protective layer 124 disposed on the first insulating layer 121 to cover at least a portion of the fourth wiring layer 122. In this case, the first insulating layer 121, the fourth wiring layer 122, and the fourth via layer 123 may be a plurality of first insulating layers 121, a plurality of fourth wiring layers 122, and a plurality of fourth via layers 123, respectively.

[0041] The second stacked structure 130 may include a second insulating layer 131, a fifth wiring layer 132 disposed on the second insulating layer 131 and connected to the second passive component 112b, and a fifth via layer 133 penetrating the second insulating layer 131 to connect to the fifth wiring layer 132. Additionally, the second stacked structure 130 may also include a second protective layer 134 disposed on the second insulating layer 131 to cover at least a portion of the fifth wiring layer 132. In this case, the second insulating layer 131, the fifth wiring layer 132, and the fifth via layer 133 may be a plurality of second insulating layers 131, a plurality of fifth wiring layers 132, and a plurality of fifth via layers 133, respectively.

[0042] In this disclosure, a plurality of first passive components 112a and a plurality of second passive components 112b can be interconnected via a first wiring layer 114a disposed on a first insulating material 113a. As a result, an embedded substrate for electronic components capable of high-density integration can be provided.

[0043] The various constructions of the electronic component embedded substrate 100A according to an exemplary embodiment will be described in more detail below.

[0044] Each of the first core layer 111a and the second core layer 111b can be used to improve the rigidity of the substrate to suppress substrate warping, etc. The materials used to form each of the first core layer 111a and the second core layer 111b are not limited and any material can be used as long as it has insulating properties. For example, the materials used to form each of the first core layer 111a and the second core layer 111b can be thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or thermosetting or thermoplastic resins impregnated together with inorganic fillers in a core (such as glass fiber, glass cloth, or glass fabric) (e.g., copper-clad laminate (CCL) or unclad CCL). Optionally, the materials used to form each of the first core layer 111a and the second core layer 111b may include another type of material, such as a glass substrate or a ceramic substrate.

[0045] Each of the first passive component 112a and the second passive component 112b can be a passive component such as a capacitor, inductor, etc. The types of the first passive component 112a and the second passive component 112b may be the same or different from each other. As shown in the figures, each of the first passive component 112a and the second passive component 112b may respectively include a plurality of first passive components 112a and a plurality of second passive components 112b. The plurality of first passive components 112a may be spaced apart from each other in a first through-hole 111ah, and the plurality of second passive components 112b may be spaced apart from each other in a second through-hole 111bh.

[0046] The first passive component 112a may include a first body 112ab and a first electrode 112ae, and the second passive component 112b may include a second body 112bb and a second electrode 112be. Therefore, the first passive component 112a and the second passive component 112b may be electrically connected to at least one of the first wiring layer 114a, the second wiring layer 114b, and the third wiring layer 114c via the first electrode 112ae and the second electrode 112be, respectively.

[0047] Exemplary embodiments can be implemented by those skilled in the art by replacing the first passive component 112a and / or the second passive component 112b with active components according to design conditions. Such embodiments are also considered to be within the scope of this disclosure.

[0048] Insulating material 113 can be used to protect the first passive component 112a and the second passive component 112b. Optionally, insulating material 113 can be used to attach the first core layer 111a and the second core layer 111b to each other to protect the first core layer 111a and the second core layer 111b, etc. The insulating material can be used as the material for forming insulating material 113. In this case, the insulating material can be a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material in which the thermosetting resin or thermoplastic resin is impregnated together with an inorganic filler in a core (such as glass fiber, glass cloth, or glass fabric) (e.g., prepreg (PPG), etc.).

[0049] As described above, the insulating material 113 may include a first insulating material 113a, a second insulating material 113b, and a third insulating material 113c. In this case, the first insulating material 113a, the second insulating material 113b, and the third insulating material 113c may include the same material or different materials. Furthermore, the boundaries between the first insulating material 113a, the second insulating material 113b, and the third insulating material 113c may be obvious or indistinct.

[0050] Each of the first wiring layer 114a, the second wiring layer 114b, and the third wiring layer 114c may perform various functions according to its design. For example, each of the first wiring layer 114a, the second wiring layer 114b, and the third wiring layer 114c may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. In this case, the signal (S) pattern may include various signal patterns (e.g., data signal patterns) other than the ground (GND) pattern, the power (PWR) pattern, etc. In addition, each of the first wiring layer 114a, the second wiring layer 114b, and the third wiring layer 114c may include wiring pads connected to the first passive component 112a and / or the second passive component 112b.

[0051] The material used to form each of the first wiring layer 114a, the second wiring layer 114b, and the third wiring layer 114c can be a conductive material. For example, the material used to form each of the first wiring layer 114a, the second wiring layer 114b, and the third wiring layer 114c can be a metallic material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc., but is not limited thereto.

[0052] Each of the first via layer 115a, the second via layer 115b, and the third via layer 115c may also perform various functions according to its design. For example, each of the first via layer 115a, the second via layer 115b, and the third via layer 115c may include a via for grounding, a via for power, and a via for signals. Each of the first via layer 115a, the second via layer 115b, and the third via layer 115c may include a via connected to the first passive component 112a and / or the second passive component 112b.

[0053] The material used to form each of the first via layer 115a, the second via layer 115b, and the third via layer 115c can also be a conductive material. For example, the material used to form each of the first via layer 115a, the second via layer 115b, and the third via layer 115c can be a metallic material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc., but is not limited thereto.

[0054] Each via in the first via layer 115a, the second via layer 115b, and the third via layer 115c can be formed by completely filling the via with a conductive material, or by forming the conductive material along the wall of the via. When a via is formed by forming the conductive material along the wall of the via, the via can be filled with an insulating material. Furthermore, the vias in the first via layer 115a, the second via layer 115b, and the third via layer 115c can have all shapes known in the art, such as conical shapes, cylindrical shapes, etc.

[0055] The through-hole 116 can penetrate the first core layer 111a, the second core layer 111b and the insulating material 113, and can connect the second wiring layer 114b and the third wiring layer 114c to each other.

[0056] The material used to form the through-hole 116 can also be a conductive material. For example, the material used to form the through-hole 116 can be a metallic material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof, but is not limited thereto.

[0057] The through-hole 116 can be formed by completely filling the via with a conductive material, or by forming a conductive material along the wall of the via. When the through-hole 116 is formed by forming a conductive material along the wall of the via, the via can be filled with an insulating material. In addition, the through-hole 116 can have all shapes known in the art, such as a conical shape, a cylindrical shape, etc.

[0058] The connecting conductor 117 can be used to physically and electrically connect the second passive component 112b and the first wiring layer 114a to each other. The material used to form the connecting conductor 117 can be a low-melting-point metal, such as solder containing tin (Sn), aluminum (Al), copper (Cu), etc., but is not limited thereto.

[0059] Each of the first insulating layer 121 and the second insulating layer 131 may include an insulating material. The insulating material may be a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material in which a thermosetting or thermoplastic resin is impregnated with an inorganic filler in a core (such as glass fiber, glass cloth, or glass fabric) (e.g., Ajinomoto Build-up Film (ABF)), but is not limited thereto. Each of the first insulating layer 121 and the second insulating layer 131 may include the same material as the insulating material 113, or may include a different material. The boundaries between adjacent first insulating layers 121 and adjacent second insulating layers 131 may be distinct, but may not be distinct.

[0060] The number of layers in each of the first insulating layer 121 and the second insulating layer 131 is not limited and can vary depending on their design. The number of layers in the first insulating layer 121 and the second insulating layer 131 can be the same or different. In addition, each of the first insulating layer 121 and the second insulating layer 131 can have a thickness smaller than the thickness of each of the first core layer 111a and the second core layer 111b.

[0061] Each of the fourth routing layer 122 and the fifth routing layer 132 may perform various functions according to its design. For example, each of the fourth routing layer 122 and the fifth routing layer 132 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. In this case, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, power (PWR) pattern, etc., such as data signal patterns, etc. In addition, each of the fourth routing layer 122 and the fifth routing layer 132 may contain various pads.

[0062] The material used to form each of the fourth wiring layer 122 and the fifth wiring layer 132 can be a conductive material. For example, the material used to form each of the fourth wiring layer 122 and the fifth wiring layer 132 can be a metallic material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc., but is not limited thereto.

[0063] Each of the fourth via layer 123 and the fifth via layer 133 may also perform various functions depending on their design. For example, each of the fourth via layer 123 and the fifth via layer 133 may include vias for grounding, vias for power, vias for signals, etc.

[0064] The material used to form each of the fourth via layer 123 and the fifth via layer 133 can be a conductive material. For example, the material used to form each of the fourth via layer 123 and the fifth via layer 133 can be a metallic material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc., but is not limited thereto.

[0065] Each via included in the fourth via layer 123 and the fifth via layer 133 can be formed by completely filling the via with a conductive material, or by forming a conductive material along the wall of the via. When the via is formed by forming a conductive material along the wall of the via, the via can be filled with an insulating material. Furthermore, the vias included in the fourth via layer 123 and the fifth via layer 133 can have all shapes known in the art, such as conical shapes, cylindrical shapes, etc.

[0066] The first protective layer 124 and the second protective layer 134 may be used to protect the fourth wiring layer 122 and the fifth wiring layer 132, respectively. The first protective layer 124 may have an opening that exposes a portion of the fourth wiring layer 122, and the second protective layer 134 may have an opening that exposes a portion of the fifth wiring layer 132.

[0067] The materials used to form each of the first protective layer 124 and the second protective layer 134 are not limited. For example, the materials used to form each of the first protective layer 124 and the second protective layer 134 may be solder resists, but are not limited thereto. The materials used to form each of the first protective layer 124 and the second protective layer 134 may be insulating materials, such as prepreg, Ajinomoto laminate (ABF), etc.

[0068] Figures 4A to 4J This is a schematic process diagram illustrating the process of manufacturing an embedded substrate for electronic components according to an exemplary embodiment.

[0069] Reference Figure 4A A first through-hole 111ah can be formed in the first core layer 111a. The method of forming the first through-hole 111ah is not limited and can be a known method such as laser drilling or mechanical drilling.

[0070] Reference Figure 4B The first core layer 111a with the first through hole 111ah formed can be attached to the carrier 220 and the adhesive film 210.

[0071] Reference Figure 4C The first passive component 112a is disposed in the first through-hole 111ah. In this case, the first passive component 112a can be disposed in such a way that it is attached to the adhesive film 210 exposed through the first through-hole 111ah.

[0072] Reference Figure 4D A first insulating material 113a can be formed to cover at least a portion of the first passive component 112a, while filling the first through-hole 111ah. In this case, the first insulating material 113a can be formed by sequentially stacking the first insulating material 113a and the first copper cladding layer 230a and then laminating the first insulating material 113a and the first copper cladding layer 230a.

[0073] Reference Figure 4E The carrier 220 and the adhesive film 210 can be removed. The carrier 220 and the adhesive film 210 can be removed in a manner that separates the adhesive film 210 into layers.

[0074] Reference Figure 4FA first wiring layer 114a can be formed on the first insulating material 113a, and a first via layer 115a can be formed to penetrate the first insulating material 113a. After forming vias using laser drilling or mechanical drilling, the first wiring layer 114a and the first via layer 115a can be formed by known plating processes, and the first copper plating layer 230a can be used as a seed layer.

[0075] Reference Figure 4G The second passive component 112b can be mounted on the first wiring layer 114a. The second passive component 112b can be mounted on the first wiring layer 114a via the connecting conductor 117.

[0076] Reference Figure 4H A second core layer 111b with a second through-hole 111bh formed thereon can be disposed on the first insulating material 113a, and a second insulating material 113b and a third insulating material 113c can be formed. In this case, the method of forming the second through-hole 111bh is not limited, and can be a known method such as laser drilling or mechanical drilling. The second insulating material 113b can be formed by sequentially stacking the second insulating material 113b and the second copper clad layer 230b and then laminating the second insulating material 113b and the second copper clad layer 230b. In addition, the third insulating material 113c can also be formed by sequentially stacking the third insulating material 113c and the third copper clad layer 230c and then laminating the third insulating material 113c and the third copper clad layer 230c.

[0077] Each of the first insulating material 113a, the second insulating material 113b, and the third insulating material 113c can be formed by laminating uncured prepreg and curing the laminated prepreg. The boundaries between the insulating materials 113a, 113b, and 113c may not be distinct. However, this disclosure is not limited thereto, and the boundaries can be distinct depending on the materials used to form the first insulating material 113a, 113b, and 113c, the method of forming them, etc.

[0078] Reference Figure 4IA second wiring layer 114b can be formed on the second insulating material 113b, and a second via layer 115b can be formed to penetrate the second insulating material 113b, thus forming a core structure. Additionally, a third wiring layer 114c can be formed on the third insulating material 113c, and a third via layer 115c can be formed to penetrate the third insulating material 113c. Furthermore, a through-hole 116 penetrating the first core layer 111a, the second core layer 111b, and the insulating material 113 can be formed. The method for forming each of the second wiring layer 114b, the third wiring layer 114c, the second via layer 115b, the third via layer 115c, and the through-hole 116 can be the same as the method for forming the first wiring layer 114a or the first via layer 115a.

[0079] Reference Figure 4J A first stacked structure 120 and a second stacked structure 130 can be formed on both sides of the core structure 110. Each of the first insulating layer 121 and the second insulating layer 131 can be formed by laminating ABF or the like and curing the laminated ABF or the like. The method for forming each of the fourth wiring layer 122, the fifth wiring layer 132, the fourth via layer 123, and the fifth via layer 133 can also be the same as the method for forming the first wiring layer 114a or the first via layer 115a. In addition, each of the first protective layer 124 and the second protective layer 134 can also be formed by laminating ABF or the like and curing the laminated ABF or the like.

[0080] Figure 5 This is a schematic cross-sectional view of an electronic component embedded substrate according to another exemplary embodiment of the present disclosure.

[0081] exist Figure 5 In the diagram, “A” is the perspective view of the second passive component 112b and the first wiring layer 114a when viewed from above.

[0082] Reference Figure 5 In an electronic component embedded substrate 100B according to another exemplary embodiment, the first passive component 112a and the second passive component 112b of the electronic component embedded substrate 100A are configured to be misaligned with each other on a plane.

[0083] As described above, the second passive component 112b can be connected to the first passive component 112a via a wiring pattern included in the first wiring layer 114a. In this case, the wiring pattern can be freely designed. Therefore, the first passive component 112a and the second passive component 112b can be connected to each other via a wiring pattern without being stacked vertically on top of each other, and the wiring pattern can be designed to significantly improve characteristics such as signal integrity, power integrity, etc.

[0084] Other details are substantially the same as those described above in the description of the electronic component embedded substrate 100A according to an exemplary embodiment, and therefore, their detailed description will be omitted.

[0085] Figure 6 This is a schematic cross-sectional view of an electronic component embedded substrate according to another exemplary embodiment of the present disclosure.

[0086] Reference Figure 6 Compared with the embedded electronic component substrate 100A according to an exemplary embodiment, the insulating layer 113 of the embedded electronic component substrate 100C according to another exemplary embodiment may include a first insulating material 113a, a second insulating material 113b, a third insulating material 113c and a fourth insulating material 113d.

[0087] A first insulating material 113a may cover the surface of the first passive component 112a and the surface of the first core layer 111a facing the second core layer 111b, while filling at least a portion of the first through-hole 111ah. A second insulating material 113b may cover the second passive component 112b, while filling at least a portion of the second through-hole 111bh. A third insulating material 113c may be disposed on the surface of the first core layer 111a opposite to the surface of the first core layer 111a facing the second core layer 111b. A fourth insulating material 113d may be disposed on the surface of the second core layer 111b opposite to the surface of the second core layer 111b facing the first core layer 111a.

[0088] The first insulating material 113a, the second insulating material 113b, the third insulating material 113c, and the fourth insulating material 113d may comprise the same material or different materials. The boundary between any two adjacent materials 113a, 113b, 113c, and 113d may be explicit or implicit. Only a portion of the boundary between any two adjacent materials 113a, 113b, 113c, and 113d may be explicit, while the remaining portion may be implicit.

[0089] For example, each of the third insulating material 113c and the fourth insulating material 113d may include a material different from that included in the first insulating material 113a and / or the second insulating material 113b. As a non-limiting example, the first insulating material 113a and the second insulating material 113b may be formed using prepreg (PPG) such that the boundary between the first insulating material 113a and the second insulating material 113b may be indistinct, and each of the third insulating material 113c and the fourth insulating material 113d may be formed using Ajinomoto Build-up Film (ABF) such that the boundary between each of the third insulating material 113c and the fourth insulating material 113d and each of the first insulating material 113a and the second insulating material 113b may be distinct. When each of the third insulating material 113c and the fourth insulating material 113d is formed using Ajinomoto Build-up Film (ABF), fine circuit patterns can be easily realized.

[0090] Other details are substantially the same as those described above in the description of the electronic component embedded substrate 100A according to an exemplary embodiment, and therefore, their detailed description will be omitted.

[0091] Figure 7 This is a schematic cross-sectional view of an electronic component embedded substrate according to another exemplary embodiment of the present disclosure.

[0092] Reference Figure 7 Compared with the electronic component embedded substrate 100A according to an exemplary embodiment, the core structure 110 of the electronic component embedded substrate 100D according to another exemplary embodiment may further include a first die 118a and a second die 118b.

[0093] The first die 118a may be configured to be spaced apart from the first passive component 112a in the first via 111ah, and may include a body 118ab and a first connection pad 118ap. The second die 118b may be configured to be spaced apart from the second passive component 112b in the second via 111bh, and may include a second body 118bb and a second connection pad 118bp.

[0094] In this configuration, the first die 118a can be connected to the third wiring layer 114c via a via included in the third via layer 115c, and the second die 118b can be connected to the second wiring layer 114b via a via included in the second via layer 115b. The vias connecting the first die 118a and the second die 118b to the third wiring layer 114c and the second wiring layer 114b, respectively, can be formed to have a depth different from or the same as the depth of the vias connecting the first passive component 112a and the second passive component 112b to the third wiring layer 114c and the second wiring layer 114b, respectively.

[0095] For example, the first connection pad 118ap may be configured to face the third routing layer 114c for connection to the third routing layer 114c, and the second connection pad 118bp may be configured to face the second routing layer 114b for connection to the second routing layer 114b. Therefore, the second routing layer 114b may include a routing pattern connected to the second connection pad 118bp, and the third routing layer 114c may include a routing pattern connected to the first connection pad 118ap.

[0096] The second via layer 115b may have a via penetrating a portion of the second insulating material 113b to connect the second connection pad 118bp to the second wiring layer 114b, and the third via layer 115c may have a via penetrating the third insulating material 113c to connect the first connection pad 118ap to the third wiring layer 114c.

[0097] However, the configuration of each of the first die 118a and the second die 118b is not limited thereto, and the first connection pad 118ap may be configured to face the second die 118b. Additionally, the second connection pad 118bp may be configured to face the first die 118a.

[0098] Other details are substantially the same as those described above in the description of the electronic component embedded substrate 100A according to an exemplary embodiment, and therefore, their detailed description will be omitted.

[0099] Figure 8 This is a schematic cross-sectional view of an electronic component embedded substrate according to another exemplary embodiment of the present disclosure.

[0100] Reference Figure 8 Compared to the electronic component embedded substrate 100D according to an exemplary embodiment, each of the first connection pad 118ap and the second connection pad 118bp of the electronic component embedded substrate 100E according to another exemplary embodiment may be configured to face the first wiring layer 114a for connection to the first wiring layer 114a. Therefore, the first wiring layer 114a may include wiring patterns connected to each of the first connection pad 118ap and the second connection pad 118bp.

[0101] Additionally, the first via layer 115a may have a via that penetrates a portion of the first insulating material 113a to connect the first connection pad 118ap to the first wiring layer 114a. The second connection pad 118bp can be connected to the first wiring layer 114a disposed on the first wiring layer 114a via a connection conductor 117 disposed on the first wiring layer 114a.

[0102] The first die 118a may further include a first through electrode 118av penetrating the first body 118ab, and the second die 118b may further include a second through electrode 118bv penetrating the second body 118bb. The first through electrode 118av and the second through electrode 118bv may be connected to the first connection pad 118ap and the second connection pad 118bp, respectively.

[0103] In this configuration, the first through electrode 118av can electrically connect the first connection pad 118ap and the third wiring layer 114c to each other, and the second through electrode 118bv can electrically connect the second connection pad 118bp and the second wiring layer 114b to each other.

[0104] Additionally, the second via layer 115b may have a via penetrating a portion of the second insulating material 113b to connect the second through electrode 118bv and the second wiring layer 114b to each other, and the third via layer 115c may include a via penetrating the third insulating material 113c to connect the first through electrode 118av and the third wiring layer 114c to each other. Therefore, the first through electrode 118av can be connected to the third wiring layer 114c through the vias in the third via layer 115c, and the second through electrode 118bv can be connected to the second wiring layer 114b through the vias in the second via layer 115b.

[0105] As shown in the attached figure, when the second connection pad 118bp is set to face the first wiring layer 114a, the second connection pad 118bp can be easily connected to the first wiring layer 114a.

[0106] Other details are substantially the same as those described above in the descriptions of the electronic component embedded substrate 100A according to an exemplary embodiment and the electronic component embedded substrate 100D according to another exemplary embodiment, and therefore, their detailed descriptions will be omitted.

[0107] Figure 9 This is a schematic cross-sectional view illustrating an example of a semiconductor chip disposed on an embedded substrate of an electronic component according to an exemplary embodiment of the present disclosure.

[0108] Reference Figure 9According to an exemplary embodiment, the semiconductor chip 300 may be mounted on an electronic component embedded substrate 100A. Passive components may not be mounted on the substrate but may be embedded within the electronic component embedded substrate 100A. Therefore, the passive components can be electrically connected to the semiconductor chip 300 via a significantly shorter electrical path. In this case, the passive components may be mounted via a connecting conductor 510, and the connecting conductor 510 may be formed using solder. When the connecting conductor 510 is solder, solder resist 520 may be stacked.

[0109] Semiconductor chip 300 may be a central processing unit (CPU), but is not limited to this.

[0110] Semiconductor chip 300 can be mounted on electronic component embedded substrates 100B, 100C, 100D and 100E according to other exemplary embodiments in substantially the same manner as electronic component embedded substrate 100A according to an exemplary embodiment.

[0111] Figure 10 This is a schematic cross-sectional view illustrating an example of a semiconductor package disposed on an embedded substrate of an electronic component according to an exemplary embodiment of the present disclosure.

[0112] Reference Figure 10 According to an exemplary embodiment, the semiconductor package 400 may be mounted on an electronic component embedded substrate 100A. Passive components may not be mounted on the substrate but may be embedded within the electronic component embedded substrate 100A. Therefore, the passive components can be electrically connected to the semiconductor chip 420 in the semiconductor package 400 via a significantly shorter electrical path. In this case, the passive components can be mounted via a connecting conductor 510, and the connecting conductor 510 may be formed using solder. When the connecting conductor 510 is solder, solder resist 520 may be stacked.

[0113] The semiconductor package 400 may include an interposer substrate 410 and one or more semiconductor chips 420 mounted on the interposer substrate 410, and may also include an encapsulant 430 covering the semiconductor chips 420.

[0114] Semiconductor chip 420 may include at least one of application-specific integrated circuit (ASIC) and high-bandwidth memory (HBM). For example, semiconductor chip 420 may include one ASIC and two HBMs, but is not limited thereto.

[0115] The semiconductor package 400 according to other exemplary embodiments can be mounted on the electronic component embedded substrates 100B, 100C, 100D and 100E in substantially the same manner as the electronic component embedded substrate 100A according to exemplary embodiments.

[0116] The term "coplanar" in this specification means that the components are positioned on substantially the same horizontal plane / height, and is a concept that includes not only precisely identical cases but also minor positional differences that may occur due to errors in the manufacturing process.

[0117] The terms "connecting" or "connection" in this specification can refer not only to direct connections but also to indirect connections, including those via adhesive layers, etc. Furthermore, the terms "electrically connecting" or "electrically connecting" in this specification encompass both physical and non-physical connections.

[0118] Furthermore, the terms "first," "second," etc., used in this specification are used to distinguish one component from another, without limiting the order and / or importance of the components. In some cases, without departing from the spirit of this disclosure, a "first" component may be referred to as a "second" component, and similarly, a "second" component may be referred to as a "first" component.

[0119] As described above, an electronic component embedded substrate in which multiple electronic components are embedded can be provided.

[0120] In addition, embedded substrates for electronic components that enable high-density integration can be provided.

[0121] Additionally, embedded substrates for electronic components with improved signal integrity and power integrity can be provided.

[0122] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. An embedded substrate for electronic components, comprising: The first core layer has a first through-hole; A first passive component is disposed in the first through hole; The second core layer is disposed on the first core layer and has a second through hole; A second passive component is disposed in the second through hole; An insulating material covers at least a portion of each of the first passive component and the second passive component and is disposed in at least a portion of each of the first through hole and the second through hole; A first wiring layer is disposed between the first passive component and the second passive component, and at least a portion of the first wiring layer is covered by the insulating material; as well as First via layer, The first wiring layer is located in the second via, the first via layer passes through the insulating material to connect the first wiring layer to the first passive component, and the first wiring layer is also connected to the second passive component.

2. The embedded substrate for electronic components according to claim 1, wherein, The insulating material includes: A first insulating material extends from the surface of the first core layer facing the second core layer into the first through-hole and covers at least a portion of the first passive component; and A second insulating material covers at least a portion of the second passive component and is disposed within at least a portion of the second through-hole. The first wiring layer is formed on and in contact with the first insulating material.

3. The embedded substrate for electronic components according to claim 1, further comprising: Connecting conductors are disposed on the first wiring layer. The second passive component is connected to the first wiring layer via the connecting conductor.

4. The embedded substrate for electronic components according to claim 3, wherein, The connecting conductor includes solder.

5. The electronic component embedded substrate according to any one of claims 1-4, wherein, The surface of the second core layer facing the first core layer and the surface of the first wiring layer facing the first passive component are coplanar.

6. The embedded substrate for electronic components according to claim 1, wherein, The first passive component and the second passive component are configured to be misaligned with each other on the plane.

7. The embedded substrate for electronic components according to claim 1, wherein, The insulating material covers the other surface of the first core layer opposite to the surface of the first core layer facing the second core layer, and the other surface of the second core layer opposite to the surface of the second core layer facing the first core layer, and the insulating material is disposed in the space between the first core layer and the second core layer.

8. The embedded substrate for electronic components according to claim 7, wherein, The insulating material includes a first insulating material covering at least a portion of the first passive component, a second insulating material disposed on the second core layer and covering at least a portion of the second passive component, and a third insulating material disposed on another surface of the first core layer opposite to the surface facing the second core layer.

9. The embedded substrate for electronic components according to claim 8, wherein, At least one of the second insulating material and the third insulating material contains a material different from the material contained in the first insulating material.

10. The embedded substrate for electronic components according to claim 1, wherein the embedded substrate for electronic components further comprises: A second wiring layer is disposed on the insulating material and connected to the second passive component; as well as A third wiring layer is disposed on the insulating material and connected to the first passive component.

11. The embedded substrate for electronic components according to claim 10, further comprising: Through-holes penetrate the first core layer, the second core layer, and the insulating material, and connect the second wiring layer and the third wiring layer to each other.

12. The embedded substrate for electronic components according to claim 10, further comprising: The first die is configured to be spaced apart from the first passive component in the first via and includes a first body and a first connection pad; as well as The second die, configured to be spaced apart from the second passive component in the second via, and including a second body and a second connection pad, The second die is connected to the second wiring layer, and the first die is connected to the third wiring layer.

13. The embedded substrate for electronic components according to claim 12, wherein, The first connection pad is configured to face the third wiring layer for connection to the third wiring layer, and The second connection pad is configured to face the second wiring layer for connection to the second wiring layer.

14. The embedded substrate for electronic components according to claim 12, wherein, Each of the first connection pad and the second connection pad is configured to face the first wiring layer to connect to the first wiring layer.

15. The embedded substrate for electronic components according to claim 14, wherein, The first die also includes a first through electrode that penetrates the first body and connects the first connection pad and the third wiring layer to each other. The second die also includes a second through electrode that penetrates the second body and connects the second connection pad to the second wiring layer.

16. The embedded substrate for electronic components according to claim 1, wherein, The first passive component includes a plurality of first passive components, and the second passive component includes a plurality of second passive components. The plurality of first passive components are spaced apart from each other in the first through hole, and the plurality of second passive components are spaced apart from each other in the second through hole.

17. An embedded substrate for electronic components, comprising: The core structure includes a first core layer having a first through hole, a first passive component disposed in the first through hole, a second core layer disposed on the first core layer and having a second through hole, a second passive component disposed in the second through hole, and an insulating material covering each of the first passive component and the second passive component and disposed in at least a portion of each of the first through hole and the second through hole; A first stacked structure includes a first insulating layer and a first wiring layer connected to the first passive component, wherein the first core layer is disposed between the first stacked structure and the second core layer; as well as The second stacked structure includes a second insulating layer and a second wiring layer connected to the second passive component, wherein the second core layer is disposed between the second stacked structure and the first core layer. The core structure further includes a third wiring layer and a first via layer. The third wiring layer is disposed between the first passive component and the second passive component, and at least a portion of the third wiring layer is covered by the insulating material. The third wiring layer is located in the second via, the first via layer passes through the insulating material to connect the third wiring layer to the first passive component, and the third wiring layer is also connected to the second passive component.

18. The embedded substrate for electronic components according to claim 17, further comprising: A second via layer is embedded in the insulating material and connects the first passive component and the first wiring layer to each other. The insulating material covers the side surface of the second passive component and the surface of the second passive component facing the second stacked structure.

19. An embedded substrate for electronic components, comprising: The first core layer has a first through-hole; A first passive component is disposed in the first through hole; The second core layer is disposed on the first core layer and has a second through hole; A second passive component is disposed in the second through hole; An insulating material covers at least a portion of each of the first passive component and the second passive component and is disposed in at least a portion of each of the first through hole and the second through hole; as well as A conductive structure is embedded in the insulating material and disposed between the first passive component and the second passive component. The conductive structure includes a first wiring layer and a first via layer. The first wiring layer is located in the second via, and the first via layer passes through the insulating material to connect the first wiring layer to the first passive component. The first wiring layer is also connected to the second passive component. The embedded substrate of the electronic component further includes a second wiring layer, which is disposed on the insulating material and connected to the second passive component.

20. The embedded substrate for electronic components according to claim 19, wherein, The insulating material covers the other surface of the first core layer opposite to the surface of the first core layer facing the second core layer, and the other surface of the second core layer opposite to the surface of the second core layer facing the first core layer, and the insulating material is disposed in the space between the first core layer and the second core layer.

21. The embedded substrate for electronic components according to claim 19, wherein, The insulating material includes: A first insulating material extends from the surface of the first core layer facing the second core layer into the first through-hole and covers at least a portion of the first passive component; and A second insulating material is disposed on the second core layer and covers at least a portion of the second passive component. The first wiring layer is formed on and in contact with the first insulating material.

22. The embedded substrate for electronic components according to claim 19, wherein, The conductive structure further includes a connecting conductor disposed on the first wiring layer to connect the second passive component and the first wiring layer. The embedded substrate of the electronic component further includes a third wiring layer, which is disposed on the insulating material and connected to the first passive component.

23. The embedded substrate for electronic components according to claim 22, further comprising: The first die is configured to be spaced apart from the first passive component in the first through-hole; as well as The second die is configured to be spaced apart from the second passive component in the second via. The second die is connected to the second wiring layer, and the first die is connected to the third wiring layer.

24. The electronic component embedded substrate according to claim 23, further comprising another conductive structure embedded in the insulating material and disposed between the first die and the second die, in, The first die and the second die are connected to each other through the other conductive structure.

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