Apparatus and method for driving a display

Abstract

The present disclosure relates to an apparatus and method for driving a display. A display driving apparatus capable of operating a source driver integrated circuit (IC) in a low power mode during a touch sensing period includes a source driver IC configured to operate in a first low power mode that deactivates an analog data processing unit or a second low power mode that deactivates both the analog data processing unit and a digital data processing unit during a touch sensing period of a first frame, and a readout IC configured to provide a touch sensor driving signal to a touch sensor during the touch sensing period and receive touch sensing data from the touch sensor according to the touch sensor driving signal.

Description

Technical Field

[0001] This disclosure relates to a display driver, and more specifically, to a display driver with reduced power consumption. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. Recently, various types of display devices have been used, such as liquid crystal display (LCD) devices or organic light-emitting diode (OLED) display devices.

[0003] Recently, traditional input methods such as buttons, keyboards and mice have been abandoned, and display devices with touch screen panels that can detect touch input from the user's finger or stylus pen (hereinafter referred to as "touch display devices") are widely used.

[0004] In addition to the general functions of driving a touch display device, the display driver for driving the touch display device also performs the function of detecting the presence or absence of a touch and touch coordinates (or touch position). Specifically, the display driver detects touch sensing signals by driving a touch sensor (or touch electrode), and uses the detected touch sensing signals to detect touch information including touch coordinates or the presence or absence of a touch.

[0005] In particular, regarding touch display devices that integrate a touchscreen panel and a display panel, such as Figure 1A or Figure 1B As shown, during a frame period 1F, the display driver can be driven by dividing the frame period 1F into a display period DP (DP1 to DPn) and a touch sensing period TP (TP1 to TPm). During the display period DP, image data is input and output to the display panel, while during the touch sensing period TP, the touch sensor is driven to detect touch information.

[0006] A time-division driven display driver can drive a source driver integrated circuit (IC) to allow input image data to be output to the display panel during the display period DP (DP1 to DPn), and can drive a touch IC to allow touch information to be detected during the touch sensing period TP (TP1 to TPm).

[0007] However, for display drivers driven in a time-division manner, even if the source driver IC does not need to operate during the touch sensing period TP (TP1 to TPm), the source driver IC will still consume static and dynamic current in order to receive the clock training signal sent from the timing controller during the touch sensing period TP (TP1 to TPm), which will lead to increased power consumption. Summary of the Invention

[0008] Therefore, this disclosure is dedicated to solving the above-mentioned problems, and one technical objective of this disclosure is to provide a device and method for driving a display that is capable of operating a source driver integrated circuit (IC) in a low-power mode during touch sensing.

[0009] Furthermore, another technical objective of this disclosure is to provide an apparatus and method for driving a display, which is capable of operating a source driver IC in a low-power mode based on image data displayed during a display period.

[0010] In addition, another technical objective is to provide a device and method for driving a display that allows a timing controller to skip the transmission of clock training data during touch sensing periods.

[0011] According to one aspect of this disclosure, a display driving device is provided, the display driving device comprising: a source driver IC configured to operate in a first low-power mode by disabling an analog data processing unit or in a second low-power mode by disabling both the analog data processing unit and the digital data processing unit during a touch sensing period of a first frame; and a readout IC configured to provide a touch sensor driving signal to a touch sensor during the touch sensing period and to receive touch sensing data from the touch sensor based on the touch sensor driving signal.

[0012] According to another aspect of this disclosure, a display driving method is provided, the display driving method comprising the steps of: driving a source driver integrated circuit (IC) to output image data to a display panel in a normal mode activating a digital data processing unit and an analog data processing unit during a display period of a first frame; and driving the source driver IC in a first low-power mode disabling the analog data processing unit or a second low-power mode disabling both the analog data processing unit and the digital data processing unit during a touch sensing period of the first frame. Attached Figure Description

[0013] The accompanying drawings were added to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0014] Figure 1A and Figure 1B This is a diagram showing the display period and touch sensing period of a frame when a typical touch display device operates in a time-division manner;

[0015] Figure 2 This is a block diagram illustrating a touch display device according to one embodiment of the present disclosure;

[0016] Figure 3 This is a block diagram illustrating the connection relationship between a timing controller and a source driver integrated circuit (IC) according to one embodiment of the present disclosure;

[0017] Figure 4 This is a diagram showing the waveforms of the Clock Embedded Data Signaling (CEDS) packets sent from the timing controller to the source driver IC and the waveform of the LOCK signal according to this disclosure;

[0018] Figure 5 This is a schematic block diagram illustrating the configuration of a source driver IC according to one embodiment of the present disclosure;

[0019] Figure 6A This is a graph showing the waveform of each signal when the source driver IC operates in the first low-power mode;

[0020] Figure 6B This is a graph showing the waveform of each signal when the source driver IC operates in the second low-power mode;

[0021] Figure 7 This is a diagram showing the waveforms of the signals sent and received between the touch controller and the readout IC; and

[0022] Figure 8 This is a flowchart illustrating a display driving method according to one embodiment of the present disclosure. Detailed Implementation

[0023] In this specification, it should be noted that, whenever possible, the same reference numerals used to denote the same element in other figures are used for that element. In the following description, detailed descriptions of functions and configurations known to those skilled in the art that are unrelated to the basic configuration of this disclosure will be omitted. The terminology described in this specification should be understood as follows.

[0024] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0025] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the details shown. The same reference numerals always denote the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where such descriptions unnecessarily obscure the essential points of this disclosure.

[0026] When using the terms "including," "having," and "comprising" as described in this specification, an additional part may be added unless "only" is used. Singular terms may include plural forms unless otherwise stated.

[0027] When explaining a component, even if there is no explicit description, the component is also interpreted as including the tolerance range.

[0028] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may be included unless “only” or “directly” is used.

[0029] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0030] The term "at least one" should be understood to include any and all combinations of one or more related listed items. For example, "at least one of the first, second, and third items" means a combination of all items drawn from two or more of the first, second, and third items, as well as the first, second, or third item.

[0031] Features of the various embodiments of this disclosure may be partially or wholly coupled or combined with each other, and may interoperate and be technically driven with each other in various ways, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0032] In the following description, embodiments of this specification will be described in detail with reference to the accompanying drawings.

[0033] Figure 2 This is a block diagram illustrating a touch display device according to one embodiment of the present disclosure. The touch display device 200 according to one embodiment of the present disclosure performs display functions and touch sensing functions, and can be implemented as a flat panel display device, such as a liquid crystal display (LCD) device or an organic light-emitting diode (OLED) display device.

[0034] The touch display device 200 according to this disclosure may include a capacitive touchscreen for sensing touches caused by contact with a conductive object such as a finger or an active pen. The capacitive touchscreen may be formed independently of a display panel used to implement the display, or it may be formed as a touch sensor (or touch electrode) embedded in a pixel array of the display panel.

[0035] like Figure 2 As shown, the touch display device 200 according to the present disclosure includes a display panel 205 and a display driver 210 for driving the display panel 205.

[0036] Display panel 205 displays an image at a predetermined grayscale level or receives touches from a finger or active stylus. In one embodiment, display panel 205 may be a display panel having an in-cell touch structure using a capacitance scheme. According to one embodiment, display panel 205 may be an in-cell touch display panel using a self-capacitance scheme or an in-cell touch display panel using a mutual capacitance scheme. Hereinafter, for ease of description, it will be described by assuming that display panel 205 is an in-cell touch display panel using a self-capacitance scheme.

[0037] The display panel 205 operates in display mode and touch sensing mode. During the display period, the display panel 205 operates in display mode to display an image using light emitted from a backlight unit (not shown), and during the touch sensing period, it operates in touch sensing mode to act as a touch panel for touch sensing.

[0038] In one implementation, it can be as follows: Figure 1A The display mode is maintained during the display period DP set in one of the frames shown, or it can be maintained as follows: Figure 1B The display mode is maintained in each of the multiple display periods DP1 to DPn set in a single frame, as shown. Furthermore, it is possible to... Figure 1A The touch sensing mode is maintained during the touch sensing period TP set in a frame shown, or it can be maintained as follows: Figure 1B The frame shown maintains touch sensing mode in each of the multiple sensing periods TP1 to TPm between multiple display periods DP1 to DPn. In this case, for a high-resolution implementation, the length of the display period DP can be set to be longer than the length of the touch sensing period TP in a single frame, or the number of display periods DP1 to DPn can be greater than the number of touch sensing periods TP1 to TPm.

[0039] The display panel 205 includes multiple data lines D1 to Dn, multiple gate lines G1 to Gm, multiple pixels P, multiple touch sensors TE, and multiple touch lines T1 to Tk.

[0040] In display mode, each of the multiple data lines D1 to Dn receives a data signal. In display mode, each of the multiple gate lines G1 to Gm receives a scan pulse. Each of the multiple data lines D1 to Dn and each of the multiple gate lines G1 to Gm are configured to intersect each other on the substrate, thereby defining multiple pixel regions. Each of the multiple pixels P may include a thin-film transistor (not shown) connected to adjacent gate lines and adjacent data lines, a pixel electrode (not shown) connected to the thin-film transistor, and a storage capacitor (not shown) connected to the pixel electrode.

[0041] Each of the multiple touch sensors TE can be used as a touch electrode for sensing touches made with a finger or active pen, or as a common electrode for driving liquid crystals by forming an electric field together with pixel electrodes. That is, each of the multiple touch sensors TE functions as a touch electrode in touch sensing mode and as a common electrode in display mode. Since each of the multiple touch sensors TE also functions as a common electrode for driving liquid crystals, each of the multiple touch sensors TE can be made of a transparent conductive material.

[0042] Since each of the multiple touch sensors TE functions as a self-capacitance touch sensor in touch sensing mode, the size of each of the multiple touch sensors TE should be larger than the minimum contact size between the touch object and the display panel 205. Therefore, each of the multiple touch sensors TE can have a size corresponding to one or more pixels P. In one embodiment, the multiple touch sensors TE can be arranged at regular intervals along multiple horizontal lines and multiple vertical lines.

[0043] Each of the multiple touch lines T1 to Tk is individually connected to each of the multiple touch sensors TE. In a frame period of 1F... Figure 1A The displayed time period DP or Figure 1B During the display period DP1 to DPn, each of the multiple touch lines T1 to Tk provides a common voltage Vcom to the corresponding touch sensor TE.

[0044] The display driver 210 displays an image via the display panel 205 by providing data signals to a plurality of pixels P included in the display panel 205 during the display period DP1 to DPn (hereinafter referred to as "DP"), and senses a touch via the touch sensor TE during the touch sensing period TP1 to TPm.

[0045] Therefore, the display driver 210 may include a data driver circuit 212, a gating driver circuit 214, a timing controller 216, a touch driver circuit 218, and a touch controller 220.

[0046] During the display period DP, the data driving circuit 212 receives clock embedded data signaling (CEDS) packets from the timing controller 216 and obtains clock, control data, and digital image data from the CEDS packets. Here, a CEDS packet refers to a packet in which a clock is embedded between multiple data lines.

[0047] The data driving circuit 212 converts the acquired digital image data into analog data signals and provides the analog data signals to the pixel P through multiple data lines D1 to Dn.

[0048] Therefore, such as Figure 3 As shown, the data driver circuit 212 includes a plurality of source driver integrated circuits (ICs) SDIC#1 to SDIC#i. In one embodiment, the source driver ICs SDIC#1 to SDIC#i are cascaded and connected to the timing controller 216 in a point-to-point manner via CEDS line pairs CEDS#1 to CEDS#i, and each of the source driver ICs SDIC#1 to SDIC#i receives CEDS packets from the timing controller 216.

[0049] Specifically, such as Figure 4 As shown, each of the source driver ICs SDIC#1 to SDIC#i receives a CEDS packet including clock training data CT for clock recovery, and when clock recovery is complete, each of the source driver ICs SDIC#1 to SDIC#i sequentially receives a CEDS packet including control data CP and digital image data RGB.

[0050] In one implementation, such as Figure 5 As shown, each of the source driver ICs SDIC#1 to SDIC#i includes a digital data processing unit 510 and an analog data processing unit 520.

[0051] The digital data processing unit 510 receives and analyzes CEDS packets from the timing controller 216, latches digital image data RGB in predetermined units according to the sampled signal, and then converts the digital image data RGB into an analog data signal. For this purpose, the digital data processing unit 510 includes a data receiver 512, a recovery circuit 514, a data sampling unit 516, and a digital-to-analog converter (DAC) 518.

[0052] Data receiver 512 receives CEDS packets provided as differential signal pairs via CEDS line pairs. In one embodiment, data receiver 512 may be implemented as a receive buffer.

[0053] Recovery circuit 514 uses the clock training data CT included in the CEDS packet to recover the clock to be used for data sampling. When clock recovery is complete, recovery circuit 514 recovers control data CP and digital image data RGB from the CEDS packet based on the recovered clock.

[0054] Specifically, when the recovery circuit 514 receives a high-level LOCK signal LOCK#0 from the timing controller 216 via the data receiver 512 or from another source driver IC SDIC, the recovery circuit 514 recovers the clock to be used for data sampling from the CEDS packet. Figure 4 As shown, when the phase and frequency of the recovered clock are fixed, thus stabilizing the clock, the recovery circuit 514 outputs a high-level LOCK signal to the outside. In this case, when the source driver IC SDIC including the recovery circuit 514 is the last source driver IC SDIC#i, the recovery circuit 514 outputs a high-level LOCK signal LOCK#i to the timing controller 216. When the source driver IC SDIC including the recovery circuit 514 is not the last source driver IC SDIC#i, the recovery circuit 514 outputs a high-level LOCK signal to another source driver IC SDIC.

[0055] When a low-level LOCK signal is received from the outside, the recovery circuit 514 outputs a low-level LOCK signal to the outside even when the clock recovered in the recovery circuit 514 is stable. Therefore, even if one of the clocks of the multiple source driver ICs SDIC#1 to SDIC#i is unstable, since the low-level LOCK LOCK#i is eventually output to the timing controller 216, the timing controller 216 will send a CEDS packet including the clock training data CT to the source driver ICs SDIC#1 to SDIC#i until the clocks of all source driver ICs SDIC#1 to SDIC#i are stable, and each of the source driver ICs SDIC#1 to SDIC#i continues clock training.

[0056] Meanwhile, when clock recovery is completed according to clock training, recovery circuit 514 recovers control data CP and digital image data RGB from the CEDS packets received by data receiver 512, and sends the recovered control data CP and recovered digital image data RGB to data sampling unit 516.

[0057] In one embodiment, the control data CP recovered by the recovery circuit 514 may include at least one of the following: polarity control signal POL, source start pulse SSP, source sampling clock SSC, source output enable signal SOE, first operation mode setting information, and second operation mode setting information.

[0058] In this case, the first operating mode setting information indicates information for setting the source driver IC SDIC to a first low-power mode during the touch sensing period TP. The first low-power mode refers to a power mode that disables the analog data processing unit 520 of the source driver IC SDIC to reduce the quiescent and dynamic current consumed in the source driver IC SDIC. Specifically, as... Figure 6A As shown, during the touch sensing period TP following the corresponding display period DP, when the first operation mode setting information is set to a high level, the recovery circuit 514 disables the analog data processing unit 520 and keeps the digital data processing unit 510 in an active state, thereby allowing the source driver IC SDIC to operate in a first low-power mode.

[0059] When the source driver IC SDIC operates in the first low-power mode, the digital data processing unit 510 is activated while only the analog data processing unit 520 is disabled. Therefore, the operation of the digital data processing unit 510 consumes both quiescent and dynamometer current. However, clock training data CT of CEDS packets can be received normally from the timing controller 216, allowing clock training to be performed. Therefore, it is advantageous that the display period DP can begin after the touch sensing period TP, while simultaneously receiving CEDS packets normally.

[0060] The second operating mode setting information indicates information for setting the source driver IC SDIC to a second low-power mode during the touch sensing period TP. The second low-power mode refers to disabling both the analog data processing unit 520 and the digital data processing unit 510 of the source driver IC SDIC to further reduce the quiescent and dynamism current consumed in the source driver IC SDIC. Specifically, as... Figure 6B As shown, during the touch sensing period TP following the corresponding display period DP, when the second operation mode setting information is set to a high level, the recovery circuit 514 disables both the digital data processing unit 510 and the analog data processing unit 520, thereby allowing the source driver IC SDIC to operate in the second low-power mode.

[0061] When the source driver IC SDIC operates in the second low-power mode, it may not receive CEDS packets from the timing controller 216 because both the analog data processing unit 520 and the digital data processing unit 510 are disabled. Therefore, since the display period DP should begin after the touch sensing period TP and clock training can then be performed, it cannot properly receive digital image data RGB with the start of the display period DP. However, compared to the first low-power mode, there is an advantage of reduced quiescent and dynamic current consumption.

[0062] In one implementation, when transmitting digital image data RGB corresponding to the last horizontal row of the CEDS group, first and second operation mode setting information can be included in control data CP mapped to the corresponding digital image data RGB. According to this example, when the output of the data signal corresponding to the corresponding digital image data RGB is complete, the recovery circuit 514 can enter a first low-power mode or a second low-power mode.

[0063] Meanwhile, when both the first operation mode setting information and the second operation mode setting information are set to low level, during the touch sensing period TP after the corresponding display period DP, the recovery circuit 514 activates both the digital data processing unit 510 and the analog data processing unit 520, thereby allowing the source driver IC SDIC to operate in normal mode.

[0064] When the source driver IC SDIC operates in a first low-power mode or a second low-power mode during the touch sensing period TP, the recovery circuit 514 monitors the touch synchronization signal Tsync. When the touch synchronization signal Tsync goes high, the recovery circuit 514 determines that the display period DP has started and reactivates the deactivated analog data processing unit 520 or digital data processing unit 510, thereby allowing the source driver IC SDIC to operate in normal mode.

[0065] As described above, according to this disclosure, based on the first or second operating mode setting information included in the control data CP recovered by the recovery circuit 514, the source driver IC SDIC can operate in a first low-power mode or a second low-power mode during the touch sensing period TP, thereby reducing the power consumption of the source driver IC SDIC.

[0066] Refer again Figure 5The data sampling unit 516 generates a sampling clock based on the control data CP sent from the recovery circuit 514, sequentially latches digital image data RGB corresponding to a horizontal row provided by the recovery circuit 514 according to the sampling clock, and then outputs the digital image data RGB corresponding to a horizontal row to the DAC 518. For this purpose, the data sampling unit 516 may include: a shift register (not shown) for sequentially generating the sampling clock by shifting the source start pulse SSP included in the control data CP according to the source sampling clock SSC; and a latch (not shown) for sequentially latching the digital image data RGB according to the sampling clock.

[0067] In response to the polarity control signal POL, the DAC 518 converts each digital image data RGB output from the data sampling unit 516 into an analog data signal with positive polarity or an analog data signal with negative polarity, and sends the analog data signal to the analog data processing unit 520.

[0068] The analog data processing unit 520 outputs the analog data signal generated by the digital data processing unit 510 to the display panel 205. In one embodiment, the analog data processing unit 520 may include an output buffer 522. The output buffer 522 outputs data signals to the data lines D1 to Dn during the period when the source output enable signal SOE is low, and provides a charge-sharing voltage or common voltage Vcom to the data lines D1 to Dn during the period when the source output enable signal SOE is high.

[0069] Refer again Figure 2 During the display period DP, the gating drive circuit 214, under the control of the timing controller 216, generates gating pulses (or scan pulses) synchronized with the data signal, shifts the generated gating pulses, and sequentially provides them to gating lines G1 to Gm. For this purpose, the gating drive circuit 214 may include multiple gating driver ICs (not shown). During the display period DP, under the control of the timing controller 216, the gating driver ICs sequentially provide gating pulses synchronized with the data signal to gating lines G1 to Gm to select the data lines for writing data signals. The gating pulses oscillate between a gating high voltage VGH and a gating low voltage VGL.

[0070] During the touch sensing period TP, the gating drive circuit 214 can provide a low gating voltage VGL to the gating lines G1 to Gm without generating gating pulses. Therefore, the gating lines G1 to Gm provide gating pulses to the TFT of each pixel during the display period DP to sequentially select the data lines in the display panel 205 to which data signals will be written, and remain at a low gating voltage VGL during the touch sensing period TP to prevent changes in the output of the touch sensor TE.

[0071] The timing controller 216 uses timing signals input from an external host system (not shown) to encode control data CP for controlling the operating timing of the source driver IC SDIC, and sends the encoded control data CP to the source driver IC SDIC via the CEDS line pair. In one embodiment, the timing signals may include at least one of a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a master clock MCLK.

[0072] In one embodiment, the control data CP for controlling the operating timing of the source driver IC SDIC includes a polarity control signal POL, a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, and first operating mode setting information and second operating mode setting information for setting the operating mode of the source driver IC SDIC.

[0073] As described above, the first operation mode setting information indicates information for operating the source driver IC SDIC in a first low-power mode by disabling the analog data processing unit 520 of the source driver IC SDIC during the touch sensing period TP. In order to operate the source driver IC SDIC in the first low-power mode, the timing controller 216 can set the first operation mode setting information to a high level.

[0074] The second operation mode setting information indicates information for operating the source driver IC SDIC in a second low-power mode by disabling both the digital data processing unit 510 and the analog data processing unit 520 of the source driver ICSDIC during the touch sensing period TP. To operate the source driver IC SDIC in the second low-power mode, the timing controller 216 can set the second operation mode setting information to a high level.

[0075] Furthermore, the timing controller 216 can use timing signals input from an external host system to send control data CP for controlling the operating timing of the gating drive circuit 214 to the gating drive circuit 214. The control data CP for controlling the operating timing of the gating drive circuit 214 may include at least one of a gating start pulse GSP, a gating shift clock GSC, and a gating output enable signal GOE.

[0076] Simultaneously, the timing controller 216 can compress the external data enable signal sent from the external host system within a preset display period DP, thereby generating an internal data enable signal iDE. The timing controller 216 can generate a touch synchronization signal Tsync based on the timing of the vertical synchronization signal Vsync and the internal data enable signal iDE, used to divide a frame period into a display period DP and a touch sensing period TP. The timing controller 216 can send the touch synchronization signal Tsync to the data driving circuit 212, the gating driving circuit 214, the touch driving circuit 218, and the touch controller 220.

[0077] When the internal data enable signal iDE is generated, the timing controller 216 generates CEDS packets in the form of differential signals CEDA and CEDB, in which the clock is embedded between each data, and sends the CEDS packets to the source driver ICSDIC.

[0078] Specifically, during the display period DP, the timing controller 216 sends the clock synchronization signal LOCK#0 and clock training data CT to the source driver ICSDIC according to the CEDS interface protocol. When a high-level LOCK signal LOCK#i is received from the last source driver IC SDIC#i in the source driver IC SDIC, the timing controller 216 sends CEDS packets to the source driver IC SDIC in the order of control data CP and digital image data RGB. In this case, as shown... Figure 4 As shown, after the LOCK settling time Tlock, the LOCK signal is inverted to a high level. The LOCK settling time Tlock is the time elapsed from the start of sending the clock training data CT to the source driver IC SDIC until the output of the recovery circuit 514 of the source driver IC SDIC is stably fixed.

[0079] On the other hand, when a low-level LOCK signal LOCK#i is received from the last source driver IC SDIC#i, the timing controller 216 sends clock training data to the source driver IC SDIC again to continue the clock training of the source driver IC SDIC.

[0080] In one implementation, when the source driver IC SDIC operates in a first low-power mode or a second low-power mode during the touch sensing period TP, the timing controller 216 may not send CEDS packets to the source driver ICSDIC. Therefore, the timing controller 216 is able to reduce the power consumption required to send CEDS packets during the touch sensing period TP.

[0081] Specifically, when the source driver IC SDIC operates in a first low-power mode or a second low-power mode, the timing controller 216 can apply a first voltage V used to generate clock training data. CEDN Second voltage V CEDP Setting them to the same level, thus setting the input of the source driver IC SDIC to a high-impedance Hi-Z state or allowing the clock training data to always be held at a predetermined level, thereby preventing toggling and preventing the transmission of clock training data.

[0082] Meanwhile, when the source driver IC SDIC should be driven in a second low-power mode during the touch sensing period TP, the timing controller 216 according to this disclosure can monitor whether the source driver IC SDIC is operating in the second low-power mode based on the level of the LOCK signal sent from the source driver IC SDIC.

[0083] Specifically, such as Figure 6B As shown, when the source driver IC SDIC operates in the second low-power mode during the touch sensing period TP, the phase and frequency of the clock may be unstable because the digital data processing unit 510 is disabled, resulting in a low-level LOCK signal output. Therefore, during the touch sensing period TP, when the level of the LOCK signal sent from the source driver IC SDIC is low, the timing controller 216 determines that the source driver IC SDIC is operating in the second low-power mode. However, during the touch sensing period TP, when the level of the LOCK signal sent from the source driver IC SDIC is high, the timing controller 216 may determine that the source driver IC SDIC is not operating in the second low-power mode, and set the second operation mode setting information to be included in the control data CP of the CEDS group in the next display period DP to a high level again, or request the second low-power mode to be set by the touch controller 220 described below.

[0084] The host system converts the digital image data RGB into a format suitable for display on the display panel 205. The host system sends timing signals along with the digital image data RGB to the timing controller 216. The host system can be implemented as any of a television system, set-top box, navigation system, digital multi-disc (DVD) player, Blu-ray player, personal computer (PC), home theater system, and telephone system, and receives input images.

[0085] At the same time, the host system can receive touch input coordinates from the touch controller 220 and execute applications related to the received touch input coordinates.

[0086] The touch driving circuit 218 drives the touch sensor TE during the touch sensing period TP to acquire touch sensing data from the touch sensor TE. For this purpose, the touch driving circuit 218 may include multiple readout ICs ROICs.

[0087] In one embodiment, when the display panel 205 is implemented as a mutual capacitance type display panel, the readout IC ROIC may include: a driving circuit for generating a touch driving signal for driving the touch sensor TE, so as to provide the touch driving signal to the touch sensor TE through touch lines T1 to Tk; and a sensing circuit for detecting the change in capacitance of the touch sensor TE through touch lines T1 to Tk, so as to generate a touch sensing signal (touch raw data).

[0088] In another example, when the display panel 205 is implemented as a self-capacitance display panel, the readout IC ROIC can provide a touch drive signal to the touch sensor TE and obtain a touch sensing signal from the touch sensor TE by using a single circuit.

[0089] Simultaneously, the readout IC ROIC provides a common voltage Vcom to the touch sensor TE via touch lines T1 to Tk during the display period DP. Therefore, the touch sensor TE serves as the common electrode during the display period DP.

[0090] Furthermore, although the source driver IC SDIC and the readout IC ROIC have been shown as separate components in the above embodiments, in another embodiment, the source driver IC SDIC and the readout IC ROIC can be implemented as integrated on a single chip SRIC.

[0091] The touch controller 220 can use a preset touch recognition algorithm to analyze the touch sensing data received from the readout IC ROIC, identify touch sensing data with a voltage greater than or equal to a predetermined threshold as touch input data, and calculate the coordinates of the touch input position. The coordinates of the touch input position output from the touch controller 220 are then sent to the host system.

[0092] In the above embodiment, the timing controller 216 has been described as sending second operating mode setting information to the source driver IC SDIC for setting a second low-power mode of the source driver IC SDIC. In a variant embodiment, the touch controller 220 may send second operating mode setting information to the source driver IC SDIC for setting a second low-power mode of the source driver IC SDIC.

[0093] According to this implementation, the second operation mode setting information can be included in the read IC control data used to control the read IC ROIC. The touch controller 220 can send the read IC control data including the second operation mode setting information to the read IC ROIC, and the read IC ROIC can obtain the second operation mode setting information from the read IC control data, thereby sending the obtained second operation mode setting information to the source driver IC SDIC.

[0094] Specifically, the touch controller 220 communicates with the readout IC ROIC using the Serial Peripheral Interface (SPI) protocol. When sending control data to the readout IC, the touch controller 220 operates as the master device, and the readout IC ROIC operates as the slave device. In this scenario, as follows... Figure 7 As shown, the touch controller 220 can send addresses A15 to A0, command R / W, multiple virtual data lines DM15 to DM0, and multiple second operation mode setting information lines D0 to D15 via the master output slave input (MOSI) lines. In this case, when the source driver IC SDIC should operate in the second low-power mode, the multiple second operation mode setting information lines D0 to D15 can be set to a high level, and when the source driver IC SDIC should operate in the normal mode, the multiple second operation mode setting information lines D0 to D15 can be set to a low level.

[0095] Furthermore, as described above, although the timing controller 216 sends the second operating mode setting information to the source driver IC SDIC, when the feedback LOCK signal is high, the timing controller 216 can determine that the source driver IC SDIC is not operating in the second low-power mode, and then request the touch controller 220 to set the source driver IC SDIC to the second low-power mode. Based on this request, the touch controller 220 can send read IC control data, including the second operating mode setting information, to the read IC ROIC for controlling the read IC ROIC.

[0096] Meanwhile, in the above embodiments, the source driver IC SDIC has been described as operating only in a first low-power mode or a second low-power mode during the touch sensing period TP.

[0097] However, in another embodiment, the source driver IC SDIC can operate in a first low-power mode even during the display period DP. Specifically, when displaying still images on multiple frames or changing the frame rate of image data from a first frame rate to a second frame rate lower than the first frame rate, the source driver IC SDIC can operate in the first low-power mode during the display period DP.

[0098] According to this embodiment, during the display period DP, the timing controller 216 sets the third operation mode setting information for operating the source driver IC SDIC in a first low-power mode to a high level, includes the third operation mode setting information in the control data CP of the CEDS packet, and then sends the CEDS packet. When the third operation mode setting information is included in the control data CP of the CEDS packet received from the timing controller 216 and is set to a high level, the source driver IC SDIC disables the analog data processing unit 520 during the display period DP, thereby operating in the first low-power mode.

[0099] In the above embodiments, it has been described that when the touch synchronization signal Tsync changes to a high level while operating in a first low-power mode or a second low-power mode, the source driver IC SDIC is woken up to operate in normal mode. However, in another embodiment, the timing controller 216 may generate a wake-up control signal for waking up the source driver IC SDIC separately, and the source driver IC SDIC may additionally include a separate input pin for receiving the wake-up control signal from the timing controller 216, through which the wake-up control signal is received from the timing controller 216.

[0100] In this embodiment, the source driver IC SDIC receives the wake-up control signal from the timing controller 216 via a separate input pin because when the source driver IC SDIC operates in the second low-power mode, it does not perform clock training during the touch sensing period TP, inevitably requiring a predetermined time until image data output even when the display period DP begins. Therefore, when the wake-up control signal is received via a separate input pin, the source driver IC SDIC can be woken up to change from the second low-power mode to the normal mode, even during the touch sensing period TP, thereby activating the digital data processing unit 510 and resuming clock training to process image data simultaneously with the start of the display period DP.

[0101] In the following text, reference will be made to Figure 8 This disclosure describes a display driving method.

[0102] Figure 8This is a flowchart illustrating a display driving method according to one embodiment of the present disclosure. Figure 8 The display driving method shown can be derived from... Figure 2 The source driver IC SDIC of the display driver device shown is used to perform the operation.

[0103] First, during the display period DP within a frame cycle, the source driver IC SDIC operates in normal mode to receive CEDS packets (S800) including clock training data from the timing controller. In one embodiment, the source driver IC SDIC can identify the display period DP when the touch synchronization signal Tsync received from the timing controller is high.

[0104] The source driver IC SDIC uses clock training data to recover the clock to fix the frequency and phase (S810), and when the clock recovery is complete, the source driver IC SDIC receives CEDS packets including control data and digital image data from the timing controller (S820). The source driver IC SDIC recovers the control data and digital image data from the CEDS packets based on the clock recovered in operation S810 (S830). In one embodiment, the control data includes at least one of a polarity control signal POL, a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, and first operating mode setting information and second operating mode setting information for setting the operating mode of the source driver ICSDIC.

[0105] In this case, the first operation mode setting information indicates information for operating the source driver IC SDIC in a first low-power mode by disabling the analog data processing unit of the source driver IC SDIC during the touch sensing period TP, and the second operation mode setting information indicates information for operating the source driver ICSDIC in a second low-power mode by disabling the digital data processing unit and the analog data processing unit of the source driver ICSDIC during the touch sensing period TP.

[0106] When the recovery of control data and digital image data is completed, the source driver IC activates the digital data processing unit and the analog data processing unit. Based on the polarity control signal POL, the source start pulse SSP, the source sampling clock SSC and the source output enable signal SOE obtained in operation S820, the digital image data is converted into an analog data signal and the analog data signal is output to the display panel (S840).

[0107] During the touch sensing period TP after the display period DP ends, when the first operation mode setting information acquired in operation S820 is set to a high level or the second operation mode setting information is set to a high level, the source driver ICSDIC disables at least one of the digital data processing unit and the analog data processing unit, thereby operating in a first low power mode or a second low power mode (S850).

[0108] Specifically, when the first operating mode setting information is obtained at a high level in the S820, the source driver ICSDIC disables the analog data processing unit and thus operates in the first low-power mode.

[0109] Alternatively, when a high-level second operating mode setting information is obtained in operation S820, the source driver ICSDIC disables both the analog data processing unit and the digital data processing unit, thereby operating in a second low-power mode.

[0110] Subsequently, while operating in either the first low-power mode or the second low-power mode, the source driver IC SDIC monitors whether the touch synchronization signal Tsync sent from the timing controller changes to a high level (S860). When the touch synchronization signal Tsync changes to a high level, the source driver IC SDIC determines that the display period DP has arrived and is woken up (S870), and then returns to operation S800 to repeat the process of operating in normal mode. Otherwise, when the touch synchronization signal Tsync remains low in operation S860, the first low-power mode or the second low-power mode is maintained according to operation S850.

[0111] In the above embodiments, although the source driver IC (SDIC) has been described as being woken up using the touch synchronization signal Tsync while operating in a first low-power mode or a second low-power mode, in another embodiment, the source driver IC SDIC can be woken up to operate in normal mode when a separate wake-up control signal is received from the timing controller. According to the above embodiments, the source driver IC may additionally include a separate input pin for receiving the separate wake-up control signal.

[0112] In this embodiment, the source driver IC SDIC receives the wake-up control signal from the timing controller via a separate input pin because when the source driver IC SDIC operates in the second low-power mode, the source driver IC IC does not perform clock training during the touch sensing period TP. Therefore, even when the display period DP begins, a predetermined time is inevitably required until the image data is output. Thus, when the wake-up control signal is received via a separate input pin, the source driver IC SDIC can be woken up even during the touch sensing period TP to change from the second low-power mode to the normal mode, thereby activating the digital data processing unit and resuming clock training to process image data simultaneously with the start of the display period DP.

[0113] Meanwhile, in the above embodiments, although the source driver IC SDIC is described as receiving both first low-power mode setting information and second low-power mode setting information from the timing controller, in another embodiment, the source driver IC SDIC can receive the first low-power mode setting information from the timing controller and the second low-power mode setting information from the touch controller.

[0114] According to this embodiment, the second operation mode setting information can be included in the read IC control data used to control the read IC ROIC. The touch controller can send the read IC control data including the second operation mode setting information to the read IC ROIC, and the read IC ROIC can obtain the second operation mode setting information from the read IC control data, thereby sending the obtained second operation mode setting information to the source driver IC SDIC.

[0115] Specifically, the touch controller can send the second operating mode setting information to the readout IC ROIC via the MOSI line according to the SPI protocol, and the readout IC ROIC will send the received second operating mode setting information to the source driver ICSDIC. In this case, when the source driver IC SDIC should operate in the second low-power mode, the second operating mode setting information can be set to a high level, and when the source driver IC SDIC should operate in normal mode, the second operating mode setting information can be set to a low level.

[0116] In another embodiment, although the timing controller sends the second operating mode setting information to the source driver IC SDIC, when the LOCK signal fed back from the source driver IC SDIC is at a high level, the timing controller can determine that the source driver IC SDIC is not operating in the second low-power mode, and then request the touch controller to set the source driver IC SDIC to the second low-power mode. Based on the above request, the touch controller can send read IC control data, including the second operating mode setting information, to the read IC ROIC for controlling the read IC ROIC.

[0117] Meanwhile, in the above embodiments, the source driver IC SDIC has been described as operating only in a first low-power mode or a second low-power mode during the touch sensing period TP.

[0118] However, in another embodiment, the source driver IC SDIC can operate in a first low-power mode even during the display period DP. Specifically, when the frame rate for displaying still images or image data on multiple frames changes from a first frame rate to a second frame rate lower than the first frame rate, the source driver IC SDIC can operate in the first low-power mode during the display period DP.

[0119] According to this embodiment, during the display period DP, the timing controller sets the third operation mode setting information for operating the source driver IC SDIC in a first low-power mode to a high level, includes the third operation mode setting information in the control data CP of the CEDS packet, and then sends the CEDS packet. When the third operation mode setting information is included in the control data CP of the CEDS packet received from the timing controller and is set to a high level, the source driver ICSDIC disables the analog data processing unit 520 during the display period DP, thereby operating in the first low-power mode.

[0120] According to this disclosure, during the touch sensing period, since the source driver IC can operate in a first low-power mode that disables the analog data processing unit, or in a second low-power mode that disables both the digital data processing unit and the analog data processing unit, the consumption of static and dynamic current generated in the source driver IC during the touch sensing period can be prevented, thereby reducing the power consumption of the source driver IC.

[0121] Furthermore, according to this disclosure, even during a display period, when displaying a still image or when the frame rate of the second frame is lower than that of the first frame, the source driver IC can operate in a first low-power mode, thereby reducing the power consumption of the source driver IC even during a display period.

[0122] Furthermore, according to this disclosure, since the timing controller cannot send clock training data during the touch sensing period, the source driver IC cannot receive clock training data during the touch sensing period even when operating in the first low-power mode, thereby maximizing the reduction of power consumption of the source driver IC.

[0123] Cross-reference to related applications

[0124] This application claims the benefit of Korean Patent Application No. 10-2020-0084693, filed on July 9, 2020, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A display driving device, the display driving device comprising: The source driver integrated circuit IC is configured to operate in a first low-power mode that disables the analog data processing circuitry or in a second low-power mode that disables both the analog data processing circuitry and the digital data processing circuitry during the touch sensing period of the first frame. A readout IC configured to provide a touch sensor drive signal to the touch sensor during the touch sensing period and to receive touch sensing data from the touch sensor based on the touch sensor drive signal; as well as A timing controller is configured to generate Clock Embedded Data Signaling (CEDS) packets, comprising clock training data, control data, and image data, during the display period of the first frame, and to send the CEDS packets to the source driver IC. Wherein, when the source driver IC operates in the first low-power mode or the second low-power mode during the touch sensing period, the timing controller will be used to generate the first voltage (V) of the clock training data. CEDN ) and second voltage (V CEDP The source driver IC is set to the same level to control the source driver IC to become a high-impedance Hi-Z state, or the clock training data is kept at a predetermined level to prevent the clock training data from being sent.

2. The display driving device according to claim 1, wherein, During the display period of the first frame, the source driver IC operates in normal mode, activating the digital data processing circuit and the analog data processing circuit, thereby outputting image data to the display panel. During the display period, the source driver IC receives the CEDS packets from the timing controller and outputs the image data to the display panel according to the clock recovered based on the clock training data.

3. The display driving device according to claim 1, wherein, The control data includes first operating mode setting information for setting the first low-power mode or second operating mode setting information for setting the second low-power mode. Specifically, when the first operation mode setting information is at a high level, the source driver IC disables the analog data processing circuit, thereby operating in the first low-power mode.

4. The display driving device according to claim 1, wherein, The control data includes first operating mode setting information for setting the first low-power mode or second operating mode setting information for setting the second low-power mode. When the second operation mode setting information is at a high level, the source driver IC disables the analog data processing circuit and the digital data processing circuit, thereby operating in the second low-power mode.

5. The display driving device according to claim 1, wherein, The readout IC obtains second operation mode setting information from the readout IC control data for setting the operation mode of the source driver IC during the touch sensing period, and sends the second operation mode setting information to the source driver IC. The readout IC control data is sent from the touch controller during the display period to control the operation of the readout IC. When the second operation mode setting information sent from the readout IC is at a high level, the source driver IC operates in the second low-power mode.

6. A display device, the display device comprising: The source driver integrated circuit IC is configured to operate in at least one low-power mode during a touch sensing period of a frame; A readout IC configured to provide a touch sensor drive signal to the touch sensor during the touch sensing period and to receive touch sensing data from the touch sensor based on the touch sensor drive signal; as well as A timing controller is configured to generate control data, image data, and data for synchronizing a clock between the timing controller and the source driver IC during the display period of the frame, and to send the synchronization data, the control data, and the image data to the source driver IC. Wherein, when the source driver IC operates in the at least one low-power mode during the touch sensing period, the timing controller is further configured to: Prevent the transmission of the data used for synchronization. The first voltage (V) used to generate the data for synchronization will be used. CEDN ) and second voltage (V CEDP ) set to the same level, and The source driver IC is controlled to become a high-impedance Hi-Z state, or the data used for synchronization is controlled to remain at a predetermined level.

7. The display device according to claim 6, wherein, The at least one low-power mode includes a first low-power mode that disables analog data processing circuitry during the touch sensing period of the first frame.

8. The display device according to claim 7, wherein, The at least one low-power mode includes a second low-power mode that disables both the analog data processing circuitry and the digital data processing circuitry during the touch sensing period of the first frame.

9. The display device according to claim 6, wherein, The frame includes at least one touch sensing period and at least one display period.

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