Method and apparatus for erasing non-volatile memory

Abstract

Embodiments according to the present disclosure relate to methods and apparatus for erasing non-volatile memory. A method for erasing non-volatile memory includes applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation of the non-volatile memory cell and determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. The method also includes updating a dedicated memory location with a value and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase verify voltage to verify that the first erase operation has been successfully performed.

Description

Technical Field

[0001] The present invention relates to a method and apparatus for erasing non-volatile memory. Background Technology

[0002] Erasing operations on non-volatile memory cells can involve applying high voltage pulses to the non-volatile memory cells. As more erase operations are performed, the physical characteristics of the non-volatile memory cells may degrade over their lifetime. As a result, even higher voltage pulses may be required to successfully perform the erase operation. Furthermore, if the initial voltage pulse fails to perform the erase operation, multiple voltage pulses may be required for a given erase operation. Limiting the number of voltage pulses required to perform an erase operation can increase the speed and efficiency of non-volatile memory erase operations and devices. Summary of the Invention

[0003] According to one embodiment of the present invention, a method includes: applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation on the non-volatile memory cell; determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage; updating a dedicated memory location using the value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase verification voltage to verify that the first erase operation has been successfully performed.

[0004] According to one embodiment of the present invention, a non-volatile memory device includes a set of non-volatile memory cells. Each non-volatile memory cell in the set includes a control gate region and is configured to lose information stored in the non-volatile memory cell when a threshold voltage of the non-volatile memory cell is less than an erase verification voltage. The non-volatile memory device may further include a bias circuit configured to apply an erase voltage to each non-volatile memory cell in the set between the control gate region of the non-volatile memory cell and the body region of the non-volatile memory cell, and the bias circuit is configured to apply a control voltage to the control gate region of each non-volatile memory cell in the set. The non-volatile memory device may further include sensing circuitry configured to sense the conduction characteristics of each non-volatile memory cell in the non-volatile memory cell set, the conduction characteristics indicating whether the threshold voltage of the non-volatile memory cell is less than a control voltage applied to the control gate region of the non-volatile memory cell; and wherein the control circuitry communicates with the bias circuitry and the sensing circuitry and is configured to: retrieve a data value from a dedicated memory location corresponding to the non-volatile memory cell set; and perform an erase operation such that the threshold voltage of each non-volatile memory cell in the non-volatile memory cell set is less than... For the erase verification voltage: the control bias circuit sets the erase voltage to a value determined by the data value and applies the erase voltage to each non-volatile memory cell in the non-volatile memory cell set; the test operation is performed to determine whether the threshold voltage of each non-volatile memory cell in the non-volatile memory cell set is less than the test voltage by: the control bias circuit sets the control voltage value to the test voltage and applies the control voltage to each non-volatile memory cell in the non-volatile memory cell set; and the new data value determined by the result of the test operation is used to replace the data value in the dedicated memory location.

[0005] According to one embodiment of the present invention, a method includes: having a memory array comprising a plurality of nonvolatile memory cell sets, each nonvolatile memory cell set comprising a plurality of nonvolatile memory cells; applying a first voltage pulse to a selected nonvolatile memory cell set to perform a first erase operation on the selected nonvolatile memory cell set; determining that a threshold voltage of at least one nonvolatile memory cell in the selected nonvolatile memory cell set is greater than a test voltage; updating a dedicated memory location using the value; and checking at least one nonvolatile memory cell to determine whether the threshold voltage of the at least one nonvolatile memory cell is less than an erase verification voltage to verify that the first erase operation has been successfully performed. Attached Figure Description

[0006] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, wherein:

[0007] Figure 1 A schematic cross-sectional view of a floating-gate memory cell in a non-volatile flash memory device is shown.

[0008] Figure 2A A plot of the voltage applied to the memory cell during the erase operation is shown;

[0009] Figure 2B The diagram shows that the voltage required to perform the erase operation increases with the number of cycles.

[0010] Figure 3A A plot of the voltage pulses applied during the initial erase operation of a known method is shown;

[0011] Figure 3B A plot of the voltage pulses applied during a subsequent erase operation using a known method is shown;

[0012] Figure 4A The figure illustrates the distribution of threshold voltages of multiple memory cells in a memory cell set before and after a single pulse has been applied to a memory cell to perform an erase operation using a known method.

[0013] Figure 4B The figure illustrates the distribution of threshold voltages of multiple memory cells in a memory cell set before and after a single pulse of a subsequent erase operation using a known method.

[0014] Figure 4C The illustration shows the distribution of threshold voltages of multiple memory cells in the memory cell set before and after the second pulse of a subsequent erase operation using a known method that requires a second voltage pulse.

[0015] Figure 5A The illustration shows the distribution of threshold voltages of multiple memory cells in the memory cell set before and after a single pulse has been applied to the memory cell for the erase operation of the embodiment.

[0016] Figure 5B The illustration shows the distribution of threshold voltages of multiple memory cells in the memory cell set before and after a single pulse of the subsequent erase operation in the embodiment.

[0017] Figure 5C The illustration shows the distribution of threshold voltages of multiple memory cells in the memory cell set before and after a single pulse has been applied to the memory cell for subsequent erase operations in the embodiment.

[0018] Figure 6AThe timeline of the erase operation using known methods is depicted after a successful single-pulse operation;

[0019] Figure 6B The timeline of an erase operation using known methods that requires more than one voltage pulse is depicted;

[0020] Figure 7A A timeline of the erase operation following a successful single-pulse operation, according to an embodiment, is depicted;

[0021] Figure 7B A timeline of erase operations according to an embodiment and updates of erase voltage for future erase operations are depicted;

[0022] Figure 8 A schematic diagram of a non-volatile memory device according to an embodiment is depicted;

[0023] Figure 9 An embodiment of a dedicated memory location is depicted;

[0024] Figure 10A It depicts the 16-bit data values ​​in the initial configuration;

[0025] Figure 10B The 16-bit data value in the added configuration is depicted;

[0026] Figure 10C The 16-bit data value in the added configuration is depicted;

[0027] Figure 11 A flowchart depicting the method of the embodiment is shown; and

[0028] Figure 12 A flowchart illustrating the method of an embodiment is provided. Detailed Implementation

[0029] Figure 1 A schematic cross-sectional view of a floating-gate memory cell in a non-volatile flash memory device is shown.

[0030] As is well known, and as Figure 1As schematically shown, a floating-gate type memory cell 1 of a non-volatile memory device (e.g., a flash memory type non-volatile memory device) may include: a body region 2 having p-type doping, provided in a substrate 3 of a semiconductor material such as silicon. The memory cell 1 may also include: a source region 4 and a drain region 5 having n-type doping, provided within a surface portion of the body region 2; a floating gate region 6 disposed above the body region 2 and separated from the body region 2 by a tunnel oxide region 7; and a control gate region 8 disposed above the floating gate region 6 and separated from the gate region 6 by an intermediate oxide (so-called "ONO") region 9.

[0031] For storing information, charge is injected from substrate 3 into floating gate region 6 (programming operation), thereby changing the threshold of memory cell 1, that is, applying a voltage between control gate region 8 and source region 4 to turn on memory cell 1 and obtain current conduction between source region 4 and drain region 5.

[0032] For sensing operations, when an appropriate bias voltage is applied to the control gate region 8, the sensing circuit detects the conduction characteristics of the memory cell 1, from which the stored information can be obtained.

[0033] The erasure operation for erasing information is expected to remove the charge stored in the floating gate region 6 via electronic extraction. Specifically, this operation is expected to (e.g., Figure 1 As shown, a high electric field is applied between the body region 2, which is subjected to a positive high voltage (e.g., +10V), and the control gate region 8, which is subjected to a negative high voltage (e.g., -10V). In a known manner, the generated high electric field causes the Fowler-Nordheim (“FN”) tunneling effect to be triggered, which causes electrons to migrate from the floating gate region 6 through the tunnel oxide region 7 (again, as shown). Figure 1 (Illustrative illustration).

[0034] In particular, in a known manner, erase operations can be performed simultaneously on a set of memory cells 1, which, for example, belong to the same block, sector, or page of a non-volatile memory device, and these cells are thus erased together in the same erase operation.

[0035] The erasure process can take effect when the applied electric field is strong enough to trigger the FN tunneling effect.

[0036] However, due to the natural degradation process of memory cell 1 (e.g., due to charge trapping in tunnel oxide region 7), this value increases with the increase of the so-called "cycle" (i.e., the number of programming / erase cycles that memory cell 1 undergoes).

[0037] To account for this degradation phenomenon, a method typically used to perform an erase operation on a set of memory cells (sectors or pages) is to iteratively apply a certain number of pulses with increasing voltage values ​​and fixed durations, each pulse followed by a verification operation to verify whether the erase was successful. Once the verification operation determines that the erase has been performed correctly, the method is interrupted.

[0038] Figure 2A A plot of the voltage applied to the memory cell during the erase operation is shown.

[0039] This method is in Figure 2A The middle is shown schematically. Figure 2A A plot of pulses with increasing values ​​for the body voltage Vpp is shown, where the control gate region 8 is negatively selected (i.e., set to a high negative voltage VCG, such as -10V). As previously described, the potential difference between body region 2 and control gate region 8 determines the electric field designed to trigger the FN tunneling effect.

[0040] The pulses of the body voltage Vpp begin with a minimum value Vpp_min, determined during the design or characterization phase of the non-volatile memory device, and gradually increase in equal increments until reaching a maximum value Vpp_max, which is also determined during the design or characterization of the memory device. Between consecutive pulses, the method anticipates a verification step, verifying whether the erase has been successful through a read or sensing operation.

[0041] If the verification does not produce a positive result, subsequent pulses are applied iteratively with incrementing values; otherwise, when it is verified that erasure has been successful (i.e., when it is verified that the electric field value required to activate the FN tunneling effect has been reached or exceeded), as if again... Figure 2A (As shown in the image), the process ends.

[0042] The envelopes of all applied pulses (represented by dashed lines) can determine the slope used to perform the erase operation (i.e., the temporal variation of the electric field applied to memory cell 1), and the rate at which the electric field reaches and / or surpasses the value required to activate the FN tunneling effect. A high slope can put stress on memory cell 1 and accelerate memory cell degradation; therefore, the slope affects the duration of the erase operation and the long-term performance of the memory cell.

[0043] As the number of programming / erasing cycles performed on memory cell 1 increases, the value of the electric field required to activate the FN tunneling effect also increases, thus increasing the number of pulses required to effectively erase memory cell 1, resulting in an increase in the total duration of the erase operation.

[0044] Figure 2BThe diagram shows that the voltage required to perform the erase operation increases with the number of cycles.

[0045] like Figure 2B As illustrated in the diagram, the number of pulses required for the erase operation increases with the number of cycles. For example, as... Figure 2B As shown, the required number of pulses can be increased from one or two pulses required to erase a memory cell with fewer than 10Kc or 50Kc cycles to N-1 or N pulses (where N is equal to 10, for example) required to erase a memory cell with 450Kc or 500Kc cycles.

[0046] Because the various pulses have a constant duration Tpulse, the erase operation takes a short time for cells with low cycles, but becomes very long for cells with high cycles, potentially making it incompatible with certain applications of memory devices (such as those requiring high response rates, or in any case, a pre-set response time that is substantially constant in time). Therefore, reducing the number of pulses used to erase memory cell 1 allows for faster memory.

[0047] A known method for reducing the number of pulses includes: storing information associated with an operation configuration that allows a past memory operation to complete successfully, and using the information to restore the corresponding operation configuration as the starting point for a subsequent memory operation.

[0048] Figure 3A A plot of the voltage pulses applied during the initial erase operation of a known method is shown.

[0049] Figure 3A The known method shown includes: increasing the value of the pulse until the level of the actual pulse of the body voltage Vpp reaches or exceeds the threshold for triggering the FN tunneling effect; and recording information about the configuration that triggered the FN tunneling effect. This information is accessed at the start of a subsequent erase procedure, so that the first pulse of the subsequent erase procedure can be equal to the last pulse from the previous erase operation, which was sufficient to trigger the FN tunneling effect in the previous loop.

[0050] Consistent with this known method, in Figure 3AIn the example shown, a successful erase procedure requires three pulses. An erase verification performed between the first and second pulses does not show that a valid erase operation has been successfully performed. Therefore, an additional voltage pulse at an increased voltage level is executed. Verification performed after the third pulse determines that memory cell 1 of the desired set (e.g., page or sector) has been successfully erased, and that the pulse voltage level is large enough to trigger the FN tunneling effect. Information associated with the actual bias configuration (e.g., the actual level or digital representation of the body voltage Vpp) is then stored for subsequent erase procedures.

[0051] Figure 3B A plot of the voltage pulses applied during a subsequent erase operation using a known method is shown.

[0052] Subsequent erase operations can be performed on the same set of memory cells 1. Previously stored information about the previous bias configuration is used to determine the bias configuration for the first step of the iterative process of the subsequent erase operations based on the retrieved information. Figure 3B In the example, the level of the first pulse of the body voltage Vpp is the stored value (for which the previous erase operation was successful). This first pulse is unsuccessful in the new erase operation, so a second pulse needs to be applied to successfully perform the erase operation (the level of this second pulse will be stored by the control circuit 14 for future memory operations).

[0053] This method can prevent some unwanted pulses. However, it may be desirable to further reduce the number of pulses.

[0054] Figure 4A The figure illustrates the distribution of threshold voltages of multiple memory cells in the memory cell set before and after a single pulse has been applied to memory cell 1 to perform an erase operation using a known method.

[0055] Figure 4A Two curves are plotted to represent the distribution of threshold voltages for multiple memory cells 1. The first curve 402A represents the distribution of threshold voltages before a single pulse of the erase operation has been executed. The second curve 404A represents the distribution of threshold voltages after a single pulse of the erase operation has been executed. To determine whether the erase operation has been successfully executed, the distribution of threshold voltages for the multiple memory cells 1 is compared with an erase verification voltage 406 after the single pulse is applied.

[0056] The first curve 402A is greater than the erase verification voltage 406. A single voltage pulse of the erase operation shifts the distribution of the threshold voltage of memory cell 1 to the second curve 404A. The second curve 404A is less than the erase verification voltage 406, therefore the erase operation is successfully performed. No second pulse is needed. Furthermore, the pulse configuration of the erase operation is saved for subsequent erase operations. However, as more erase operations are performed, the distribution of the threshold voltage of memory cell 1 becomes less sensitive to voltage pulses at previously successful levels. The distribution of the threshold voltage of the memory cells shifts less and less. Eventually, the voltage level previously used to successfully execute the previous erase operation will not shift the distribution of the threshold voltage of memory cell 1 far enough to successfully execute the erase operation for subsequent erase operations. In this case, the voltage level must be increased, and a second pulse must be applied to complete the erase operation. The new voltage level is stored for future erase operations.

[0057] Figure 4B The illustration shows the distribution of threshold voltages of multiple memory cells in a memory cell set before and after a single pulse of a subsequent erase operation using a known method.

[0058] The first curve 402B represents the distribution of the threshold voltage of memory cell 1 before the single voltage pulse of the subsequent erase operation. Again, before the erase operation, the first curve 402B is greater than the erase verification voltage. However, in the previous... Figure 4A The application of the voltage pulse at the level depicted in the erase operation no longer shifts the distribution of the threshold voltage of memory cell 1 far enough to clear the erase verification voltage 406. Now, the voltage pulse at the previous level only shifts the distribution of the threshold voltage of memory cell 1 from the first curve 402B to the second curve 404B. Only a portion of the second curve 404B is smaller than the erase verification voltage 406. Therefore, the first voltage pulse fails to successfully perform the erase operation.

[0059] Figure 4C The illustration shows the distribution of threshold voltages of multiple memory cells in a memory cell set before and after the second pulse of a subsequent erase operation using a known method that requires a second voltage pulse.

[0060] The erasure operation is now performed using a second voltage pulse at the increased voltage level. Figure 4C The distribution of the threshold voltage of memory cell 1 after the second pulse is illustrated using the third curve 408B. After the second pulse, the distribution of the threshold voltage of the memory cell has shifted from the second curve 404B to the third curve 408B, which is completely below the erase verification voltage 406.

[0061] Eliminating the need for a second voltage pulse (as shown in Figure C) during some or all erase operations can help reduce power consumption, increase the speed of the erase operation, and make the duration of the erase operation more predictable. These benefits can be advantageously applied to a number of applications, including but not limited to memory devices in devices with high safety levels (in telecommunications, pay television, field banking, etc.), memory devices in microcontrollers (for home applications, for radio frequency applications, for display devices), or memory devices in the automotive field in general.

[0062] In various embodiments, unnecessary voltage pulses can be avoided by predicting when a voltage pulse at a given level will not be sufficient to move the distribution of the threshold voltage of memory cell 1 to perform an erase operation. When it is predicted that a given voltage level will soon fail, the voltage can be increased in advance before performing the erase operation to avoid the need for a second pulse.

[0063] Figure 5A The illustration shows the distribution of threshold voltages of multiple memory cells in the memory cell set before and after a single pulse has been applied to memory cell 1 for the erase operation of the embodiment.

[0064] and Figure 4A Same, Figure 5A Two curves are plotted, representing the distribution of threshold voltages of multiple memory cells 1 before and after a single pulse of the erase operation performed on memory cell 1. The first curve 502A represents the distribution of threshold voltages before the single pulse of the erase operation. And the second curve 504A represents the distribution of threshold voltages after the single pulse of the erase operation has been applied. In various embodiments, the distribution of threshold voltages of the multiple memory cells 1 can be compared with a test voltage 505. Figure 5A As shown, the test voltage 505 can be less than the erase verification voltage. This allows for a comparison between the test voltage and the threshold voltage of the memory cell to predict failure before it occurs.

[0065] After a single pulse of the erase operation is applied, the voltage threshold distribution of memory cell 1 shifts from the first curve 502A to the second curve 504A. The second curve 504A is lower than the test voltage 505 and the erase verification voltage, indicating that the erase operation was successfully performed and the voltage level of the successful voltage pulse can be maintained for subsequent erase operations.

[0066] Figure 5B The illustration shows the distribution of threshold voltages of multiple memory cells in the memory cell set before and after a single pulse of the subsequent erase operation in the embodiment.

[0067] exist Figure 5B In the diagram, the first curve 502B again represents the distribution of the threshold voltage of memory cell 1 before a single voltage pulse in a subsequent erase operation. Before the erase operation, the first curve 502B is greater than both the erase verification voltage 406 and the test voltage 505. After a voltage pulse is applied at the level where a previous erase operation was successfully performed, the distribution of the threshold voltage of the memory cell can shift from the first curve 502B to the second curve 504B. Although the second curve 504B still clears the erase verification voltage 406, the effectiveness of the voltage pulse at the previous level may be weakened, so the distribution of the threshold voltage of memory cell 1 may not shift as far as before. Furthermore, even if the erase verification voltage is cleared, the shift in the distribution of the threshold voltage of memory cell 1 may not clear the test voltage 505. By comparing the threshold voltage of the memory cell with the test voltage, the failure of the voltage pulse to clear the test voltage 505 can predict future failures to clear the erase verification voltage during future erase operations. Furthermore, if the applied erase voltage fails to shift the threshold voltage distribution of memory cell 1 away from the test voltage 505, the voltage pulse level can be increased—even if the erase memory operation is successful. This can predict future failures and avoid a second pulse during future erase operations.

[0068] Figure 5C The illustration shows the distribution of threshold voltages of multiple memory cells in the memory cell set before and after a single pulse has been applied to memory cell 1 for subsequent erase operations in the embodiment.

[0069] The increased voltage level can change the distribution of the threshold voltage of the memory cell from the first curve 502C (e.g.) Figure 5C (As shown in the diagram) Move to the second curve 504C. The second curve clears the erase verification voltage 406, thereby avoiding a second pulse that might be needed without increasing the voltage pulse level applied during the erase operation.

[0070] Figure 6A The timeline of the erase operation using known methods following a successful single-pulse operation is depicted.

[0071] exist Figure 6A In this process, a first voltage pulse 602A is applied to the set of memory cells 1 to which an erase operation is performed. After the first voltage pulse 602A is applied, at 604A, the threshold voltage of memory cell 1 is compared with the erase verification voltage. The comparison at 604A is solid to indicate a successful erase operation. In this case, it means that the distributed threshold voltage of memory cell 1 has been moved to be less than the erase verification voltage. As a result, a second pulse is not needed, and there is no need to save new data about the voltage pulse level.

[0072] Figure 6B The timeline of an erase operation using a known method that requires more than one voltage pulse is depicted.

[0073] exist Figure 6B In the process, a first voltage pulse 602B is applied to the set of memory cells 1 to which an erase operation is performed. After applying the first voltage pulse 602B, at 604B, the threshold voltage of memory cell 1 is compared with the erase verification voltage. This time, the comparison at 604B indicates that the erase operation was unsuccessful, which is represented by an unfilled box. The voltage pulse does not shift the distribution of the threshold voltage of the memory cells away from the erase verification voltage. At 606B, a second voltage pulse at a higher level is applied. After applying the second pulse, at 608B, the threshold voltage of memory cell 1 is compared with the erase verification voltage again. This time, the comparison indicates that the erase operation was successful, so no additional pulse is needed. And at 610B, data for the level of the last successful voltage pulse is saved. Eliminating the second pulse 606B and the second comparison 608B can speed up the erase process.

[0074] Figure 7A A timeline of the erase operation following a successful single-pulse operation is depicted according to one embodiment.

[0075] exist Figure 7A In this embodiment, a first voltage pulse 702A can be applied to the set of memory cells 1 to which an erase operation can be performed. After applying the first voltage pulse 702A, at 704A, the threshold voltage of the memory cell 1 can be compared with a test voltage 703A and an erase verification voltage. This comparison can indicate that the erase operation was successful, which is represented by a solid box at 703A, so a second pulse may not be necessary. The comparison with the test voltage can indicate that the distribution of the threshold voltage of the memory cell 1 has been shifted sufficiently to clear the test voltage, so the level of the update voltage pulse may not be preferred. In various embodiments, if the comparison with the test voltage at 703A is successful, the comparison with the erase verification voltage at 704A can be skipped.

[0076] Figure 7B A timeline of erase operations according to an embodiment and updates of the erase voltage for future erase operations are depicted.

[0077] exist Figure 7BIn this process, a first voltage pulse 702B is applied to the set of memory cells 1 to which an erase operation can be performed. After applying the first voltage pulse 702B, at 704B, the threshold voltage of the set of memory cells 1 can be compared with a test voltage 703B and an erase verification voltage. The comparison with the erase verification voltage can indicate that the erase operation was successful—a filled box—so a second pulse may not be preferred. However, the comparison with the test voltage can indicate that the test operation may have failed—an empty box—so at 707A, the voltage pulse level for the next erase operation can be increased by saving the new voltage level to avoid a second pulse during future erase operations.

[0078] In various embodiments, the order of comparisons with the test voltage and the erase verification voltage after the voltage pulse is applied can be switched. For example, in some embodiments, a comparison can be made first between the erase verification voltage and the distribution of threshold voltages of the memory cells. And, secondly, a comparison can be made between the test voltage and the distribution of threshold voltages of the memory cells. In some embodiments, it may be preferred to compare the test voltage with the threshold voltage first to avoid the need for an erase verification comparison. In some cases, a comparison with the erase verification voltage can be performed only after a comparison with the test voltage fails. This can speed up some erase operations.

[0079] Figure 8 Schematic diagrams of a memory device 10 with various embodiments are depicted.

[0080] In various embodiments, memory device 10 may include a non-volatile memory device, such as flash memory or page flash memory. Memory device 10 may include a memory array 12 comprising a plurality of memory cells 1. Memory cells 1 may include floating gate type (e.g., as referenced). Figure 1 (As described). Memory cells 1 can be arranged by rows (word lines) and columns (bit lines) and operably combined by sets (e.g., sectors or pages). In different embodiments, the set may include a different number of memory cells 1. In various embodiments, each memory cell 1 in the set of memory cells may include a floating gate type. Memory cells 1 can be configured such that when the threshold voltage of a non-volatile memory cell is less than the erase verification voltage, the memory cell loses the information stored therein. This can be achieved by an erase operation that applies a voltage between the control region and the body region of the memory cell, as described in reference. Figure 1 As described.

[0081] Various memory operations of the memory device 10 can be performed simultaneously on all memory cells 1 of the set. For example, for all memory cells 1 belonging to set 12A (e.g., sector or page), an erase operation for erasing information stored in memory cells 1 can be performed simultaneously in the memory device 10.

[0082] The memory device 10 may also include control circuitry 14, which in various embodiments may include a microprocessor or a microcontroller. The control circuitry 14 is operatively associated with the memory array 12 and is designed to control the operation of the memory array, and in particular to control the execution of memory operations, which may include, for example, an erase operation.

[0083] The memory device 10 may further include a bias circuit 15, which communicates with and is controlled by the control circuit 14. The bias circuit 15 may provide an appropriate bias signal (e.g., the aforementioned pulse body voltage Vpp during an erase operation) to the memory cells 1 of the memory array 12 during memory operation. The bias circuit 15 may be configured to apply an erase voltage to the memory array 12 to perform an erase operation on a selected set of memory cells 1. A set 12A may be selected according to an instruction received from the control circuit, which determines which set should be erased. The erase voltage may be applied to more than one set of memory cells simultaneously. In various embodiments, the bias circuit may include a digital-to-analog converter (“DAC”) that receives a control signal DAC_IN from the control circuit.

[0084] The bias circuit can be configured to apply an erase voltage to each memory cell 1 in the memory cell set 12A between the control gate region 8 and the body region 2 of each memory cell 1 in the memory cell set 1, for performing an erase operation on the set 12A of memory cells 1. The erase voltage can be changed by varying the voltage applied to the control gate region 8, the body region 2, or both. The bias circuit 15 can be configured to apply a control voltage to the control gate region of each memory cell 1 in the memory cell set 12A to perform an erase verification operation or a test operation.

[0085] The memory device 10 may also include sensing circuitry 16, which also communicates with control circuitry 14, for detecting the conduction characteristics of memory cell 1 (e.g., for comparing a control voltage with a threshold voltage of memory cell 1 or a set of memory cells 1 during an erase verification operation, a test operation, or both). The sensing circuitry may include a sensing amplifier.

[0086] The conduction characteristics of memory cell 1 can indicate whether the threshold voltage of memory cell 1 is less than the control voltage applied to the control gate region 8 of memory cell 1. In various embodiments, the sensing circuit 16 may include a sensing amplifier that detects the current through a channel formed between the source region 4 and the drain region 5 of the memory cell when an appropriate voltage is applied to the control gate region 8. The region in memory cell 1 where the channel is formed is... Figure 1 The middle is represented by 17.

[0087] Memory device 10 may include a dedicated memory location 18, which is managed and communicates with control circuitry 14. Dedicated memory location 18 may include memory cells 1. In various embodiments, dedicated memory location 18 may not be accessible to the user of memory device 10 for memory operations. Configuration information of memory device 10—e.g., voltage levels for future erase operations on corresponding memory sets—may be stored in this dedicated memory location 18. In various embodiments, dedicated memory location 18 may be a portion of memory array 12 that is inaccessible to the user.

[0088] Figure 9 An embodiment of a dedicated memory location is depicted.

[0089] The control circuit 14 can be configured to retrieve data values ​​from dedicated memory location 18. For example... Figure 9 As schematically shown, dedicated memory location 18 may include a lookup table (LUT) having: a first field 18a “sector” containing a reference associated with a sector (or page, set, or other type of group) of memory cell 1; and a second field 18b “data value” in which the configuration used for the next memory operation is stored in association with the corresponding sector (e.g., the level of the body voltage Vpp used to perform the erase operation, or similarly, the digital value of the corresponding digital control signal DAC_IN delivered to the DAC of bias circuit 15).

[0090] In various embodiments, the data value stored in the second field 18B may include a variety of forms.

[0091] Figure 10A It depicts the 16-bit data values ​​in the initial configuration.

[0092] In various embodiments, the data value 1002 may be incremented and correspond to the value of the erase voltage used for the erase operation. In various embodiments, it may be preferred to vary the voltage applied to the control gate region 8 of the memory cell, the voltage applied to the body region 2 of the memory cell, or both, to change the erase voltage used for the erase operation. In some embodiments, a first segment 1002A including the three most significant bits depicted in FIG. 10 may determine the voltage value to be applied to the control gate region 8 of the memory cell 1 for the erase operation. A second segment 1002B including the 13 most significant bits depicted in FIG. 10 may correspond to the voltage value to be applied to the body region 2 of the memory cell 1 for the erase operation.

[0093] The initial setting of data value 1002 may correspond to the initial voltage level of the erase voltage used for the first erase operation at the start of the lifetime of memory device 10. The initial voltage level required to perform the first operation may be determined during the manufacture or testing of memory device 10. In various embodiments, the initial value of the data value may include all "1"s. However, it should be understood that the initial value may include any combination of desired digital values. Data value 1002 can be changed by varying the bits of data value 1002. This can also be based on changing the level of the erase voltage. The first segment 1002A, the second segment 1002B, or both may be changed to vary the level of the erase voltage.

[0094] Figure 10B The 16-bit data value in the added configuration is depicted.

[0095] The data value 1002 can be incremented by changing the value of one bit in the data value 1002. Figure 10B In the data value 1002, the least significant bit of the second segment 1002B has been switched from "1" to "0". This new configuration can correspond to an increased erase voltage level. Each possible value of the data value 1002 can correspond to an erase voltage level. In various embodiments, the bits of the data value 1002 can be changed only once, thus allowing multiple increments in the 16-bit data value, each corresponding to a different possible erase voltage value.

[0096] Figure 10C The 16-bit data value in the added configuration is depicted.

[0097] The least significant bit of segment 1002A in the first section has already been... Figure 10C The values ​​in the second segment 1002B have been increased. This corresponds to a change in the voltage value to be applied to the control gate region 8 of memory cell 1. The five least significant values ​​of the second segment 1002B have also been increased. Figure 10C The configuration of data value 1002 in the middle can correspond to the data from... Figure 10AThe data value 1002 is incremented six times starting from its initial value. However, it should be understood that the data value 1002 can be incremented in any desired manner. In various embodiments, the data value may include more or fewer bits, it may have more or fewer segments, and these segments may include different lengths.

[0098] return Figure 8 The control circuit 14 of the memory device can be configured to perform an erase operation after retrieving the data value 1002 from a dedicated memory location 18 corresponding to the set 12A of the memory array 12. Based on the data value 1002, the control circuit 14 can deliver a control signal to the bias circuit 15. In various embodiments, the control signal may include DAC_IN for the DAC used by the bias circuit. Then, under the guidance of the control circuit 14, the bias circuit 15 can apply an erase voltage to the memory cell 1 in the set 12A of the memory array selected for the erase operation.

[0099] The control circuit 14 can also be configured to perform a test operation to determine whether the distribution of threshold voltages of memory cells 1 in the selected set 12A of memory cells 1 is less than the test voltage 505. This can be achieved by the control bias circuit 15 applying a control voltage equal to the level of the test voltage 505 to the memory cells 1 in the set 12A of memory array 12. The sensing circuit 16 can detect the conduction characteristics of the memory cells 1 in the set 12A of memory array 12, which can be used to determine whether the distribution of threshold voltages of memory cells 1 is greater than or less than the test voltage 505. If it is determined that all, a predetermined number, or a percentage of the threshold voltages of the memory cells have moved sufficiently to clear the test voltage 505, it can be determined that set 12A has passed the test operation. If set 12A passes the test operation, the voltage level of the erase voltage does not need to be increased.

[0100] If assembly 12A fails the test operation, this indicates that the effectiveness of the erase voltage is diminishing. (See at least the reference...) Figure 5A , Figure 5B , Figure 5C , Figure 7A and Figure 7BThis allows memory device 10 to detect future failures and preemptively increase the level of the erase voltage for subsequent erase operations to avoid requiring more than one pulse to complete the erase operation. In various embodiments, when a test operation fails (i.e., in various embodiments, the threshold voltage does not move below test voltage 505), control circuitry 14 can be triggered to update a data value—in various embodiments, for example, by increasing the data value corresponding to the voltage level of the non-volatile memory cell set. In various embodiments, this can occur when the current detected by sensing circuitry 16 during the test operation is less than a reference current. This can indicate that test voltage 505 is not turning on the memory cell, which can mean that no channel for allowing current is formed between the source region 4 and drain region 5 of the memory cell. This can also indicate that the threshold voltage of the memory cell being tested is greater than test voltage 505.

[0101] After a test operation fails, various embodiments may delay the increase in the erase voltage level. For example, after set 12A fails a test operation, the control circuit may wait for two cycles before updating the data value and increasing the erase voltage. It should be understood that the delay length regarding the erase cycle may vary in different embodiments.

[0102] In various embodiments, control circuitry 14 can increase the level of the erase voltage for future erase operations by replacing the data value 1002 in dedicated memory location 18 with a new value. In some embodiments, this can be achieved by increasing the data value 1002, as referenced... Figure 10A , Figure 10B and Figure 10C As described. The new value can correspond to a higher level of the erase voltage, so if the update is delayed, the erase voltage will increase for the next erase operation or a future erase operation.

[0103] The control circuit can also be configured to perform an erase verification operation by controlling the bias circuit 14 to apply a control voltage at a level equal to the erase verification voltage 406 to the memory cells 1 of the memory array 12A. When the erase verification voltage 406 is applied, the sensing circuit 16 can detect the current characteristics of the memory cells 1 of the memory array 12A, which can be used to determine whether the threshold voltage of the memory cells 1 of the memory array 12A is greater than or less than the erase verification voltage. If the test fails, the voltage level can be increased, and a second pulse is applied to the memory cells 1 of the memory array 12A to complete the erase operation.

[0104] Finally, it is evident that modifications and variations can be made to the content described and shown herein without departing from the scope of the invention as defined by the appended claims.

[0105] It is also emphasized that the described solution can be generally applied to any memory operation that can be optimized based on knowledge of the configuration of previous memory operations performed on the same memory cell, and can be applied to any non-volatile memory device.

[0106] For example, in cases where programming operations require reduced parallelism (for reasons such as power consumption), the described solution can be applied to programming operations implemented in non-volatile memory devices, making the duration of the programming operations potentially comparable. Furthermore, it should be understood that the scope of this disclosure is not limited to a single type of memory cell. Various other memory cells, including other doping types, can be utilized in various embodiments. This may affect other configurations, such as the voltage required to form channels in the memory cell, and the positions of the erase verification voltage and test voltage relative to the threshold voltage. Another type of memory cell may have a test voltage greater than the erase verification position.

[0107] Figure 11 A method 1100 of one embodiment is described.

[0108] Method 1100 may include: at step 1102, applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation on the non-volatile memory cell; and at step 1104, determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage. Method 1100 may further include: at step 1106, updating a dedicated memory location using a value; and at step 1108, checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase verification voltage to verify that the first erase operation has been successfully performed.

[0109] In various embodiments, method 1100 may further include: confirming that the first erase operation has been successfully performed; and applying a second voltage pulse to the non-volatile memory cell to perform a second erase operation on the non-volatile memory cell, the second voltage pulse being based on a value of a dedicated memory location.

[0110] In various embodiments, method 1100 may include: wherein the value of the dedicated memory location includes operating parameters for generating a second voltage pulse.

[0111] In various embodiments, method 1100 may further include: wherein the non-volatile memory cell includes a floating gate memory cell, the floating gate memory cell including a body region and a control gate region, and wherein a first voltage pulse is applied between the control gate region and the body region.

[0112] In various embodiments, method 1100 may further include: wherein determining that a threshold voltage of a non-volatile memory cell is greater than a test voltage includes: applying a test voltage to a control gate region of the non-volatile memory cell and sensing current characteristics through the channel of the non-volatile memory cell.

[0113] In various embodiments, method 1100 may further include: determining that a threshold voltage of the non-volatile memory cell is greater than an erase verification voltage; and applying a second voltage pulse to the non-volatile memory cell to complete a first erase operation of the non-volatile memory cell, the second voltage pulse being determined by a value of a dedicated memory location.

[0114] In various embodiments, method 1100 may further include: wherein the test voltage is less than the erase verification voltage.

[0115] Figure 12 The method 1200 of the embodiment is described.

[0116] Method 1200 may include: at step 1202, having a memory array comprising a plurality of nonvolatile memory cell sets, each nonvolatile memory cell set comprising a plurality of nonvolatile memory cells; at step 1204, applying a first voltage pulse to a selected nonvolatile memory cell set to perform a first erase operation on the selected nonvolatile memory cell set; at step 1206, determining that a threshold voltage of at least one nonvolatile memory cell in the selected nonvolatile memory cell set is greater than a test voltage; at step 1208, updating a dedicated memory location using a value; and at step 1210, checking at least one nonvolatile memory cell to determine whether a threshold voltage of at least one nonvolatile memory cell is less than an erase verification voltage to verify that the first erase operation has been successfully performed.

[0117] In various embodiments, method 1200 may further include: confirming that the first erase operation has been successfully performed; and applying a second voltage pulse to a selected set of non-volatile memory cells to perform a second erase operation on the selected set of non-volatile memory cells, the second voltage pulse being determined by a value of a dedicated memory location.

[0118] In various embodiments, method 1200 may further include: wherein the value of the dedicated memory location includes operating parameters for generating the second voltage pulse.

[0119] In various embodiments, method 1200 may further include: each of a plurality of non-volatile memory cells in a selected set of non-volatile memory cells includes a floating gate memory cell, the floating gate memory cell including a body region and a control gate region, and wherein a first voltage pulse is applied between the control gate region and the body region of each non-volatile memory cell.

[0120] In various embodiments, method 1200 may further include: wherein determining that the threshold voltage of at least one non-volatile memory cell in the selected non-volatile memory cell set is greater than a test voltage includes: applying a test voltage to the control gate region of at least one non-volatile memory cell in the selected non-volatile memory cell set, and sensing the current characteristics through the channel of at least one non-volatile memory cell in the selected non-volatile memory cell set.

[0121] In various embodiments, method 1200 may further include: determining that a threshold voltage of one or more non-volatile memory cells in a selected set of non-volatile memory cells is greater than an erase verification voltage; and applying a second voltage pulse to the selected set of non-volatile memory cells to complete a first erase operation of the non-volatile memory cells, the second voltage pulse being determined by a value of a dedicated memory location.

[0122] In various embodiments, method 1200 may further include: wherein the test voltage is less than the erase verification voltage.

[0123] Exemplary embodiments of the invention are summarized herein. Other embodiments can be understood from the entire specification and the claims submitted herein.

[0124] Example 1. A method comprising: applying a first voltage pulse to a non-volatile memory cell to perform a first erase operation on the non-volatile memory cell; determining that a threshold voltage of the non-volatile memory cell is greater than a test voltage; updating a dedicated memory location using a value; and checking the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than an erase verification voltage to verify that the first erase operation has been successfully performed.

[0125] Example 2. The method according to Example 1 further includes: confirming that the first erase operation has been successfully performed; and applying a second voltage pulse to the non-volatile memory cell to perform a second erase operation on the non-volatile memory cell, the second voltage pulse being based on the value of the dedicated memory location.

[0126] Example 3. The method according to Example 1 or Example 2, wherein the value of the dedicated memory location includes operating parameters for generating the second voltage pulse.

[0127] Example 4. The method according to Examples 1 to 3, wherein the non-volatile memory cell includes a floating gate memory cell, the floating gate memory cell includes a body region and a control gate region, and wherein the first voltage pulse is applied between the control gate region and the body region.

[0128] Example 5. The method according to Examples 1 to 4, wherein determining that the threshold voltage of the non-volatile memory cell is greater than the test voltage comprises: applying the test voltage to the control gate region of the non-volatile memory cell and sensing the current characteristics through the channel of the non-volatile memory cell.

[0129] Example 6. The method according to Examples 1 to 5 further includes: determining that the threshold voltage of the non-volatile memory cell is greater than the erase verification voltage; and applying a second voltage pulse to the non-volatile memory cell to complete the first erase operation of the non-volatile memory cell, the second voltage pulse being determined by the value of the dedicated memory location.

[0130] Example 7. The method according to Examples 1 to 6, wherein the test voltage is less than the erase verification voltage.

[0131] Example 8. A non-volatile memory device, comprising: a set of non-volatile memory cells, each non-volatile memory cell in the set including a control gate region and configured to: lose information stored in the non-volatile memory cell when a threshold voltage of the non-volatile memory cell is less than an erase verification voltage; a bias circuit configured to: apply an erase voltage to each non-volatile memory cell in the set between the control gate region of the non-volatile memory cell and a body region of the non-volatile memory cell, and the bias circuit configured to: apply a control voltage to the control gate region of each non-volatile memory cell in the set; and a sensing circuit configured to sense a conduction characteristic of each non-volatile memory cell in the set, the conduction characteristic indicating whether the threshold voltage of the non-volatile memory cell is less than the control voltage applied to the control gate region of the non-volatile memory cell. The control circuit communicates with the bias circuit and the sensing circuit and is configured to: retrieve a data value from a dedicated memory location corresponding to the set of non-volatile memory cells; perform an erase operation such that the threshold voltage of each non-volatile memory cell in the set of non-volatile memory cells is less than the erase verification voltage by controlling the bias circuit to set the erase voltage to a value determined by the data value and applying the erase voltage to each non-volatile memory cell in the set of non-volatile memory cells; perform a test operation to determine whether the threshold voltage of each non-volatile memory cell in the set of non-volatile memory cells is less than a test voltage by controlling the bias circuit to set the value of the control voltage to the test voltage and applying the control voltage to each non-volatile memory cell in the set of non-volatile memory cells; and replace the data value in the dedicated memory location with a new data value determined by the result of the test operation.

[0132] Example 9. The non-volatile memory device according to Example 8, wherein the control circuitry is further configured to perform an erase verification operation to determine whether the threshold voltage of each non-volatile memory cell in the set of non-volatile memory cells is less than the erase verification voltage by controlling the bias circuitry to set the value of the control voltage to the erase verification voltage and applying the control voltage to each non-volatile memory cell in the set of non-volatile memory cells.

[0133] Example 10. A non-volatile memory device according to Example 8 or Example 9, wherein when it is determined that each non-volatile memory cell in the set of non-volatile memory cells is less than the test voltage, the new data value is equal to the data value.

[0134] Example 11. A non-volatile memory device according to Examples 8 to 10, wherein the new data value is incremented from the data value when it is determined that at least one non-volatile memory cell in the set of non-volatile memory cells is not less than the test voltage.

[0135] Example 12. A non-volatile memory device according to Examples 8 to 11, wherein the test voltage is less than the erase verification voltage.

[0136] Example 13. A non-volatile memory device according to Examples 8 to 12, wherein each non-volatile memory cell in the set of non-volatile memory cells includes a floating gate memory cell.

[0137] Example 14. A non-volatile memory device according to Examples 8 to 13, wherein the control voltage is applied between the control gate region of the non-volatile memory cell and the source region of the non-volatile memory cell to each non-volatile memory cell in the set of non-volatile memory cells.

[0138] Example 15. A method comprising: having a memory array including a plurality of nonvolatile memory cell sets, each nonvolatile memory cell set including a plurality of nonvolatile memory cells; applying a first voltage pulse to a selected set of nonvolatile memory cells to perform a first erase operation on the selected set of nonvolatile memory cells; determining that a threshold voltage of at least one nonvolatile memory cell in the selected set of nonvolatile memory cells is greater than a test voltage; updating a dedicated memory location using a value; and checking the at least one nonvolatile memory cell to determine whether the threshold voltage of the at least one nonvolatile memory cell is less than an erase verification voltage to verify that the first erase operation has been successfully performed.

[0139] Example 16. The method according to Example 15 further includes: confirming that the first erase operation has been successfully performed; and applying a second voltage pulse to the selected set of non-volatile memory cells to perform a second erase operation on the selected set of non-volatile memory cells, the second voltage pulse being determined by the value of the dedicated memory location.

[0140] Example 17. The method according to Example 15 or Example 16, wherein the value of the dedicated memory location includes operating parameters for generating the second voltage pulse.

[0141] Example 18. The method according to Examples 15 to 17, wherein each of the plurality of non-volatile memory cells in the selected set of non-volatile memory cells includes a floating gate memory cell, the floating gate memory cell including a body region and a control gate region, and wherein a first voltage pulse is applied between the control gate region and the body region of each non-volatile memory cell.

[0142] Example 19. The method according to Examples 15 to 18, wherein determining that the threshold voltage of at least one non-volatile memory cell in the selected non-volatile memory cell set is greater than the test voltage comprises: applying the test voltage to the control gate region of the at least one non-volatile memory cell in the selected non-volatile memory cell set, and sensing the current characteristics through the channel of the at least one non-volatile memory cell in the selected non-volatile memory cell set.

[0143] Example 20. The method according to Examples 15 to 19 further includes: determining that a threshold voltage of one or more non-volatile memory cells in the selected set of non-volatile memory cells is greater than the erase verification voltage; and applying a second voltage pulse to the selected set of non-volatile memory cells to complete the first erase operation of the non-volatile memory cells, the second voltage pulse being determined by the value of the dedicated memory location.

[0144] Example 21. The method according to Examples 15 to 19, wherein the test voltage is less than the erase verification voltage.

[0145] References to illustrative embodiments in this description are not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative and other embodiments will become apparent to those skilled in the art upon reference to this specification. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method for erasing non-volatile memory, comprising: A first voltage pulse is applied to a non-volatile memory cell to perform a first erase operation on the non-volatile memory cell; The threshold voltage of the non-volatile memory cell is determined to be greater than the test voltage, and the test voltage is less than the erase verification voltage; The location of the dedicated memory is updated using the value used to set the second voltage pulse; as well as The non-volatile memory cell is checked to determine whether the threshold voltage of the non-volatile memory cell is less than the erase verification voltage, in order to verify that the first erase operation has been successfully executed.

2. The method according to claim 1, further comprising: Confirm that the first erasure operation has been successfully executed; as well as The second voltage pulse is applied to the non-volatile memory cell to perform a second erase operation on the non-volatile memory cell, the second voltage pulse being based on the value of the dedicated memory location.

3. The method of claim 2, wherein the value of the dedicated memory location includes operating parameters for generating the second voltage pulse.

4. The method of claim 1, wherein the non-volatile memory cell comprises a floating gate memory cell, the floating gate memory cell comprising a body region and a control gate region, and wherein the first voltage pulse is applied between the control gate region and the body region.

5. The method of claim 4, wherein determining that the threshold voltage of the non-volatile memory cell is greater than the test voltage comprises: The test voltage is applied to the control gate region of the non-volatile memory cell, and the current characteristics through the channel of the non-volatile memory cell are sensed.

6. The method according to claim 1, further comprising: The threshold voltage of the non-volatile memory cell is determined to be greater than the erase verification voltage; as well as A second voltage pulse is applied to the non-volatile memory cell to complete the first erase operation of the non-volatile memory cell, the second voltage pulse being determined by the value of the dedicated memory location.

7. A non-volatile memory device, comprising: A set of non-volatile memory cells, each non-volatile memory cell in the set of non-volatile memory cells including a control gate region and configured to: lose information stored in the non-volatile memory cell when a threshold voltage of the non-volatile memory cell is less than an erase verification voltage; A bias circuit is configured to apply an erase voltage to each non-volatile memory in the set of non-volatile memory cells between the control gate region of the non-volatile memory cell and the body region of the non-volatile memory cell, and the bias circuit is configured to apply a control voltage to the control gate region of each non-volatile memory cell in the set of non-volatile memory cells. A sensing circuit is configured to sense the conduction characteristics of each non-volatile memory cell in the set of non-volatile memory cells, the conduction characteristics indicating whether the threshold voltage of the non-volatile memory cell is less than the control voltage applied to the control gate region of the non-volatile memory cell. and The control circuit communicates with the bias circuit and the sensing circuit and is configured to: Retrieve the data value from the dedicated memory location corresponding to the set of non-volatile memory cells; The erase operation is performed such that the threshold voltage of each non-volatile memory cell in the set of non-volatile memory cells is less than the erase verification voltage by controlling the bias circuit to set the erase voltage to a value determined by the data value and applying the erase voltage to each non-volatile memory cell in the set of non-volatile memory cells. The test operation is performed to determine whether the threshold voltage of each non-volatile memory cell in the set of non-volatile memory cells is less than the test voltage by controlling the bias circuit to set the value of the control voltage to the test voltage and applying the control voltage to each non-volatile memory cell in the set of non-volatile memory cells. as well as The new data value determined by the result of the test operation is used to replace the data value in the dedicated memory location.

8. The non-volatile memory device of claim 7, wherein the control circuitry is further configured to perform an erase verification operation to determine whether the threshold voltage of each non-volatile memory cell in the set of non-volatile memory cells is less than the erase verification voltage by controlling the bias circuitry to set the value of the control voltage to the erase verification voltage and applying the control voltage to each non-volatile memory cell in the set of non-volatile memory cells.

9. The non-volatile memory device of claim 8, wherein when it is determined that each non-volatile memory cell in the set of non-volatile memory cells is less than the test voltage, the new data value is equal to the data value.

10. The non-volatile memory device of claim 9, wherein the new data value is incremented from the data value when it is determined that at least one non-volatile memory cell in the set of non-volatile memory cells is not less than the test voltage.

11. The non-volatile memory device of claim 8, wherein the test voltage is less than the erase verification voltage.

12. The non-volatile memory device of claim 8, wherein each non-volatile memory cell in the set of non-volatile memory cells comprises a floating-gate memory cell.

13. The non-volatile memory device of claim 12, wherein the control voltage is applied between the control gate region of the non-volatile memory cell and the source region of the non-volatile memory cell to each non-volatile memory cell in the set of non-volatile memory cells.

14. A method for erasing non-volatile memory, comprising: A memory array having multiple sets of non-volatile memory cells, each set of non-volatile memory cells comprising multiple non-volatile memory cells; A first voltage pulse is applied to the selected set of non-volatile memory cells to perform a first erase operation on the selected set of non-volatile memory cells; The threshold voltage of at least one non-volatile memory cell in the selected set of non-volatile memory cells is determined to be greater than the test voltage, wherein the test voltage is less than the erase verification voltage. The location of the dedicated memory is updated using the value used to set the second voltage pulse; as well as The at least one non-volatile memory cell is checked to determine whether the threshold voltage of the at least one non-volatile memory cell is less than the erase verification voltage, in order to verify that the first erase operation has been successfully executed.

15. The method of claim 14, further comprising: Confirm that the first erasure operation has been successfully executed; as well as A second voltage pulse is applied to the selected set of non-volatile memory cells to perform a second erase operation on the selected set of non-volatile memory cells, the second voltage pulse being determined by the value of the dedicated memory location.

16. The method of claim 15, wherein the value of the dedicated memory location includes operating parameters for generating the second voltage pulse.

17. The method of claim 14, wherein each of the plurality of non-volatile memory cells in the selected set of non-volatile memory cells comprises a floating gate memory cell, the floating gate memory cell comprising a body region and a control gate region, and wherein the first voltage pulse is applied between the control gate region and the body region of each non-volatile memory cell.

18. The method of claim 17, wherein determining that the threshold voltage of at least one non-volatile memory cell in the selected set of non-volatile memory cells is greater than the test voltage comprises: The test voltage is applied to the control gate region of at least one non-volatile memory cell in the selected non-volatile memory cell set, and the current characteristics through the channel of the at least one non-volatile memory cell in the selected non-volatile memory cell set are sensed.

19. The method of claim 14, further comprising: Determine that the threshold voltage of one or more non-volatile memory cells in the selected set of non-volatile memory cells is greater than the erase verification voltage; as well as A second voltage pulse is applied to the selected set of non-volatile memory cells to complete the first erase operation of the non-volatile memory cells, the second voltage pulse being determined by the value of the dedicated memory location.

20. A non-volatile memory device, comprising: A non-volatile memory cell is configured to conduct current in response to the application of a threshold voltage, wherein the non-volatile memory cell includes an unwritten state when the threshold voltage is less than an erase verification voltage; A bias circuit is configured to apply a voltage to the non-volatile memory cell; A sensing circuit is configured to sense whether the non-volatile memory cell conducts current; as well as A control circuit, communicating with the bias circuit and the sensing circuit, is configured to: The bias circuit is controlled to apply an erase voltage to the non-volatile memory cell to reduce the threshold voltage. The erase voltage has an amplitude set by operating parameters stored in the data location. The bias circuit is controlled to apply a test voltage to the non-volatile memory cell to determine whether the threshold voltage is less than the test voltage, wherein the test voltage is less than the erase verification voltage; as well as In response to determining that the threshold voltage of the non-volatile memory cell is greater than the test voltage, the operating parameters in the data location are replaced with new operating parameters.

21. The non-volatile memory device of claim 20, wherein the control circuit is further configured to: perform an erase verification operation by controlling the bias circuit to apply the erase verification voltage to the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than the erase verification voltage.

22. The non-volatile memory device of claim 21, wherein the control circuitry is configured to: in response to determining that the threshold voltage of the non-volatile memory cell is greater than the erase verification voltage, apply an additional erase voltage to the non-volatile memory cell to reduce the threshold voltage, the additional erase voltage having an amplitude set by the new operating parameter stored in the data location.

23. The non-volatile memory device of claim 20, wherein the new operating parameter is incremented from the operating parameter.

24. The non-volatile memory device of claim 20, wherein the non-volatile memory cell comprises a floating-gate memory cell.

25. The non-volatile memory device of claim 24, wherein a control voltage is applied to the non-volatile memory cell between the control gate region of the non-volatile memory cell and the source region of the non-volatile memory cell.

26. The non-volatile memory device of claim 20, wherein the control circuitry is configured to delay replacing the operating parameters in the data location with the new operating parameters by a plurality of erase cycles.

27. The non-volatile memory device of claim 20, wherein the bias circuitry includes a digital-to-analog converter.

28. The non-volatile memory device of claim 27, wherein the control circuit provides the bias circuit with a digital control signal received by the digital-to-analog converter.

29. A non-volatile memory device, comprising: Non-volatile memory cells are configured to conduct current in response to the application of a threshold voltage; as well as The control circuit is configured to: control the application of an erase voltage to the non-volatile memory cell to reduce the threshold voltage, the erase voltage having an amplitude set by operating parameters stored in the data location; and control the application of a test voltage to the non-volatile memory cell to determine whether the threshold voltage is less than the test voltage. And in response to determining that the threshold voltage of the non-volatile memory cell is greater than the test voltage, the operating parameters in the data location are replaced with new operating parameters.

30. The non-volatile memory device of claim 29, further comprising the test voltage being less than the erase verification voltage.

31. The non-volatile memory device of claim 30, wherein when the threshold voltage is less than the erase verification voltage, the non-volatile memory cell includes an unwritten state.

32. The non-volatile memory device of claim 31, wherein the control circuit is further configured to perform an erase verification operation by directly applying the erase verification voltage to the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than the erase verification voltage.

33. The non-volatile memory device of claim 32, wherein the control circuitry is configured to: in response to determining that the threshold voltage of the non-volatile memory cell is greater than the erase verification voltage, apply an additional erase voltage to the non-volatile memory cell to reduce the threshold voltage, the additional erase voltage having an amplitude set by the new operating parameter stored in the data location.

34. The non-volatile memory device of claim 29, wherein the control circuit communicates with a bias circuit configured to apply a voltage to the non-volatile memory cell, and the control circuit communicates with a sensing circuit configured to sense whether the non-volatile memory cell conducts current.

35. A non-volatile memory device, comprising: A non-volatile memory cell is configured to conduct current in response to the application of a threshold voltage, wherein the non-volatile memory cell includes an unwritten state when the threshold voltage is less than an erase verification voltage; A bias circuit is configured to apply a voltage to the non-volatile memory cell, the bias circuit including a digital-to-analog converter to receive digital control signals from a control circuit; A sensing circuit is configured to sense whether the non-volatile memory cell conducts current; as well as The control circuit communicates with the bias circuit and the sensing circuit, and the control circuit is configured to: The bias circuit is controlled to apply an erase voltage to the non-volatile memory cell to reduce the threshold voltage. The erase voltage has an amplitude set by operating parameters stored in the data location. The bias circuit is controlled to apply a test voltage to the non-volatile memory cell to determine whether the threshold voltage is less than the test voltage, wherein the test voltage is less than the erase verification voltage; In response to determining that the threshold voltage of the non-volatile memory cell is greater than the test voltage, the operating parameters in the data location are replaced with new operating parameters; as well as An erase verification operation is performed by controlling the bias circuit to apply the erase verification voltage to the non-volatile memory cell to determine whether the threshold voltage of the non-volatile memory cell is less than the erase verification voltage.

36. The non-volatile memory device of claim 35, wherein the control circuitry is configured to: in response to determining that the threshold voltage of the non-volatile memory cell is greater than the erase verification voltage, apply an additional erase voltage to the non-volatile memory cell to reduce the threshold voltage, the additional erase voltage having an amplitude set by the new operating parameter stored in the data location.

37. The non-volatile memory device of claim 35, wherein the new operating parameter is incremented from the operating parameter.

38. The non-volatile memory device of claim 35, wherein the non-volatile memory cell comprises a floating-gate memory cell.

39. The non-volatile memory device of claim 38, wherein a control voltage is applied to the non-volatile memory cell between the control gate region of the non-volatile memory cell and the source region of the non-volatile memory cell.

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