Mid-section interconnect structure and method of manufacture

Abstract

This application relates to middle-of-line interconnect structures and methods of manufacture. In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source / drain regions and a gate electrode between the pair of source / drain regions. A lower interlayer dielectric (ILD) layer is disposed over the pair of source / drain regions and around the gate electrode. The gate electrode is recessed from a top of the lower ILD layer. A gate cap layer is disposed on the gate electrode. A top surface of the gate cap layer is aligned with or coplanar with a top surface of the lower ILD layer.

Description

Technical Field

[0001] This disclosure relates to a mid-segment interconnect structure and a method for manufacturing it. Background Technology

[0002] In the fabrication of integrated circuits (ICs), devices are formed on wafers and interconnected via conductive interconnect layers. These conductive interconnect layers can be formed during so-called middle-of-the-line (MOL) or back-end-of-line (BEOL) processes. The similarity between MOL and BEOL processes lies in the fact that they both involve forming openings (e.g., contact holes, trenches, or vias) in dielectric layers and then filling these openings with a conductive material. The difference between MOL and BEOL is that MOL typically occurs early in the manufacturing process and can refer to the process of forming contacts directly on or near the device structure (e.g., gate electrodes or source / drain regions); however, BEOL typically occurs late in the manufacturing process and can refer to the process of forming continuous metallization layers and vias over the contacts formed by MOL. Summary of the Invention

[0003] According to a first aspect of this disclosure, an integrated circuit device is provided, comprising: a transistor structure disposed on a substrate and including a pair of source / drain regions and a gate electrode between the pair of source / drain regions; a lower interlayer dielectric (ILD) layer disposed on the pair of source / drain regions and surrounding the gate electrode, the gate electrode being recessed from the top of the lower ILD layer; and a gate cap layer disposed on the gate electrode; wherein the top surface of the gate cap layer is aligned with the top surface of the lower ILD layer.

[0004] According to a second aspect of this disclosure, an integrated circuit device is provided, comprising: a transistor structure disposed on a substrate and including a pair of source / drain regions and a gate electrode between the pair of source / drain regions; a gate cap layer disposed on the gate electrode; a lower etch stop layer lining the sidewalls of the gate electrode and the gate cap layer; and a lower source / drain contact disposed on the side of the lower etch stop layer opposite to the gate electrode and extending to the source / drain region of the pair of source / drain regions.

[0005] According to a third aspect of this disclosure, a method of manufacturing an integrated circuit device is provided, comprising: forming a transistor structure disposed on a substrate and including a pair of source / drain regions and a gate electrode between the pair of source / drain regions; forming a lower etch stop layer and a lower interlayer dielectric (ILD) layer over the pair of source / drain regions and around the gate electrode; recessing the gate electrode and forming a gate cap precursor layer on the recessed gate electrode; forming a lower source / drain contact over the source / drain regions of the pair of source / drain regions; replacing the gate cap precursor layer with a gate cap layer, the dielectric constant of the gate cap layer being less than the dielectric constant of the gate cap precursor layer; forming an upper ILD layer over the lower ILD layer and the gate cap layer; and forming a gate contact that passes through the upper ILD layer and the gate cap layer and reaches the gate electrode. Attached Figure Description

[0006] Various aspects of this disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figures 1A-1E Various cross-sectional views of some additional embodiments of an integrated circuit device with a contact cap layer are shown.

[0008] Figure 2 A perspective view of some embodiments of an integrated circuit with a contact cap layer is shown.

[0009] Figures 3A-3G A series of cross-sectional views and flowcharts illustrating some embodiments of a method for forming an integrated circuit device with a contact cap layer are shown.

[0010] Figures 4-17 Cross-sectional views of some embodiments of a method for forming an integrated circuit with a contact cap layer are shown.

[0011] Figure 18 Flowcharts of some embodiments of a method for forming an integrated circuit with a contact cap layer are shown. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] In addition, spatially related terms such as “below,” “under,” “lower than,” “above,” “upper,” etc., may be used herein to readily describe the relationship of one element or feature relative to another element(s) shown in the accompanying drawings. Besides the orientations shown in the accompanying drawings, spatially related terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0014] In middle-range (MOL) interconnect structures, contacts, interconnect vias, and metal lines all play a crucial role in transistor and circuit performance. As scaling continues, the distances between various contacts and interconnect features decrease, and current leakage and parasitic capacitance become key limiting factors for device performance. It is desirable to reduce or prevent current leakage between contacts and other conductive features while limiting increases in resistance and capacitance.

[0015] Therefore, this disclosure relates to an integrated circuit device with an improved MOL interconnect structure and an associated manufacturing method for protecting contacts, reducing contact resistance, and also improving parasitic capacitance. As a result, device reliability is improved and the manufacturing process is simplified. In some embodiments, the integrated circuit device includes a transistor structure disposed on a substrate and including a pair of source / drain regions disposed on the substrate and a gate electrode between the pair of source / drain regions. A lower interlayer dielectric (ILD) layer is disposed on the pair of source / drain regions and surrounds the gate electrode. The gate electrode can be recessed from the top of the lower ILD layer. A gate cap layer can be disposed on the recessed gate electrode and can have a top surface aligned with or coplanar with the top surface of the lower ILD layer. By recessing the gate electrode and implementing the gate cap layer, the gate electrode is isolated and protected from adjacent conductive features, thereby reducing or eliminating leakage problems. In some embodiments, the gate cap layer comprises an oxide material or a low-k dielectric material, such that the parasitic capacitance can be very small. In some other embodiments, the integrated circuit device further includes a lower source / drain contact disposed on a first source / drain region of the pair of source / drain regions. The lower source / drain contact may also be recessed from the top. A source / drain capping layer may be disposed on the recessed lower source / drain contact to protect and isolate the lower source / drain contact from the influence of adjacent conductive features. Therefore, leakage problems can be further reduced or eliminated. The source / drain capping layer comprises a dielectric material that may be the same as or different from that of the gate capping layer.

[0016] Figures 1A-1E Various cross-sectional views of an integrated circuit device according to some embodiments are shown. Figures 1A-1EAs shown, in some embodiments, transistor structure 101 is disposed on substrate 102. In various embodiments, substrate 102 can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.) (e.g., a semiconductor wafer and / or one or more dies on a wafer) and any other type of semiconductor layer, epitaxial layer, or dielectric layer associated therewith. Transistor structure 101 can be a logic device including a gate electrode 104 separated from substrate 102 by a gate dielectric layer 105. A pair of source / drain regions 103 are disposed within substrate 102 and on opposite sides of gate electrode 104. Transistor structure 101 can be a single-gate planar device and a multi-gate device, such as a FinFET device. Transistor structure 101 can also be other devices, such as gate-all-around (GAA) devices, omega-gate devices, or pi-gate devices, as well as strained semiconductor devices, silicon-on-insulator (SOI) devices, partially depleted SOI (PD-SOI) devices, fully depleted SOI (FD-SOI) devices, or other suitable devices.

[0017] Contacts are coupled to the gate electrode 104, source / drain region 103, body contact region, or other active region of transistor structure 101, respectively. In some embodiments, the contacts may include a lower contact structure 142 surrounded by a lower interlayer dielectric (ILD) layer 110, and / or an upper contact structure 144 surrounded by an upper interlayer dielectric (ILD) layer 128 and disposed above the lower ILD layer 110. The contacts may include a metal core 138 and a barrier layer (not shown in the figures). In some embodiments, the metal core 138 includes, or is made of, tungsten, cobalt, ruthenium, titanium nitride, tantalum nitride, or other suitable metals. The barrier layer acts as an adhesive and barrier layer to bond the metal core to prevent the formation of voids and to prevent the metal core 138 from diffusing into the lower ILD layer 110 and / or the upper ILD layer 128. In some embodiments, the thickness of the barrier layer is in the range of about 2 nm to about 10 nm. The lower etch stop layer 108 can be disposed along the sidewall of the lower ILD layer 110 and lined within the sidewall of the lower ILD layer 110.

[0018] In some embodiments, the upper etch stop layer 126 may be disposed between the upper ILD layer 128 and the lower ILD layer 110. The lower etch stop layer 108 and the upper etch stop layer 126 may each comprise a different dielectric material than the lower ILD layer 110 and the upper ILD layer 128. For example, the lower etch stop layer 108 and the upper etch stop layer 126 may each comprise silicon nitride or silicon carbide, and may have a thickness in the range of about 3 nm to 10 nm.

[0019] In some embodiments, the gate electrode 104 is recessed from the top of the lower ILD layer 110. A gate cap layer 116 is disposed on the gate electrode 104. The top surface of the gate cap layer 116 may be aligned with or coplanar with the top surface of the lower ILD layer 110. For example, the thickness of the recessed gate electrode 104 may be in the range of about 10 nm to 20 nm. The thickness of the gate cap layer 116 may be in the range of about 20 nm to 40 nm. In some embodiments, the gate cap layer 116 comprises silicon dioxide or a low-κ dielectric material. Silicon dioxide has a dielectric constant of about 3.9, and the low-κ dielectric material has a dielectric constant of less than 3. For example, the gate cap layer 116 may comprise a carbon-doped oxide dielectric (SiCOH) composed of Si, C, O, and H, low-hydrogen-content silicon carbonitride (SiOCN), silicon carbonitride (SiOC), or other suitable low-κ dielectric materials. Compared to using semiconductor or dielectric materials with higher dielectric constants (e.g., silicon with a dielectric constant of about 11.7 or silicon nitride with a dielectric constant of about 7-8), the relatively small dielectric constant of the gate cap layer 116 helps to reduce the parasitic capacitance of integrated circuit devices.

[0020] In some embodiments, the lower contact structure 142 includes a lower source / drain contact 120 disposed on the source / drain regions of a pair of source / drain regions 103. In some embodiments, the lower source / drain contact 120 fills a groove between the sidewalls of the lower etch stop layer 108 and directly contacts the sidewalls of the lower etch stop layer 108.

[0021] In some embodiments, the upper contact structure 144 includes an upper source / drain contact 137 configured to pass through the upper ILD layer 128 and reach the source / drain regions of a pair of source / drain regions 103. The upper source / drain contact 137 may be disposed on a lower source / drain contact 120 and electrically coupled to the source / drain regions of the pair of source / drain regions 103 via the lower source / drain contact 120. In some embodiments, the upper contact structure 144 further includes a gate electrode contact 139 configured to be adjacent to the upper source / drain contact 137 and pass through the upper ILD layer 128. The gate electrode contact 139 may be configured to pass through the gate cap layer 116 and be electrically coupled to the gate electrode 104. The gate electrode 104 may include a stack of metal layers, including a work function metal disposed on a core gate metal. The gate electrode contact 139 may include, or be made of, the same material as the upper source / drain contact 137. The upper contact structure 144 may also include a body contact 141, which includes a first portion 141a and a second portion 141b. The first portion 141a is electrically coupled to one of the source / drain regions via the lower source / drain contact 120, and the second portion 141b is electrically coupled to the gate electrode 104. In some embodiments, the body contact 141 includes, or is made of the same material as the upper source / drain contact 137 and the gate electrode contact 139.

[0022] Upper contact structures 144 (e.g., upper source / drain contact 137, gate electrode contact 139, and body contact 141) may be disposed on the recessed upper surface of the lower conductive features (e.g., gate electrode 104 and lower source / drain contact 120) to improve landing and reduce contact resistance. The upper contact structures 144 may each have lateral dimensions close to the lateral dimensions of the lower conductive features to achieve low resistance. For example, the bottom lateral dimension of the upper source / drain contact 137 may be substantially equal to the top lateral dimension of the lower source / drain contact 120, for example, within approximately 3-5 nm greater than or less than this dimension. The lateral dimension of the gate electrode contact 139 may be substantially equal to the top lateral dimension of the gate electrode 104, for example, within approximately 3-5 nm greater than or less than this dimension. The tilt angles of the upper source / drain contact 137 and the gate electrode contact 139 may be approximately 86°-89° relative to the side surface of the integrated circuit device. As a result, within a limited space, the lower contact structure 142 and the upper contact structure 144 can be arranged to be effectively isolated while maximizing the lateral dimensions, thereby preventing leakage problems while minimizing resistance.

[0023] like Figure 1A and Figure 1C As shown, in some embodiments, the top surface of the lower source / drain contact 120 is aligned with or coplanar with the top surface of the lower etch stop layer 108. The upper etch stop layer 126 can be directly disposed on the gate cap layer 116 and the lower source / drain contact 120.

[0024] like Figure 1B , Figure 1D and Figure 1E As shown, in some alternative embodiments, the lower source / drain contact 120 is recessed from the lower etch stop layer 108, and a source / drain cap layer 124 is disposed on the recessed lower source / drain contact 120. The top surface of the source / drain cap layer 124 may be aligned or coplanar with the top surface of the gate cap layer 116, and may further be aligned or coplanar with the top surface of the lower etch stop layer 108. For example, the thickness of the recessed lower source / drain contact 120 may be in the range of about 30 nm to 60 nm. The thickness of the source / drain cap layer 124 may be in the range of about 5 nm to 25 nm. In some embodiments, the source / drain cap layer 124 may have a sidewall surface that directly contacts the upper source / drain contact 137 and a bottom surface that directly contacts the lower source / drain contact 120. As an example, the source / drain capping layer 124 may include, or be made of, silicon nitride, silicon carbide, or combinations thereof. In some embodiments, the thickness of the source / drain capping layer 124 may be in the range of about 5 nm to about 25 nm. The heights of the recessed lower source / drain contact 120 and the recessed gate electrode 104, as well as the thicknesses of the gate capping layer 116 and the source / drain capping layer 124, may vary. For example, as... Figure 1B and Figure 1D As shown, the recessed lower source / drain contact 120 can be higher than the gate electrode 104, and the source / drain capping layer 124 is thinner than the gate capping layer 116. Alternatively, as Figure 1E As shown, the recessed lower source / drain contact 120 can be lower than the gate electrode 104, and the source / drain capping layer 124 is thicker than the gate capping layer 116.

[0025] In some embodiments, an upper etch stop layer 126 is disposed above the gate cap layer 116 and the source / drain cap layer 124. The bottom surface of the upper etch stop layer 126 may contact the gate cap layer 116 and the source / drain cap layer 124. As an example, the upper etch stop layer 126 may include, or be made of, alumina, silicon nitride, or other suitable dielectric materials. In some embodiments, the upper ILD layer 128 may include, or be made of, materials such as PECVD oxide, FCVD oxide, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon dioxide (e.g., borosilicate glass (BPSG), fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)), and / or other suitable dielectric materials. In some cases, the upper ILD layer 128 may include the same dielectric material as the lower ILD layer 110. In this configuration, the upper etch stop layer 126 may comprise a non-oxide dielectric material, such as silicon nitride. In some examples, the upper etch stop layer 126 has a thickness of about 3 nm to about 20 nm, and the upper ILD layer 128 has a thickness of about 5 nm to about 40 nm.

[0026] In some embodiments, the sidewall spacer 106 is disposed adjacent to the gate electrode 104. For example... Figure 1A and Figure 1B As shown, the top surface of the sidewall spacer 106 can be aligned with or coplanar with the top surface of the gate electrode 104. A gate cap layer 116 can be disposed on both the gate electrode 104 and the sidewall spacer 106. Alternatively, the top surface of the sidewall spacer 106 can be higher than the top surface of the gate electrode 104. Figures 1C-1D As shown, the top surface of the sidewall spacer 106 can be aligned with or coplanar with the top surface of the lower etch stop layer 108. A gate cap layer 116 can be disposed between the upper portions of the sidewall spacers 106. (As shown...) Figure 1E As shown, the top surface of the sidewall spacer 106 may also be located between the recessed gate electrode 104 and the top surface of the lower etch stop layer 108. The gate cap layer 116 may be disposed between the upper portions of the sidewall spacers 106 and extend above the top surface of the sidewall spacers 106.

[0027] Figure 2A perspective view of an integrated circuit device with a contact cap layer according to some other embodiments is shown. In some embodiments, the integrated circuit device includes a FinFET device, a nanowire device, or other gate all-around (GAA) device. Substrate 102 may include a lower base and a plurality of upper pillars rising from the lower base, extending along the channel length direction, and arranged parallel to each other. An epitaxial semiconductor layer may be disposed on the plurality of upper pillars of substrate 102 and may include heavily doped portions on opposite sides as source / drain regions 103, and lightly doped or undoped portions between the source / drain regions 103 as channel regions. A conductive layer may be disposed on the channel regions as a gate electrode 104 and may be separated from the channel regions by a gate dielectric and may be configured to control the current in the channel regions. Gate electrode 104 may extend along a channel width direction perpendicular to the channel length direction. Gate electrode 104 may extend to surround the sidewalls of the channel regions. As discussed above in relation to the figures, in some embodiments, a gate cap layer 116 is disposed on gate electrode 104. The top surface of the gate cap layer 116 may be aligned with or coplanar with the top surface of the lower etch stop layer 108. In some other embodiments, the source / drain cap layer 124 is disposed on the lower source / drain contact 120. The top surface of the source / drain cap layer 124 may be aligned with or coplanar with the top surface of the lower etch stop layer 108. The upper source / drain contact 137 may be configured to pass through the upper ILD layer 128 and the source / drain cap layer 124 and reach the lower source / drain contact 120. The gate electrode contact 139 may be configured to pass through the upper ILD layer 128 and the gate cap layer 116 and reach the gate electrode 104. The body contact 141 may be configured to pass through both the gate cap layer 116 and the source / drain cap layer 124 and electrically couple the gate electrode 104 and the lower source / drain contact 120.

[0028] Figures 3A-3G A series of cross-sectional views and flowcharts illustrating some embodiments of a method for forming an integrated circuit device with a contact cap layer are shown. Figure 3A and Figure 3G As shown in action 152, in some embodiments, a first lower contact structure 142a is formed on the substrate 102. The first lower contact structure 142a may be a device feature or a MOL contact feature, such as the gate electrode 104 or the lower source / drain contact 120 shown in the figure above. Before or after the formation of the first lower contact structure 142a, a lower etch stop layer 108 and a lower ILD layer 110 may be formed as linings on the upper surface of the substrate 102 and the sidewalls of the first lower contact structure 142a.

[0029] like Figure 3B as well as Figure 3GAs shown in action 154, in some embodiments, the first lower contact structure 142a is recessed. Then, a first contact cap precursor layer 114a' is formed on the recessed upper surface of the first lower contact structure 142a. The first contact cap precursor layer 114a' may include a semiconductor or dielectric material different from the lower ILD layer 110. The first contact cap precursor layer 114a' may be formed by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process.

[0030] like Figure 3C as well as Figure 3G As shown in action 156, in some embodiments, with the first contact cap precursor layer 114a' in place, a second lower contact structure 142b is formed next to the first lower contact structure 142a. In some embodiments, the lower ILD layer 110 and the side portions of the lower etch stop layer 108 below the lower ILD layer 110 are partially or completely removed to form an opening, wherein the first contact cap precursor layer 114a' serves as a masking and protective layer. The lower ILD layer 110 can be removed by an etching process that is selective for the lower etch stop layer 108 and the first contact cap precursor layer 114a'. During the removal of the lower ILD layer 110, the first contact cap precursor layer 114a' protects the first lower contact structure 142a from exposure. The second lower contact structure 142b then fills the opening between the vertical portions of the lower etch stop layer 108. The second lower contact structure 142b can be an MOL contact feature or a device feature, such as the lower source / drain contact 120 or gate electrode 104 in the figure above.

[0031] like Figure 3D and Figure 3G As shown in action 158, in some embodiments, the first contact cap precursor layer 114a' is replaced with a first contact cap layer 114a' whose dielectric constant is less than that of the first contact cap precursor layer 114a'. As an example, the first contact cap layer 114a may comprise, or be made of, a low-κ dielectric material with a dielectric constant less than 3.9. Therefore, the parasitic capacitance associated with the first contact cap precursor layer 114a can be reduced compared to using the first contact cap precursor layer 114a'.

[0032] like Figure 3E and Figure 3GAs shown in action 160, instead of an embodiment where the top surface of the second lower contact structure 142b is aligned or coplanar with the upper surface of the lower etch stop layer 108, in some other embodiments, the second lower contact structure 142b is recessed below the top of the lower etch stop layer 108. A second contact cap layer 114b is then formed on the recessed upper surface of the second lower contact structure 142b. The second contact cap layer 114b protects the underlying second lower contact structure 142b during subsequent manufacturing steps, for example, preventing current leakage caused by the formation of an upper contact structure landing on the second lower contact structure 142b. As an example, the second contact cap layer 114b may include, or be made of, silicon nitride, silicon carbide, combinations thereof, etc. In some alternative embodiments, the second contact cap layer 114b may be replaced with a dielectric material with a low dielectric constant, such as a low-κ dielectric material with a dielectric constant less than 3. Therefore, the parasitic capacitance associated with the second contact cap layer 114b can be reduced.

[0033] like Figure 3F and Figure 3G As shown in action 162, in some embodiments, the first upper contact structure 144a may be formed to pass through the first contact cap layer 114a and reach the first lower contact structure 142a. The second upper contact structure 144b may be formed to pass through the second contact cap layer 114b and reach the second lower contact structure 142b.

[0034] Figures 4-17 Cross-sectional views 400-1700 show some embodiments of a method for forming an integrated circuit with a contact cap layer. Although Figures 4-17 This is relative to the method description, but it should be understood that... Figures 4-17 The structures disclosed herein are not limited to this method, but can exist independently of the method.

[0035] like Figure 4 and Figure 5 As shown, transistor structure 101 is fabricated on substrate 102 and surrounded by a lower ILD layer 110. Transistor structure 101 has a gate dielectric layer 105 on substrate 102, a gate electrode 104 on gate dielectric layer 105, and a pair of source / drain regions 103 disposed on the opposite side of gate electrode 104 within substrate 102 (see [reference]). Figure 5 The gate electrode 104 may be a polysilicon gate or a metal gate. The gate dielectric layer 105 may include or be made of the following: a silicon dioxide layer, or a high-k dielectric material with a dielectric constant greater than 7 (e.g., hafnium dioxide).

[0036] In some embodiments, the transistor structure 101 can be formed by replacing the gate process. For example... Figure 4 As shown, a dummy gate 404 is first formed and patterned on a substrate 102. Sidewall spacers 106 are formed adjacent to the dummy gate 404 and line or cover the sidewalls of the dummy gate 404. A pair of source / drain regions 103 are formed on opposite sides of the sidewall spacers 106 and within the substrate 102. In various embodiments, the sidewall spacers 106 comprise silicon dioxide, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, combinations thereof, or other suitable dielectric materials. In some embodiments, the sidewall spacers 106 may comprise multiple layers, such as a main spacer wall, a liner layer, etc. As an example, the sidewall spacers 106 can be formed by depositing a dielectric material on the dummy gate 404 and vertically etching back the dielectric material to have a top surface substantially coplanar with the top surface of the dummy gate 404.

[0037] like Figure 5 As shown, a dielectric layer is deposited on transistor structure 101, followed by a planarization process to form a lower ILD layer 110. In some embodiments, a lower etch stop layer 108 is formed prior to the formation of the lower ILD layer 110, lining the upper surface of the substrate and extending upward along the sidewall spacers 106. The lower etch stop layer 108 can be formed by a deposition process such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). The lower ILD layer 110 can be deposited using subatmospheric pressure CVD (SACVD), flowable CVD, or other suitable deposition techniques. The lower etch stop layer 108 and the dielectric layer can be planarized using a chemical mechanical planarization (CMP) process so that their top surfaces are substantially coplanar with the top surface of the sidewall spacers 106. As an example, the dielectric layer used to form the lower ILD layer 110 may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon dioxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)), and / or other suitable dielectric materials. As an example, the lower ILD layer 110 has a thickness of about 40 nm to about 80 nm.

[0038] For gate replacement processes Figure 4The dummy gate 404 can be removed and replaced by a gate electrode 104 made of metal. After removing the dummy gate 404, a gate dielectric layer 105 can also be formed. To form the gate electrode 104, a stack of metal material can be filled into the gate opening, followed by a planarization process to remove excess material above the underlying ILD layer 110. Depending on the device, the stack of metal material can include or be made of the following: titanium nitride, tantalum nitride, titanium aluminum, and aluminum, etc. Other materials can also be used for the gate electrode 104.

[0039] like Figure 6 As shown, in some embodiments, the gate electrode 104 is recessed. As an example, a patterning process is first performed to form a masking layer 112 over the lower ILD layer 110, exposing the gate electrode. Then, an etching process is performed on the gate electrode 104 to lower the top surface of the gate electrode 104 to a position below the top surface of the lower ILD layer. Alternatively, the etching process is highly selective for the gate electrode 104 and does not require a masking layer. In some embodiments, the etching process includes anisotropic etching, such as vertical dry etching, and the recessed top surface of the gate electrode 104 is substantially flat, as shown. In some alternative embodiments, the etching process includes isotropic etching, such as wet etching, and the recessed top surface of the gate electrode 104 may be concave, although not shown in the figures. In some embodiments, the sidewall spacer 106 may be lowered along with the gate electrode 104. Depending on the selectivity of the etchant, the top surface of the sidewall spacer 106 may be changed to be below, equal to, or above the top surface of the gate electrode 104, for example, as... Figures 1A-1E As shown. The gate electrode recess process can expose the upper sidewall of the lower etch stop layer 108. The etching process controls the thickness of the gate electrode 104, and thus adjusts the effective work function of the gate electrode 104 to the desired value.

[0040] like Figure 7 As shown, in some embodiments, a gate cap precursor layer 116' is formed on the recessed gate electrode 104 and can serve as a protective layer to protect the gate electrode 104 from subsequent processing steps. In some embodiments, the gate cap precursor layer 116' can be deposited and then planarized to be aligned with or coplanar with the top surfaces of the underlying ILD layer 110 and / or the underlying etch stop layer 108. The gate cap precursor layer 116' may include or be made of silicon, silicon nitride, or metal oxide.

[0041] like Figure 8As shown, the opening 118 is formed through the lower ILD layer 110 and the lower etch stop layer 108 below the lower ILD layer 110. In some cases, the opening 118 provides access to the source / drain region 103 and / or the body contact region. As an example, the opening 118 can be formed by a suitable combination of photolithographic patterning and etching (e.g., wet or dry etching) processes.

[0042] like Figure 9 As shown, in some embodiments, the lower source / drain contact 120 fills within the opening 118 and is formed on the source / drain region 103. In some embodiments, the lower source / drain contact 120 can be formed as self-aligned by completely removing the lower ILD layer 110, and thus the lower source / drain contact 120 can directly contact the sidewalls of the lower etch stop layer 108. The gate cap precursor layer 116' covers and protects the gate electrode 104 during the formation of the opening 118 and the lower source / drain contact 120. In some examples, the lower source / drain contact 120 may include cobalt or other suitable materials, such as W, Cu, Ru, Al, Rh, Mo, Ta, Ti. The lower source / drain contact 120 may also include an adhesive or barrier layer that facilitates adhesion and / or prevents diffusion. After depositing the lower source / drain contact 120, a chemical mechanical planarization (CMP) process can be performed to remove excess material from the lower source / drain contact 120 and planarize the top surface of the workpiece. Prior to forming the lower source / drain contact 120, a metallization process can be performed to form a semiconductor metal compound film (e.g., silicide, germanide, germanium silicide) at the interface between the lower source / drain contact 120 and the exposed portion of the upper surface of the source / drain region 103, thus providing a low-resistance contact.

[0043] like Figure 10 As shown, in some embodiments, the gate capping precursor layer 116' is removed and replaced with a gate capping layer 116 having a smaller dielectric constant, thus reducing parasitic capacitance. The gate capping layer 116 may comprise silicon dioxide or a low-κ dielectric material with a dielectric constant less than 3.9. For example, the gate capping layer 116 may comprise a carbon-doped oxide dielectric (SiCOH) composed of Si, C, O, and H, low-hydrogen-content silicon oxycarbide (SiOCN), silicon oxycarbide (SiOC), or other suitable low-κ dielectric materials.

[0044] like Figure 11As shown, in some embodiments, the lower source / drain contact 120 is recessed, thus forming an opening 122 within the upper portion of the lower etch stop layer 108. An etching process is performed on the lower source / drain contact 120 to lower the top surface of the lower source / drain contact 120 to a position below the top surface of the lower etch stop layer 108. In some embodiments, the etching process includes anisotropic etching, such as vertical dry etching, and the recessed top surface of the lower source / drain contact 120 is substantially planar, as shown. In some alternative embodiments, the etching process includes isotropic etching, such as wet etching, and the recessed top surface of the lower source / drain contact 120 may be concave, although not shown in the figures.

[0045] like Figure 12 As shown, a source / drain capping layer 124 is formed to fill the opening 122 within the upper portion of the lower source / drain contact 120. In some embodiments, the source / drain capping layer 124 can be formed by depositing a dielectric material followed by a CMP process. The top surface of the source / drain capping layer 124 may be aligned with or coplanar with the top surface of the gate capping layer 116 and / or the lower etch stop layer 108. The source / drain capping layer 124 provides protection and isolation for the lower source / drain contact 120.

[0046] like Figure 13 As shown, an upper etch stop layer 126 is formed over the gate cap layer 116, and an upper ILD layer 128 is formed over the upper etch stop layer 126. As an example, the upper etch stop layer 126 may include or be made of alumina, silicon nitride, or zirconium oxide. Other suitable dielectric materials may also be used for the upper etch stop layer 126. In some embodiments, the upper ILD layer 128 may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon dioxide (e.g., borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG)), and / or other suitable dielectric materials. Therefore, in some cases, the upper ILD layer 128 may be substantially the same as the lower ILD layer 110. In various embodiments, the upper etch stop layer 126 and the upper ILD layer 128 can be deposited using subatmospheric pressure CVD (SACVD), flowable CVD, ALD, PECVD, or other suitable deposition techniques. In some examples, the upper etch stop layer 126 has a thickness of about 5 nm to about 20 nm, and the upper ILD layer 128 has a thickness of about 20 nm to about 40 nm.

[0047] like Figures 14-16As shown, multiple openings 130, 132, 134, and 136 are formed to reach the gate cap layer 116 or the source / drain cap layer 124, and then filled with a core metal material. In some embodiments, the core metal material may be tungsten, cobalt, ruthenium, titanium nitride, tantalum nitride, or other suitable metals. The multiple openings 130, 132, 134, and 136 may be formed one after another in any order or in some combination, and the multiple openings 130, 132, 134, and 136 may all be formed before simultaneously filling with the core metal material. The heights of the recessed lower source / drain contact 120 and the recessed gate electrode 104, as well as the thicknesses of the gate cap layer 116 and the source / drain cap layer 124, may vary based on subsequent manufacturing steps. For example, as shown, the lower source / drain contact 120 can be recessed less than the gate electrode 104, and the source / drain capping layer 124 can be formed thinner than the gate capping layer 116, so that the gate electrode 104 can be better protected when openings 134, 136 are formed through the source / drain capping layer 124. Alternatively, if openings 134, 136 are formed first, the lower source / drain contact 120 can be recessed more and lower than the gate electrode 104, although not shown in the figure, so that the source / drain region 103 can be better protected when openings 130, 132 are subsequently formed through the gate capping layer 116. Openings 130, 132, 134, and 136 can be formed individually by a multi-step etching process to improve etch selectivity and provide over-etch control.

[0048] For example, refer to Figure 14 The openings 130 and 132 can be formed as a first pattern by performing a first etch at a high etch rate on the upper ILD layer 128 and stopping at the upper etch stop layer 126. Then, a second etch is performed to slowly etch the upper etch stop layer 126 and the gate cap layer 116, thus exposing the gate electrode 104 with appropriate over-etching. Alternatively, the openings 130 and 132 can be formed by performing a first etch at a high etch rate on the upper ILD layer 128 and the upper etch stop layer 126 and stopping at the gate cap layer 116. Then, a second etch is performed to etch through the gate cap layer 116, thus exposing the gate electrode 104. The openings 130 and 132 can also be formed by a suitable combination of photolithographic patterning and etching (e.g., wet or dry etching) processes.

[0049] Similarly, refer to Figure 15The openings 134 and 136 can be formed as a second pattern by performing a first etch with a high etch rate on the upper ILD layer 128 and stopping at the upper etch stop layer 126. Then, a second etch is performed to slowly etch the upper etch stop layer 126 and the source / drain cap layer 124, thus exposing the lower source / drain contacts 120 with appropriate over-etching. The openings 134 and 136 can also be formed by a suitable combination of photolithographic patterning and etching (e.g., wet or dry etching) processes.

[0050] like Figure 16 As shown, the third pattern is formed by merging openings 132 and 136 by etching through the upper ILD layer 128 and the upper etch stop layer 126 between openings 132 and 136. In some embodiments, the patterning process (e.g., for forming multiple openings) may include a multi-step etching process to etch the upper ILD layer 128 and the upper etch stop layer 126 separately, thereby improving etch selectivity and providing over-etch control.

[0051] like Figure 17 As shown, one or more metal layers are formed in openings 130, 132, 134, and 136. In some cases, body contact 141 provides direct contact between gate electrode 104 and adjacent source, drain, and / or body regions. Upper source / drain contact 137 provides access to source / drain regions within substrate 102 via lower source / drain contact 120, and gate electrode contact 139 provides access to gate electrode 104. Drain cap layer 124 isolates and protects lower source / drain contact 120. Gate cap layer 116 isolates and protects gate electrode 104. As disclosed, by arranging the gate cap layer 116, the upper etch stop layer 126, and the source / drain cap layer 124 on the lower source / drain contact 120, and arranging the gate cap layer 116 on the gate electrode 104, the formation process of the upper source / drain contact 137 can be integrated with the formation of the gate electrode contact 139 and the body contact 141. In some embodiments, the formation of the metal layer includes forming a metal core 138 and a barrier layer (not shown in the figures) by a deposition process.

[0052] Figure 18 Flowcharts of some embodiments of a method 1800 for forming an integrated chip having an interconnect structure with an inter-mixing barrier layer are shown.

[0053] Although method 1800 is illustrated and described below as a series of actions or events, it should be understood that the illustrated order of such actions or events should not be interpreted in a limiting sense. For example, some actions may occur in a different order than those illustrated and / or described herein, and / or simultaneously with other actions or events. Furthermore, implementing one or more aspects or embodiments described herein may not require all the actions shown. Additionally, one or more actions described herein may be performed in one or more separate actions and / or phases.

[0054] At 1802, a transistor structure is formed and surrounded by a lower ILD layer. The transistor structure includes a gate electrode formed on the substrate and a pair of source / drain regions disposed on the opposite side of the gate electrode. Sidewall spacers are formed next to the gate electrode and line or cover the sidewalls of the gate electrode. In some embodiments, a first etch stop layer is formed as a liner on the upper surface of the source / drain regions and extends along the gate electrode. The gate electrode can be formed by a replacement gate process, which removes the gate precursor and replaces it with a high-k dielectric material and a metal gate material. Figures 4-5 Cross-sectional views 400-500 are shown for some embodiments corresponding to action 1802.

[0055] At 1804, in some embodiments, the gate electrode is recessed, and a gate cap precursor layer is formed on the recessed upper surface of the gate electrode. In some embodiments, the gate cap precursor layer comprises or is made of silicon, silicon nitride, or metal oxide. Figures 6-7 Cross-sectional views 600-700 are shown for some embodiments corresponding to action 1804.

[0056] At 1806, a lower source / drain contact is formed to reach the source / drain region of the transistor structure within the substrate. In some embodiments, with the gate cap precursor layer in place, an opening is formed by partially or completely removing the lower ILD layer. A conductive material is then filled into the opening as the lower source / drain contact. The gate cap precursor layer protects the underlying gate electrode from exposure during the formation of the lower source / drain contact. Figures 8-9 Cross-sectional views 800-900 are shown for some embodiments corresponding to action 1806.

[0057] At 1808, in some embodiments, the gate cap precursor layer is replaced with a gate cap layer having a smaller dielectric constant. In some embodiments, the gate cap layer comprises or is made of silicon dioxide or a low-k dielectric material with a dielectric constant less than 3.9. Therefore, the parasitic capacitance associated with the gate cap layer is reduced, thereby improving device performance. Figure 10A cross-sectional view 1000 corresponding to some embodiments of action 1808 is shown.

[0058] At 1810, in some embodiments, the lower source / drain contact may be recessed, and a source / drain capping layer may be formed on the lower source / drain contact to fill the opening in the upper portion of the lower etch stop layer. In some embodiments, the source / drain capping layer may be formed by depositing a dielectric material followed by a CMP process. Figures 11-12 Cross-sectional views 1100-1200 are shown for some embodiments corresponding to action 1810.

[0059] At position 1812, an upper ILD layer is formed above the gate cap layer and the source / drain cap layer. An upper etch stop layer can be formed before the upper ILD layer is formed. Figure 13 A cross-sectional view 1300 is shown, corresponding to some embodiments of action 1812.

[0060] At position 1814, multiple openings are formed through the upper ILD layer and the upper etch stop layer, and also through the gate cap layer and the source / drain cap layer, to expose the gate electrode and the lower source / drain contacts. The multiple openings are then filled with a metallic material to form multiple contacts for the gate electrode, source / drain regions, body contact regions, and / or other device features. In some embodiments, the metallic material includes tungsten, cobalt, ruthenium, titanium nitride, tantalum nitride, or other suitable metals. Figures 14-17 Cross-sectional views 1400-1700 are shown for some embodiments corresponding to action 1814.

[0061] Therefore, this disclosure relates to a novel integrated circuit device including a gate cap layer on a recessed gate electrode, a source / drain cap layer on a recessed source / drain contact, or both, for protecting against and preventing current leakage. The gate cap layer and / or the source / drain cap layer may comprise a dielectric material with a relatively low dielectric constant (e.g., a low-κ dielectric material with a dielectric constant less than 3.9), thereby minimizing parasitic capacitance.

[0062] Therefore, in some embodiments, this disclosure relates to an integrated circuit device. A transistor structure is disposed on a substrate and includes a pair of source / drain regions and a gate electrode between the pair of source / drain regions. A lower interlayer dielectric (ILD) layer is disposed on the pair of source / drain regions and surrounds the gate electrode. The gate electrode is recessed from the top of the lower ILD layer. A gate cap layer is disposed on the gate electrode. The top surface of the gate cap layer is aligned with or coplanar with the top surface of the lower ILD layer.

[0063] In other embodiments, this disclosure relates to an integrated circuit device. A transistor structure is disposed on a substrate and includes a pair of source / drain regions and a gate electrode between the pair of source / drain regions. A gate cap layer is disposed on the gate electrode. A lower etch stop layer is lining the sidewalls of the gate electrode and the gate cap layer. Lower source / drain contacts are disposed on the side of the lower etch stop layer opposite to the gate electrode and extend to the first source / drain region in the pair of source / drain regions.

[0064] In other embodiments, this disclosure relates to a method of forming an integrated circuit device. The method includes: forming a transistor structure disposed on a substrate and including a pair of source / drain regions and a gate electrode between the pair of source / drain regions; and forming a lower etch stop layer and an interlayer dielectric (ILD) layer over the pair of source / drain regions and around the gate electrode. The method further includes: recessing the gate electrode and forming a gate cover precursor layer on the recessed gate electrode; and forming lower source / drain contacts over the source / drain regions of the pair of source / drain regions. The method further includes: replacing the gate cap precursor layer with a gate cap layer, the gate cap layer having a lower dielectric constant than the gate cap precursor layer; and forming an upper ILD layer over the lower ILD layer and the gate cap layer. The method further includes: forming a gate contact that extends through the upper ILD layer and the gate cap layer and reaches the gate electrode.

[0065] The foregoing has outlined features of several embodiments or examples, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

[0066] Example 1. An integrated circuit device comprising: a transistor structure disposed on a substrate and including a pair of source / drain regions and a gate electrode between the pair of source / drain regions; a lower interlayer dielectric (ILD) layer disposed on the pair of source / drain regions and surrounding the gate electrode, the gate electrode being recessed from the top of the lower ILD layer; and a gate cap layer disposed on the gate electrode; wherein the top surface of the gate cap layer is aligned with the top surface of the lower ILD layer.

[0067] Example 2. The integrated circuit device according to Example 1, wherein the gate cap layer comprises a low-k dielectric material.

[0068] Example 3. The integrated circuit device according to Example 1 further includes: an upper ILD layer disposed above the gate cap layer and the lower ILD layer; and a gate electrode contact configured to pass through the upper ILD layer and the gate cap layer and reach the gate electrode.

[0069] Example 4. The integrated circuit device according to Example 3 further includes: a lower source / drain contact disposed on a source / drain region of the pair of source / drain regions; a source / drain capping layer disposed on the lower source / drain contact; and an upper source / drain contact configured to pass through the upper ILD layer and the source / drain capping layer to reach the lower source / drain contact.

[0070] Example 5. The integrated circuit device according to Example 4, wherein the source / drain cap layer comprises silicon carbide or silicon nitride.

[0071] Example 6. An integrated circuit device according to Example 4, wherein the gate cap layer and the source / drain cap layer have top surfaces aligned with each other.

[0072] Example 7. The integrated circuit device according to Example 4 further includes: a lower etch stop layer lining the sidewall of the lower ILD layer; wherein the lower etch stop layer contacts the sidewall of the lower source / drain contact.

[0073] Example 8. An integrated circuit device according to Example 7, wherein the top surface of the lower etch stop layer is aligned with the top surfaces of the gate cap layer and the source / drain cap layer.

[0074] Example 9. The integrated circuit device according to Example 4 further includes: an upper etch stop layer disposed between the upper ILD layer and the lower ILD layer; wherein the bottom surface of the upper etch stop layer contacts the gate cap layer and the source / drain cap layer.

[0075] Example 10. The integrated circuit device according to Example 4 further includes: a body contact comprising a first portion and a second portion, wherein the first portion is configured to pass through the upper ILD layer and the gate cap layer, and wherein the second portion is configured to pass through the upper ILD layer and the source / drain cap layer.

[0076] Example 11. An integrated circuit device comprising: a transistor structure disposed on a substrate and including a pair of source / drain regions and a gate electrode between the pair of source / drain regions; a gate cap layer disposed on the gate electrode; a lower etch stop layer lining the sidewalls of the gate electrode and the gate cap layer; and a lower source / drain contact disposed on the side of the lower etch stop layer opposite to the gate electrode and extending to the source / drain region of the pair of source / drain regions.

[0077] Example 12. The integrated circuit device according to Example 11 further includes: a source / drain cap layer disposed on the lower source / drain contact.

[0078] Example 13. The integrated circuit device according to Example 12 further includes: an upper ILD layer disposed above the gate cap layer, the lower etch stop layer, and the source / drain cap layer.

[0079] Example 14. The integrated circuit device according to Example 13 further includes: an upper source / drain contact configured to pass through the upper ILD layer and the source / drain cap layer and reach the lower source / drain contact.

[0080] Example 15. The integrated circuit device according to Example 13 further includes: a gate electrode contact configured to pass through the upper ILD layer and the gate cap layer and reach the gate electrode.

[0081] Example 16. The integrated circuit device according to Example 13 further includes: a body contact comprising a first portion and a second portion, wherein the first portion is configured to pass through the upper ILD layer and the gate cap layer, and wherein the second portion is configured to pass through the upper ILD layer and the source / drain cap layer.

[0082] Example 17. The integrated circuit device according to Example 11 further includes: a sidewall spacer disposed between the gate electrode and the lower etch stop layer.

[0083] Example 18. The integrated circuit device according to Example 17 further includes: an upper etch stop layer disposed on the gate cap layer, the lower etch stop layer and the sidewall spacer.

[0084] Example 19. A method of manufacturing an integrated circuit device, comprising: forming a transistor structure disposed on a substrate and including a pair of source / drain regions and a gate electrode between the pair of source / drain regions; forming a lower etch stop layer and a lower interlayer dielectric (ILD) layer over the pair of source / drain regions and around the gate electrode; recessing the gate electrode and forming a gate cap precursor layer on the recessed gate electrode; forming a lower source / drain contact over the source / drain regions of the pair of source / drain regions; replacing the gate cap precursor layer with a gate cap layer, the dielectric constant of the gate cap layer being less than the dielectric constant of the gate cap precursor layer; forming an upper ILD layer over the lower ILD layer and the gate cap layer; and forming a gate contact that passes through the upper ILD layer and the gate cap layer and reaches the gate electrode.

[0085] Example 20. The method according to Example 19 further includes: forming a source / drain capping layer on the lower source / drain contact before forming the upper ILD layer; and forming an upper source / drain contact that passes through the upper ILD layer and the source / drain capping layer and reaches the lower source / drain contact.

Claims

1. An integrated circuit device, comprising: A transistor structure disposed on a substrate and including a pair of source / drain regions and a gate electrode between the pair of source / drain regions; A lower interlayer dielectric (ILD) layer is disposed above the pair of source / drain regions and surrounds the gate electrode, the gate electrode being recessed from the top of the lower ILD layer; as well as A gate cap layer is disposed on the gate electrode, wherein the gate cap layer comprises a low-k dielectric material; The lower etch stop layer is lined within the sidewall of the gate electrode and is also lined within and contacts the sidewall of the gate cap layer. A sidewall spacer is disposed between the gate electrode and the lower etch stop layer, the sidewall spacer having an upper surface that contacts the lower surface of the gate cap layer and an upper sidewall that contacts the lower sidewall of the gate cap layer. A first source / drain contact is disposed on the source / drain region of the pair of source / drain regions; and The contact structure includes a first portion and a second portion, wherein the first portion is configured to pass through the gate cap layer, and wherein the second portion contacts the first source / drain contact. The top surface of the gate cap layer is aligned with the top surface of the lower ILD layer.

2. The integrated circuit device according to claim 1, wherein, The gate cap layer includes a carbon-doped oxide dielectric SiCOH composed of Si, C, O and H, a low-hydrogen-content silicon oxycarbonate SiOCN, or silicon oxycarbonate SiOC.

3. The integrated circuit device according to claim 1, further comprising: An upper ILD layer is disposed above the gate cap layer and the lower ILD layer; as well as The gate electrode contact is configured to pass through the upper ILD layer and the gate cap layer and reach the gate electrode.

4. The integrated circuit device according to claim 3, further comprising: A source / drain cap layer is disposed on the first source / drain contact; as well as The second source / drain contact is configured to pass through the upper ILD layer and the source / drain cap layer to reach the first source / drain contact.

5. The integrated circuit device according to claim 4, wherein, The source / drain capping layer comprises silicon carbide or silicon nitride.

6. The integrated circuit device according to claim 4, wherein, The gate cap layer and the source / drain cap layer have top surfaces aligned with each other.

7. The integrated circuit device according to claim 4, wherein, The lower etch stop layer contacts the first source / drain contact and the sidewall of the source / drain cap layer.

8. The integrated circuit device according to claim 7, wherein, The top surface of the lower etch stop layer is aligned with the top surfaces of the gate cap layer and the source / drain cap layer.

9. The integrated circuit device according to claim 4, further comprising: An upper etch stop layer is disposed between the upper ILD layer and the lower ILD layer; The bottom surface of the upper etch stop layer contacts the gate cap layer and the source / drain cap layer.

10. The integrated circuit device according to claim 3, wherein, The first and second portions are configured to pass through the upper ILD layer.

11. An integrated circuit device, comprising: A transistor structure disposed on a substrate and including a pair of source / drain regions and a gate electrode between the pair of source / drain regions; A gate cap layer is disposed on the gate electrode; The lower etch stop layer is lined within the sidewall of the gate electrode and is also lined within and contacts the sidewall of the gate cap layer. A sidewall spacer is disposed between the gate electrode and the lower etch stop layer, the sidewall spacer having an upper surface that contacts the lower surface of the gate cap layer and an upper sidewall that contacts the lower sidewall of the gate cap layer. The lower source / drain contact is disposed on the side of the lower etch stop layer opposite to the gate electrode and extends to the source / drain region of the pair of source / drain regions; as well as A gate electrode contact is configured to pass through the gate cap layer and reach the gate electrode.

12. The integrated circuit device according to claim 11, further comprising: A source / drain cap layer is disposed on the lower source / drain contact.

13. The integrated circuit device according to claim 12, further comprising: The upper ILD layer is disposed above the gate cap layer, the lower etch stop layer, and the source / drain cap layer.

14. The integrated circuit device according to claim 13, further comprising: The upper source / drain contact is configured to pass through the upper ILD layer and the source / drain cap layer and reach the lower source / drain contact, wherein the upper source / drain contact is separated from the gate electrode through the source / drain cap layer.

15. The integrated circuit device according to claim 13, wherein, The gate electrode extends upward through the upper ILD layer.

16. The integrated circuit device according to claim 13, further comprising: The contact structure includes a first part and a second part, wherein the first part is configured to pass through the upper ILD layer and the gate cap layer, and wherein the second part is configured to pass through the upper ILD layer and the source / drain cap layer.

17. The integrated circuit device according to claim 11, further comprising: An upper etch stop layer is disposed on the gate cap layer and the lower etch stop layer.

18. A method for manufacturing an integrated circuit device, comprising: A transistor structure is formed, the transistor structure being disposed on a substrate and including a pair of source / drain regions and a gate electrode between the pair of source / drain regions; A lower etch stop layer and a lower interlayer dielectric (ILD) layer are formed above the pair of source / drain regions and around the gate electrode; The gate electrode is recessed and a gate cap precursor layer is formed on the recessed gate electrode; A lower source / drain contact is formed above the source / drain region in the pair of source / drain regions; A gate cap layer is used to replace the gate cap precursor layer, wherein the dielectric constant of the gate cap layer is smaller than the dielectric constant of the gate cap precursor layer. An upper ILD layer is formed on top of the lower ILD layer and the gate cap layer; as well as A gate contact is formed, which passes through the upper ILD layer and the gate cap layer and reaches the gate electrode.

19. The method of claim 18, further comprising: Before forming the upper ILD layer, a source / drain capping layer is formed on the lower source / drain contact; as well as An upper source / drain contact is formed, which passes through the upper ILD layer and the source / drain cap layer and reaches the lower source / drain contact.

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