Packaged high voltage mosfet device with connection clip and manufacturing process thereof

Abstract

The present disclosure relates to a packaged high voltage MOSFET device with a connection clamp and a manufacturing process thereof. The HV MOSFET device has a body with a source conduction region integrated. A protruding gate structure is disposed over the body laterally offset from the source conduction region. A source contact region of a first metal is arranged on the body in electrical contact with the source conduction region and a source connection region of a second metal is arranged over the source contact region and has a height raised relative to the protruding gate structure. A package includes a metal support bonded with a second surface of the body and a dissipation region over a first surface of the semiconductor die. The dissipation region includes a conductive plate having a flat face bonded with the source connection region and spaced apart from the protruding gate structure. A package mass of dielectric material is disposed between the support and the dissipation region and incorporates the semiconductor die.

Description

Technical Field

[0001] This disclosure relates to a packaged high-voltage MOSFET device with a connection clamp and a manufacturing process thereof. Background Technology

[0002] As is well known, high-voltage and / or high-current MOSFET devices are widely used in applications (e.g., power conversion) where they are subjected to high or very high bias voltages (values ​​as high as 1000V-2000V) and are driven by currents that may switch rapidly.

[0003] Therefore, special measures are required in the packaging of these devices to ensure the necessary electrical insulation and appropriate spacing between the leads associated with the gate, source and drain terminals, and to ensure the necessary heat dissipation to the outside.

[0004] High-voltage and / or high-current MOSFET devices are formed in a die of semiconductor material (typically silicon) having a first main surface (typically the back surface) carrying drain pads and a second main surface (typically the front surface) opposite the first main surface carrying source and gate pads.

[0005] The die is bonded to a conductive support known as a "leadframe," which has leads for external connections to the MOSFET device terminals. Specifically, the drain pad is typically bonded to a leadframe carrier, which also serves a heat dissipation function; the gate and source leads are coupled to the gate and source pads, respectively, via bonding wires, clamps, or jigs. The die / leadframe assembly is encapsulated in a large amount of resin or other encapsulating insulating material.

[0006] Traditional packages for MOSFET devices are typically vertically arranged and include a single bottom-projecting lead (usually parallelepiped in shape) for electrical coupling to a PCB (printed circuit board). A suitable heat sink (usually a thin metal sheet) is coupled to the package structure, which is also vertically arranged relative to the PCB.

[0007] In order to achieve increasingly compact dimensions in terms of thickness, horizontal packages, such as SMD (Surface Mount Device) type packages, have been developed.

[0008] For example, Italian Patent No. 102018000004209 (corresponding to US10,720,373) describes a power semiconductor device formed from a die, and a package housing the die. The die has multiple protruding gate regions spaced apart from each other by windows having contact areas disposed therein. A dissipative plate formed of an insulating multilayer is disposed on the die and includes a bottom metal layer with a shape opposite to that of the protruding gate regions. Specifically, the bottom metal layer has contact protrusions extending within the windows and electrically contacting the contact areas. Summary of the Invention

[0009] In various embodiments, this disclosure provides improved packaged high-voltage MOSFET devices to allow them to be used in applications requiring high voltage and, possibly, high current capabilities.

[0010] According to this disclosure, a packaged high-voltage HV MOSFET device and its manufacturing process are provided.

[0011] In at least one embodiment, a packaged high-voltage (HV) MOSFET device is provided. The packaged high-voltage (HV) MOSFET device includes a body comprising a plurality of source conductive regions and having a first surface and a second surface. A plurality of protruding gate structures are disposed on the first surface of the body, wherein the protruding gate structures are laterally offset relative to the plurality of source conductive regions. A plurality of source contact regions of a first metal are disposed on the first surface of the body and electrically contact the plurality of source conductive regions. A plurality of source connection regions of a second metal extend over the plurality of source contact regions and have a height that protrudes relative to the protruding gate structures. A package contains a semiconductor die therein and includes a metal support of dielectric material, a dissipative region, and a package mass. The metal support is bonded to the second surface of the semiconductor die. The dissipative region extends over the first surface of the body and includes a conductive plate having a flat surface bonded to the plurality of source connection regions and spaced apart from the protruding gate structures. The package mass extends between the support and the dissipative region and incorporates the semiconductor die.

[0012] In at least one embodiment, a process for manufacturing a high-voltage (HV) MOSFET device is provided, the process comprising: forming a semiconductor die having a body including a plurality of source conductive regions and having a first surface and a second surface; forming a plurality of protruding gate structures on the first surface of the body, the protruding gate structures being laterally offset relative to the plurality of source conductive regions; forming a plurality of source contact regions of a first metal on the first surface of the body, the plurality of source contact regions being in electrical contact with the plurality of source conductive regions; and forming a plurality of source connection regions of a second metal over the plurality of source contact regions, the plurality of source connection regions having The package comprises: a height relative to the protrusion of the prominent gate structure; and forming a package therein to house a semiconductor die, the package comprising: bonding the semiconductor die to a metal support; coupling a second surface of a body to the support; coupling a first surface of the body to a dissipation region including a conductive plate having a flat surface by bonding a flat surface of a conductive plate to a plurality of source connection regions, such that the flat surface of the conductive plate extends a distance from the protruding gate structure; and a package mass body feeding dielectric material such that the package mass body fills the space between the support and the dissipation region and incorporates the semiconductor die, thereby forming the package. Attached Figure Description

[0013] To better understand this disclosure, embodiments thereof will now be described by way of non-limiting example with reference to the accompanying drawings, in which:

[0014] Figure 1A It is along Figure 1B A cross-sectional view of a portion of a power MOSFET device taken by the cross-section line IA-IA;

[0015] Figure 1B It is along Figure 1A The section line IB-IB intercepts Figure 1A A cross-sectional view of a MOSFET device;

[0016] Figure 2 This is a bottom view of a portion of a power MOSFET device;

[0017] Figure 3 This is a top view of the power MOSFET device before the dissipation plate 2 is coupled to the bare die 3;

[0018] Figure 4A It is along Figure 4B A cross-sectional view of a portion of a high-voltage device taken from the cross-sectional line IVA-IVA;

[0019] Figure 4B It is along Figure 4A The cross-section of the device is taken by the IVB-IVB section line;

[0020] Figure 5This is a schematic top view of the bare die of the high-voltage device before it is coupled to the dissipation plate;

[0021] Figure 6A and Figure 6B These are before and after the dissipation plate coupled to the high-voltage device, respectively. Figure 5 A perspective top view of the nude film;

[0022] Figures 7 to 10 In subsequent manufacturing steps Figure 4A and Figure 4B A cross-sectional view of the bare die;

[0023] Figure 11 This is a schematic diagram of the molding process for high-voltage devices;

[0024] Figure 12 This is a perspective top view of the high-voltage device in Figure 6 at the end of manufacturing;

[0025] Figure 13 Cross sections of different high-voltage devices are shown;

[0026] Figure 14 A cross-section of an embodiment of the high-voltage device is shown;

[0027] Figure 15 A cross-section of another embodiment of the high-voltage device is shown;

[0028] Figure 16A and Figure 16B Side views and perspective views of different embodiments of the high-voltage device are shown; and

[0029] Figure 17A and Figure 17B A side view and perspective view of another embodiment of the high-voltage device are shown. Detailed Implementation

[0030] Figure 1A , Figure 1B , Figure 2 and Figure 3 Comparative examples of embodiments are illustrated, each relating to two cross-sections of a portion of a power semiconductor device indicated by 1, a perspective view of a dissipation plate indicated by 2, and a top view of a die indicated by 3. The die 3 houses multiple basic units (or cells) of MOSFET transistors, which are arranged in a strip having a vertical columnar structure. Specifically, Figure 1 shows a portion of the power device 1 forming the basic units. Figure 2 , Figure 3 In the simplified representation shown, die 3 includes three basic units, but the number of basic units can vary depending on design requirements, particularly the value of the operating charge of power device 1.

[0031] The bare die 3 includes a silicon substrate 5 forming a drain region. The silicon substrate 5 has a rear surface 5A, and a first metal layer 6 extends at the rear surface 5A to form a drain metallization layer. The substrate 5 integrates conductive regions. Figure 1B Only the main conductive region 4 and the source region 7 are shown in the diagram.

[0032] Figure 1A The gate conductive region 8 (connected to) is also shown. Figure 1B The visible lateral gate portion 8' is present; the gate conductive region 8 and the lateral gate portion 8' are disposed on the front surface 5B of the substrate 5 and surrounded by a gate insulating region 9, which is formed in a known manner by a field oxide layer (below the gate conductive region 8 and the lateral gate portion 8') and an intermetallic oxide layer (on the gate conductive region 8 and the lateral gate portion 8'). A metal gate contact region 12 (gate metallization layer 12, in...) is also present. Figure 1A Only one of the gate contact regions (visible in the middle) extends above the gate conductive region 8 and is in electrical contact with the gate conductive region 8. The sides and top of the gate contact region 12 are surrounded by the gate passivation region 13. Figure 3 As shown, each gate contact region 12 extends approximately along the entire length of the strip forming the basic unit (in a direction parallel to the first Cartesian axis Y), where the gate contact regions 12 (so-called gate fingers) are represented in a simplified manner by lines. The gate contact regions 12 allow biasing of all gate conductive regions 8 and lateral gate portions 8' of the power device 1, and can be continuous, or, as in the example shown, have interruptions and breaks along their longitudinal extension.

[0033] For example, the source contact region 15 (source metallization layer 15) of AlCu extends laterally over the substrate 5 to the gate insulating region 9 and the gate passivation region 13. The source contact region 15 is formed by rods 15A that extend along the entire length of the strip forming the basic unit, contacting the substrate 5 (wherein they contact the source region 7). Figure 1B In fact, the source contact region 15 extends between the gate passivation regions 13 of adjacent basic units.

[0034] like Figure 1A As indicated in the document, in each basic unit, the source contact region 15 has a top surface extending below the level of the gate passivation region 13; in fact, the gate passivation region 13 extends partially above the source contact region 15; therefore, the metal gate region 12 and the gate passivation region 13 protrude in height relative to the source contact region 15, and also as... Figure 3 As shown, this forms a prominent gate region 16 and a lateral demarcation window 17.

[0035] A thin metal layer 18 (e.g., TiNiVAg) covers the source contact region 15 (electrically connected thereto) and the gate passivation region 13, and is bonded to the dissipation plate 2 via a solder layer 19.

[0036] Dissipative plate 2 is formed, for example, from multiple layers of DBC (direct bonded copper), such as Figure 2 As shown, the DBC multilayer is formed by a bottom metal layer 20A, a top metal layer 20B (both copper), and an intermediate insulating layer 20C of ceramic (e.g., alumina (Al2O3), aluminum nitride (AlN), or beryllium oxide (BeO)). Layers 20A-20C are coupled together by high-temperature eutectic bonding. The intermediate insulating layer 20C electrically insulates the bottom and top metal layers 20A and 20B; the bottom layer 20A is bonded to the bare die 3 via a connection portion not shown.

[0037] The bottom layer 20A is shaped to form a protrusion 21, and a cavity 22 extends within the protrusion 21. For example... Figure 2 As indicated in the document, the protrusion 21 and cavity 22 actually extend the entire length of the dissipation plate 2, which is parallel to the basic unit formed by the die 3 (parallel to the first Cartesian axis Y). The dissipation plate 2 is bonded to the die 3 such that the protrusion 21 extends in the window 17 (FIG. 1) and is soldered to the die 3 at the source contact area 15 (and as shown in the document). Figure 1A As can be seen, it is electrically contacted through the thin metal layer 18 and the solder layer 19. In addition, each cavity 22 covers the corresponding protruding gate region 16 at a certain distance.

[0038] Even for power devices operating at high voltages (up to 1600-2000V), the above solution can achieve a very compact structure, and can be cooled on both sides and electrically insulated on one or both larger sides.

[0039] However, the dissipation plate 2 is quite complex to manufacture because it is specifically extruded on a particular die 3. The protrusions 21 and cavities 22 of the bottom layer 20A are therefore specifically designed and adapted to the specific layout of the die 3. In particular, the arrangement and dimensions of the protrusions 21 and cavities 22 will be studied to vary according to the number, width and / or length of the basic cells, the protruding gate regions 16 and the windows 17 of the die 3.

[0040] Furthermore, the placement of the dissipation plate 2 is precise and critical: in fact, the protrusion 21 is precisely positioned and aligned with the window 17 to avoid contact with the protruding gate region 16, and especially with the gate passivation region 13. Indeed, any improper placement could damage the gate passivation region 13, risking loss of electrical insulation between the gate contact region 12 and the thin metal layer 18, thus leading to a failure of the power semiconductor device 1.

[0041] Figure 4A , Figure 4B and Figure 5 A high-voltage MOSFET device 30 with an overall structure similar to the power semiconductor device 1 of FIG1 is shown, therefore only the common parts are briefly described.

[0042] As in the power semiconductor device 1 of Figure 1, the high-voltage MOSFET device 30 includes a die 31 that is bonded to a dissipation plate 32 and houses a plurality of basic units (or cells) of MOSFET transistors, which are arranged as strips with vertical columnar structures.

[0043] In particular, Figure 4A A portion of the basic unit forming a high-voltage MOSFET device 30 is shown. Figure 5 In the simplified representation shown, die 31 includes three basic units, but the number of basic units can vary according to design specifications.

[0044] The die 31 includes a silicon substrate 35 of a first conductivity type, the silicon substrate 35 forming a drain region and having a back surface 35A, where a drain metallization layer 36 extends. Figure 4B As can be seen in the cross-section, the body region 34 and the source region 37 of the second conductivity type extend in the substrate 35 and face the front surface 35B of the substrate 35.

[0045] exist Figure 4A In the basic unit shown, the gate conductive region 38 is disposed on the front surface 35B of the substrate 35 and surrounded by the gate insulating region 39, which is interrupted at only one point to allow electrical connection between the gate conductive region 38 and the metal gate contact region 42 extending on the gate conductive region 38.

[0046] In a known manner, the gate conductive region 38 is connected to Figure 4B The visible transverse gate portion 38' is also surrounded by a corresponding portion of the gate insulating region 39.

[0047] Each gate contact region 42 is surrounded on its sides and top by a gate passivation region 43, which includes a bottom portion 43A and a top portion 43B formed by one or more dielectric layers. Figure 5 As shown, each gate contact region 42 extends approximately along the entire length of the strip forming the basic unit (parallel to the first Cartesian axis Y), but can be interrupted. The gate contact region 42 allows all gate conductive regions 38 and lateral gate portions 38' of the basic unit of the high-voltage device 30 to be biased and can be continuous, or, as in the example shown, have interruptions along its longitudinal direction.

[0048] Source contact regions 45, such as AlCu, with a thickness between 3 and 6 μm, extend over the substrate 35, laterally to the gate insulating region 39 and the gate passivation region 43. The source contact regions 45 extend the entire length of the basic unit between adjacent basic units of the gate passivation region 43, parallel to the first Cartesian axis Y, and contact the substrate 35 (where they contact the source 37 and the body region 34).

[0049] The top 43B of the gate passivation region 43 extends at a higher level than the source contact region 45 and is partially disposed above the source contact region 45. The metal gate region 42 and the gate passivation region 43 thus form a protruding gate region 46 that is higher than the source contact region 45 and the lateral demarcation window 47 (see also...). Figure 5 ).

[0050] Metal and thick source connection regions 48 extend above and are electrically in contact with rod 45 within window 47. For example, copper source connection regions 48 have a thickness that causes them to protrude from window 47, such that their top surface, indicated by 48A in FIG. 4, protrudes from window 47 and is at a higher level than the top 43B of gate passivation region 43 (see also...). Figure 6A The thickness of the source connection region 48 can be between 2 and 15 μm, for example, 10 μm.

[0051] Here, too Figure 6B As shown, the dissipation plate 32 has a parallelepiped shape and a flat, planar bottom surface 32A, which is coupled to the source connection region 48 via solder portions 49. Therefore, in this embodiment, the dissipation plate 32 is in electrical contact with the source region 37 and forms a source pad.

[0052] Because the source connection region 48 has a height that protrudes from the window 47, the dissipation plate 32 extends vertically at a distance from the gate passivation region 43 and therefore from the gate contact region 42. Thus, the dissipation plate 32 is safely electrically insulated from the gate contact region 42.

[0053] Because the dissipation plate 32 has a flat bottom surface, it allows for standard dimensions regardless of the structure of a particular die 31, and in particular regardless of the number, shape, and size of the protruding gate regions 46, as discussed below. Therefore, as described below, it simplifies the manufacturing process of the high-voltage MOSFET device 30, and its placement and soldering are not critical.

[0054] The fabrication process of the HV MOSFET device 30 includes known initial steps for forming the electrically active regions of the device inside and on the surface of the substrate 35.

[0055] Specifically, refer to Figure 7 The initial manufacturing steps specifically include:

[0056] A host region 34 is formed in the substrate 35;

[0057] A field oxide region (not shown, forming the bottom of the gate insulating region 39 in FIG4) is grown on the front surface 35B of the substrate 35;

[0058] For example, by depositing and defining a polysilicon layer, a gate conductive region 38 is formed over a field oxide region (not shown). Figure 7 (Illustrative representation in Chinese);

[0059] An intermetallic oxide region (not shown, forming the top of the gate insulating region 39 in FIG4) is formed above the gate conductive region 38;

[0060] A source region 37 is formed in the substrate 35;

[0061] For example, a single AlCu metal layer is defined by deposition and photolithography to form gate contact region 42 and source contact region 45; and

[0062] For example, the gate passivation region 43 is formed by depositing one or more passivation layers with a thickness of 1-10 μm, forming a bottom portion 43A of the gate passivation region 45 (which extends between the gate contact region 42 and the source contact region 45) and a top portion 43B of the gate passivation region 45 (which extends above the gate contact region 42 and partially above the source contact region 45).

[0063] Therefore, the gate passivation region 43 together with the gate conductive region 38 (and the gate insulating region 39 of FIG4) forms a protruding gate region 46, and windows 47 are defined between the gate regions 46.

[0064] The process then includes the steps of forming a barrier layer 50, such as titanium-tungsten, with a sputtering thickness of 0.2 nm and covering the top portion 43B of the source contact region 45 and the gate passivation region 43; forming a seed layer 51, such as copper, with a sputtering thickness of 0.1 nm; and forming a redistribution mask 52, which covers the area where the source connection region 48 does not need to be formed and has an opening slightly wider than the window 47 (therefore referred to as such hereinafter). Thus, obtaining... Figure 7 The intermediate structure.

[0065] Then, in Figure 8 In this process, electroplating copper growth is performed, with a thickness greater than that of the gate passivation region 43. For example, electroplating growth can continue until a thickness between 2 and 15 μm, such as 10 μm, is obtained.

[0066] Therefore, the source connection region 48 is formed at a location where there is no redistribution mask 52 (at window 47).

[0067] Subsequently, Figure 9In this process, the redistribution mask 52 is removed and the portions of the seed layer 51 and the barrier layer 50 above the top portion 43B of the gate passivation region 43 are removed.

[0068] Then, the back surface 35A of the substrate 35 is polished and the drain metallization layer 36 is deposited.

[0069] After the wafer is diced to separate individual dies 31, each die 31 is packaged in a known manner.

[0070] Specifically, for this purpose and with reference Figure 10 A first solder paste layer 54 is deposited on the support portion 55D of the conductive support 55 (also referred to as the “lead frame”), the conductive support 55 being properly shaped and provided with leads, the source leads 55S of which are visible.

[0071] The die 31 is then placed on the support portion 55D of the conductive support 55 (forming a drain lead), wherein the drain metallization layer 36 contacts the first solder paste layer 54. The die 31 is thus coupled to the lead frame 55.

[0072] The gate pad (invisible) is coupled to the invisible gate lead (in) via a wire (also invisible). Figure 12 (Using 55G to indicate).

[0073] A second solder paste layer 56 is deposited on the source connection region 48 to form the solder region 49 of FIG4; and a dissipation region 32 is placed on the second solder paste layer 56 and the source lead 55S. In particular, the dissipation region 32 is formed here by a fixture 57 having a flat portion 57A.

[0074] Specifically, the flat portion 57 has a flat connection surface 57', which is simply "placed" on the source connection region 48 and centered relative to the die 31 using a standard centering mark.

[0075] The clamp 57 also has a folded portion 57B and a lower portion 57C located directly on the source lead 55S.

[0076] Then, the resin encapsulation 58 is molded to insulate the bare die 31. Specifically, as... Figure 11 As shown, the resin fluid mass indicated by 59 flows in a direction parallel to the flat portion 57A of the clamp 57 to fill the space between the die 31 and the clamp 57, as well as the space between the support portion 55D of the lead frame 55, the source lead 55S, and the gate lead (not visible). Figure 10 ).

[0077] Figure 12The resulting high-voltage MOSFET device 30 is shown. In this case, the high-voltage MOSFET device 30 is doubly (thermally and electrically) exposed to dual-sided cooling via the support portion 55D of the lead frame 55 and the flat portion 57A of the clamp 57.

[0078] The above solutions can be used to form, for example, Figure 13 The diagram shows a fully packaged high-voltage MOSFET device using the 60 specification. Here, the dissipation region 32 is composed of... Figure 10 The same clamp 57 is formed, and the sealing resin 59 also extends on and covers the flat portion 57A of the clamp 57. Therefore, the clamp 57 is no longer exposed and the high-voltage MOSFET device 60 is electrically insulated on the top side.

[0079] like Figure 14 As shown, the dissipation region 32 can also be formed by multiple layers. Here, the high-voltage MOSFET device indicated by 70 has a DBC (direct-bonded copper) multilayer 71, which is formed by a bottom metal layer, a flat portion 57A of the clamp 57, a top metal layer 73 of copper, and an intermediate insulating layer 72 of ceramic (e.g., aluminum oxide (Al2O3), aluminum nitride (AlN), or beryllium oxide (BeO)). The intermediate insulating layer 72 electrically insulates the top metal layer 73 and the bottom metal layer 57A; the bottom layer 57A is bonded to the die 31 in the manner described above.

[0080] therefore, Figure 14 The high-voltage MOSFET device 70 is doubly exposed and has dual-sided cooling and is isolated only at the top.

[0081] Figure 14 The high-voltage MOSFET device 70 can be used in applications requiring high voltage.

[0082] In practice, the bottom metal layer 57A is decoupled from the top metal layer 73 via the intermediate insulating layer 72, and can be molded and sized as required, without being limited by the safety distance (so-called creepage distance) between areas with very different electrical differentials, which is considered during the design phase and may limit design freedom. Therefore, in Figure 14 In the high-voltage MOSFET device 70, the top metal layer 73 is safely decoupled from the source connection region 48, and its distance from the drain metallization layer 36 is not critical. Therefore, the top metal layer 73 can be designed with a large area and can ensure extremely high dissipation.

[0083] High-voltage MOSFET devices can also include multiple dies connected in parallel. For example, Figure 15A high-voltage MOSFET device 80 is shown, which incorporates two dies 31, a single lead frame 55, and a single dissipation region 32, also formed here by a fixture 57. Here, the flat portion 57A of the fixture 57 is planarly soldered to the source connections 48 of the two dies 31, and electrically coupled to each other and to the source leads 55S.

[0084] Therefore, more dies can be coupled in parallel, thereby reducing the resistance R of the high-voltage MOSFET device 80. DSon As a result, the safe operating area of ​​the high-voltage MOSFET device 80 is expanded, and the device can operate at higher currents.

[0085] like Figure 16A , Figure 16B , Figure 17A , Figure 17B As shown, the dissipation region 32 may or may not completely cover one or more dies 31.

[0086] In particular, Figure 16A and Figure 16B An embodiment is shown in which the dissipation region 32 forms a clamp 57, the planar portion 57A of which has a larger area relative to the bare die 31 to completely cover its top surface 31A. Similarly, the clamp 57 has a lower portion 57C for connection to the source lead 55S.

[0087] Furthermore, the dissipation region 32 consists of multiple layers (e.g. Figure 14 The DBC multilayer 71 shown is formed.

[0088] on the contrary, Figure 17A and Figure 17B An embodiment is shown in which the dissipation region 32 does not completely cover the die 31; here, the dissipation region 32 (again formed as a clamp 57) exposes a portion of the top surface 31A of the die 31 and has a lower portion 57C for connection to the source lead 55S.

[0089] Similarly, in this case, the dissipation region 32 consists of multiple layers (e.g., Figure 14 The DBC multilayer 71 shown is formed.

[0090] The HV MOSFET devices described in this article have many advantages.

[0091] In fact, the presence of the source connection region 48 allows the use of a dissipation plate with a flat bottom surface; this allows the dissipation plate to be designed and sized so that it can be used for HV MOSFET devices of different sizes and layouts, regardless of the shape, number and size of the contact windows, as the flat portion 57A can completely or partially cover the underlying die, as mentioned above.

[0092] Furthermore, the fabrication and arrangement of the dissipation plate, as well as its bonding to the die, are simplified. In particular, centering is not critical, and small centering errors do not pose a risk of damaging the die or causing reliability issues in HV MOSFET devices.

[0093] Easier assembly and easier fabrication of the protruding source contact portion (source connection region 48) directly on the die in the final step of the wafer-level manufacturing process allow for reduced manufacturing costs.

[0094] By determining the size of the protruding contact portion at a suitable height, there is no creepage problem. That is, the areas placed at very different electrical differentials are extremely close to each other, thus allowing for the formation of a small number of dissipation regions of different sizes for a variety of dies, even with small volume and high layout variability.

[0095] If the dissipative plate is part of a multilayer structure, high electrical insulation can be achieved, while maintaining high heat dissipation and low parasitic phenomena.

[0096] Finally, it is apparent that modifications and variations can be made to the HV MOSFET devices and their fabrication processes described and illustrated herein without departing from the scope of this disclosure as defined by the appended claims. For example, the different embodiments described can be combined to provide further solutions.

[0097] For example, with Figure 16A , Figure 16B and Figure 17A , Figure 17B As shown, even if formed by multiple layers of DBC, the size of the dissipation region 32 can be greater than, equal to or smaller than the size of the bare die 31.

[0098] Packaged HV MOSFET devices can be broadly categorized as including:

[0099] Semiconductor die (31), comprising:

[0100] The main body (35) integrates multiple source conductive regions (37) and has a first surface and a second surface (35B, 35A).

[0101] Multiple protruding gate structures (46) are arranged on the first surface (35B) of the body, laterally offset relative to the source conductive region (37);

[0102] Multiple source contact regions (45) of the first metal are arranged on the first surface (35B) of the body and are in electrical contact with the source conductive region (37); and

[0103] Multiple source connection regions (48) of the second metal extend over multiple source contact regions (45) and have a height that protrudes relative to the protruding gate structure (46), and

[0104] Package (59), which houses the semiconductor die (31) and includes:

[0105] A metal support (55) is bonded to the second surface (35A) of the semiconductor die;

[0106] A dissipation region (32) extends over a first surface (35B) of the body (35) and includes a conductive plate (57) having a flat surface (57') bonded to a plurality of source connection regions (48) and spaced apart from a protruding gate structure; and

[0107] The dielectric material encapsulation mass (59) extends between the support (55) and the dissipation region (32) and incorporates the semiconductor die (31).

[0108] The multiple source connection regions (48) can be copper, and the multiple source contact regions (45) can be copper-aluminum.

[0109] The conductive plate (32) can form a flat portion of the metal clamp (57), which is coupled to at least a first lead (55S) that extends outside the package (59) and is accessible from the outside.

[0110] The dissipation region (32) may be a DBC-type insulating multilayer (71) comprising a conductive plate (57), an intermediate insulating region (72) of ceramic coupled to the conductive plate (57), and a top conductive region (73) coupled to the intermediate insulating region (72).

[0111] The encapsulated mass body (59) can cover the conductive plate (57).

[0112] The encapsulated mass body (59) can expose the conductive plate (57).

[0113] The conductive plate (57) can have a larger area than the semiconductor die (31) and can completely cover the semiconductor die.

[0114] The conductive plate (57) may not completely cover the semiconductor die (31).

[0115] The HV MOSFET device may include a second die (31) that is coupled in parallel with the semiconductor die (31), has the same structure and is supported by a support (55), and a conductive plate (57) may also be coupled to the source connection region (48) of the second die (31).

[0116] The thickness of the source connection region (48) can be between 2 and 15 μm, for example 10 μm.

[0117] The manufacturing process for HV MOSFET devices can be summarized as including:

[0118] A semiconductor die (31) is formed, the semiconductor die (31) includes a body (35), the body (35) integrates multiple source conductive regions (37) and has a first surface and a second surface (35B, 35A);

[0119] Multiple protruding gate structures (46) are formed on the first surface (35B) of the body, and the multiple protruding gate structures (46) are laterally offset relative to the source conductive region (37).

[0120] Multiple source contact regions (45) of a first metal are formed on the first surface (35B) of the body (35), and the multiple source contact regions (45) are in electrical contact with multiple source conductive regions (37).

[0121] A plurality of source connection regions (48) of a second metal are formed above the source contact region (45), the plurality of source connection regions (48) having a height that protrudes relative to the protruding gate structure (46); and

[0122] A package (59) is formed therein to house a semiconductor die and includes:

[0123] The semiconductor die (31) is bonded to the metal support (55), thereby coupling the second surface of the body to the support, and

[0124] The first surface (35B) of the body (35) is coupled to the dissipation region (32) of the conductive plate (57) including the conductive plate (57') by bonding the flat surface of the conductive plate to the source connection region (48), such that the flat surface of the conductive plate extends at a distance from the protruding gate structure (46); and

[0125] The package mass (59) that feeds dielectric material fills the space between the support (55) and the dissipation region (32) and incorporates the semiconductor die (31) to form a package.

[0126] Forming multiple source connection regions (48) may include electroplating to grow source connection regions (48).

[0127] The process may also include forming a seed layer (51) and forming a structure-defining mask (52) on the seed layer before electroplating the source contact region (48), the structure-defining mask (52) having a window (47) covering the source contact region (45).

[0128] The conductive plate (32) may form a flat portion (57A) of the metal clamp (57), which is coupled to at least one source lead (55S) that extends outside the package (59) and is accessible from the outside.

[0129] Coupling the first surface (35B) of the body (35) to the dissipation region (32) may include a coupled DBC-type insulating multilayer (71).

[0130] The various embodiments described above can be combined to provide further embodiments. Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments claimed by such claims and the full scope of their equivalents. Therefore, the claims are not limited by the disclosure.

Claims

1. A packaged high-voltage HV MOSFET device, comprising: Semiconductor dies, including: The body includes multiple source conductive regions and has a first surface and a second surface; Multiple protruding gate structures are arranged on the first surface of the body, the protruding gate structures being laterally offset relative to the source conductive region; Multiple source contact regions of a first metal are arranged on the first surface of the body and are in electrical contact with the source conductive regions; and Multiple source connection regions of the second metal extend above the source contact region and have a height that protrudes relative to the protruding gate structure; and A package that houses the semiconductor die therein, the package comprising: A metal support is bonded to the second surface of the semiconductor die; A dissipation region extends over the first surface of the body and includes a conductive plate having a flat surface bonded to the source connection region and spaced apart from the protruding gate structure; and A dielectric material encapsulation mass extends between the support and the dissipation region, and incorporates the semiconductor die. The dissipation region is a direct-bonded copper DBC type insulating multilayer, which includes the conductive plate, an intermediate insulating region coupled to the conductive plate, and a top conductive region coupled to the intermediate insulating region. The plurality of protruding gate structures include a gate conductive region and a lateral gate portion electrically connected to the gate conductive region, the lateral gate portion being located above the source conductive region on the first surface of the body.

2. The HV MOSFET device according to claim 1, wherein the source connection region is copper and the source contact region is copper-aluminum.

3. The HV MOSFET device of claim 1, wherein the conductive plate forms a flat portion of a metal clamp, the metal clamp being at least coupled to a first lead extending outside the package and accessible from the outside.

4. The HV MOSFET device according to claim 1, wherein the intermediate insulating region is ceramic.

5. The HV MOSFET device of claim 1, wherein the package mass exposes the dissipation region.

6. The HV MOSFET device of claim 1, wherein the conductive plate has an area larger than that of the semiconductor die and completely covers the semiconductor die.

7. The HV MOSFET device of claim 1, wherein the conductive plate does not completely cover the semiconductor die.

8. The HV MOSFET device of claim 1, comprising a second die coupled in parallel to the semiconductor die, the second die having the same structure as the semiconductor die and being supported by the metal support, wherein the conductive plate is coupled to the source connection region of the second die.

9. The HV MOSFET device of claim 1, wherein the source connection region has a thickness between 2 μm and 15 μm.

10. The HV MOSFET device according to claim 9, wherein the thickness of the source connection region is 10 μm.

11. A method for manufacturing a high-voltage HV MOSFET device, comprising: A semiconductor die is formed having a body comprising a plurality of source conductive regions and having a first surface and a second surface; A plurality of protruding gate structures are formed on the first surface of the body, the protruding gate structures being laterally offset relative to the source conductive region; A plurality of source contact regions of a first metal are formed on the first surface of the body, and the plurality of source contact regions of the first metal are in electrical contact with the source conductive region. A plurality of source connection regions of a second metal are formed above the source contact region, the plurality of source connection regions of the second metal having a height that protrudes relative to the protruding gate structure. as well as Forming a package to house the semiconductor die includes: The semiconductor die is bonded to a metal support, thereby coupling the second surface of the body to the support; By bonding the flat surface of a conductive plate to the source connection region, the first surface of the body is coupled to a dissipation region including the conductive plate, the conductive plate being part of a direct-bonded copper DBC-type insulating multilayer and having a flat surface, such that the flat surface of the conductive plate extends at a distance from the protruding gate structure; and A package mass body that feeds dielectric material fills the space between the support and the dissipation region, and incorporates the semiconductor die, thereby forming a package. The plurality of protruding gate structures include a gate conductive region and a lateral gate portion electrically connected to the gate conductive region, the lateral gate portion being located above the source conductive region on the first surface of the body.

12. The method of claim 11, wherein forming a plurality of source connection regions comprises: The source connection region is grown by electroplating.

13. The method of claim 12, further comprising: Before electroplating to grow the source connection region, a seed layer is formed, and a structure defining mask is formed on the seed layer, the structure defining mask having a window covering the source contact region.

14. The method of claim 11, wherein the conductive plate forms a flat portion of a metal clamp, the metal clamp being coupled to at least one source lead extending outside the package and accessible from the outside.

15. The method of claim 11, further comprising: After the semiconductor die is bonded to the support, and before the first surface of the body of the semiconductor die is bonded to the dissipation region, The bonding includes a second die comprising a second body, the second body integrating multiple second source conductive regions and having a third surface and a fourth surface, the bonding of the second die comprising the second body being performed by bonding the third surface to the support member. The coupling of the first surface of the body of the semiconductor die to the dissipation region includes coupling the fourth surface of the second body to the dissipation region.

16. A device comprising: Lead frame; A plurality of semiconductor dies are disposed on the lead frame, each of the semiconductor dies comprising: The body includes multiple source conductive regions and has a first surface and a second surface; Multiple protruding gate structures are arranged on the first surface of the body, the protruding gate structures being laterally offset relative to the source conductive region; Multiple source contact regions of a first metal are arranged on the first surface of the body and are in electrical contact with the source conductive regions; and Multiple source connection regions of the second metal extend above the source contact region and have a height that protrudes relative to the protruding gate structure; and A dissipation region extends over the first surface of the body of each semiconductor die in the semiconductor dies and includes a conductive plate with a flat surface bonded to the source connection region and spaced apart from the protruding gate structure. The plurality of protruding gate structures include a gate conductive region and a lateral gate portion electrically connected to the gate conductive region, the lateral gate portion being located above the source conductive region on the first surface of the body.

17. The device of claim 16, wherein the conductive plate completely covers the plurality of semiconductor dies.

18. The device of claim 16, wherein the conductive plate does not completely cover the semiconductor die.

19. The device of claim 16, wherein the source connection region has a thickness between 2 μm and 15 μm.

20. The device of claim 16, wherein the conductive plate is part of a direct-bonded copper DBC-type insulating multilayer.

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