Semiconductor devices and their manufacturing methods

Abstract

This disclosure provides a semiconductor device and a method for manufacturing the same, which ensures overlap and processing margin between storage nodes and storage node contact plugs by eliminating the connection structure between the storage node and the storage node contact plug. The semiconductor device includes: a storage node contact hole disposed between bit line structures; a first plug filling the lower part of the storage node contact hole; a second plug protruding from the first plug; an insulating layer spacer covering the sidewall of the second plug; and a storage node located at a level higher than the second plug and including an extension contacting another sidewall of the second plug and a portion of the top surface of the first plug.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0084606, filed on July 9, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure generally relate to a semiconductor device and a method of manufacturing the same, and more specifically, to a semiconductor device including a storage node and a method of manufacturing the semiconductor device. Background Technology

[0004] As semiconductor integration becomes increasingly sophisticated, ensuring the overlay margin between memory nodes and memory node contact plugs has become challenging. Typically, to ensure this margin, a connection structure (e.g., memory node contact plug 2 (SNC2)) is formed between the memory node and the memory node contact plug. However, this requires expensive EUV equipment and complex processing techniques. Furthermore, the fabrication margin of this connection structure is relatively small, making overlap failures between the memory node and the memory node contact plug highly likely. Therefore, a new solution is urgently needed. Summary of the Invention

[0005] According to various embodiments of this disclosure, a semiconductor device and a method for manufacturing the semiconductor device are provided, which can ensure overlap margin and processing margin between the storage node and the storage node contact plug. The semiconductor device and the method of manufacturing the same do not include a connection structure between the storage node and the storage node contact plug.

[0006] According to one embodiment, a semiconductor device includes: a storage node contact hole disposed between bit line structures; a first plug filling the lower portion of the storage node contact hole; a second plug protruding from the first plug; an insulating spacer covering one sidewall of the second plug; and a storage node located at a level higher than the second plug, and including an extension contacting the other sidewall of the second plug and a portion of the top surface of the first plug.

[0007] According to another embodiment, a semiconductor device includes: a storage node contact hole disposed between bit line structures; a first plug filling a lower portion of the storage node contact hole; a second plug protruding from the first plug; an insulating layer spacer partially covering and partially exposing one sidewall of the second plug; and an extension contacting the exposed sidewall of the second plug.

[0008] According to another embodiment, a method for manufacturing a semiconductor device includes: forming a storage node contact hole between bit line structures; forming a first plug that fills a lower portion of the storage node contact hole; forming an insulating layer spacer on the first plug that covers the sidewalls of the storage node contact hole; and forming a second plug between the insulating layer spacers that fills the remaining portion of the storage node contact hole; forming a sacrificial layer on the second plug, the insulating layer spacer, and the bit line structure; forming a storage node hole through the sacrificial layer; recessing the insulating layer spacer exposed by the storage node hole; and forming a storage node in the storage node hole.

[0009] According to another embodiment, a semiconductor device includes: a storage node contact plug disposed between bit line structures, the storage node contact plug including a first plug and a second plug located on top of the first plug; an insulating spacer covering a first sidewall of the second plug; and a storage node including an upper portion and an extension projecting from the upper portion, wherein the extension covers a second sidewall of the second plug.

[0010] This invention is advantageous over the prior art because it ensures overlap and manufacturing margins between storage nodes and storage node contact plugs by eliminating the connection structure between them. Therefore, the reliability of semiconductor devices can now be enhanced.

[0011] These and other features and advantages of the invention will be better understood through the following figures and detailed description. Attached Figure Description

[0012] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure;

[0013] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 This is a cross-sectional view illustrating a semiconductor device according to various embodiments of the present disclosure; and

[0014] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G , Figure 10H , Figure 10I and Figure 10JThis is a cross-sectional view used to describe a method of manufacturing a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0015] In the following description, embodiments of the present disclosure are illustrated with reference to schematic sectional views, plan views, or block diagrams. Changes or modifications may be made to the views depending on manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure are not limited to the specific types shown and illustrated herein, but may encompass changes or modifications resulting from manufacturing processes. For example, areas or regions shown in the figures may be schematically illustrated, and the shapes they represent are provided merely as examples and should not limit the category or scope of the present disclosure. It should also be understood that the figures are simplified schematic diagrams of the described devices and do not include well-known details to avoid obscuring the features of the invention.

[0016] It should also be noted that, without departing from the scope of the invention, a feature present in one embodiment may be used in conjunction with one or more features in another embodiment.

[0017] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure. Figures 2 to 9 This is a cross-sectional view showing a semiconductor device according to different embodiments of the present disclosure. Figures 2 to 9 It is along Figure 1 The cross-sectional view observed in the direction of the arrow. Figures 3 to 9 This is an enlarged view showing the structural features of the storage node contact plug and storage node of a semiconductor device. Figures 3 to 9 The structures shown, other than the storage node contact plug and the storage node, can be used with... Figure 2 The structures are the same.

[0018] like Figure 1 and Figure 2 As shown, the semiconductor device 100 may include a storage node contact hole 121 disposed between bit line structures 110 and a storage node contact plug 120 filling the storage node contact hole 121. The storage node contact plug 120 may include first plugs 122 and 123 filling the lower portion of the storage node contact hole 121 and a second plug 124 protruding from the first plugs 122 and 123. The semiconductor device 100 may include an insulating layer spacer 130 covering one sidewall of the second plug 124 and a storage node 160 including an extension 160a. The cross-section of the extension 160a may be smaller than the rest of the storage node 160 (which may be referred to as the upper portion of the storage node 160). The extension 160a contacts a portion of the sidewall of the second plug 124 and the top surface of the first plugs 122 and 123. The top surface of the storage node 160 is located at a level higher than the second plug 124.

[0019] Semiconductor device 100 may be part of a memory cell (also simply referred to as a cell). For example, semiconductor device 100 may be part of a dynamic random access memory (DRAM) memory cell.

[0020] Substrate 101 may include materials suitable for semiconductor processing. Substrate 101 may include a semiconductor substrate. Substrate 101 may be formed, for example, from a silicon-containing material. Substrate 101 may include, for example, single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, single-crystal silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multilayer structures thereof. Substrate 101 may include other semiconductor materials, such as germanium. Substrate 101 may include a composite semiconductor substrate, such as a Group III / V semiconductor substrate, such as GaAs. Substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0021] An element separation layer 102 and an active region 103 may be formed in the substrate 101. The active region 103 may be defined by the element separation layer 102. The element separation layer 102 may be a shallow trench isolation (STI) region formed by trench etching. The element separation layer 102 may include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0022] The gate structure 104 may be formed to extend along the short axis of the active region 103 on the substrate 101. The gate structure 104 may include a buried gate structure located at a level lower than the top surface of the substrate 101.

[0023] Bit line structure 110 may extend along the long axis of active region 103. Bit line structure 110 may intersect gate structure 104. Bit line structure 110 and gate structure 104 may be perpendicular to each other. Bit line structure 110 may include a vertical stack of bit line contacts 111, bit lines 112, and bit line hard mask 113. Bit line structure 110 may also include bit line spacers 114 covering the sidewalls of the vertical stack of bit line structure 110. Bit line contacts 111 and bit lines 112 may include metal-containing materials. Bit line 112 may include metal, metal nitride, metal silicide, or combinations thereof. Bit line 112 may include, for example, tungsten (W). According to one embodiment, bit line 112 may include, for example, a stack of ruthenium (Ru), molybdenum (Mo), or titanium nitride and tungsten (TiN / W). Titanium nitride may act as a barrier. Bit line hard mask 113 may include an insulating material. Bit line hard mask 113 may include, for example, silicon oxide or silicon nitride. Bit line spacers 114 can be formed as a multilayer structure. Bit line spacers 114 may include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0024] The bottom surface of the storage node contact hole 121 can be located at a level lower than the bottom surface of the bit line structure 110. Specifically, the width of the bottom of the storage node contact hole 121 located at a level lower than the bottom surface of the bit line structure 110 can be greater than the width of the top of the storage node contact hole 121.

[0025] The storage node contact plug 120 may include first plugs 122 and 123 that fill the lower portion of the storage node contact hole 121 and a second plug 124 that protrudes from the first plugs 122 and 123.

[0026] The first plugs 122 and 123 may include a multilayer structure. The first plugs 122 and 123 may include multilayer structures of different conductive materials. The lower portion 122 of the first plug may include a silicon-containing material. The lower portion 122 of the first plug may include, for example, polycrystalline silicon. The upper portion 123 of the first plug may include a metal-containing material. The upper portion 123 of the first plug may include, for example, a stacked structure of metal silicide 123a and metal material 123b. Metal silicide 123a may include, for example, cobalt silicide (CoSix). Metal material 123b may include, for example, titanium nitride (TiN) or tungsten (W). According to another embodiment, the upper portion 123 of the first plug may include a single-layer structure of metal silicide.

[0027] The second plug 124 may include a metallic material. The metallic material may include, for example, titanium nitride or tungsten.

[0028] The width of the second plug 124 may be smaller than the width of the first plugs 122 and 123. The second plug 124 may protrude from the first plugs 122 and 123 in a direction perpendicular to the substrate 101. The two opposing sidewalls of the second plug 124 may be spaced apart from the sidewalls of the storage node contact hole 121. The two opposing sidewalls of the second plug 124 may be spaced at the same distance from the two opposing sidewalls of the storage node contact hole 121.

[0029] The insulating spacer 130 may cover one sidewall of the second plug 124. The insulating spacer 130 may fill the gap between one sidewall of the second plug 124 and the sidewall of the storage node contact hole 121 (which faces the sidewall of the second plug 124). The insulating spacer 130 may comprise, for example, silicon oxide or silicon nitride.

[0030] The top surface of the bit line structure 110, the top surface of the second plug 124, and the top surface of the insulating spacer 130 can be located at the same horizontal LV.

[0031] Storage node 160 may include an extension 160a, a portion of the bottom surface of which contacts the top surfaces of the first plugs 122 and 123. The extension 160a may be part of storage node 160 located at a level lower than the top surface LV of bit line structure 110. The remainder of storage node 160, excluding the extension 160a, may be located at a level higher than the top surface of bit line structure 110, and the bottom surface of this remainder may contact the top surface of bit line structure 110. The extension 160a may extend from storage node 160, and the bottom surface of the extension 160a may contact the top surfaces of the first plugs 122 and 123. Two sidewalls of the extension 160a may contact another sidewall of the second plug 124 and a sidewall of storage node contact hole 121 (facing the other sidewall of the second plug 124), respectively. Since the extension 160a is buried between the second plug 124 and the storage node contact hole 121, the effect of preventing the storage node 160 from bending or tilting can be maximized.

[0032] The storage node 160, including the extension 160a, can be aligned with the other sidewall of the second plug 124. The storage node 160 can be cylindrical.

[0033] The etch stop layer 141 may be located on the top surface of the bit line structure 110 between the storage nodes 160. The etch stop layer 141 may include an insulating material.

[0034] Supports 143 may be located between storage nodes 160. Supports 143 may be configured to prevent bending or tilting of storage nodes 160 and may be structures connecting adjacent storage nodes 160. Supports 143 may be positioned to prevent tilting of storage nodes 160. Supports 143 may be spaced apart from etch stop layer 141 in a direction perpendicular to substrate 101, with a space between them. Supports 143 may include an insulating material. Supports 143 may include a single-layer or multi-layer structure. The top surface of support 143 may be located at a level lower than the top surface of storage node 160. According to another embodiment, the top surface of support 143 may be located at the same level as the top surface of storage node 160. According to another embodiment, a plurality of supports 143 may be formed, spaced apart from substrate 101 by a predetermined distance in a direction perpendicular to substrate 101. Optionally, supports 143 may be omitted.

[0035] like Figure 3As shown, the semiconductor device 200 can be configured such that the two opposing sidewalls of the second plug 124 are spaced at different distances from the two opposing sidewalls of the storage node contact hole 121. Specifically, the gap between the second plug 124 and the sidewalls of the storage node contact hole 121, filled with insulating spacer 130, can be smaller than the gap between the second plug 124 and the sidewalls of the storage node contact hole 121, which buries the extension 160a of the storage node 160. The top surface of the second plug 124 can be located at the same horizontal level LV as the top surface of the bit line structure 110.

[0036] like Figure 4 As shown, the semiconductor device 300 can be configured such that the storage node 360 ​​is not aligned with any sidewall of the second plug 124. The storage node 360 ​​can be aligned at various locations within a range where it may contact the extension 360a but not its adjacent storage node contact plug 120. The top surface of the second plug 124 can be located at the same level LV as the bit line structure 110.

[0037] According to another embodiment, since the storage node 360 ​​is so aligned, therefore... Figure 3 Similar to the semiconductor device 200 in the memory, the second plug 124 can be located at different distances from the two opposite sidewalls of the storage node contact hole 121.

[0038] like Figure 5 As shown, the semiconductor device 400 can be configured such that the width of the top of the second plug 124 is greater than the width of the bottom of the second plug 124. A portion of the bottom surface of the storage node 460, excluding the extension 460a, can contact the top surfaces of the bit line structure 110 and the second plug 124, respectively. In one embodiment, a portion of the bottom surface of the upper part of the storage node 460, except for the extension 460a which contacts the sidewall of the second plug 124, contacts the top surfaces of the bit line structure 110 and the second plug 124. The width of the top of the second plug 124 can be adjusted within a range where the conductive material used to form the extension 460a can be easily buried. The top surface of the second plug 124 can be located at the same level LV as the bit line structure 110.

[0039] According to another embodiment, the alignment of the storage node 460 and the position of the second plug 124 can be as follows: Figure 3 and Figure 4 Make the changes as shown.

[0040] like Figure 6 As shown, the semiconductor device 500 may include a cylindrical storage node 560, which includes a cylindrical upper portion and a cylindrical extension 560a. (As previously mentioned...) Figure 2As defined, the upper part of storage node 560 is the storage node 560 excluding the extension 560a. The top surface of the second plug 124 may be located at the same level LV as the bit line structure 110.

[0041] According to another embodiment, the alignment of the storage node 560 and the position of the second plug 124 can be as follows: Figure 3 and Figure 4 Make the changes as shown.

[0042] like Figure 7 As shown, the semiconductor device 600 may include a hybrid-shaped storage node 660, which includes a cylindrical upper portion and a cylindrical extension 660a. The top surface of the second plug 124 may be located at the same level LV as the bit line structure 110.

[0043] According to another embodiment, the alignment of the storage node 660 and the position of the second plug 124 can be as follows: Figure 3 and Figure 4 Make the changes as shown.

[0044] like Figure 8 As shown, the semiconductor device 700 may include a storage node 760, which includes an extension 760a having the same width as the upper portion of the storage node 760. The extension 760a may partially cover the sidewall of the second plug 124. A portion of the bottom surface of the extension 760a may contact the top surface of the second portion 731 of the insulating spacer. In other words, the storage node 760 may include the extension 760a contacting the exposed sidewall of the second portion 731 of the insulating spacer and the second plug 124, wherein the exposed sidewall is a portion of the sidewall of the second plug 124 exposed by the second portion 731 of the insulating spacer. The storage node 760 including the extension 760a may have a cylindrical shape with the same cross-sectional dimensions along its entire span. The top surface of the second plug 124 may be located at the same level LV as the bit line structure 110.

[0045] According to another embodiment, the second plug 124 can be as follows: Figure 3 The alignment is shown in different positions. For example, the storage node 760, including the extension 760a, can be cylindrical.

[0046] like Figure 9 As shown, the semiconductor device 800 may include an air gap 115 formed within the bit line spacer 114. The top surface of the air gap 115 may be located at a level lower than the top surfaces of the first plugs 122 and 123. The air gap 115 may be completely located within the bit line spacer 114.

[0047] According to another embodiment, the storage node 160, the extension 160a, and the second plug 124 may include the above-described components. Figures 3 to 8 The various structures shown.

[0048] Figures 10A to 10J This is a cross-sectional view used to describe a method of manufacturing a semiconductor device according to one embodiment. Figures 10A to 10J It is used to describe manufacturing such as Figure 2 A cross-sectional view of the method for using the semiconductor device shown.

[0049] refer to Figure 10A Bit line structures 110 can be formed on top of substrate 101. Storage node contact holes 121 can be disposed between bit line structures 110.

[0050] Substrate 101 may include materials suitable for semiconductor processing. Substrate 101 may include a semiconductor substrate. Substrate 101 may be formed, for example, from a silicon-containing material. Substrate 101 may include, for example, single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, single-crystal silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, combinations thereof, or multilayer structures thereof. Substrate 101 may include other semiconductor materials, such as germanium. Substrate 101 may include a composite semiconductor substrate, such as a Group III / V semiconductor substrate, such as GaAs. Substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0051] Subsequently, an element separation layer 102 may be formed on the substrate 101. An active region 103 may be defined by the element separation layer 102. The element separation layer 102 may be a shallow trench isolation (STI) region formed by trench etching. The element separation layer 102 may include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0052] Subsequently, bit line structure 110 can be formed on substrate 101. Before forming bit line structure 110, gate structure (not shown) can be formed. Gate structure (not shown) may include buried gate.

[0053] The bitline structure 110 may include a vertical stacked structure of bitline contacts 111, bitlines 112, and bitline hard masks 113, and bitline spacers 114 covering the sidewalls of the vertical stacked structure.

[0054] Bit line contacts 111 and bit line 112 may comprise a metallic material. Bit line 112 may comprise a metal, a metal nitride, a metal silicide, or a combination thereof. Bit line 112 may comprise, for example, tungsten (W). According to another embodiment, bit line 112 may comprise, for example, a laminated structure of titanium nitride and tungsten (TiN / W). Titanium nitride may act as a barrier.

[0055] Bit line hard mask 113 may include an insulating material. Bit line hard mask 113 may include, for example, silicon oxide or silicon nitride.

[0056] Bit line spacers 114 can be formed as a multilayer structure. Bit line spacers 114 may include, for example, silicon oxide, silicon nitride, or combinations thereof. Bit line spacers 114 may also include, for example, silicon oxide, silicon nitride, or combinations thereof. Figure 9 The air gap 115 in the semiconductor device 800.

[0057] The bottom surface of the storage node contact hole 121 can be located at a level lower than the bottom surface of the bit line structure 110. Specifically, the width of the bottom of the storage node contact hole 121 located at a level lower than the bottom surface of the bit line structure 110 can be greater than the width of the top of the storage node contact hole 121. For this purpose, the storage node contact hole 121 can be formed between the bit line structures 110, and then etching can be performed to widen the bottom.

[0058] like Figure 10B As shown, the lower portion of the first plug can be formed to fill the lower portion of the storage node contact hole 121. To form the lower portion 122 of the first plug, a conductive material can be formed to fill the storage node contact hole 121, and then a series of processes can be performed to recess the conductive material. The lower portion 122 of the first plug may include, for example, a silicon-containing material. The lower portion 122 of the first plug may include, for example, polysilicon.

[0059] like Figure 10C As shown, the upper portion 123 of the first plug may be formed on the lower portion 122 of the first plug. The upper portion 123 of the first plug may include a metal-containing material. The upper portion 123 of the first plug may include, for example, a laminated structure of metal silicide 123a and metal material 123b. Metal silicide 123a may include, for example, cobalt silicide. Metal material 123b may include, for example, titanium nitride (TiN) or tungsten (W). According to another embodiment, the upper portion 123 of the first plug may include a single-layer structure of metal silicide 123a.

[0060] like Figure 10D and Figure 10E As shown, the insulating layer 130' can be formed to cover the upper sidewall of the storage node contact hole 121 and the top of the first plugs 122 and 123. The insulating layer 130' may include, for example, silicon oxide or silicon nitride.

[0061] Subsequently, the insulating layer 130' can be etched to form the insulating layer spacer 130. The etching of the insulating layer 130' can be performed by etch-back. Therefore, the insulating layer spacer 130 is formed on the first plugs 122 and 123 to cover the sidewall of the storage node contact hole 121. When in Figure 10DWhen the thickness of the insulating layer 130' shown varies due to step coverage during its formation, such as... Figure 5 As shown, the insulating layer spacer 130 can be formed such that the width of its top is smaller than the width of its bottom.

[0062] like Figure 10F As shown, a second plug 124 may be formed between the insulating spacers 130 on the first plugs 122 and 123 to fill the remainder of the storage node contact hole 121. To form the second plug 124, a conductive material may be formed on the first plugs 122 and 123 to fill the remainder of the storage node contact hole 121, and a series of processes may be performed to etch the conductive material to a position at the same level as the top surface of the insulating spacers 130. The second plug 124 may comprise a metallic material. The second plug 124 may comprise, for example, titanium nitride (TiN) or tungsten (W).

[0063] According to another embodiment, the shape and position of the second plug 124 can be as follows: Figure 3 and Figure 5 It can be changed in the same way as semiconductor devices.

[0064] like Figure 10G As shown, the etch stop layer 141a, the release layer 142a, and the support 143a can be sequentially formed on the second plug 124, the bit line structure 110, and the insulating spacer 130. The etch stop layer 141a, the release layer 142a, and the support 143a may include an insulating material. The etch stop layer 141a, the release layer 142a, and the support 143a may be formed of materials with different etching selectivity. Specifically, the etch stop layer 141a and the support 143a may be formed of, for example, a material having a wet etching selectivity different from that of the release layer 142a. For example, the etch stop layer 141a and the support 143a may include silicon nitride, while the release layer 142a may include, for example, silicon oxide.

[0065] The support 143a may comprise a single-layer or multi-layer structure. The support 143a may be located between the separating layers 142a. According to another embodiment, the support 143a may be formed on the separating layers 142a. According to another embodiment, the support 143a may be formed in the middle of the separating layers 142a and on top of the separating layers 142a. Optionally, the support 143a may be omitted.

[0066] like Figure 10HAs shown, the storage node hole 150 can be formed to penetrate the etch stop layer 141, the separation layer 142, and the support 143. One sidewall of the storage node hole 150 can be perpendicularly aligned with one sidewall of the second plug 124. A portion of the insulating spacer 130 and the bit line structure 110 can be exposed through the storage node hole 150. According to another embodiment, it can be as follows... Figure 4 Like semiconductor devices, the storage node hole 150 is not aligned with one sidewall of the second plug 124.

[0067] like Figure 10I As shown, the insulating spacer 130 exposed by the storage node hole 150 can be removed, thereby forming a gap 150a. The top surfaces of the first plugs 122 and 123, a sidewall of the second plug 124, and a sidewall of the storage node contact hole 121 (which faces the sidewall of the second plug 124) can be exposed by the gap 150a.

[0068] According to another embodiment, such as Figure 8 As with semiconductor devices, the gap 150a can be formed to have the same width as the storage node hole 150.

[0069] like Figure 10J As shown, a storage node 160, including an extension 160a, can be formed in the storage node hole 150 and the gap 150a. The extension 160a may have a bottom surface located at a level lower than the top surface of the second plug 124, and may extend continuously from the storage node 160. The bottom surface of the extension 160a may contact a portion of the top surfaces of the first plugs 122 and 123, and one sidewall of the extension 160a may contact one sidewall of the second plug 124. In this embodiment, a cylindrical storage node 160 is shown, but alternatively, it may be as follows: Figure 6 and Figure 7 As shown, a cylindrical storage node is formed.

[0070] As described above, since the extension 160a extends from the storage node 160 to a level lower than the top surface of the bit line structure 110, bending or tilting of the storage node 160 can be prevented. Furthermore, short circuits can be prevented by ensuring the contact area between the storage node 160 and the storage node contact plug 120, as well as the overlap margin with adjacent storage nodes and storage node contact plugs 120, via the extension 160a. Additionally, since the storage node contact plug 2 (SNC2), which was previously formed at a level higher than the top surface of the bit line structure 110, is omitted, processing steps can be reduced, processing margins can be ensured, and costs can be lowered. Moreover, since the storage node contact plug 2 (SNC2) is omitted, defects associated with the storage node contact plug 2 (SNC2) can be fundamentally prevented.

[0071] While various embodiments of this disclosure have been described above, those skilled in the art will readily understand that various changes or modifications can be made without departing from the scope or spirit of this disclosure.

[0072] The embodiments of the invention described above are intended to illustrate, not limit, the invention. Various alternatives and equivalents are possible. The invention is not limited to the embodiments described herein. The invention is also not limited to any particular type of semiconductor device. Other additions, reductions, or modifications will be apparent in light of this disclosure and are intended to fall within the scope of the appended claims.

Claims

1. A semiconductor device, comprising: Storage node contact holes are located between bit line structures; A first plug fills the lower part of the storage node contact hole; The second plug protrudes from the first plug; An insulating spacer that covers one sidewall of the second plug; as well as A storage node, located at a level higher than the second plug, includes an extension that contacts the other sidewall of the second plug and a portion of the top surface of the first plug. The two opposing sidewalls of the second plug are spaced apart from the two opposing sidewalls of the storage node contact hole.

2. The semiconductor device of claim 1, wherein, The width of the second plug is smaller than the width of the first plug.

3. The semiconductor device of claim 1, wherein, The second plug protrudes from the first plug in the vertical direction.

4. The semiconductor device of claim 1, wherein, The top surface of the insulating spacer, the top surface of the second plug, and the top surface of the bit line structure are at the same level.

5. The semiconductor device of claim 1, wherein, The bitline structure includes bitline contacts, a vertical stack of bitlines and bitline hard masks, and bitline spacers covering the sidewalls of the vertical stack.

6. The semiconductor device according to claim 5, wherein, The bit line spacers include air gaps.

7. The semiconductor device of claim 1, wherein, The first plug and the second plug are made of different materials.

8. The semiconductor device of claim 1, wherein, The first plug comprises a stacked structure containing a silicon layer and a metal layer, or a stacked structure containing a silicon layer, a metal silicide, and a metal material.

9. The semiconductor device according to claim 1, wherein, The second plug is made of metal.

10. The semiconductor device according to claim 8, wherein, The metallic material includes titanium nitride or tungsten.

11. A semiconductor device, comprising: Storage node contact holes are located between bit line structures; A first plug fills the lower part of the storage node contact hole; The second plug protrudes from the first plug; An insulating spacer that partially covers one sidewall of the second plug and partially exposes said one sidewall of the second plug; as well as A storage node having an extension that contacts the exposed sidewall of the second plug. The two opposing sidewalls of the second plug are spaced apart from the two opposing sidewalls of the storage node contact hole.

12. The semiconductor device of claim 11, wherein, The insulating spacer includes: a first portion whose top surface is at the same level as the top surface of the second plug; and a second portion whose top surface is at a lower level than the top surface of the second plug.

13. The semiconductor device of claim 11, wherein, The width of the extension is the same as the width of the storage node.

14. The semiconductor device of claim 11, wherein, The bottom surface of the extension is located at a level lower than the top surface of the second plug.

15. The semiconductor device according to claim 11, wherein, A portion of the bottom surface of the extension contacts a second portion of the insulating layer spacer.

16. A method for manufacturing a semiconductor device, the method comprising: Storage node contact holes are formed between the bitline structures; A first plug is formed to fill the lower part of the contact hole of the storage node; An insulating layer spacer is formed on the first plug to cover the sidewall of the storage node contact hole, and a second plug is formed between the insulating layer spacers to fill the remaining portion of the storage node contact hole; A sacrificial layer is formed on the second plug, the insulating spacer, and the bit line structure; Form storage node holes that penetrate the sacrificial layer; The insulating spacer exposed by the storage node hole is recessed to expose a portion of the sidewall of the second plug; as well as Storage nodes are formed in the storage node holes. The two opposing sidewalls of the second plug are spaced apart from the two opposing sidewalls of the storage node contact hole.

17. The method of claim 16, wherein, The steps of forming the insulating layer spacers covering the sidewalls of the storage node contact hole on the first plug and filling the remainder of the storage node contact hole between the insulating layer spacers include: An insulating layer is formed on the first plug to cover the storage node contact hole; The insulating layer spacers covering the sidewalls of the storage node contact holes are formed by etching the insulating layer; and A second plug is formed on the first plug, and the second plug fills the remainder of the storage node contact hole between the insulating layer spacers.

18. The method of claim 16, wherein, The step of recessing the insulating spacer includes recessing the insulating spacer to expose a portion of the sidewall of the second plug.

19. The method of claim 16, wherein, The step of recessing the insulating spacer includes removing all of the insulating spacer that contacts one sidewall of the second plug to expose a portion of the top surface of the first plug.

20. A semiconductor device, comprising: A storage node contact plug is disposed between bit line structures. The storage node contact plug includes a first plug and a second plug located on top of the first plug. The storage node contact plug is located in a storage node contact hole. An insulating spacer that covers the first sidewall of the second plug; as well as A storage node includes an upper portion and an extension protruding from the upper portion, wherein the extension covers the second sidewall of the second plug. The two opposing sidewalls of the second plug are spaced apart from the two opposing sidewalls of the storage node contact hole.

21. The semiconductor device according to claim 20, wherein, The cross-section of the second plug is smaller than that of the first plug. The insulating spacer contacts the first portion of the top surface of the first plug that is not covered by the second plug, and The extension covers the second portion of the top surface of the first plug that is not covered by the second plug.

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