Display device

Abstract

A display device is provided. The display device includes a substrate, pads, a first line, a second line, a first connector line, and a first power line. The substrate has a display area and a peripheral area outside the display area. The pads are positioned in the peripheral area. The first line is positioned in the peripheral area and has one end electrically connected to the pads and another end facing the display area. The second line has one end facing the other end of the first line and extends into the display area. One end of the second line is spaced apart from the first line. The first connector line electrically connects the other end of the first line to one end of the second line. The first power line intersects with the first line and is disposed on a first layer different from a second layer on which the first line is disposed.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0083670, filed on July 7, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary implementations of the present invention generally relate to display devices, and more specifically, to display devices in which the likelihood of defects occurring during the manufacturing process is reduced. Background Technology

[0004] When forming thin films in the process of manufacturing display devices, sputtering is used to create conductive films, and chemical vapor deposition (CVD) is used to create insulating films. In either case, the substrate on which the film will be formed must be physically processed; for example, the substrate must be separated from the support.

[0005] The information disclosed in this background section is only for understanding the background of the concept of the present invention, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] The applicant recognizes that defects (e.g., short circuits) may occur between conductive layers on different layers within the display device when the substrate is physically handled during the manufacturing process of the display device.

[0007] Display devices constructed according to the principles and exemplary implementations of the present invention are able to reduce defects between conductive layers on different layers when the substrate is physically processed during the manufacturing process of the display device (e.g., by bridging lines that electrically connect data extension lines and data lines spaced apart from the data extension lines).

[0008] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the inventive concept.

[0009] According to one aspect of the present invention, a display device includes a substrate, pads, a first line, a second line, a first connector line, and a first power line, wherein the substrate has a display area and a peripheral area outside the display area, the pads are positioned in the peripheral area, the first line is positioned in the peripheral area and has one end electrically connected to the pads and another end facing the display area, the second line has one end facing the other end of the first line and extends into the display area, wherein one end of the second line is spaced apart from the first line, the first connector line electrically connects the other end of the first line to one end of the second line, and the first power line intersects the first line, the first power line being disposed on a first layer different from a second layer on which the first line is disposed.

[0010] The first and second lines may contain the same material and have substantially the same layered structure.

[0011] The first and second lines can be arranged on the same layer.

[0012] The first power line can be placed above the first line.

[0013] The first connector wire and the first power wire may be made of the same material and have substantially the same layered structure.

[0014] The first connector line and the first power line can be arranged on the same layer.

[0015] The display device may also include a second power line located above the first power line.

[0016] The pads may include a first pad disposed on the same layer as the first line, a second pad disposed above the first pad and comprising the same material as the first power line, and a third pad disposed above the second pad and comprising the same material as the second power line.

[0017] The pads can be spaced apart from the first power line and the second power line.

[0018] The pad may include a first pad integrally formed with the first line and a third pad disposed above the first pad and comprising the same material as the second power line.

[0019] The pads can be spaced apart from the second power line.

[0020] The first connector wire and the first power wire may be made of the same material and have substantially the same layered structure.

[0021] The first connector line and the first power line can be arranged on the same layer.

[0022] The first connector wire and the second power wire may be made of the same material and have substantially the same layered structure.

[0023] The first connector line and the first power line can be arranged on the same layer.

[0024] The display device may also include a second connector line that electrically connects one end of the first line to a pad, the first line being spaced apart from the pad.

[0025] The second connector line can be arranged on the same layer as the first connector line.

[0026] The second connector wire may include the same material as the first connector wire and have the same layer structure as the first connector wire.

[0027] The second line can be placed on the same layer as the first power line, and the first line can be placed above the first power line.

[0028] The display device may also include a second power line disposed above the first line.

[0029] The first connector wire and the second power wire may be made of the same material and have substantially the same layered structure.

[0030] The first connector wire and the second power wire can be arranged on the same layer.

[0031] The pad may include a first pad integrally formed with the first line and a third pad disposed above the first pad and comprising the same material as the second power line.

[0032] The display device may further include a second power line between the first power line and the first line. The second line may be arranged on the same layer as the first power line.

[0033] The display device may also include pixel electrodes in the display area. The first connector line and the pixel electrodes may be made of the same material and may have substantially the same layer structure.

[0034] The display device may also include pixel electrodes in the display area. The first connector line and the pixel electrodes may be arranged on the same layer.

[0035] The first line may include a data extension line, the second line may include a data line, and the first connector line may include a first bridge wire.

[0036] The first line may include a data extension line, the second line may include a data line, the first connector line may include a first bridge wire, and the second connector line may include a second bridge wire.

[0037] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0038] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the concepts of the invention.

[0039] Figure 1 This is a plan view of an exemplary embodiment of a display device constructed according to the principles of the present invention.

[0040] Figure 2 yes Figure 1 An enlarged plan view of area A in the diagram.

[0041] Figure 3 It is along Figure 2 The first exemplary embodiment of the display device is shown in cross-sectional view taken by line B-B'.

[0042] Figure 4 yes Figure 2 A cross-sectional view of a portion of the display area (DA) in the image.

[0043] Figure 5 It is an illustrative representation of the manufacturing process. Figure 1 A perspective view of the support components used in the manufacturing process of the display device.

[0044] Figure 6 This schematically illustrates the process of manufacturing a display device. Figure 5 A diagram illustrating the process of separating the support components from the substrate.

[0045] Figure 7 yes Figure 1 A cross-sectional view of a second exemplary embodiment of the display device.

[0046] Figure 8 yes Figure 1 A cross-sectional view of a third exemplary embodiment of the display device.

[0047] Figure 9 yes Figure 1 A cross-sectional view of a fourth exemplary embodiment of the display device.

[0048] Figure 10 yes Figure 1 A cross-sectional view of a fifth exemplary embodiment of the display device.

[0049] Figure 11 yes Figure 1 A cross-sectional view of a sixth exemplary embodiment of the display device.

[0050] Figure 12 yes Figure 1 A cross-sectional view of a seventh exemplary embodiment of the display device.

[0051] Figure 13 yes Figure 1 A cross-sectional view of an eighth exemplary embodiment of the display device.

[0052] Figure 14 yes Figure 1 A cross-sectional view of a ninth exemplary embodiment of the display device.

[0053] Figure 15 yes Figure 1 A cross-sectional view of the tenth exemplary embodiment of the display device. Detailed Implementation

[0054] In the following description, numerous specific details are set forth for purposes of explanation to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “implementation” and “method” are interchangeable terms and are non-limiting examples of apparatuses or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or in one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, a particular shape, construction, and characteristic of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the concept of the invention.

[0055] Unless otherwise specified, the exemplary embodiments shown are to be understood as exemplary features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, features, components, modules, layers, films, panels, areas and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0056] Crosshairs and / or shading are typically provided in the accompanying drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristics, properties, performance, etc., of the elements. Additionally, the size and relative size of elements may be exaggerated in the drawings for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, similar reference numerals denote similar elements.

[0057] When a component or layer is referred to as being "on," "connected to," or "attached to" another component or layer, the component (such as a layer) may be directly on, directly connected to, or directly attached to the other component or layer, or there may be intermediate components or layers present. However, when a component or layer is referred to as being "directly" on, directly connected to, or directly attached to another component or layer, there are no intermediate components or layers present. Therefore, the term "connection" can indicate a physical, electrical, and / or fluid connection, with or without intermediate components. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system (such as the X, Y, and Z axes) and can be interpreted in a broader sense. For example, the D1, D2, and D3 axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the cluster consisting of X, Y, and Z” can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0058] While the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0059] Spatial relative terms, such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” and “side” (e.g., as in “sidewall”), may be used herein for descriptive purposes and thus to describe the relationship between one element and another as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the exemplary term “below” can cover both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thereby the spatial relative descriptive terms used herein are interpreted accordingly.

[0060] The technical terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” as used herein are intended to include the plural forms as well. Furthermore, the terms “comprise,” “comprising,” “include,” and / or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and / or clusters thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or clusters thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximations rather than terms of degree, and are thus utilized to account for inherent deviations in measurements, calculations, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0061] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms, such as those defined in common dictionaries, shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense.

[0062] Figure 1 This is a plan view of an exemplary embodiment of a display device constructed according to the concept of the present invention.

[0063] The display device includes a substrate 100, which has a display area DA and a peripheral area PA outside the display area DA. The shape of the substrate 100 is not limited to, for example... Figure 1 The substrate 100 is generally rectangular in shape (in the XY plane) and can have various shapes, such as circles. Additionally, the substrate 100 may have bent regions and can be bent within those regions.

[0064] The substrate 100 may include glass or metal. Alternatively, the substrate 100 may include various flexible or bendable materials such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or polymeric resins such as cellulose acetate propionate.

[0065] However, the substrate 100 can be modified in various ways, for example, to have a multilayer structure comprising two layers containing such a polymer resin and a barrier layer containing an inorganic material between the two layers. In this case, the barrier layer may comprise silicon oxide, silicon nitride, and / or silicon oxynitride.

[0066] Multiple display devices may be located in the display area DA. For example, the display device may be an organic light-emitting diode (OLED) and may emit red, green, blue, or white light. Drivers, power lines, and the like may be located in the peripheral area PA. Additionally, the peripheral area PA may include pad areas, where pads electrically attached to various electronic devices such as driver integrated circuits or printed circuit boards are positioned.

[0067] Figure 2 yes Figure 1 An enlarged plan view of area A in the diagram. Figure 3 It is along Figure 2 The first exemplary embodiment of the display device is shown in cross-sectional view taken by line B-B'. Figure 4 yes Figure 2 A cross-sectional view of a portion of the display area DA. Figure 2 The line B-B' shown extends in the Y-axis direction and then forms an angle in the X-axis direction. Therefore, Figure 3 The sectional view is not a sectional view taken along a straight line, but rather a sectional view taken along an angled line B-B'. For reference, Figure 3 The coordinate axes shown are used to illustrate a cross-sectional view along a portion of line B-B' extending along the Y-axis. Additionally, Figure 3 Also includes Figure 2 The area outside line B-B' in the first thin-film transistor TFT1.

[0068] Reference Figure 2 , Figure 3 and Figure 4 A first thin-film transistor (TFT1) and a second thin-film transistor (TFT2) for controlling a display device are formed on the substrate 100. These first thin-film transistors (TFT1) and second thin-film transistors (TFT2) each include a semiconductor layer, for example, a first semiconductor layer 121-1 and a second semiconductor layer 121-2. Figure 4 A cross-sectional view of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 is shown.

[0069] Reference Figure 4The first semiconductor layer 121-1 includes a first source region S1, a first drain region D1, and a first channel region C1 therebetween. The second semiconductor layer 121-2 includes a second source region S2, a second drain region D2, and a second channel region C2 therebetween. The first semiconductor layer 121-1 and the second semiconductor layer 121-2 may be formed on the substrate 100. Furthermore, as... Figure 3 and Figure 4 As shown, a buffer layer 101 may be formed on the substrate 100, and a first semiconductor layer 121-1 and a second semiconductor layer 121-2 may be formed on the buffer layer 101.

[0070] Buffer layer 101 reduces or blocks the penetration of foreign matter, moisture, or ambient air from the lower part of substrate 100 and provides a substantially flat surface on substrate 100. Buffer layer 101 may comprise inorganic materials, organic materials, or organic-inorganic composites such as oxides or nitrides, and may have a monolayer structure or a multilayer structure of inorganic and organic materials. For example, buffer layer 101 may have a structure of a first buffer layer and a second buffer layer stacked, and in this case, the first buffer layer and the second buffer layer may comprise different materials. For example, the first buffer layer may comprise silicon nitride, and the second buffer layer may comprise silicon oxide.

[0071] As described above, when the first buffer layer comprises silicon nitride, hydrogen may be included during the formation of the silicon nitride. This improves the carrier mobility of the semiconductor layer formed on the buffer layer 101, and therefore improves the electrical characteristics of the first thin-film transistor TFT1 and the second thin-film transistor TFT2. Furthermore, the first semiconductor layer 121-1 and the second semiconductor layer 121-2 may comprise silicon material, and in this case, the interface bonding characteristics between the silicon-containing first semiconductor layer 121-1 and second semiconductor layer 121-2 and the second buffer layer comprising silicon oxide are improved, and therefore improve the electrical characteristics of the first thin-film transistor TFT1 and the second thin-film transistor TFT2.

[0072] The first semiconductor layer 121-1 and the second semiconductor layer 121-2 may comprise low-temperature polycrystalline silicon (LTPS). Polycrystalline silicon materials have high electron mobility (greater than 100 cm⁻¹). 2 ( / Vs), low power consumption, and excellent reliability. As another example, the first semiconductor layer 121-1 and the second semiconductor layer 121-2 may comprise amorphous silicon (a-Si) and / or oxide semiconductors. Alternatively, some semiconductor layers of the plurality of thin-film transistors may comprise LTPS, and some of the plurality of semiconductor layers may comprise a-Si and / or oxide semiconductors.

[0073] The first source region S1 and the second source region S2, as well as the first drain region D1 and the second drain region D2 of the first semiconductor layer 121-1 and the second semiconductor layer 121-2, may be doped with impurities, and the impurities may include N-type impurities or P-type impurities. The first source region S1 and the second source region S2, as well as the first drain region D1 and the second drain region D2, may correspond to the source electrode and the drain electrode, respectively. The first source region S1 and the second source region S2, as well as the first drain region D1 and the second drain region D2, may be interchanged according to the characteristics of the first thin-film transistor TFT1 and the second thin-film transistor TFT2. In the following, the terms "first source region S1 and the second source region S2" and "first drain region D1 and the second drain region D2" are used to refer to the source electrode or the drain electrode.

[0074] The gate insulating layer 103 is located on the first semiconductor layer 121-1 and the second semiconductor layer 121-2, and the first gate electrode 123-1, the second gate electrode 123-2, the first power line PL1, and the second pad PD2 may be located on the gate insulating layer 103. The gate insulating layer 103 may include silicon oxide (SiO2) or silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2).

[0075] The first gate electrode 123-1 and the second gate electrode 123-2, the first power line PL1 and the second pad PD2, and the like may include a conductive material comprising molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a multilayer structure or a single-layer structure comprising the above materials. For example, the first gate electrode 123-1 and the second gate electrode 123-2, the first power line PL1 and the second pad PD2 may have a Mo / Al multilayer structure or a Mo / Al / Mo multilayer structure.

[0076] The first thin-film transistor TFT1 is a driving transistor, and it controls the current supplied to the organic light-emitting diode 200 by controlling the amount of current from the diode. Figure 4 The amount of light emitted by the organic light-emitting diode 200 shown. The second thin-film transistor TFT2 is from... Figure 3 The data line DL shown is a switching transistor that receives data signals and determines the voltage between the first gate electrode 123-1 and the first source region S1 of the first thin-film transistor TFT1. For this purpose, the second drain region D2 of the second thin-film transistor TFT2 can be electrically connected to the first gate electrode 123-1 of the first thin-film transistor TFT1.

[0077] exist Figure 3 In the middle, located with Figure 4The third bridge line BR3 on the same layer as the pixel electrode 210 shown in the diagram contacts the data line DL and the second source region S2 of the second thin-film transistor TFT 2 via contact holes formed in the buffer layer 101, the first interlayer insulating layer 105, the second interlayer insulating layer 107, and the planarization layer 109, respectively. Additionally, in Figure 3 In the diagram, the fourth bridge wire BR4, located on the same layer as the pixel electrode 210, is shown to contact the second drain region D2 of the second thin film transistor TFT2 and the first gate electrode 123-1 of the first thin film transistor TFT1 via contact holes formed in the first interlayer insulating layer 105, the second interlayer insulating layer 107 and the planarization layer 109.

[0078] The first interlayer insulating layer 105 and the second interlayer insulating layer 107 may be sequentially stacked on the first gate electrode 123-1 and the second gate electrode 123-2, the first power line PL1, and the second pad PD2. Each of the first interlayer insulating layer 105 and the second interlayer insulating layer 107 may include silicon oxide (SiO2) and silicon nitride (SiN). x Materials may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). If desired, a wire formed of conductive material may be located between the first interlayer insulating layer 105 and the second interlayer insulating layer 107. For example, Figure 3 The diagram shows a third pad PD3 in the peripheral region PA located between a first interlayer insulating layer 105 and a second interlayer insulating layer 107. The second interlayer insulating layer 107 can be used as a protective layer to protect the first thin-film transistor TFT1 and the second thin-film transistor TFT2.

[0079] like Figure 4 As shown, the planarization layer 109 may be located on the second interlayer insulating layer 107, and the organic light-emitting diode 200 may be located on the planarization layer 109.

[0080] Reference Figure 4The planarization layer 109 may have a substantially flat upper surface, such that the pixel electrode 210 of the organic light-emitting diode 200 can be formed substantially flat. The planarization layer 109 may include organic materials and may have a single-layer or multi-layer structure. The planarization layer 109 is a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), poly(methyl methacrylate) (PMMA), or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aromatic ether polymer, an amide polymer, a fluoropolymer, a p-xylyl polymer, a vinyl alcohol polymer, or a blend thereof. The planarization layer 109 may contain inorganic materials. The planarization layer 109 may include silicon oxide (SiO2), silicon nitride (SiN2), etc. x The planarization layer 109 may contain inorganic materials such as silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). When the planarization layer 109 comprises inorganic materials, chemical planarization polishing may be performed in some cases. Furthermore, the planarization layer 109 may comprise both organic and inorganic materials.

[0081] like Figure 4 As shown, the organic light-emitting diode 200 in the display area DA may include a pixel electrode 210, a common electrode 230, and an intermediate layer 220 therebetween, which includes an emission layer.

[0082] Reference Figure 4The pixel electrode 210 is connected to the first drain region D1 of the first thin-film transistor TFT1 via contact holes formed in the first interlayer insulating layer 105, the second interlayer insulating layer 107, and the planarization layer 109. The pixel electrode 210 may be a (semi-)transparent electrode or a reflective electrode. In some exemplary embodiments, the pixel electrode 210 may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and compounds thereof, and a transparent or semi-transparent electrode layer formed on the reflective film. The transparent or semi-transparent electrode layer may include at least one selected from a cluster consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some exemplary embodiments, the pixel electrode 210 may have an ITO / Ag / ITO stacked structure.

[0083] A pixel defining layer 110 may be arranged on the planarization layer 109, and the pixel defining layer 110 may define the light-emitting area of ​​the pixel by having an opening having an exposed central portion of the pixel electrode 210. Additionally, the pixel defining layer 110 may reduce or prevent arcing at the edges of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the edge of the common electrode 230 above the pixel electrode 210. The pixel defining layer 110 is an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be formed by methods such as spin coating or similar methods.

[0084] An intermediate layer 220 of the organic light-emitting diode 200 is located on the pixel electrode 210 and may include an organic emitting layer. The organic emitting layer may include organic materials, such as fluorescent or phosphorescent materials that emit red, green, blue, or white light. The organic emitting layer may be a low-molecular-weight organic material or a high-molecular-weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), an electron injection layer (EIL), and similar layers may be selectively arranged below and above the organic emitting layer. The intermediate layer 220 may overlap with each pixel electrode 210. However, exemplary embodiments are not limited thereto, and layers such as HTL, HIL, ETL, EIL, or similar layers included in the intermediate layer 220 may be integrally formed across several pixel electrodes 210 in the display area DA. The intermediate layer 220 may be formed by various methods such as inkjet printing, vapor deposition, laser thermal transfer, or similar methods.

[0085] The common electrode 230 can be a transparent electrode or a reflective electrode. In some exemplary embodiments, the common electrode 230 can be a transparent or translucent electrode and may include a metal thin film with a low work function comprising lithium (Li), calcium (Ca), LiF / Ca, LiF / Al, Al, Ag, Mg, and their compounds. In addition to the metal thin film, the common electrode 230 may also include a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, In2O3, or similar materials. The common electrode 230 may be integrally formed across multiple pixel electrodes 210 in the display area DA.

[0086] An encapsulation layer (not shown), comprising a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer therebetween, may be present on the common electrode 230. The first and second inorganic encapsulation layers may comprise silicon oxide (SiO2) or silicon nitride (SiN). x The organic encapsulation layer may comprise polyethylene terephthalate (PET), polyethylene naphthalate (PAN), polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, HMDSO, acrylic resin (e.g., PMMA, polyacrylic acid and the like), or any combination thereof.

[0087] like Figure 3 and Figure 4 As shown, a bottom metal layer (BML) 300 may be arranged between the substrate 100 and the first thin-film transistor TFT 1. The BML 300 may be arranged in an isolated shape below the first semiconductor layer 121-1 of the first thin-film transistor TFT 1. In this case, a buffer layer 101 may be located on the substrate 100 to cover the BML 300. The BML 300 may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, tungsten (W), and / or Cu. The BML 300 may be a single layer or multiple layers comprising the above materials. The BML 300 can protect the first thin-film transistor TFT 1 from external electromagnetic waves or the like. In this case, the pixel electrode 210 may contact the BML 300 via a contact hole.

[0088] Reference Figure 2 and Figure 3 The pads (PDs) are located within the pad area of ​​the outer region PA. The pads (PDs) can comprise multiple layers as needed. Figure 3 The diagram shows that pad PD includes a first pad PD1, a second pad PD2 above the first pad PD1, and a third pad PD3 above the second pad PD2. For example... Figure 3 As shown, the first pad PD1 may be integrated with the data extension line DEL. In this case, when viewed from a direction perpendicular to the substrate 100, the first pad PD1 may be defined as a portion of which overlaps with the second pad PD2 and / or the third pad PD3. Of course, at the edge of the pad PD, a buffer layer 101 and / or a gate insulating layer 103 may be between the first pad PD1 and the second pad PD2, and a first interlayer insulating layer 105 may be between the second pad PD2 and the third pad PD3.

[0089] Data signals transmitted from the pad PD are passed through Figure 3 The data line DL shown is transmitted to the second thin-film transistor TFT2. For example... Figure 2 and Figure 3 As shown, data extension lines DEL are arranged between pad PD and data line DL. One end of data extension line DEL (e.g., in the +Y direction) is electrically connected to pad PD, and the other end of data extension line DEL (e.g., in the -Y direction) extends towards display area DA, wherein data extension line DEL is positioned in peripheral area PA. Additionally, one end of data line DL is spaced apart from data extension line DEL, but faces the other end of data extension line DEL. Figure 3 As shown, the data line DL extends into the display area DA and is electrically connected to the second thin-film transistor TFT2.

[0090] As described above, the pad PD may include first pad PD1 to third pad PD3. In this case, first pad PD1, data extension line DEL, and data line DL may be positioned on the same layer as BML 300. That is, first pad PD1, data extension line DEL, data line DL, and BML 300 may include the same material and have substantially the same layer structure.

[0091] like Figure 3 As shown, the first pad PD1 and the data extension line DEL can be combined into one unit. (Refer to...) Figure 3 The data extension line DEL and the data line DL can be electrically connected using a first bridging wire BR1. That is, the first bridging wire BR1 can electrically connect the other end of the data extension line DEL and one end of the data line DL to each other. Like the pixel electrode 210, the first bridging wire BR1 is positioned on the planarization layer 109 and can contact the other end of the data extension line DEL and one end of the data line DL through contact holes formed in the buffer layer 101, the first interlayer insulating layer 105, the second interlayer insulating layer 107, and the planarization layer 109. In this case, the first bridging wire BR1 may include... Figure 4 The pixel electrode 210 shown is made of the same material and has essentially the same layer structure.

[0092] Reference Figure 2 and Figure 3 The first power line PL1 can also be located in the peripheral area PA. The first power line PL1 can be located on a different layer than the layer where the data extension line DEL is located. For example, the first power line PL1 can be located above the data extension line DEL and can extend in a direction intersecting the direction of extension of the data extension line DEL (e.g., the Y-axis direction) (e.g., the X-axis direction). However, an auxiliary power line (not shown) can be electrically connected to the first power line PL1 and extend into the display area DA. Hereinafter, for convenience, the auxiliary power line extending into the display area DA will also be referred to as the first power line PL1 (see [link to documentation]). Figure 4 ).exist Figure 3 In the diagram, the first power line PL1 is shown positioned on the same layer as the first gate electrode 123-1 and the second gate electrode 123-2. That is, the first power line PL1 may contain the same material as the first gate electrode 123-1 and the second gate electrode 123-2 and have substantially the same layer structure.

[0093] Figure 5 It is an illustrative representation of the manufacturing process. Figure 1 A perspective view of the support components used in the manufacturing process of the display device. Figure 6 This schematically illustrates the process of manufacturing a display device. Figure 5 A diagram showing the process of separating the support from the substrate 100.

[0094] Reference Figure 5 and Figure 6 In manufacturing Figure 1 The support used in the manufacturing process of the display device includes a base 10 and pins 21 and 22. The base 10 may comprise a conductive material. Pins 21 and 22 have a vertically extending shape (e.g., along the Z-axis). The base 10 has through openings through which these pins 21 and 22 pass. The base 10 has a substrate mounting surface 10a for... Figure 6 The substrate 100 to be processed shown is supported. The base 10 comprises a conductive material and is conductive overall. For example, the base 10 may comprise Al.

[0095] During the arrangement of the substrate 100 and the like on the substrate mounting surface 10a of the base 10, after a process of forming a thin film on the substrate 100, the substrate 100 is separated from the substrate mounting surface 10a of the base 10. For example, in the process of forming a thin film on the substrate 100... Figure 5 A schematic cross-section of the support member taken from line VI-VI. Figure 6 Conceptually illustrated, the substrate 100 is separated from the base 10 at its edge by raising a pin 22 positioned at the edge of the base 10 higher than a pin 21 positioned on the inside of the base 10. This is because when the pin 22 positioned at the edge of the base 10 and the pin 21 positioned on the inside are raised by the same amount simultaneously (e.g., in the +Z direction), the substrate 100 is not easily separated from the base 10 due to the electrostatic force between the substrate mounting surface 10a and the substrate 100. By raising the pin 22 positioned at the edge of the base 10 higher than the pin 21 positioned on the inside of the base 10 as described above, the central portion of the substrate 100 can contact the base 10, while the edge of the substrate 100 is separated from the base 10.

[0096] Depending on the manufacturing process of the display device, charge may temporarily exist in the data lines DL and the like on the substrate 100. When the data extension lines DEL and DL are integrally formed and not spaced apart from each other, a large amount of charge can accumulate in the data extension lines DEL and DL. This is because the data lines DL extend across the display area DA of the substrate 100 for a long time and therefore have a large total area. In the manufacturing process, charge may also accumulate in the first power line PL1, which is located on a different layer than the layer on which the data extension lines DEL are located. Accordingly, a substantially constant potential difference may exist between the first power line PL1 and the data extension lines DEL and DL, which are integrally formed together.

[0097] In this case, such as Figure 6As shown, when the central portion of the substrate 100 contacts the base 10 and the edge of the substrate 100 separates from the base 10, due to effects such as tunneling, the charge accumulated in the data extension lines DEL and DL, which are integrally formed with each other, can flow out to the base 10 through the central portion of the substrate 100. However, the charge accumulated in the first power line PL1 positioned above the data extension line DEL cannot flow out, and therefore, the potential difference between the data extension line DEL and the first power line PL1 can increase rapidly and instantaneously. As a result, a short circuit may occur between the data extension line DEL and the first power line PL1, leading to a display device malfunction.

[0098] However, in the display device constructed according to the principles of the present invention and the exemplary embodiments shown, such as Figure 2 and Figure 3 As shown, the data extension line DEL and the data line DL, which are made of the same material and have substantially the same layer structure, are separated from each other. Accordingly, as Figure 6 As shown, when the central portion of the substrate 100 contacts the base 10 and the edge of the substrate 100 separates from the base 10, the charge accumulated in the data line DL can be transferred to the substrate 100 due to effects such as tunneling and similar phenomena. However, the charge accumulated in the data extension line DEL and the first power line PL1 positioned above the data extension line DEL cannot flow out. Accordingly, the potential difference between the data extension line DEL and the first power line PL1 remains substantially constant, and thus a short circuit between the data extension line DEL and the first power line PL1 is prevented.

[0099] The first power line PL1 can be a so-called ELVDD line that applies power to the organic light-emitting diode 200. Accordingly, as... Figure 4 As shown, in the display area DA, the pixel electrode 210 can contact the first power line PL1 through contact holes formed in the first interlayer insulating layer 105, the second interlayer insulating layer 107 and the planarization layer 109.

[0100] The upper surface of the pad PD can be exposed to the outside and electrically connected to an integrated circuit (IC) chip (not shown), such as a driver circuit chip. For this purpose, the pad PD can have, for example... Figure 3 The three-layer structure is shown. The bumps of the IC chip are electrically connected to the pads PD via anisotropic conductive films and the like, and therefore, if possible, it is desirable to increase the distance between the upper surface of the pads PD and the substrate 100. For this purpose, in Figure 3In the process, the pad PD includes a first pad PD1 on the same layer as the data extension line DEL, a second pad PD2 located above the first pad PD1 and made of the same material as the first power line PL1, and a third pad PD3 above the second pad PD2.

[0101] Figure 7 yes Figure 1 A cross-sectional view of a second exemplary embodiment of the display device. For example, Figure 7 Can correspond to Figure 3 The cross-sectional area. (Refer to...) Figure 7 The display device may further include a second power line PL2 above the first power line PL1. When viewed from a direction perpendicular to the substrate 100, the pad PD may be spaced apart from the first power line PL1 and the second power line PL2. The second power line PL2 may be, for example, an ELVSS line and may be in contact with the common electrode 230 to maintain a constant potential of the common electrode 230. The second power line PL2 may be located between the first interlayer insulating layer 105 and the second interlayer insulating layer 107, and may contain conductive materials including Mo, Al, Cu, and Ti, and may have a multilayer structure or a single-layer structure including the above materials. As an example, the second power line PL2 may have a Ti / Al / Ti multilayer structure. In this case, the third pad PD3 above the second pad PD2 may contain the same material as the second power line PL2.

[0102] Figure 8 yes Figure 1 A cross-sectional view of a third exemplary embodiment of a display device. For example, Figure 8 Can correspond to Figure 7 The cross-sectional area. (Refer to...) Figure 8 The pad PD may have only a first pad PD1 and a third pad PD3, or not all three of the first pad PD1 to the third pad PD3. In this case, the first pad PD1 may be integrated with the data extension line DEL, and the third pad PD3 may be above the first pad PD1 and include the same material as the second power line PL2. Of course, the third pad PD3 contacts the first pad PD1 via contact holes formed in the buffer layer 101 and the first interlayer insulating layer 105. In addition, when viewed from a direction perpendicular to the substrate 100, the pad PD may be spaced apart from the second power line PL2.

[0103] So far, the first bridging wire BR1 has been described as being on the same layer as the pixel electrode 210, but exemplary embodiments are not limited to this. Figure 9 yes Figure 1 A cross-sectional view of a fourth exemplary embodiment of a display device. For example, Figure 9 Can correspond to Figure 3 The cross-sectional area. (Refer to...) Figure 9The first bridging wire BR1 may be on the same layer as the first power line PL1. That is, the first bridging wire BR1 may comprise the same material as the first power line PL1 and have substantially the same layer structure. In this case, the first bridging wire BR1 electrically connects the data extension line DEL to the data line DL via contact holes formed in the buffer layer 101, by contacting the other end of the data extension line DEL and one end of the data line DL. Here, the second power line may also be arranged above the first power line PL1.

[0104] Figure 10 yes Figure 1 A cross-sectional view of a fifth exemplary embodiment of a display device. For example, Figure 10 Can correspond to Figure 9 The cross-sectional area. (Refer to...) Figure 10 The first bridging wire BR1 may be on the same layer as the second power line PL2. That is, the first bridging wire BR1 may contain the same material as the second power line PL2 and have substantially the same layer structure. In this case, the first bridging wire BR1 electrically connects the data extension line DEL and the data line DL to each other by contacting the other end of the data extension line DEL and one end of the data line DL through contact holes formed in the buffer layer 101 and the first interlayer insulation layer 105.

[0105] Figure 11 yes Figure 1 A cross-sectional view of a sixth exemplary embodiment of a display device. For example, Figure 11 Can correspond to Figure 3 The cross-sectional area. (Refer to...) Figure 11 In addition to the first bridge wire BR1, the display device may also include a second bridge wire BR2. Furthermore, the data extension line DEL is spaced apart from the pad PD, and the second bridge wire BR2 electrically connects the pad PD and the data extension line DEL to each other. In this case, as... Figure 11 As shown, the pad PD includes a second pad PD2 positioned on the same layer as the first power line PL1, and may also include a third pad disposed above the second pad PD2 if desired. In the latter case, a second power line comprising the same material as the third pad and having substantially the same layer structure as the third pad may be located above the first power line PL1. This configuration is also the same in the exemplary embodiments and variations thereof described below.

[0106] The second bridge wire BR2 may be on the same layer as the first bridge wire BR1. That is, the second bridge wire BR2 may comprise the same material as the first bridge wire BR1 and have substantially the same layer structure. However, as Figure 11As shown, the first bridge line BR1 and the second bridge line BR2 can be positioned on the same layer as the pixel electrode 210. As a modified example, when the display device includes a second power line PL2 above the first power line PL1 (see...), Figure 10 When ), at least one of the first bridge wire BR1 and the second bridge wire BR2 may be located on the same layer as the second power line PL2.

[0107] The second bridge wire BR2 can contact the pad PD via contact holes formed in the first interlayer insulating layer 105, the second interlayer insulating layer 107 and the planarization layer 109, and the second bridge wire BR2 can contact the data extension line DEL via contact holes formed in the buffer layer 101, the first interlayer insulating layer 105, the second interlayer insulating layer 107 and the planarization layer 109.

[0108] like Figure 11 As shown, the data extension line DEL can extend below the pad PD, and thus the upper surface of the pad PD can be sufficiently far away from the substrate 100.

[0109] So far, the data extension line DEL has been described as being on the same layer as the data lines DL and BML 300. However, the exemplary implementation is not limited to this. Figure 12 yes Figure 1 A cross-sectional view of a seventh exemplary embodiment of a display device. For example, Figure 12 Can correspond to Figure 11 The cross-sectional area. (Refer to...) Figure 12 The first power line PL1 may be on the same layer as the data lines DL and BML 300. That is, the first power line PL1 may contain the same material as the data lines DL and BML 300 and have substantially the same layer structure. In this case, the data extension line DEL may be above the first power line PL1.

[0110] exist Figure 12 In this configuration, the pad PD, including the second pad PD2, is spaced apart from the data extension line DEL, and the second bridging wire BR2 contacts each of the pad PD and the data extension line DEL to electrically connect them. Alternatively, the second pad PD2 and the data extension line DEL can be integrated into a single component. This is because the second pad PD2 and the data extension line DEL are located on the same layer. This structure can also be applied in the same way in the exemplary embodiments and variations thereof described below. In this case, the second pad PD2 and the data extension line DEL may contain the same material as the first gate electrode 123-1 and the second gate electrode 123-2 and have substantially the same layer structure.

[0111] The data extension line DEL, located on the same layer as the first gate electrode 123-1 and the second gate electrode 123-2, can be electrically connected via the first bridge wire BR1 to the data line DL on the same layer as BML 300.

[0112] like Figure 12 As shown, the first power line PL1 can extend below the pad PD, and therefore the upper surface of the pad PD can be sufficiently far away from the substrate 100. This structure can also be applied in the following exemplary embodiments and variations thereof.

[0113] Figure 13 yes Figure 1 A cross-sectional view of an eighth exemplary embodiment of the display device, and Figure 14 yes Figure 1 A cross-sectional view of a ninth exemplary embodiment of a display device. For example, Figure 13 and Figure 14 Can correspond to Figure 12 The cross-sectional area. (Refer to...) Figure 13 The display device may further include a second power line PL2 between the first interlayer insulating layer 105 and the second interlayer insulating layer 107, such that the second power line PL2 is above the data extension line DEL. In this case, as Figure 13 As shown, the first bridging line BR1 can be on the planarization layer 109, just like the pixel electrode 210. Alternatively, refer to... Figure 14 The first bridging wire BR1 may be located between the first interlayer insulation layer 105 and the second interlayer insulation layer 107. In this case, the first bridging wire BR1 may contain the same material as the second power line PL2 and have substantially the same layer structure.

[0114] As a reference, in the case of such Figure 13 and Figure 14 In the display device with the structure shown, in addition to the second pad PD2, the pad PD may also include a third pad, which is positioned above the second pad PD2, electrically connected to the second pad PD2, and contains the same material as the second power line PL2 and has substantially the same layer structure.

[0115] Figure 15 yes Figure 1 A cross-sectional view of a tenth exemplary embodiment of a display device. For example, Figure 15 Can correspond to Figure 12 The cross-sectional area. (Refer to...) Figure 15 As described above, the first power line PL1 is on the same layer as the data lines DL and BML 300. That is, the first power line PL1 may contain the same material as the data lines DL and BML 300 and have substantially the same layer structure.

[0116] The data extension line DEL may be located above the first power line PL1. For example, the data extension line DEL is located between the first interlayer insulation layer 105 and the second interlayer insulation layer 107. The second power line PL2 is located between the first power line PL1 and the data extension line DEL. The second power line PL2 is located on the same layer as the first gate electrode 123-1 and the second gate electrode 123-2, includes the same material as them, and has substantially the same layer structure as them.

[0117] The data extension line DEL between the first interlayer insulation layer 105 and the second interlayer insulation layer 107 can be electrically connected to the data line DL on the same layer as BML 300 via the first bridge wire BR1.

[0118] like Figure 15 As shown, the first power line PL1 can extend below the pad PD, and thus the upper surface of the pad PD can be sufficiently far away from the substrate 100.

[0119] In the accompanying drawings described so far as to illustrate various exemplary embodiments and variations, the gate insulating layer 103 is shown patterned in the same manner as the first gate electrode 123-1 or the second gate electrode 123-2. However, the exemplary embodiments are not limited thereto, and the gate insulating layer 103 may substantially overlap the entire surface of the substrate 100. In this case, the first bridge connection BR1 to the fourth bridge connection BR4 may, in some cases, pass through contact holes also formed in the gate insulating layer 103.

[0120] Organic light-emitting display devices have been primarily described so far, but exemplary embodiments are not limited thereto. That is, exemplary embodiments can be applied to any display device having pixel electrodes 210 as shown in the figures, such as, as an example, a quantum dot display device configured to emit light of a single wavelength, such as blue light, and to convert the blue light into red or green light by using quantum dots thereon.

[0121] According to the principles and exemplary embodiments of the present invention, it is possible to manufacture display devices in which the likelihood of defects occurring during the manufacturing process is reduced. However, the exemplary embodiments are not limited to these effects.

[0122] While certain exemplary embodiments and implementations have been described herein, other embodiments and variations will become apparent from this description. Accordingly, the inventive concept is not limited to these embodiments, but is limited to the broader scope of the appended claims and the various obvious variations and equivalent arrangements as will be apparent to those skilled in the art.

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a peripheral area outside the display area; Pads, the pads being positioned in the peripheral area; The first line is positioned in the peripheral area and has one end electrically connected to the pad and the other end facing the display area. A second line has one end facing the other end of the first line, and the second line extends into the display area, the one end of the second line being spaced apart from the first line; A first connector wire, wherein the first connector wire electrically connects the other end of the first wire to the first end of the second wire; as well as A first power line, which intersects with the first wire, is arranged on a first layer different from the second layer on which the first wire is arranged. The first power line is positioned above the first line.

2. The display device as claimed in claim 1, wherein, The first line and the second line are made of the same material and have the same layered structure.

3. The display device as claimed in claim 1, wherein, The first line and the second line are arranged on the same layer.

4. The display device as claimed in claim 1, wherein, The first connector wire and the first power wire are made of the same material and have the same layered structure.

5. The display device as claimed in claim 4, wherein, The first connector wire and the first power wire are arranged on the same layer.

6. The display device as claimed in claim 1, further comprising: The second power line is arranged above the first power line.

7. The display device as claimed in claim 6, wherein, The pads include: The first pad is disposed on the same layer as the first line; A second pad, disposed above the first pad and comprising the same material as the first power line; and A third pad is disposed above the second pad and comprises the same material as the second power line.

8. The display device as claimed in claim 7, wherein, The pads are spaced apart from the first power line and the second power line.

9. The display device as claimed in claim 6, wherein, The pads include: The first pad is integrally formed with the first line; and A third pad is disposed above the first pad and comprises the same material as the second power line.

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