Display device

Abstract

A display device includes a display panel including a first display area including first pixels and a second display area including a pixel portion in which second pixels are provided, and a transmissive portion through which light is transmitted. The pixel portion of the second display area includes a base member, a metal layer provided over the base member to define the transmissive portion, a first active layer provided over the metal layer and including a first material, and a first gate layer provided over the first active layer. A hole is defined by the metal layer so as to overlap at least a part of the first active layer in a thickness direction of the display panel.

Description

Technical Field

[0001] This disclosure relates to a display device. Background Technology

[0002] With the advancement of information technology, display devices for displaying images have become more widely used in various fields. Such display devices are used in a variety of electronic devices, such as smartphones, digital cameras, laptops, navigation devices, and smart televisions. In display devices where each pixel in the display panel includes a self-emissive light-emitting element, images can be displayed without a backlight unit for providing light to the display panel. Summary of the Invention

[0003] With the diversification of electronic devices employing display devices, it is desirable to provide display devices in various designs. In smartphones, for example, the display area can be expanded by removing the holes provided on the front surface of the display device. Sensor devices disposed in holes provided on the front surface of the display device can be configured to overlap with the display panel. Therefore, some pixels of the display panel overlap with and may be affected by the sensor devices.

[0004] During the light emission inspection of the pixel portion of the display panel, a portion of the active wiring of a defective pixel can be removed to prevent the defective pixel from emitting light. However, a metal layer disposed on the rear surface of some pixels overlapping with the sensor device can block the transmission of a laser beam that removes a portion of the active wiring.

[0005] Embodiments of this disclosure provide a display device in which a hole is defined by a metal layer disposed on the rear surface of a pixel portion of a second display area, such that when a defective pixel appears in the pixel portion of the second display area, the active wiring of the defective pixel can be opened (or the active wiring of the defective pixel is disabled) by a reversal repair process to prevent the defective pixel from lighting up. In the reversal repair process, a laser of a specific wavelength is emitted through the hole onto the active wiring.

[0006] According to embodiments of this disclosure, a display device includes: a display panel, the display panel including a first display area comprising a first pixel and a second display area comprising a pixel portion therein where a second pixel is disposed; and a transmissive portion through which light is transmitted. In such an embodiment, the pixel portion of the second display area includes: a substrate member; a metal layer disposed on the substrate member to define the transmissive portion; a first active layer disposed on the metal layer, wherein the first active layer comprises a first material; and a first gate layer disposed on the first active layer. In such an embodiment, an aperture is defined by the metal layer such that the aperture overlaps with at least a portion of the first active layer in the thickness direction of the display panel.

[0007] In one embodiment, each of the second pixels may include: a light-emitting element; a first transistor that controls a drive current supplied to the light-emitting element; and a second transistor that selectively supplies a data voltage to a first node, the first node being connected to a first electrode of the first transistor. In such an embodiment, the aperture may include a first aperture that partially overlaps with the active regions of the first transistor and the second transistor.

[0008] In one embodiment, the first hole may overlap with the second electrode of the second transistor connected to the first node.

[0009] In an embodiment, each of the second pixels may further include: a third transistor selectively connecting the second node to the third node, the second node being connected to the second electrode of the first transistor, and the third node being connected to the gate electrode of the first transistor; a fourth transistor selectively supplying a first initialization voltage to the third node; and a fifth transistor selectively supplying a drive voltage to the first node. In such an embodiment, the aperture may further include a second aperture that partially overlaps with the active regions of the first transistor and the fifth transistor.

[0010] In one embodiment, the second hole may overlap with the second electrode of the fifth transistor connected to the first node.

[0011] In one embodiment, each of the second pixels may further include a sixth transistor that selectively connects the second node to a fourth node, the fourth node being connected to the first electrode of the light-emitting element. In such an embodiment, the aperture may further include a third aperture that partially overlaps with the active region of the first transistor and the active region of the sixth transistor.

[0012] In one embodiment, the third hole may overlap with the first electrode of the sixth transistor connected to the second node.

[0013] In one embodiment, each of the second pixels may further include a seventh transistor that selectively supplies a second initialization voltage to the fourth node. In such an embodiment, the aperture may further include a fourth aperture that partially overlaps with the active regions of the sixth and seventh transistors.

[0014] In one embodiment, the fourth hole may overlap with the second electrode of the seventh transistor connected to the fourth node.

[0015] In an embodiment, the active region of each of the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor is defined by a portion of the first active layer.

[0016] In an embodiment, the pixel portion of the second display area may further include: a second gate layer disposed on the first gate layer; a second active layer disposed on the second gate layer, wherein the second active layer may include a second material different from the first material; and a third gate layer disposed on the second active layer. In such an embodiment, the active region of each of the third transistor and the fourth transistor may be defined by a portion of the second active layer.

[0017] In an embodiment, each of the second pixels may include: a light-emitting element; a first transistor that controls a drive current supplied to the light-emitting element; a second transistor that selectively supplies a data voltage to a first node, the first node being connected to a first electrode of the first transistor; a third transistor that selectively connects a second node to a third node, the second node being connected to a second electrode of the first transistor, and the third node being connected to the gate electrode of the first transistor; a fourth transistor that selectively supplies a first initialization voltage to the third node; and a fifth transistor that selectively supplies a drive voltage to the first node. In such an embodiment, the aperture may include a first aperture that partially overlaps with the active regions of the second transistor and the fifth transistor.

[0018] In an embodiment, the first hole may overlap with each of the second electrode of the second transistor connected to the first node and the second electrode of the fifth transistor connected to the first node.

[0019] In one embodiment, each of the second pixels may further include: a sixth transistor that selectively connects the second node to a fourth node, the fourth node being connected to a first electrode of the light-emitting element; and a seventh transistor that selectively supplies a second initialization voltage to the fourth node. In such an embodiment, the aperture may further include a second aperture that partially overlaps with the active regions of the first transistor and the seventh transistor.

[0020] In one embodiment, the second hole may overlap with the active region of the sixth transistor.

[0021] In one embodiment, the second hole may overlap with the first electrode of the sixth transistor connected to the second node and with the second electrode of the seventh transistor connected to the fourth node.

[0022] In one embodiment, the first hole and the second hole may be spaced apart from each other in a first direction and may extend in a second direction that intersects the first direction.

[0023] In an embodiment, each of the second pixels may include: a light-emitting element; a first transistor that controls a drive current supplied to the light-emitting element; a second transistor that selectively supplies a data voltage to a first node, the first node being connected to a first electrode of the first transistor; a third transistor that selectively connects a second node to a third node, the second node being connected to a second electrode of the first transistor, the third node being connected to a gate electrode of the first transistor; a fourth transistor that selectively supplies a first initialization voltage to the third node; a fifth transistor that selectively supplies a drive voltage to the first node; a sixth transistor that selectively connects the second node to a fourth node, the fourth node being connected to the first electrode of the light-emitting element; and a seventh transistor that selectively supplies a second initialization voltage to the fourth node. In such an embodiment, the aperture may partially overlap with the active regions of the second transistor and the seventh transistor.

[0024] In one embodiment, the hole may be bent at least once along the first active layer.

[0025] In an embodiment, the aperture may overlap with each of the second electrode of the second transistor connected to the first node, the second electrode of the fifth transistor connected to the first node, the first electrode of the sixth transistor connected to the second node, and the second electrode of the seventh transistor connected to the fourth node.

[0026] In an embodiment of the present invention, the display device may include a metal layer disposed between a pixel portion of a second display area and a substrate member to define a transmissive portion and a pixel portion of the second display area, and to define an aperture through the metal layer to overlap at least a portion of the active layer of the pixel portion in the thickness direction. Therefore, when a defective pixel appears in the pixel portion of the second display area, the active wiring of the defective pixel can be opened by a reversal repair process. In this reversal repair process, a laser of a specific wavelength is emitted through the aperture to the active wiring of the defective pixel, thereby preventing the defective pixel from lighting up. Attached Figure Description

[0027] The above and other features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0028] Figure 1 This is a perspective view showing a display device according to an embodiment;

[0029] Figure 2 This is an exploded perspective view showing a display device according to an embodiment;

[0030] Figure 3 This is a plan view showing the display panel according to an embodiment;

[0031] Figure 4 This is a block diagram illustrating a display panel and a display driver according to an embodiment;

[0032] Figure 5 This is a circuit diagram illustrating the pixels of a display device according to an embodiment;

[0033] Figure 6 It is supplied to Figure 5 The waveform diagram of the signal of the pixel shown;

[0034] Figure 7 This is a plan view showing the metal layer of the display device according to an embodiment;

[0035] Figure 8 This is a plan view showing a first sub-pixel of a pixel portion in a display device according to an embodiment;

[0036] Figure 9 It is shown Figure 8 A planar view of some layers of the first sub-pixel shown;

[0037] Figure 10 It is shown Figure 8 A planar view of some other layers of the first sub-pixel shown;

[0038] Figure 11 It is along Figure 8 A cross-sectional view taken from line I-I';

[0039] Figure 12 This is a plan view illustrating the metal layer of a display device according to an alternative embodiment;

[0040] Figure 13 This is a plan view illustrating some layers of a first sub-pixel in a display device according to an alternative embodiment;

[0041] Figure 14 This is a plan view illustrating the metal layer of a display device according to another alternative embodiment; and

[0042] Figure 15 This is a plan view illustrating some layers of a first sub-pixel in a display device according to another alternative embodiment. Detailed Implementation

[0043] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms, referring to non-limiting examples of apparatus or methods employing one or more inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are illustrated in block diagram form to avoid unnecessarily obscuring the various embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, specific shapes, configurations, and characteristics of embodiments may be used or implemented in another embodiment without departing from the inventive concept.

[0044] Unless otherwise stated, the illustrated embodiments are to be understood as exemplary features providing variable details in which certain aspects of the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be additionally combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0045] Crosshairs and / or shading are typically used in accompanying drawings to clarify the boundaries between adjacent elements. Thus, unless explicitly stated otherwise, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, dimensions, scale, commonalities between illustrated elements, and / or any other characteristics, properties, performance, etc., of the elements. Furthermore, the dimensions and relative dimensions of elements may be exaggerated in the drawings for clarity and / or descriptive purposes. A particular process sequence may be performed differently than the described sequence when exemplary embodiments can be implemented differently. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Additionally, the same reference numerals denote the same elements.

[0046] When a component or layer is referred to as being "on," "connected to," or "coupled to" another component or layer, the component or layer may be directly on, directly connected to, or directly coupled to the other component or layer, or there may be intermediate components or layers present. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another component or layer, there are no intermediate components or layers present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without intermediate components. Furthermore, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system such as the x-axis, y-axis, and z-axis, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0048] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship between one element and another (or more elements) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the exemplary term “below” can cover both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0049] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” is not to be construed as limited to “a” or “an.” “Or” means “and / or.”

[0050] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Furthermore, when used in this specification, the terms "comprising," "including," "containing," and / or "having" indicate the presence of the stated feature, integer, step, operation, element, component, and / or group thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially," "approximately," and other similar terms are used as terms of approximation rather than terms of degree, and are therefore used to explain the inherent biases in measurements, calculations, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0051] Various embodiments are described herein with reference to cross-sectional and / or exploded views, which are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Thus, variations in the shapes illustrated are expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the specific shapes shown for a particular region, but will include deviations in shape caused, for example, by manufacturing processes. In this way, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are therefore not necessarily intended to be limiting.

[0052] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings according to functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry, such as logic circuits, discrete components, microprocessors, hardwired circuitry, storage elements, and wiring connections, which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module may be implemented by dedicated hardware, or implemented as a combination of dedicated hardware performing some functions and processors (e.g., one or more programmable microprocessors and associated circuitry) performing other functions. Furthermore, without departing from the scope of the inventive concept, each block, unit, and / or module of some exemplary embodiments may be physically separated into two or more interacting and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, some exemplary blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense.

[0054] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0055] Figure 1 This is a perspective view showing a display device according to an embodiment. Figure 2 This is an exploded perspective view showing a display device according to an embodiment.

[0056] Reference Figure 1 and Figure 2 An embodiment of the display device 10 includes a cover window 100, a display panel 300, a bracket 600, a main circuit board 700, and a lower cover 900.

[0057] As used herein, the terms "above," "top," and "top surface" refer to the upward direction (i.e., the Z-axis direction) relative to the display device 10. As used herein, "below," "bottom," and "bottom surface" refer to the downward direction (i.e., the direction opposite to the Z-axis direction) relative to the display device 10. Furthermore, "left," "right," "up," and "down" indicate the direction when viewed from above. For example, the term "left" indicates the direction opposite to the X-axis direction, the term "right" indicates the X-axis direction, the term "up" indicates the Y-axis direction, and the term "down" indicates the direction opposite to the Y-axis direction.

[0058] Display device 10 is a device for displaying moving or still images. For example, display device 10 can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and Internet of Things (“IoT”) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs (tablet “PCs”), smartwatches, watch phones, mobile communication terminals, e-notebooks, e-books, portable multimedia players (“PMPs”), navigation systems, and ultra-mobile PCs (“UMPCs”).

[0059] The display device 10 may have a rectangular shape in a plan view. In one embodiment, for example, as Figure 1 and Figure 2 As shown, the display device 10 may have a rectangular shape in a plan view, the rectangular shape having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). The angle where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect may be rounded to have a predetermined curvature, or it may be a right angle. The planar shape of the display device 10 is not limited to a rectangular shape, and the display device 10 may be formed into another polygonal shape, a circular shape, or an elliptical shape.

[0060] Cover window 100 can be disposed on display panel 300 to cover the top surface of display panel 300. Cover window 100 can protect the top surface of display panel 300.

[0061] The cover window 100 may include a transmissive portion DA and a light-blocking portion LBP corresponding to the area other than the display panel 300. The transmissive portion DA includes a first transmissive portion DA1 and a second transmissive portion DA2 corresponding to the display panel 300. Figure 1 and Figure 2As shown, the second transmissive portion DA2 can be disposed on one side of the first transmissive portion DA1 (e.g., on top of the first transmissive portion DA1). The light-blocking portion LBP can be opaque. In embodiments where the light-blocking portion LBP does not display an image, the light-blocking portion LBP can be a decorative layer that is visible to the user.

[0062] The display panel 300 can be positioned below the cover window 100. Therefore, the image displayed by the display panel 300 can be seen on the top surface of the display device 10 through the cover window 100.

[0063] Display panel 300 may be a light-emitting display panel including light-emitting elements. In one embodiment, for example, display panel 300 may be an organic light-emitting display panel using organic light-emitting diodes (OLEDs) including organic light-emitting layers, a micro light-emitting diode display panel using micro light-emitting diodes, a quantum dot light-emitting display panel using quantum dot light-emitting diodes including quantum dot light-emitting layers, or an inorganic light-emitting display panel using inorganic light-emitting elements including inorganic semiconductors. In the following description, for ease of description, embodiments of display panel 300 as an organic light-emitting display panel will be primarily described, but it is not limited thereto.

[0064] The display panel 300 may include a main area MA and a protruding area PA that protrudes from one side of the main area MA.

[0065] The main area MA can include the first display area MDA, the second display area SDA, and the non-display area NDA.

[0066] The first display area MDA can overlap with the first transmissive portion DA1 of the cover window 100. The second display area SDA can overlap with the second transmissive portion DA2 of the cover window 100. For example... Figure 2 As shown, the second display area SDA can be disposed on one side of the first display area MDA (e.g., above the first display area MDA), but this disclosure is not limited thereto. In an alternative embodiment, for example, the second display area SDA can be disposed around the first display area MDA, and / or can be disposed adjacent to a corner of the display panel 300. In one embodiment, as Figure 2 As shown, the display panel 300 includes a single second display area SDA, but this disclosure is not limited thereto. In an alternative embodiment, for example, the display panel 300 may include multiple second display areas SDA.

[0067] Each of the first display area MDA and the second display area SDA may include multiple pixels, scan lines and data lines connected to the multiple pixels, and power lines.

[0068] The non-display area NDA can be defined as the edge area of ​​the display panel 300. The non-display area NDA may include a scan driver for applying gate signals to scan lines and a link line for connecting data lines to the display driver 310.

[0069] The protruding region PA can protrude from one side of the main region MA. In an embodiment, such as... Figure 2 As shown, the protruding region PA can protrude from the non-display region NDA located below the first display region MDA. In one embodiment, for example, the length of the protruding region PA in the first direction (X-axis direction) can be less than the length of the main region MA in the first direction (X-axis direction).

[0070] In one embodiment, the protruding region PA may include a curved region and a pad region. In such an embodiment, the pad region may be located on one side of the curved region, and the main region MA may be located on the opposite side of the curved region. In one embodiment, for example, the pad region may be located on the lower side of the curved region, and the main region MA may be located on the upper side of the curved region.

[0071] In this embodiment, the display panel 300 may be flexible, or may be flexibly formed such that the display panel 300 may be twisted, bent, folded, or rolled up. In such an embodiment, the display panel 300 may be bent in the thickness direction (Z-axis direction) in the bending region.

[0072] The display panel 300 may include a display driver 310, a circuit board 320, a power supply unit 330, and a touch driver 340.

[0073] The display driver 310 can output signals and voltages for driving the display panel 300. In one embodiment, for example, the display driver 310 can supply data voltage to a data line. In such an embodiment, the display driver 310 can supply power voltage to a power line and supply scan control signals to a scan driver.

[0074] The circuit board 320 can be attached to the pads using an anisotropic conductive film (“ACF”). In an embodiment, the leads of the circuit board 320 can be electrically connected to the pads of the display panel 300. In one embodiment, for example, the circuit board 320 can be a flexible printed circuit board, a printed circuit board (“PCB”), or a flexible film such as chip-on-film (“COF”).

[0075] A power supply unit 330 may be disposed on a circuit board 320 to supply driving voltage to the display driver 310 and the display panel 300. In an embodiment, the power supply unit 330 may generate a driving voltage and supply it to a driving voltage line, and the power supply unit 330 may generate a common voltage and supply it to the cathode electrode of the light-emitting element of each of the sub-pixels. In one embodiment, for example, the driving voltage may be a high potential voltage for driving the light-emitting element, and the common voltage may be a low potential voltage for driving the light-emitting element.

[0076] A touch driver 340 may be disposed on a circuit board 320 to measure the capacitance of the touch electrodes. In one embodiment, for example, the touch driver 340 may determine whether a user has touched the object and the location of the user's touch based on changes in the capacitance of the touch electrodes. Here, a user's touch refers to the direct contact between an object such as a user's finger or a pen and a surface of the display device 10 disposed on the touch sensing layer. In such an embodiment, the touch driver 340 may determine the user's touch location by distinguishing between portions of the plurality of touch electrodes where a user's touch has occurred and portions of the plurality of touch electrodes where a user's touch has not occurred.

[0077] The bracket 600 may be disposed below the display panel 300. The bracket 600 may comprise or be made of plastic, metal, or a combination thereof. In one embodiment, for example, the bracket 600 defines a first camera hole CMH1 through which a first camera sensor 720 is inserted, a battery hole BH through which a battery is disposed, a cable hole CAH through which a cable connected to the display driver 310 or circuit board 320 passes, and a sensor hole SH through which sensor devices 740, 750, 760, and 770 are disposed. In an alternative embodiment, for example, the sensor hole SH may be omitted, and the bracket 600 may be configured not to overlap with the second display area SDA of the display panel 300.

[0078] The main circuit board 700 and the battery 790 can be located below the bracket 600. The main circuit board 700 can be a PCB or a flexible printed circuit board (“FPCB”).

[0079] The main circuit board 700 may include a main processor 710, a first camera sensor 720, a main connector 730, and sensor devices 740, 750, 760, and 770. The first camera sensor 720 may be disposed on both the top and bottom surfaces of the main circuit board 700, the main processor 710 may be disposed on the top surface of the main circuit board 700, and the main connector 730 may be disposed on the bottom surface of the main circuit board 700. Sensor devices 740, 750, 760, and 770 may be disposed on the top surface of the main circuit board 700.

[0080] The main processor 710 can control the entire functionality of the display device 10. In one embodiment, for example, the main processor 710 can supply digital video data to the display driver 310, causing the display panel 300 to display an image. The main processor 710 can receive touch data from the touch driver 340 and determine the user's touch coordinates, and then execute the application indicated by the icon displayed at the user's touch coordinates. In such an embodiment, the main processor 710 can control the display device 10 based on sensor signals input from sensor devices 740, 750, 760, and 770.

[0081] The first camera sensor 720 can process still images or video frames acquired by the image sensor and can output the image frames or video to the main processor 710. The first camera sensor 720 may be a complementary metal-oxide-semiconductor (“CMOS”) image sensor or a charge-coupled device (“CCD”) sensor, but is not limited thereto. The first camera sensor 720 may be exposed to the bottom surface of the lower cover 900 through a second camera hole CMH2 defined through the lower cover 900 and capture images of the background or objects disposed below the display device 10.

[0082] A cable passing through the cable hole CAH in the bracket 600 can be connected to the main connector 730. Therefore, the main circuit board 700 can be electrically connected to the display driver 310 or the circuit board 320.

[0083] Sensor devices 740, 750, 760 and 770 may include a proximity sensor 740, an illuminance sensor 750, an iris sensor 760 and a second camera sensor 770, or may be referred to as a proximity sensor 740, an illuminance sensor 750, an iris sensor 760 and a second camera sensor 770, respectively.

[0084] The proximity sensor 740 can detect whether an object is near the top surface of the display device 10. In one embodiment, for example, the proximity sensor 740 may include a light source that outputs light and a light receiver that receives light reflected by the object. The proximity sensor 740 can determine the presence of an object positioned near the top surface of the display device 10 based on the amount of light reflected by the object. Since the proximity sensor 740 overlaps with the sensor hole SH, the second display area SDA of the display panel 300, and the second transmissive portion DA2 of the cover window 100 in the thickness direction (Z-axis direction) of the display panel 300, the proximity sensor 740 can generate a proximity sensor signal indicating the presence of an object positioned near the top surface of the display device 10, and can output the proximity sensor signal to the main processor 710.

[0085] The illuminance sensor 750 can detect the brightness of the top surface of the display device 10. The illuminance sensor 750 may include a resistor whose resistance value varies according to the brightness of the incident light. The illuminance sensor 750 can determine the brightness of the top surface of the display device 10 based on the resistance value of the resistor. Since the illuminance sensor 750 overlaps with the sensor hole SH, the second display area SDA of the display panel 300, and the second transmissive portion DA2 of the cover window 100 in the thickness direction (Z-axis direction) of the display panel 300, the illuminance sensor 750 can generate an illuminance sensor signal based on the brightness of the top surface of the display device 10 and output the illuminance sensor signal to the main processor 710.

[0086] The iris sensor 760 can detect whether the image of the user's iris is the same as the iris image previously stored in the memory. The iris sensor 760 can generate an iris sensor signal based on whether the user's iris image is the same as the iris image previously stored in the memory and output the iris sensor signal to the main processor 710.

[0087] The second camera sensor 770 can process still images or video frames obtained by the image sensor and can output the image frames or video to the main processor 710. In one embodiment, for example, the second camera sensor 770 can be a CMOS image sensor or a CCD sensor, but is not limited thereto. The number of pixels of the second camera sensor 770 can be less than the number of pixels of the first camera sensor 720, and the size of the second camera sensor 770 can be smaller than the size of the first camera sensor 720. Since the second camera sensor 770 overlaps with the sensor hole SH, the second display area SDA of the display panel 300, and the second transmissive portion DA2 of the cover window 100 in the thickness direction (Z-axis direction) of the display panel 300, the second camera sensor 770 can capture images of the background or objects disposed above the display device 10.

[0088] Battery 790 can be configured not to overlap with main circuit board 700 in the third direction (Z-axis direction). Battery 790 can overlap with battery hole BH of bracket 600.

[0089] The main circuit board 700 may also include a mobile communication module capable of transmitting and receiving radio signals with at least one of a base station, external terminal, and server in a mobile communication network. Depending on the transmission and reception of voice signals, video call signals, or messages, the radio signals may include various types of data.

[0090] The lower cover 900 may be disposed below the main circuit board 700 and the battery 790. The lower cover 900 may be secured by fastening to the bracket 600. The lower cover 900 may define or form the appearance of the bottom surface of the display device 10. The lower cover 900 may include or be made of plastic, metal or a combination thereof.

[0091] The second camera aperture CMH2 is defined by the lower cover 900, and the bottom surface of the first camera sensor 720 is exposed through the second camera aperture CMH2. The position of the first camera sensor 720 and the corresponding positions of the first camera aperture CMH1 and the second camera aperture CMH2 are not limited to... Figure 2 The location shown.

[0092] Figure 3 This is a plan view showing the display panel according to an embodiment. Figure 4 This is a block diagram illustrating a display panel and a display driver according to an embodiment.

[0093] Reference Figure 3 and Figure 4 An embodiment of the display panel 300 may include a first display area MDA, a second display area SDA, and a non-display area NDA.

[0094] The first display area MDA may include a first pixel SP1, a driving voltage line VDDL connected to the first pixel SP1, a gate line GL, an emission control line EML, and a data line DL.

[0095] Each of the first pixels SP1 can be connected to a corresponding gate line GL, a corresponding data line DL, a corresponding emitter control line EML, and a corresponding drive voltage line VDDL. In an embodiment, as shown... Figure 3 and Figure 4 As shown, each of the first pixels SP1 may be connected to two gate lines GL, a single data line DL, a single transmit control line EML, and a single drive voltage line VDDL, but this disclosure is not limited thereto. In an alternative embodiment, for example, each of the first pixels SP1 may be connected to three or more gate lines SL.

[0096] Each of the first pixels SP1 may include a switching transistor, a light-emitting element, and a capacitor.

[0097] The first pixel SP1 can receive the driving voltage VDD through the driving voltage line VDDL. In an embodiment, the driving voltage VDD can be a high potential voltage used to drive the light-emitting element of the first pixel SP1.

[0098] The gate line GL and the emitter control line EML can extend in a first direction (X-axis direction) and can be spaced apart from each other in a second direction (Y-axis direction) that intersects the first direction (X-axis direction).

[0099] The data line DL and the drive voltage line VDDL can extend in a second direction (Y-axis direction) and can be spaced apart from each other in a first direction (X-axis direction).

[0100] The second display area SDA may include a second pixel SP2 and a driving voltage line VDDL, a gate line GL, an emission control line EML, and a data line DL connected to the second pixel SP2.

[0101] Each of the second pixels SP2 can be connected to a corresponding gate line GL, a corresponding data line DL, a corresponding emitter control line EML, and a corresponding drive voltage line VDDL. In an embodiment, as shown... Figure 3 and Figure 4 As shown, each of the second pixels SP2 may be connected to two gate lines GL, a single data line DL, a single transmit control line EML, and a single drive voltage line VDDL, but this disclosure is not limited thereto. In an alternative embodiment, for example, each of the second pixels SP2 may be connected to three or more gate lines GL.

[0102] Each of the second pixels SP2 may include a switching transistor, a light-emitting element, and a capacitor.

[0103] The second pixel SP2 can receive the driving voltage VDD through the driving voltage line VDDL. In an embodiment, the driving voltage VDD can be a high potential voltage used to drive the light-emitting element of the second pixel SP2.

[0104] In one embodiment, for example, the number (or pixel density) of first pixels SP1 per unit area of ​​the first display area MDA can be greater than the number of second pixels SP2 per unit area of ​​the second display area SDA. The first display area MDA is the area used to display images, and displaying images is the primary function of the display device 10. The first pixels SP1 can be densely arranged in the first display area MDA. The second display area SDA may include a pixel portion in which the second pixels SP2 are disposed and a transmissive portion for transmitting light. Therefore, as the area of ​​the transmissive region of the second display area SDA increases, the number of second pixels SP2 per unit area can be less than the number of first pixels SP1 per unit area.

[0105] The non-display area NDA can be defined as the area of ​​the display panel 300 other than the first display area MDA and the second display area SDA. The non-display area NDA may include: a gate driver 410 for applying a gate signal to the gate line GL; an emit control driver 420 for applying an emit signal to the emit control line EML; a fan-out line FL for connecting the data line DL to the display driver 310; and a pad DP for connecting to the circuit board 320 (see [link to circuit board]). Figure 2 The display driver 310 and the pad DP can be set in the pad area of ​​the display panel 300. The pad DP can be set to be closer to an edge of the pad area than the display driver 310.

[0106] In an embodiment, such as Figure 4 As shown, the display driver 310 may include a timing controller 311 and a data driver 312.

[0107] The timing controller 311 can receive digital video data DATA and timing signals from the circuit board 320. Based on the timing signals, the timing controller 311 can generate a gate control signal GCS to control the operating timing of the gate driver 410, a transmit control signal ECS to control the operating timing of the transmit control driver 420, and a data control signal DCS to control the operating timing of the data driver 312. The timing controller 311 can output the gate control signal GCS to the gate driver 410 via the first gate control line GCL1. The timing controller 311 can output the transmit control signal ECS to the transmit control driver 420 via the second gate control line GCL2. The timing controller 311 can also output the digital video data DATA and the data control signal DCS to the data driver 312.

[0108] The data driver 312 can convert digital video data DATA into analog data voltage and output the data voltage to the data line DL via the fan-out line FL. The gate signal of the gate driver 410 can select the pixel SP to which the data voltage is supplied, and the selected pixel SP can receive the data voltage via the data line DL. The pixel SP may include the first pixel SP1 and the second pixel SP2 mentioned above.

[0109] In an embodiment, such as Figure 3As shown, the gate driver 410 can be disposed outside one side of the first display area MDA and the second display area SDA, or it can be disposed on the side of the non-display area NDA. The emitter control driver 420 can be disposed outside the opposite side of the first display area MDA and the second display area SDA, or it can be disposed on the opposite side of the non-display area NDA. In an alternative embodiment, both the gate driver 410 and the emitter control driver 420 can be disposed outside one side of the first display area MDA and the second display area SDA.

[0110] The gate driver 410 may include a plurality of thin-film transistors for generating a gate signal based on a gate control signal GCS, and the emitt control driver 420 may include a plurality of thin-film transistors for generating an emitt signal based on an emitt control signal ECS. In one embodiment, for example, the thin-film transistors of the gate driver 410 and the emitt control driver 420 may be disposed in the same layer as the thin-film transistors of the first pixel SP1 and the second pixel SP2, respectively.

[0111] Figure 5 This is a circuit diagram illustrating the pixels of a display device according to an embodiment. Figure 6 It is supplied to Figure 5 The waveform diagram of the signal of the pixel shown.

[0112] Reference Figure 5 and Figure 6 An embodiment of the display panel 300 may include a first pixel SP1 of a first display area MDA and a second pixel SP2 of a second display area SDA.

[0113] Each of the first pixel SP1 and the second pixel SP2 can be connected to the first gate line GL1, the second gate line GL2, the third gate line GL3, the fourth gate line GL4, the transmit control line EML, the data line DL, the drive voltage line VDDL or VSSL, the first initialization voltage line VIL1, and the second initialization voltage line VIL2.

[0114] Each of the first pixel SP1 and the second pixel SP2 may include a light-emitting element EL and pixel circuitry for driving the light-emitting element EL. The pixel circuitry may include multiple switching elements and capacitors. The multiple switching elements may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, a sixth transistor ST6, and a seventh transistor ST7.

[0115] The first transistor ST1 can control the drive current supplied to the light-emitting element EL. The first transistor ST1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor ST1 may be connected to a third node N3, the first electrode of the first transistor ST1 may be connected to a first node N1, and the second electrode of the first transistor ST1 may be connected to a second node N2. In one embodiment, for example, the first electrode of the first transistor ST1 may be the source electrode, and the second electrode of the first transistor ST1 may be the drain electrode, but this disclosure is not limited thereto.

[0116] The first transistor ST1 can control the source-drain current Isd (hereinafter referred to as the "drive current") based on the data voltage applied to the gate electrode. The drive current Isd flowing through the channel of the first transistor ST1 can be proportional to the square of the difference between the threshold voltage (Vth) and the voltage between the source and gate electrodes of the first transistor ST1 (Vsg) (i.e., Isd = k × (Vsg - Vth)). 2 Here, k represents the scaling factor determined by the structure and physical characteristics of the first transistor ST1, Vsg represents the source-gate voltage of the first transistor ST1, and Vth represents the threshold voltage of the first transistor ST1.

[0117] A light-emitting element (EL) can emit light by receiving a drive current Isd. The amount or brightness of light emitted by the EL can be proportional to the magnitude of the drive current Isd. The EL may include a first electrode, a second electrode, and a light-emitting layer disposed between the first and second electrodes. The first electrode of the EL may be connected to a fourth node N4. The second electrode of the EL may be connected to another drive voltage line VSSL. The first electrode of the EL can be connected to the second electrodes of the sixth transistor ST6 and the seventh transistor ST7 via the fourth node N4. In one embodiment, for example, the first electrode of the EL may be an anode electrode, and the second electrode of the EL may be a cathode electrode, but this disclosure is not limited thereto.

[0118] The second transistor ST2 can be turned on by the third gate signal GS3 of the third gate line GL3 to connect the data line DL to the first node N1, which is connected to the first electrode of the first transistor ST1. The second transistor ST2 can be turned on based on the third gate signal GS3 to supply a data voltage to the first node N1. The gate electrode of the second transistor ST2 can be connected to the third gate line GL3, the first electrode of the second transistor ST2 can be connected to the data line DL, and the second electrode of the second transistor ST2 can be connected to the first node N1. The second electrode of the second transistor ST2 can be connected to the first electrode of the first transistor ST1 and the second electrode of the fifth transistor ST5 through the first node N1. In one embodiment, for example, the first electrode of the second transistor ST2 can be the source electrode, and the second electrode of the second transistor ST2 can be the drain electrode, but this disclosure is not limited thereto.

[0119] The third transistor ST3 can be turned on via the fourth gate signal GS4 of the fourth gate line GL4 to connect the second node N2 to the third node N3. The second node N2 is connected to the second electrode of the first transistor ST1, and the third node N3 is connected to the gate electrode of the first transistor ST1. The gate electrode of the third transistor ST3 can be connected to the fourth gate line GL4. The first electrode of the third transistor ST3 can be connected to the second node N2, and the second electrode of the third transistor ST3 can be connected to the third node N3. The first electrode of the third transistor ST3 can be connected via the second node N2 to the second electrode of the first transistor ST1 and the first electrode of the sixth transistor ST6. The second electrode of the third transistor ST3 can be connected via the third node N3 to the gate electrode of the first transistor ST1, the second electrode of the fourth transistor ST4, and the first electrode of the capacitor C1. In one embodiment, for example, the first electrode of the third transistor ST3 can be the drain electrode, and the second electrode of the third transistor ST3 can be the source electrode, but it is not limited thereto.

[0120] The fourth transistor ST4 can be turned on by the first gate signal GS1 of the first gate line GL1 to connect the first initialization voltage line VIL1 to the third node N3, which is connected to the gate electrode of the first transistor ST1. The fourth transistor ST4 can be turned on based on the first gate signal GS1, thereby discharging the gate electrode of the first transistor ST1 to the first initialization voltage. The gate electrode of the fourth transistor ST4 can be connected to the first gate line GL1, the first electrode of the fourth transistor ST4 can be connected to the first initialization voltage line VIL1, and the second electrode of the fourth transistor ST4 can be connected to the third node N3. The second electrode of the fourth transistor ST4 can be connected to the gate electrode of the first transistor ST1, the second electrode of the third transistor ST3, and the first electrode of the capacitor C1 via the third node N3. In one embodiment, for example, the first electrode of the fourth transistor ST4 can be the drain electrode, and the second electrode of the fourth transistor ST4 can be the source electrode, but it is not limited thereto.

[0121] The fifth transistor ST5 can be turned on by the emit signal EM of the emit control line EML to connect the drive voltage line VDDL to the first node N1, which is connected to the first electrode of the first transistor ST1. The gate electrode of the fifth transistor ST5 can be connected to the emit control line EML, the first electrode of the fifth transistor ST5 can be connected to the drive voltage line VDDL, and the second electrode of the fifth transistor ST5 can be connected to the first node N1. The second electrode of the fifth transistor ST5 can be electrically connected to the first electrode of the first transistor ST1 and the second electrode of the second transistor ST2 through the first node N1. In one embodiment, for example, the first electrode of the fifth transistor ST5 can be the source electrode, and the second electrode of the fifth transistor ST5 can be the drain electrode, but this disclosure is not limited thereto.

[0122] The sixth transistor ST6 can be turned on by the emit signal EM of the emit control line EML to connect the second node N2 to the fourth node N4. The second node N2 is connected to the second electrode of the first transistor ST1, and the fourth node N4 is connected to the first electrode of the plurality of light-emitting elements EL. The gate electrode of the sixth transistor ST6 can be connected to the emit control line EML, the first electrode of the sixth transistor ST6 can be connected to the second node N2, and the second electrode of the sixth transistor ST6 can be connected to the fourth node N4. The first electrode of the sixth transistor ST6 can be connected to the second electrode of the first transistor ST1 and the first electrode of the third transistor ST3 via the second node N2. The second electrode of the sixth transistor ST6 can be connected to the first electrode of the light-emitting element EL and the second electrode of the seventh transistor ST7 via the fourth node N4. In one embodiment, for example, the first electrode of the sixth transistor ST6 can be the source electrode, and the second electrode of the sixth transistor ST6 can be the drain electrode, but this disclosure is not limited thereto.

[0123] When the fifth transistor ST5, the first transistor ST1, and the sixth transistor ST6 are all turned on, the drive current Isd can be supplied to multiple light-emitting elements EL.

[0124] The seventh transistor ST7 can be turned on by the second gate signal GS2 of the second gate line GL2 to connect the second initialization voltage line VIL2 to the fourth node N4, which is connected to the first electrode of the light-emitting element EL. The seventh transistor ST7 can also be turned on based on the second gate signal GS2, thereby discharging the first electrode of the light-emitting element EL to the second initialization voltage. The gate electrode of the seventh transistor ST7 can be connected to the second gate line GL2, the first electrode of the seventh transistor ST7 can be connected to the second initialization voltage line VIL2, and the second electrode of the seventh transistor ST7 can be connected to the fourth node N4. The second electrode of the seventh transistor ST7 can be connected to the first electrode of the light-emitting element EL and the second electrode of the sixth transistor ST6 via the fourth node N4.

[0125] Each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 may include a silicon-based active region. In one embodiment, for example, each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 may include an active region comprising or made of low-temperature polycrystalline silicon (“LTPS”). Active regions comprising or made of LTPS can have high electron mobility and excellent conduction characteristics. Therefore, in embodiments where the display device 10 includes the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 with high conduction characteristics, multiple pixels SP (see [link to documentation]) can be driven stably and efficiently. Figure 3 ).

[0126] Each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 can be a p-type transistor. In one embodiment, for example, each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 can output the current flowing into the first electrode to the second electrode based on a low gate voltage applied to the gate electrode.

[0127] Each of the third transistor ST3 and the fourth transistor ST4 may include an oxide-based active region. In one embodiment, for example, each of the third transistor ST3 and the fourth transistor ST4 may have a coplanar structure in which the gate electrode is disposed on the oxide-based active region. Transistors with a coplanar structure can have high cutoff current characteristics and perform low-frequency driving, thereby reducing power consumption. Therefore, the display device 10 may include the third transistor ST3 and the fourth transistor ST4 with high cutoff current characteristics, thereby effectively preventing leakage current from flowing in the pixel and stably maintaining the voltage in the pixel.

[0128] Each of the third transistor ST3 and the fourth transistor ST4 can be an n-type transistor. In one embodiment, for example, each of the third transistor ST3 and the fourth transistor ST4 can output the current flowing into the first electrode to the second electrode based on a high gate voltage applied to the gate electrode.

[0129] Capacitor C1 can be connected between the third node N3 and the drive voltage line VDDL, with the third node N3 connected to the gate electrode of the first transistor ST1. In one embodiment, for example, the first electrode of capacitor C1 can be connected to the third node N3, and the second electrode of capacitor C1 can be connected to the drive voltage line VDDL, thereby maintaining the potential difference between the drive voltage line VDDL and the gate electrode of the first transistor ST1.

[0130] Combination Figure 5 For reference Figure 6 An embodiment of the display device 10 can be driven during the first time period t1 to the fifth time period t5 of a frame. Pixel SP (see...) Figure 3 It can receive the first gate signal GS1, the second gate signal GS2, the third gate signal GS3, the fourth gate signal GS4, and the transmit signal EM.

[0131] The fourth transistor ST4 can receive a high-level first gate signal GS1 during the first time period t1 of a frame. The fourth transistor ST4 can be turned on based on the high-level first gate signal GS1 to supply a first initialization voltage to the third node N3, which is connected to the gate electrode of the first transistor ST1. Therefore, the fourth transistor ST4 can initialize the gate electrode of the first transistor ST1 during the first time period t1.

[0132] The seventh transistor ST7 can receive a low-level second gate signal GS2 during the second time period t2 of a frame. The seventh transistor ST7 can be turned on based on the low-level second gate signal GS2 to supply a second initialization voltage to the fourth node N4, which is connected to the first electrode of the light-emitting element EL. Therefore, the seventh transistor ST7 can initialize the first electrode of the light-emitting element EL during the second time period t2.

[0133] The second transistor ST2 can receive a low-level third gate signal GS3 during the third time period t3 of a frame. The second transistor ST2 can be turned on based on the low-level third gate signal GS3 to supply the data voltage Vdata to the first node N1, which is connected to the first electrode of the first transistor ST1.

[0134] The third transistor ST3 can receive a high-level fourth gate signal GS4 during the fourth time period t4 of a frame. The third transistor ST3 can be turned on based on the high-level fourth gate signal GS4, and can connect the second node N2 to the third node N3.

[0135] When the first electrode of the first transistor ST1 receives the data voltage Vdata, the source-gate voltage (Vsg) of the first transistor ST1 corresponds to the voltage difference (Vdata-VI1) between the data voltage Vdata and the first initialization voltage VI1. Since the source-gate voltage (Vsg) of the first transistor ST1 is greater than the threshold voltage (hereinafter referred to as "Vth") (i.e., Vdata-VI1≥Vth), the first transistor ST1 can be turned on. Therefore, at the moment when the first transistor ST1 is turned on in the third time period t3, the source-drain current Isd of the first transistor ST1 can be determined based on the data voltage Vdata, the first initialization voltage VI1, and the threshold voltage (Vth) of the first transistor ST1 (i.e., Isd=k×(Vdata-VI1-Vth)). 2 The first transistor ST1 can supply the source-drain current Isd to the second node N2 until the source-gate voltage (Vsg) reaches the threshold voltage (Vth) of the first transistor ST1.

[0136] In such an embodiment, the third transistor ST3 can be turned on during the fourth time period t4 to supply the voltage of the second node N2 to the third node N3. In this way, when the third transistor ST3 is turned on, the voltage of the third node N3 and the source-drain current Isd of the first transistor ST1 can be changed, and the voltage of the third node N3 can eventually converge to the voltage difference (Vdata-Vth) between the data voltage Vdata and the threshold voltage (Vth) of the first transistor ST1.

[0137] The transmit signal EM can have a low gate voltage during the fifth time period t5. When the transmit signal EM is at a low level, the fifth transistor ST5 and the sixth transistor ST6 can be turned on to supply the drive current Isd to the light-emitting element EL.

[0138] Figure 7 This is a plan view showing the metal layer of the display device according to an embodiment.

[0139] Reference Figure 2 and Figure 7 The display panel 300 may include a first display area MDA and a second display area SDA, and the second display area SDA may include a pixel portion PXA and a transmissive portion TA. A metal layer BML may be disposed between the substrate component and the thin-film transistor layer to define the pixel portion PXA and the transmissive portion TA. Figure 2 For reference Figure 7The metal layer BML can overlap with the pixel portion PXA of the second display area SDA, thereby preventing light passing through the pixel portion PXA from reaching the sensor devices 740, 750, 760, and 770. The metal layer BML is configured not to overlap with the transmissive portion TA of the second display area SDA, so that the transmissive portion TA allows light incident on the display panel 300 to pass through almost exactly as it was. Therefore, even if the sensor devices 740, 750, 760, and 770 are located below the display panel 300, they can still detect light incident from above the display panel 300.

[0140] The transmissive portion TA may include multiple transmissive portions TA separated by a metal layer BML. In one embodiment, for example, the multiple transmissive portions TA may be spaced apart from each other by the metal layer BML. The multiple transmissive portions TA may be surrounded by the metal layer BML. The multiple transmissive portions TA may be arranged along a first direction (X-axis direction) and a second direction (Y-axis direction).

[0141] In one embodiment, at least one aperture BMH is defined by a metal layer BML. The at least one aperture BMH may overlap with at least a portion of a first active layer disposed in the pixel portion PXA in the thickness direction (or Z-axis direction). In another embodiment, the at least one aperture BMH is defined by the metal layer BML to overlap with at least a portion of the first active layer of the pixel portion PXA, thereby allowing light that has passed through the substrate member from the bottom of the pixel portion PXA to reach the first active layer.

[0142] In one embodiment, for example, the metal layer BML may be configured not to overlap with the first display area MDA, but is not limited thereto.

[0143] The pixel portion PXA may include a first sub-pixel region PRA, a second sub-pixel region PGA, and a third sub-pixel region PBA. The first sub-pixel region PRA, the second sub-pixel region PGA, and the third sub-pixel region PBA may each include a first sub-pixel to a third sub-pixel that emits light of a different color than the others. The first sub-pixel region PRA, the second sub-pixel region PGA, and the third sub-pixel region PBA may each emit light using a light-emitting element EL of the first sub-pixel to the third sub-pixel.

[0144] In one embodiment, for example, the number of first pixels SP1 per unit area of ​​the first display area MDA can be greater than the number of second pixels SP2 per unit area of ​​the second display area SDA. The first display area MDA is the area used to display images, and displaying images is the main function of the display device 10. The first pixels SP1 can be densely arranged in the first display area MDA. The second display area SDA may include a pixel portion PXA in which the second pixels SP2 are disposed and a transmissive portion TA for transmitting light. Therefore, as the size of the transmissive area of ​​the second display area SDA increases, the number of second pixels SP2 per unit area can be less than the number of first pixels SP1 per unit area.

[0145] Figure 8 This is a plan view showing the first sub-pixel of a pixel portion in a display device according to an embodiment. Figure 9 It is shown Figure 8 The first sub-pixel is shown in a planar diagram of some layers. Figure 10 It is shown Figure 8 The first subpixel is shown in a plan view of some other layers. Figure 8 This can correspond to a diagram showing a structure in which a metal layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, and a second source-drain layer are stacked on top of each other in sequence. Figure 9 This can correspond to a diagram showing a structure in which a metal layer, a first active layer, a first gate layer, and a second gate layer are stacked sequentially on top of each other. Figure 10 This can correspond to a diagram showing a structure in which the second active layer, the third gate layer, the first source-drain layer, and the second source-drain layer are stacked on top of each other in sequence. (See below for further details.) Figure 11 More detailed description Figures 8 to 10 The stacking relationship of each layer.

[0146] Reference Figures 7 to 10 In this embodiment, the pixel portion PXA may include a first sub-pixel region PRA, a second sub-pixel region PGA, and a third sub-pixel region PBA. The first sub-pixel may be disposed in the first sub-pixel region PRA. The first sub-pixel may include a light-emitting element EL and a pixel circuit, and the pixel circuit may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, a sixth transistor ST6, and a seventh transistor ST7, as well as a capacitor C1.

[0147] The first transistor ST1 may include an active region ACT1, a gate electrode G1, a first electrode S1, and a second electrode D1. The active region ACT1 of the first transistor ST1 may overlap with the gate electrode G1 of the first transistor ST1. In one embodiment, for example, the active region ACT1 of the first transistor ST1 may include LTPS or be formed of LTPS.

[0148] The gate electrode G1 of the first transistor ST1 can be connected to the third connection electrode BE3 through the sixth contact hole CNT6, and the third connection electrode BE3 can be connected to the second electrode S3 of the third transistor ST3 and the second electrode S4 of the fourth transistor ST4 through the fifth contact hole CNT5. Furthermore, the region where the gate electrode G1 of the first transistor ST1 overlaps with the second electrode CE2 of the capacitor C1 can correspond to the first electrode CE1 of the capacitor C1; for example, the first electrode CE1 of the capacitor C1 can be defined.

[0149] The first electrode S1 of the first transistor ST1 can be connected to the second electrode D2 of the second transistor ST2 and the second electrode D5 of the fifth transistor ST5.

[0150] The second electrode D1 of the first transistor ST1 can be connected to the first electrode D3 of the third transistor ST3 and the first electrode S6 of the sixth transistor ST6. The second electrode D1 of the first transistor ST1 can be connected to the second connecting electrode BE2 through the third contact hole CNT3, and the second connecting electrode BE2 can be connected to the first electrode D3 of the third transistor ST3 through the fourth contact hole CNT4.

[0151] The second transistor ST2 may include an active region ACT2, a gate electrode G2, a first electrode S2, and a second electrode D2. The active region ACT2 of the second transistor ST2 may overlap with the gate electrode G2 of the second transistor ST2. In one embodiment, for example, the active region ACT2 of the second transistor ST2 may include LTPS or be made of LTPS. The gate electrode G2 of the second transistor ST2, which is part of a third gate line GL3, may correspond to the region of the third gate line GL3 that overlaps with the active region ACT2.

[0152] The first electrode S2 of the second transistor ST2 can be connected to the first connection electrode BE1 through the first contact hole CNT1, and the first connection electrode BE1 can be connected to the data line DL through the second contact hole CNT2.

[0153] The second electrode D2 of the second transistor ST2 can be connected to the first electrode S1 of the first transistor ST1 and the second electrode D5 of the fifth transistor ST5.

[0154] The third transistor ST3 may include an active region ACT3, a gate electrode G3, a first electrode D3, and a second electrode S3. The active region ACT3 of the third transistor ST3 may overlap with the gate electrode G3 of the third transistor ST3. In one embodiment, for example, the active region ACT3 of the third transistor ST3 may include an oxide-based active region. The gate electrode G3 of the third transistor ST3, which is part of a fourth gate line GL4, may correspond to the region of the fourth gate line GL4 that overlaps with the active region ACT3.

[0155] The first electrode D3 of the third transistor ST3 can be connected to the second connecting electrode BE2 through the fourth contact hole CNT4, and the second connecting electrode BE2 can be connected to the second electrode D1 of the first transistor ST1 and the first electrode S6 of the sixth transistor ST6 through the third contact hole CNT3.

[0156] The second electrode S3 of the third transistor ST3 can be connected to the second electrode S4 of the fourth transistor ST4. The second electrode S3 of the third transistor ST3 can be connected to the third connection electrode BE3 through the fifth contact hole CNT5, and the third connection electrode BE3 can be connected to the gate electrode G1 of the first transistor ST1 through the sixth contact hole CNT6. In addition, the region where the gate electrode G1 of the first transistor ST1 overlaps with the second electrode CE2 of the capacitor C1 can correspond to the first electrode CE1 of the capacitor C1.

[0157] The fourth transistor ST4 may include an active region ACT4, a gate electrode G4, a first electrode D4, and a second electrode S4. The active region ACT4 of the fourth transistor ST4 may overlap with the gate electrode G4 of the fourth transistor ST4. In one embodiment, for example, the active region ACT4 of the fourth transistor ST4 may include an oxide-based active region. The gate electrode G4 of the fourth transistor ST4, which is part of a first gate line GL1, may correspond to the region of the first gate line GL1 that overlaps with the active region ACT4.

[0158] The first electrode D4 of the fourth transistor ST4 can be connected to the fourth connection electrode BE4 through the eighth contact hole CNT8, and the fourth connection electrode BE4 can be connected to the first initialization voltage line VIL1 through the seventh contact hole CNT7.

[0159] The second electrode S4 of the fourth transistor ST4 can be connected to the second electrode S3 of the third transistor ST3. The second electrode S4 of the fourth transistor ST4 can be connected to the third connection electrode BE3 through the fifth contact hole CNT5, and the third connection electrode BE3 can be connected to the gate electrode G1 of the first transistor ST1 through the sixth contact hole CNT6. In addition, the region where the gate electrode G1 of the first transistor ST1 overlaps with the second electrode CE2 of the capacitor C1 can correspond to the first electrode CE1 of the capacitor C1.

[0160] The fifth transistor ST5 may include an active region ACT5, a gate electrode G5, a first electrode S5, and a second electrode D5. The active region ACT5 of the fifth transistor ST5 may overlap with the gate electrode G5 of the fifth transistor ST5. In one embodiment, for example, the active region ACT5 of the fifth transistor ST5 may include LTPS or be formed of LTPS. The gate electrode G5 of the fifth transistor ST5, which is part of the emitter control line EML, may correspond to the region of the emitter control line EML that overlaps with the active region ACT5.

[0161] The first electrode S5 of the fifth transistor ST5 can be connected to the drive voltage line VDDL through the tenth contact hole CNT10.

[0162] The second electrode D5 of the fifth transistor ST5 can be connected to the first electrode S1 of the first transistor ST1 and the second electrode D2 of the second transistor ST2.

[0163] The sixth transistor ST6 may include an active region ACT6, a gate electrode G6, a first electrode S6, and a second electrode D6. The active region ACT6 of the sixth transistor ST6 may overlap with the gate electrode G6 of the sixth transistor ST6. In one embodiment, for example, the active region ACT6 of the sixth transistor ST6 may include or be formed of LTPS. The gate electrode G6 of the sixth transistor ST6, which is part of the emitter control line EML, may correspond to the region of the emitter control line EML that overlaps with the active region ACT6.

[0164] The first electrode S6 of the sixth transistor ST6 can be connected to the second electrode D1 of the first transistor ST1. The first electrode S6 of the sixth transistor ST6 can be connected to the second connection electrode BE2 through the third contact hole CNT3, and the second connection electrode BE2 can be connected to the first electrode D3 of the third transistor ST3 through the fourth contact hole CNT4.

[0165] The second electrode D6 of the sixth transistor ST6 can be connected to the second electrode D7 of the seventh transistor ST7. The second electrode D6 of the sixth transistor ST6 can be connected to the sixth connecting electrode BE6 through the eleventh contact hole CNT11, and the sixth connecting electrode BE6 can be connected to the anode connecting electrode ANDE through the twelfth contact hole CNT12. The anode connecting electrode ANDE can be directly or indirectly connected to the first electrode of the light-emitting element EL.

[0166] The seventh transistor ST7 may include an active region ACT7, a gate electrode G7, a first electrode S7, and a second electrode D7. The active region ACT7 of the seventh transistor ST7 may overlap with the gate electrode G7 of the seventh transistor ST7. In one embodiment, for example, the active region ACT7 of the seventh transistor ST7 may include LTPS or be formed of LTPS. The gate electrode G7 of the seventh transistor ST7, which is part of the second gate line GL2, may correspond to the region of the second gate line GL2 that overlaps with the active region ACT7.

[0167] The first electrode S7 of the seventh transistor ST7 can be connected to the fifth connection electrode BE5 through the fourteenth contact hole CNT14, and the fifth connection electrode BE5 can be connected to the second initialization voltage line VIL2 through the thirteenth contact hole CNT13.

[0168] The second electrode D7 of the seventh transistor ST7 can be connected to the second electrode D6 of the sixth transistor ST6. The second electrode D7 of the seventh transistor ST7 can be connected to the sixth connecting electrode BE6 through the eleventh contact hole CNT11, and the sixth connecting electrode BE6 can be connected to the anode connecting electrode ANDE through the twelfth contact hole CNT12. The anode connecting electrode ANDE can be directly or indirectly connected to the first electrode of the light-emitting element EL.

[0169] Capacitor C1 may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 of capacitor C1, which is part of the gate electrode G1 of the first transistor ST1, may correspond to the region of the gate electrode G1 of the first transistor ST1 that overlaps with the second electrode CE2 of capacitor C1. The second electrode CE2 of capacitor C1 may be connected to the drive voltage line VDDL through a ninth contact hole CNT9.

[0170] In one embodiment, at least one aperture BMH is defined by a metal layer BML. The at least one aperture BMH may overlap with at least a portion of a first active layer disposed in the pixel portion PXA in the thickness direction. The metal layer BML or the at least one aperture BMH may include a first aperture BMH1, a second aperture BMH2, a third aperture BMH3, and a fourth aperture BMH4. The first aperture BMH1, the second aperture BMH2, the third aperture BMH3, and the fourth aperture BMH4 may be spaced apart from each other.

[0171] The first aperture BMH1 may partially overlap with the active region ACT1 of the first transistor ST1 and the active region ACT2 of the second transistor ST2. In one embodiment, for example, the first aperture BMH1 may overlap with the second electrode D2 of the second transistor ST2 connected to the first node N1. In the inversion repair process, light of a specific wavelength (e.g., a laser) can pass through the first aperture BMH1 to remove a portion of the first active layer, thereby preventing the connection between the first transistor ST1 and the second transistor ST2.

[0172] The second aperture BMH2 may partially overlap with the active region ACT1 of the first transistor ST1 and the active region ACT5 of the fifth transistor ST5. In one embodiment, for example, the second aperture BMH2 may overlap with the second electrode D5 of the fifth transistor ST5 connected to the first node N1. In the inversion repair process, light of a specific wavelength (e.g., a laser) can pass through the second aperture BMH2 to remove a portion of the first active layer, thereby preventing the connection between the first transistor ST1 and the fifth transistor ST5.

[0173] The third aperture BMH3 may partially overlap with the active region ACT1 of the first transistor ST1 and the active region ACT6 of the sixth transistor ST6. In one embodiment, for example, the third aperture BMH3 may overlap with the first electrode S6 of the sixth transistor ST6 connected to the second node N2. In the inversion repair process, light of a specific wavelength (e.g., a laser) can pass through the third aperture BMH3 to remove a portion of the first active layer, thereby preventing the connection between the first transistor ST1 and the sixth transistor ST6.

[0174] The fourth aperture BMH4 may partially overlap with the active region ACT6 of the sixth transistor ST6 and the active region ACT7 of the seventh transistor ST7. In one embodiment, for example, the fourth aperture BMH4 may overlap with the second electrode D7 of the seventh transistor ST7 connected to the fourth node N4. In the inversion repair process, light of a specific wavelength (e.g., a laser) can pass through the fourth aperture BMH4 to remove a portion of the first active layer, thereby preventing the connection between the sixth transistor ST6 and the seventh transistor ST7 from being established.

[0175] In an embodiment of the method for manufacturing the display device 10, after forming the second pixel SP2 of the pixel portion PXA, defective pixels in the second pixel SP2 of the display device 10 can be detected. When a defective pixel of the pixel portion PXA is detected, the active wiring or pixel circuit wiring of the defective pixel can be opened (i.e., the active wiring or pixel circuit wiring of the defective pixel is disconnected or disabled) through a reversal repair process. In the reversal repair process, a laser of a specific wavelength is emitted through the first hole BMH1 to the fourth hole BMH4 toward the active wiring or pixel circuit wiring of the defective pixel. In the reversal repair process, light of a specific wavelength (e.g., laser) can irradiate from the bottom of the substrate member toward a portion of the first active layer, and the light of the specific wavelength can pass through at least one hole BMH of the metal layer BML to reach a portion of the first active layer. In such an embodiment, the metal layer BML can prevent light of the specific wavelength from reaching unwanted points. Therefore, since the light-blocking metal layer BML includes at least one aperture BMH, when a defective pixel appears, the active wiring or pixel circuit wiring of the defective pixel can be opened by a reversal repair process, thereby preventing the defective pixel from lighting up. In the reversal repair process, a laser of a specific wavelength is emitted through at least one aperture BMH to the active wiring or pixel circuit wiring of the defective pixel. The display device 10 can have improved reliability and improved image quality.

[0176] Figure 11 It is along Figure 8 The cross-sectional view taken from line I-I'.

[0177] Combination Figure 2 , Figure 5 , Figures 7 to 10 For reference Figure 11 An embodiment of the display panel 300 may include a substrate SUB, a metal layer BML, a buffer layer BF, a first active layer ACTL1, a first gate insulating layer GI1, a first gate layer GTL1, a first interlayer insulating layer ILD1, a second gate layer GTL2, a second interlayer insulating layer ILD2, a second active layer ACTL2, a second gate insulating layer GI2, a third gate layer GTL3, a third interlayer insulating layer ILD3, a first source-drain layer SDL1, a fourth interlayer insulating layer ILD4, and a second source-drain layer SDL2.

[0178] The substrate SUB can be a matrix substrate or a matrix component, and can include or be made of an insulating material such as a polymer resin. In one embodiment, for example, the substrate SUB can be a flexible substrate that is bendable, foldable, and / or rollable.

[0179] A metal layer BML can be disposed on the substrate SUB to define the pixel portion PXA and the transmissive portion TA of the second display area SDA. The metal layer BML can overlap at least a portion of the first active layer ACTL1 disposed in the pixel portion PXA in the thickness direction. The metal layer BML can overlap with the pixel portion PXA of the second display area SDA, thereby preventing light passing through the pixel portion PXA from reaching the sensor devices 740, 750, 760, and 770. The metal layer BML is configured not to overlap with the transmissive portion TA of the second display area SDA, such that the transmissive portion TA allows light incident on the display panel 300 to pass through almost unchanged. Therefore, even if the sensor devices 740, 750, 760, and 770 are disposed below the display panel 300, the sensor devices 740, 750, 760, and 770 can detect light incident from above the display panel 300.

[0180] In one embodiment, a first via BMH1 is defined by a metal layer BML. The first via BMH1 may partially overlap with the active region ACT1 of the first transistor ST1 and the active region ACT2 of the second transistor ST2. In one embodiment, for example, the first via BMH1 may be connected to the first node N1 of the second transistor ST2 (see [link to embodiment]). Figure 5 The second electrode D2 overlaps. In the inversion repair process, light of a specific wavelength (e.g., laser) can pass through the first hole BMH1 to remove a portion of the first active layer ACTL1, thereby preventing the connection between the first transistor ST1 and the second transistor ST2.

[0181] A buffer layer BF can be disposed on the substrate SUB to cover the metal layer BML. In one embodiment, for example, the buffer layer BF may include multiple inorganic layers and may be formed on the entire top surface of the substrate SUB to prevent moisture from penetrating through the substrate SUB into the light-emitting element EL.

[0182] The first active layer ACTL1 may be disposed on the buffer layer BF. The first active layer ACTL1 may include or be made of a silicon-based material. In one embodiment, for example, the first active layer ACTL1 may include or be formed of LTPS. Each of the active regions ACT1, ACT2, ACT5, ACT6 and ACT7 of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6 and the seventh transistor ST7, the first electrodes S1, S2, S5, S6 and S7, and the second electrodes D1, D2, D5, D6 and D7 may be defined by a portion of the first active layer ACTL1.

[0183] The first gate insulating layer GI1 can cover the buffer layer BF and the first active layer ACTL1, and make the first active layer ACTL1 insulated from the first gate layer GTL1.

[0184] The first gate layer GTL1 may be disposed on the first gate insulating layer GI1. Each of the gate electrode G1, the second gate line GL2, the third gate line GL3, and the emitter control line EML of the first transistor ST1 may be defined by a portion of the first gate layer GTL1.

[0185] A portion of the gate electrode G1 of the first transistor ST1 can overlap with the second electrode CE2 of the capacitor C1 to form the first electrode CE1 of the capacitor C1.

[0186] Reference Figure 8 A portion of the second gate line GL2 may overlap with the active region ACT7 of the seventh transistor ST7 to form (e.g., define or serve as) the gate electrode G7 of the seventh transistor ST7.

[0187] A portion of the third gate line GL3 may overlap with the active region ACT2 of the second transistor ST2 to form the gate electrode G2 of the second transistor ST2.

[0188] Reference Figure 8 A portion of the emitter control line EML may overlap with the active region ACT5 of the fifth transistor ST5 to form the gate electrode G5 of the fifth transistor ST5. Another portion of the emitter control line EML may overlap with the active region ACT6 of the sixth transistor ST6 to form the gate electrode G6 of the sixth transistor ST6.

[0189] The first interlayer insulating layer ILD1 can cover the first gate layer GTL1 and the first gate insulating layer GI1. The first interlayer insulating layer ILD1 can insulate the first gate layer GTL1 from the second gate layer GTL2.

[0190] The second gate layer GTL2 may be disposed on the first interlayer insulating layer ILD1. Each of the first light-blocking layer LS1, the second light-blocking layer LS2, the second electrode CE2 of capacitor C1, the first initialization voltage line VIL1, and the second initialization voltage line VIL2 may be defined by a portion of the second gate layer GTL2.

[0191] The first light-blocking layer LS1 can overlap with the third transistor ST3 to block light incident on the third transistor ST3. The second light-blocking layer LS2 can overlap with the fourth transistor ST4 and block light incident on the fourth transistor ST4.

[0192] The second electrode CE2 of capacitor C1 can be connected to the drive voltage line VDDL through the ninth contact hole CNT9. Therefore, capacitor C1 can maintain the potential difference between the drive voltage line VDDL and the gate electrode G1 of the first transistor ST1.

[0193] The second interlayer insulating layer ILD2 can cover the second gate layer GTL2 and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 can insulate the second gate layer GTL2 from the second active layer ACTL2.

[0194] The second active layer ACTL2 may be disposed on the second interlayer insulating layer ILD2. In one embodiment, for example, the second active layer ACTL2 may comprise or be made of an oxide-based material. Each of the active region ACT3 of the third transistor ST3, the first electrode D3 and the second electrode S3, and the active region ACT4 of the fourth transistor ST4, the first electrode D4 and the second electrode S4 may be defined by a portion of the second active layer ACTL2.

[0195] The second gate insulating layer GI2 can cover the second interlayer insulating layer ILD2 and the second active layer ACTL2, and can insulate the second active layer ACTL2 from the third gate layer GTL3.

[0196] The third gate layer GTL3 may be disposed on the second gate insulating layer GI2. Each of the first gate line GL1 and the fourth gate line GL4 may be defined by a portion of the third gate layer GTL3.

[0197] A portion of the first gate line GL1 may overlap with the active region ACT4 of the fourth transistor ST4 to form the gate electrode G4 of the fourth transistor ST4.

[0198] A portion of the fourth gate line GL4 may overlap with the active region ACT3 of the third transistor ST3 to form the gate electrode G3 of the third transistor ST3.

[0199] The third interlayer insulating layer ILD3 can cover the third gate layer GTL3 and the second gate insulating layer GI2. The third interlayer insulating layer ILD3 can insulate the third gate layer GTL3 from the first source-drain layer SDL1.

[0200] The first source-drain layer SDL1 may be disposed on the third interlayer insulating layer ILD3. The drive voltage line VDDL and each of the first connecting electrode BE1, the second connecting electrode BE2, the third connecting electrode BE3, the fourth connecting electrode BE4, the fifth connecting electrode BE5, and the sixth connecting electrode BE6 may be defined by a portion of the first source-drain layer SDL1.

[0201] The first connection electrode BE1 can be connected to the first electrode S2 of the second transistor ST2 through the first contact hole CNT1, and can be connected to the data line DL through the second contact hole CNT2.

[0202] The second connection electrode BE2 can be connected to the second electrode D1 of the first transistor ST1 and the first electrode S6 of the sixth transistor ST6 through the third contact hole CNT3, and can be connected to the first electrode D3 of the third transistor ST3 through the fourth contact hole CNT4.

[0203] The third connection electrode BE3 can be connected to the second electrode S3 of the third transistor ST3 through the fifth contact hole CNT5, and can be connected to the gate electrode G1 of the first transistor ST1 through the sixth contact hole CNT6.

[0204] The fourth connection electrode BE4 can be connected to the first initialization voltage line VIL1 through the seventh contact hole CNT7, and can be connected to the first electrode D4 of the fourth transistor ST4 through the eighth contact hole CNT8.

[0205] The fifth connection electrode BE5 can be connected to the second initialization voltage line VIL2 through the thirteenth contact hole CNT13, and can be connected to the first electrode S7 of the seventh transistor ST7 through the fourteenth contact hole CNT14.

[0206] The sixth connecting electrode BE6 can be connected to the second electrode D6 of the sixth transistor ST6 and the second electrode D7 of the seventh transistor ST7 through the eleventh contact hole CNT11, and can be connected to the anode connecting electrode ANDE through the twelfth contact hole CNT12.

[0207] The fourth interlayer insulating layer ILD4 can cover the first source-drain layer SDL1 and the third interlayer insulating layer ILD3. The fourth interlayer insulating layer ILD4 can insulate the first source-drain layer SDL1 from the second source-drain layer SDL2.

[0208] The second source-drain layer SDL2 can be disposed on the fourth interlayer insulating layer ILD4. Each of the data line DL and the anode connection electrode ANDE can be defined by a portion of the second source-drain layer SDL2.

[0209] Figure 12 This is a plan view illustrating the metal layer of a display device according to an alternative embodiment. Figure 13 This is a plan view illustrating some layers of a first sub-pixel in a display device according to an alternative embodiment. Besides the configuration of the metal layer BML, Figure 12 and Figure 13 Display device and Figures 7 to 10 The display devices are basically the same. Figure 12and Figure 13 The same or similar elements shown have been used in conjunction with those described above. Figures 7 to 10 The embodiments of the display devices shown are labeled with the same reference numerals, and any repeated detailed descriptions thereof will be omitted or simplified below.

[0210] Reference Figure 2 , Figure 12 and Figure 13 In embodiments of the display device, the metal layer BML may be disposed on the substrate SUB (see...). Figure 11 The second display area SDA is defined by a pixel portion PXA and a transmissive portion TA. A metal layer BML can overlap with the pixel portion PXA of the second display area SDA, thereby preventing light passing through the pixel portion PXA from reaching the sensor devices 740, 750, 760, and 770. The metal layer BML is configured not to overlap with the transmissive portion TA of the second display area SDA, such that the transmissive portion TA allows light incident on the display panel 300 to pass through almost as is. Therefore, even if the sensor devices 740, 750, 760, and 770 are located below the display panel 300, they can still detect light incident from above the display panel 300.

[0211] In such an embodiment, at least one aperture BMH is defined by a metal layer BML. The at least one aperture BMH may be located in the thickness direction adjacent to a first active layer ACTL1 disposed in the pixel portion PXA (see [link to relevant documentation]). Figure 11 At least a portion of the metal layer BML overlaps with the first hole BMH1 and the second hole BMH2. The first hole BMH1 and the second hole BMH2 may be spaced apart from each other in a first direction (X-axis direction) and may extend in a second direction (Y-axis direction).

[0212] The first aperture BMH1 may partially overlap with the active region ACT2 of the second transistor ST2 and the active region ACT5 of the fifth transistor ST5. In one embodiment, for example, the first aperture BMH1 may be connected to the first node N1 of the second transistor ST2 (see...). Figure 5 The second electrode D2 and the fifth transistor ST5 are connected to the first node N1 (see...). Figure 5 Each overlap in the second electrode D5. In the reverse repair process, light of a specific wavelength (e.g., laser) can pass through the first aperture BMH1 to remove the first active layer ACTL1 (see Figure 11This is part of a process that allows the connection between the second transistor ST2 and the fifth transistor ST5 to be blocked. Additionally, in the reverse repair process, the connection between the first transistor ST1 and the second transistor ST2, as well as the connection between the first transistor ST1 and the fifth transistor ST5, can be blocked through the first hole BMH1.

[0213] The second hole BMH2 may partially overlap with the area between the active region ACT1 of the first transistor ST1 and the active region ACT7 of the seventh transistor ST7. In one embodiment, for example, the second hole BMH2 may overlap with the active region ACT6 of the sixth transistor ST6. The second hole BMH2 may also overlap with the area of ​​the sixth transistor ST6 connected to the second node N2 (see [link to documentation]). Figure 5 The first electrode S6 overlaps with the seventh transistor ST7 and can be connected to the fourth node N4 (see...). Figure 5 The second electrode D7 overlaps. In the inversion repair process, light of a specific wavelength (e.g., laser) can pass through the second aperture BMH2 to remove the first active layer ACTL1 (see...). Figure 11 This is part of a process that allows the connection between the sixth transistor ST6 and the seventh transistor ST7 to be blocked. Additionally, in the reverse repair process, the connection between the first transistor ST1 and the sixth transistor ST6, as well as the connection between the first transistor ST1 and the seventh transistor ST7, can be blocked via the second hole BMH2.

[0214] Therefore, since the light-blocking metal layer BML includes at least one aperture BMH, when a defective pixel appears, the active wiring or pixel circuit wiring of the defective pixel can be opened by a reversal repair process. In the reversal repair process, a laser of a specific wavelength is emitted through the first aperture BMH1 and the second aperture BMH2 to the active wiring or pixel circuit wiring of the defective pixel, thereby preventing the defective pixel from lighting up. The display device 10 can have improved reliability and improved image quality.

[0215] Figure 14 This is a plan view illustrating the metal layer of a display device according to another alternative embodiment. Figure 15 This is a plan view illustrating some layers of a first sub-pixel in a display device according to another alternative embodiment. Apart from the configuration of the metal layer BML, Figure 14 and Figure 15 Display device and Figure 12 and Figure 13 The display devices are basically the same. Figure 14 and Figure 15 The same or similar elements shown have been used in conjunction with those described above. Figure 12 and Figure 13The embodiments of the display devices shown are labeled with the same reference numerals, and any repeated detailed descriptions thereof will be omitted or simplified below.

[0216] Reference Figure 14 and Figure 15 The metal layer BML can be set in the substrate SUB (see Figure 11 The second display area SDA is defined by a metal layer BML, which overlaps the pixel portion PXA and the transmissive portion TA. This prevents light passing through the pixel portion PXA from reaching the sensor devices 740, 750, 760, and 770. The metal layer BML is configured not to overlap with the transmissive portion TA of the second display area SDA, allowing light incident on the display panel 300 to pass through almost exactly as it was. Therefore, even if the sensor devices 740, 750, 760, and 770 are located below the display panel 300, they can still detect light incident from above the display panel 300.

[0217] In this embodiment, a hole BMH is defined by a metal layer BML. The hole BMH can be connected in the thickness direction to a first active layer ACTL1 disposed in the pixel portion PXA (see [link to example]). Figure 11 At least a portion of them overlap.

[0218] The via BMH can partially overlap with the active region ACT2 of the second transistor ST2 and the active region ACT7 of the seventh transistor ST7. The via BMH can extend along the first active layer ACTL1 (see...). Figure 11 The bending occurs at least once. In one embodiment, for example, the portion of the metal layer BML overlapping the second electrode D2 of the second transistor ST2 may extend in the second direction (Y-axis direction) and may be bent in the opposite direction (X-axis direction) at the point where it overlaps with the second electrode D5 of the fifth transistor ST5. A portion of the bent metal layer BML may extend in the opposite direction (X-axis direction) and may be bent in the second direction (Y-axis direction) at the point where it overlaps with the first electrode S6 of the sixth transistor ST6. Another portion of the bent metal layer BML may extend until it overlaps with the second electrode D7 of the seventh transistor ST7.

[0219] In the inversion repair process, light of a specific wavelength (e.g., laser) can pass through the aperture BMH to remove the first active layer ACTL1 (see [link to original text]). Figure 11This is part of a process that allows the connection between the second transistor ST2 and the seventh transistor ST7 to be blocked. Additionally, in the reverse repair process, the connection between the first transistor ST1 and the second transistor ST2, the connection between the first transistor ST1 and the fifth transistor ST5, and the connection between the first transistor ST1 and the sixth transistor ST6 can be blocked via the via BMH.

[0220] Therefore, since the light-blocking metal layer BML includes a hole BMH, when a defective pixel appears, the active wiring or pixel circuit wiring of the defective pixel can be opened by a reversal repair process. In the reversal repair process, a laser of a specific wavelength is emitted towards the defective pixel through the hole BMH, thereby preventing the defective pixel from lighting up. The display device 10 can have improved reliability and improved image quality.

[0221] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0222] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display device, wherein, The display device includes: The display panel includes a first display area and a second display area. The first display area includes a first pixel, and the second display area includes a pixel portion and a transmissive portion. A second pixel is disposed in the pixel portion, and light is transmitted through the transmissive portion. The pixel portion of the second display area includes: Matrix components; A metal layer disposed on the substrate member to define the transmissive portion, the metal layer overlapping the pixel portion but not overlapping the transmissive portion; A first active layer, disposed on the metal layer, wherein the first active layer comprises a first material; and A first gate layer, wherein the first gate layer is disposed on the first active layer, and Wherein, a hole is defined through the metal layer such that the hole overlaps with a portion of the first active layer in the plan view of the display panel.

2. The display device according to claim 1, wherein, Each of the second pixels includes: Light-emitting elements; A first transistor, which controls the driving current supplied to the light-emitting element; and A second transistor selectively supplies data voltage to a first node, the first node being connected to the first electrode of the first transistor. The aperture includes a first aperture that partially overlaps with the active region of the first transistor and the active region of the second transistor.

3. The display device according to claim 2, wherein, The first hole overlaps with the second electrode of the second transistor connected to the first node.

4. The display device according to claim 2, wherein, Each of the second pixels also includes: A third transistor selectively connects a second node to a third node, the second node being connected to a second electrode of the first transistor, and the third node being connected to the gate electrode of the first transistor; A fourth transistor, which selectively supplies a first initialization voltage to the third node; and A fifth transistor, configured to selectively supply a drive voltage to the first node, The hole includes a second hole that partially overlaps with the active region of the first transistor and the active region of the fifth transistor.

5. The display device according to claim 4, wherein, The second hole overlaps with the second electrode of the fifth transistor connected to the first node.

6. The display device according to claim 4, wherein, Each of the second pixels also includes: A sixth transistor selectively connects the second node to a fourth node, the fourth node being connected to the first electrode of the light-emitting element. The hole further includes a third hole, which partially overlaps with the active region of the first transistor and the active region of the sixth transistor.

7. The display device according to claim 6, wherein, The third hole overlaps with the first electrode of the sixth transistor connected to the second node.

8. The display device according to claim 6, wherein, Each of the second pixels also includes: The seventh transistor selectively supplies the second initialization voltage to the fourth node. The hole further includes a fourth hole, which partially overlaps with the active regions of the sixth transistor and the seventh transistor.

9. The display device according to claim 8, wherein, The fourth hole overlaps with the second electrode of the seventh transistor connected to the fourth node.

10. The display device according to claim 8, wherein, The active region of each of the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor is defined by a portion of the first active layer.

11. The display device according to claim 4, wherein, The pixel portion of the second display area further includes: A second gate layer is disposed on the first gate layer; A second active layer is disposed on the second gate layer, wherein the second active layer comprises a second material different from the first material; and A third gate layer is disposed on the second active layer. The active region of each of the third transistor and the fourth transistor is defined by a portion of the second active layer.

12. The display device according to claim 1, wherein, Each of the second pixels includes: Light-emitting elements; A first transistor controls the driving current supplied to the light-emitting element; The second transistor selectively supplies data voltage to the first node, which is connected to the first electrode of the first transistor. A third transistor selectively connects a second node to a third node, the second node being connected to a second electrode of the first transistor, and the third node being connected to the gate electrode of the first transistor; A fourth transistor, which selectively supplies a first initialization voltage to the third node; and The fifth transistor selectively supplies the drive voltage to the first node. The aperture includes a first aperture that partially overlaps with the active region of the second transistor and the active region of the fifth transistor.

13. The display device according to claim 12, wherein, The first hole overlaps with each of the second electrode of the second transistor connected to the first node and the second electrode of the fifth transistor connected to the first node.

14. The display device according to claim 12, wherein, Each of the second pixels also includes: A sixth transistor selectively connects the second node to a fourth node, the fourth node being connected to the first electrode of the light-emitting element; and The seventh transistor selectively supplies the second initialization voltage to the fourth node. The hole further includes a second hole, which partially overlaps with the active regions of the first transistor and the seventh transistor.

15. The display device according to claim 14, wherein, The second hole overlaps with the active region of the sixth transistor.

16. The display device according to claim 14, wherein, The second hole overlaps with the first electrode of the sixth transistor connected to the second node, and with the second electrode of the seventh transistor connected to the fourth node.

17. The display device according to claim 14, wherein, The first hole and the second hole are spaced apart from each other in a first direction and extend in a second direction that intersects the first direction.

18. The display device according to claim 1, wherein, Each of the second pixels includes: Light-emitting elements; A first transistor controls the driving current supplied to the light-emitting element; The second transistor selectively supplies data voltage to the first node, which is connected to the first electrode of the first transistor. A third transistor selectively connects a second node to a third node, the second node being connected to a second electrode of the first transistor, and the third node being connected to the gate electrode of the first transistor; A fourth transistor selectively supplies the first initialization voltage to the third node; A fifth transistor selectively supplies a drive voltage to the first node; A sixth transistor selectively connects the second node to a fourth node, the fourth node being connected to the first electrode of the light-emitting element; and The seventh transistor selectively supplies the second initialization voltage to the fourth node. The hole partially overlaps with the active regions of the second transistor and the seventh transistor.

19. The display device according to claim 18, wherein, The hole bends at least once along the first active layer.

20. The display device according to claim 18, wherein, The hole overlaps with each of the second electrode of the second transistor connected to the first node, the second electrode of the fifth transistor connected to the first node, the first electrode of the sixth transistor connected to the second node, and the second electrode of the seventh transistor connected to the fourth node.

21. The display device according to claim 1, wherein, The pixel portion includes a transistor, the transistor including a first electrode formed by the first active layer, a second electrode, and an active region located between the first electrode and the second electrode, wherein the aperture overlaps with the first electrode or the second electrode of the transistor, but does not overlap with the active region of the transistor, and / or Wherein, the first material includes a silicon-based material, and / or The metal layer overlaps with other portions of the first active layer in the plan view of the display panel.

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