Display substrate and manufacturing method thereof, and display device

Abstract

The present application provides a display substrate and a manufacturing method thereof, and a display device. The display substrate includes a substrate, a buffer layer arranged on one side of the substrate, and a switching device layer arranged on a side of the buffer layer away from the substrate. The switching device layer includes a thin film transistor, an interlayer dielectric layer, and a signal line. The thin film transistor includes a gate layer and a source-drain electrode layer. The gate layer is close to the buffer layer, the source-drain electrode layer is located on a side of the gate layer away from the buffer layer, the interlayer dielectric layer is located between the gate layer and the source-drain electrode layer, and the signal line is located in a non-display area. By providing grooves on the interlayer dielectric layer and / or the buffer layer at positions corresponding to the positions of the signal lines, and making at least part of the signal lines located in the grooves, the thickness of the color film layer at the position corresponding to the signal line position can be increased in the subsequent process of manufacturing the color film layer, thereby improving the light shielding ability of the color film layer and reducing the risk of reduced stability of the thin film transistor after being exposed to external light.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular, to a display substrate and a method for manufacturing the same, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) displays are different from traditional liquid crystal displays in that they do not require backlights and have the advantages of high contrast, thin thickness, wide viewing angle, fast response speed, can be used for flexible panels, and have a wide operating temperature range. Their applications are becoming increasingly widespread.

[0003] Thin Film Transistor (TFT) is an important semiconductor device in OLED display devices. In large-size OLED display devices, top-gate TFT has attracted attention because of its higher aperture ratio and more stable characteristics than bottom-gate TFT. Since the active layer of TFT (especially the active layer formed by oxide semiconductor) will reduce the stability of TFT when exposed to light, in existing OLED display devices, a metal light-shielding layer is usually arranged under the active layer of top-gate TFT to shield the active layer from light, and at the same time, a color filter layer is arranged in the pixel light-emitting gap area to shield the active layer from light.

[0004] However, in the existing OLED display device, the color filter layer has a limited light shielding effect on the active layer, which leads to reduced stability of the TFT in the OLED display device. Summary of the invention

[0005] In view of the shortcomings of the existing methods, the present application proposes a display substrate and a manufacturing method thereof, and a display device, so as to solve the problem that the thin film transistors in the existing OLED display devices are easily affected by light and have low stability.

[0006] In a first aspect, an embodiment of the present application provides a display substrate, comprising:

[0007] substrate;

[0008] A buffer layer is disposed on one side of the substrate;

[0009] a switching device layer, arranged on a side of the buffer layer away from the substrate, comprising a thin film transistor, an interlayer dielectric layer and a signal line, wherein the thin film transistor comprises a gate layer and a source-drain layer, the gate layer is close to the buffer layer, the source-drain layer is located on a side of the gate layer away from the buffer layer, the interlayer dielectric layer is located between the gate layer and the source-drain layer, and the signal line is located in a non-display area;

[0010] Wherein, at a position corresponding to the position of the signal line, a groove is opened on the interlayer dielectric layer and / or the buffer layer, and at least a part of the signal line is located in the groove.

[0011] Optionally, the signal line includes a data signal line, and the data signal line is arranged in the same layer as the source and drain electrode layer and is electrically connected;

[0012] The interlayer dielectric layer is provided with a first groove at a position corresponding to the position of the data signal line, and the data signal line is located in the first groove.

[0013] Optionally, the first groove penetrates the interlayer dielectric layer and extends to the surface of the buffer layer.

[0014] Optionally, the buffer layer is provided with a second groove at a position corresponding to the position of the first groove, the first groove is connected to the second groove, and an orthographic projection area of ​​the second groove on the substrate is greater than or equal to an orthographic projection area of ​​the first groove on the substrate.

[0015] Optionally, the signal line further includes a power line and a scan line, the power line and the scan line are stacked, the scan line is arranged in the same layer as the gate layer and is electrically connected, and the power line is arranged in the same layer as the source and drain layer;

[0016] The buffer layer is provided with a third groove at a position corresponding to the positions of the power line and the scan line, and at least a part of the scan line is located in the third groove.

[0017] Optionally, the third groove passes through the buffer layer and extends to the surface of the substrate.

[0018] Optionally, the display substrate further comprises a color filter layer arranged on a side of the source and drain electrode layer away from the substrate;

[0019] The color filter layer comprises a first color filter layer and a second color filter layer, the first color filter layer and the second color filter layer are adjacent to each other, and the orthographic projections of the first color filter layer and the second color filter layer on the substrate overlap with the orthographic projections of the data signal line on the substrate;

[0020] In the direction from the substrate to the buffer layer, the first color filter layer and the second color filter layer have a first thickness near the junction therebetween, and the first color filter layer and the second color filter layer have a second thickness away from the junction therebetween, the first thickness is greater than the second thickness, and the difference between the first thickness and the second thickness is greater than or equal to 1 micron.

[0021] In a second aspect, an embodiment of the present application provides a display device, including the display substrate in the embodiment of the present application.

[0022] In a third aspect, an embodiment of the present application provides a method for manufacturing a display substrate, comprising:

[0023] providing a substrate;

[0024] Making a buffer layer on one side of the substrate;

[0025] A switching device layer is fabricated on a side of the buffer layer away from the substrate, the switching device layer comprising a thin film transistor, an interlayer dielectric layer and a signal line, the thin film transistor comprising a gate layer and a source-drain layer, the interlayer dielectric layer being located between the gate layer and the source-drain layer; wherein a groove is fabricated on the interlayer dielectric layer and / or the buffer layer at a position corresponding to the position of the signal line, and at least a portion of the signal line is located in the groove.

[0026] Optionally, the signal line includes a data signal line, a power line and a scan line;

[0027] A buffer layer is formed on one side of the substrate, and a switch device layer is formed on a side of the buffer layer away from the substrate, comprising:

[0028] A buffer layer is fabricated on one side of the substrate, and a second groove penetrating the buffer layer is formed at a position corresponding to the position of the data signal line, and a third groove penetrating the buffer layer is formed at a position corresponding to the position of the power line and the scanning line by a patterning process;

[0029] A gate layer, a scan line and an interlayer dielectric layer are sequentially formed on a side of the buffer layer away from the substrate, and a first groove penetrating the interlayer dielectric layer is formed at a position corresponding to the position of the data signal line by a patterning process, and at least part of the scan line is located in the third groove;

[0030] A source-drain layer, a data signal line and a power line are fabricated on a side of the interlayer dielectric layer away from the substrate. The data signal line is located in the first groove. The orthographic projection of the power line on the substrate overlaps with the orthographic projection of the scan line on the substrate.

[0031] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0032] The display substrate in the embodiment of the present application includes a substrate, a buffer layer arranged on one side of the substrate, and a switching device layer arranged on a side of the buffer layer away from the substrate, the switching device layer includes a thin film transistor, an interlayer dielectric layer and a signal line, the thin film transistor includes a gate layer and a source-drain layer, the gate layer is close to the buffer layer, the source-drain layer is located on the side of the gate layer away from the buffer layer, the interlayer dielectric layer is located between the gate layer and the source-drain layer, and the signal line is located in a non-display area; by opening grooves on the interlayer dielectric layer and / or the buffer layer at positions corresponding to the positions of the signal lines, and making at least part of the signal lines located in the grooves, the thickness of the color film layer corresponding to the position of the signal lines can be increased in the subsequent process of manufacturing the color film layer, thereby improving the light-shielding ability of the color film layer and reducing the risk of reduced stability of the thin film transistor after being exposed to external light.

[0033] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0035] Figure 1 It is a schematic diagram of the structure of a display substrate in the prior art;

[0036] Figure 2 This is a schematic diagram showing the structure of a substrate in one embodiment of the present application;

[0037] Figure 3 A schematic diagram showing the structure of a substrate in another embodiment of the present application;

[0038] Figure 4 This is a schematic structural diagram showing a substrate in yet another embodiment of the present application;

[0039] Figure 5 A schematic diagram showing the structure of a substrate in yet another embodiment of the present application;

[0040] Figure 6 A schematic diagram showing a process of manufacturing a substrate in an embodiment of the present application;

[0041] Figures 7a to 7j This is a schematic diagram of the structures of different processes for manufacturing a display substrate provided in this application.

[0042] In the figure:

[0043] 10-display substrate; 11-substrate; 12-buffer layer; 13-switching device layer; 110-non-display area; 111-display area;

[0044] 131 - thin film transistor; 132 - interlayer dielectric layer; 133 - signal line; 100 - groove;

[0045] 1311-active layer; 1312-gate layer; 1313-source and drain layer; 101-first groove; 102-second groove; 103-third groove; 1331-data signal line; 1332-scanning line; 1333-power line; 1314-gate insulating layer;

[0046] 14-passivation layer; 15-color filter layer; 16-planarization layer; 17-anode layer; 18-pixel definition layer; 19-light shielding layer; 151-first color filter layer; 152-second color filter layer; 153-third color filter layer;

[0047] W1-first thickness; W2-second thickness; 200-via. DETAILED DESCRIPTION

[0048] The present application is described in detail below, and examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components with the same or similar functions. In addition, if the detailed description of the known technology is unnecessary for the features of the present application shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present application.

[0049] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0050] The inventors of the present application have considered that, in the existing display substrate, the signal line in the switching device layer is relatively thick, resulting in a smaller thickness of the color filter layer at the intersection with the signal line, which will lead to a decrease in the shielding ability of the color filter layer against external light. The thin-film transistor in the switching device layer is prone to threshold voltage drift due to the influence of light, resulting in a decrease in stability.

[0051] like Figure 1As shown, in the existing display substrate 10, in order to improve the aperture ratio, a top-gate thin film transistor 131 (that is, the gate layer is located above the active layer) is usually used in the switching device layer 13. The material of the active layer can be metal oxide or amorphous silicon, which can be determined according to actual conditions. In order to prevent the threshold voltage of the thin film transistor 131 from shifting after the active layer is exposed to light, which reduces the stability of the thin film transistor 131, a light shielding layer 19 is provided under the active layer to block external light incident from the back of the display substrate 10. A passivation layer 14, a color filter layer 15, a planarization layer 16, an anode layer 17 and a pixel defining layer 18 are sequentially provided on the side of the switching device layer 13 away from the substrate 11. The anode layer 17 is electrically connected to the source and drain layers, and is located in the display area 111 (that is, Figure 1 The anode layer 17 (between two adjacent pixel defining layers 18 ) cooperates with the OLED and the color conversion layer (not shown in the figure) disposed thereon to realize the display function of the display substrate 10 .

[0052] The display substrate 10 is densely distributed with signal lines 133 that can reflect light. Therefore, when external light enters the display substrate 10 (it can be incident from the bottom of the display substrate 10 or from the gap between the pixel definition layers 18 at the top of the display substrate 10), due to the large number of metal wires disposed in the display substrate 10, reflected light will be formed in the display substrate 10. Since there is a buffer layer 12 between the light shielding layer 19 and the active layer, and the buffer layer 12 can allow light to pass through, and the metal wires in the large-sized display substrate 10 are denser, the reflected light will be irradiated onto the active layer from the gap between the light shielding layer 19 and the active layer, so that the stability of the thin film transistor 131 is affected.

[0053] In the existing display substrate 10, as Figure 1 As shown, the color filter layer 15 disposed above the switch device layer 13 can absorb part of the external light incident on the inside of the display substrate 10 (incident from the gaps between the pixel defining layers 18), thereby playing a certain light shielding role. However, in a large-sized display substrate 10, the thickness of the signal line 133 is usually thicker, and the signal line 133 occupies a larger space in the film layer of the display substrate 10, so that the thickness of the color filter layer 15 above the signal line 133 is smaller at the corresponding signal line 133 routing, resulting in a reduction in the light shielding performance of the color filter layer 15, and the thin film transistor 131 in the display substrate 10 is also easily affected by light and has a reduced stability.

[0054] The display substrate 10 and its manufacturing method, and the display device provided in the present application are intended to solve the above technical problems in the prior art.

[0055] The display substrate and its manufacturing method, and the display device provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0056] The present application embodiment provides a display substrate 10, combined with Figures 2 to 5 As shown, including:

[0057] Substrate 11;

[0058] A buffer layer 12 is disposed on one side of the substrate 11;

[0059] The switching device layer 13 is arranged on the side of the buffer layer 12 away from the substrate 11, and includes a thin film transistor 131, an interlayer dielectric layer 132 and a signal line 133. The thin film transistor 131 includes a gate layer and a source-drain layer. The gate layer is close to the buffer layer 12, the source-drain layer is located on the side of the gate layer away from the buffer layer 12, the interlayer dielectric layer 132 is located between the gate layer and the source-drain layer, and the signal line 133 is located in the non-display area 110;

[0060] A groove is formed on the interlayer dielectric layer 132 and / or the buffer layer 12 at a position corresponding to the position of the signal line 133 , and at least a portion of the signal line 133 is located in the groove.

[0061] Specifically, a buffer layer 12 is provided on the substrate 11, and the material of the buffer layer 12 includes inorganic materials such as silicon oxide. A switching device layer 13 is provided on the buffer layer 12, and the switching device layer 13 includes a thin film transistor 131 and a signal line 133. The thin film transistor 131 includes an active layer, a gate layer, and a source-drain electrode layer stacked in sequence, and the thin film transistor 131 layer also includes a gate insulating layer 1314 provided between the active layer and the gate layer, and an interlayer dielectric layer 132 provided between the gate layer and the source-drain electrode layer. The material of the interlayer dielectric layer 132 includes a material with good insulation performance such as silicon oxide or silicon nitride, and its structure can be a single layer or a multi-layer composite structure, which can be determined according to actual conditions.

[0062] A passivation layer 14, a color filter layer 15, a planarization layer 16, an anode layer 17, and a pixel definition layer 18 are sequentially stacked above the switch device layer. The anode layer 17 is electrically connected to the source and drain layers in the thin film transistor 131. The switch device layer also includes a signal line 133, which is electrically connected to the thin film transistor 131 to control and drive the thin film transistor 131. The signal line 133 is located in the non-display area 110 (i.e., the non-display area 110 of the display substrate 10). Figure 2In the area corresponding to the position of the pixel defining layer 18, that is, the area between two adjacent pixels of the display substrate 10), the orthographic projection of the signal line 133 on the substrate 11 does not overlap with the orthographic projection of the thin film transistor 131 on the substrate 11. The signal line 133 is arranged on the interlayer dielectric layer 132 and the buffer layer 12, and the color filter layer 15 corresponds to the position of the signal line 133, that is, the orthographic projection of the color filter layer 15 on the substrate 11 overlaps with the orthographic projection of the signal line 133 on the substrate 11. The orthographic projection of the display area 111 on the substrate 11 falls within the orthographic projection of the color filter layer 15 on the substrate 11, so the light incident from the display area 111 to the inside of the display substrate 10 can be absorbed by the color filter layer 15, and the color filter layer 15 can play a role in shielding.

[0063] By providing grooves on the interlayer dielectric layer 132 and / or the buffer layer 12 at positions corresponding to the positions of the signal lines 133, the signal lines 133 can be partially or completely located in the grooves during routing, so as to reduce the step difference caused by the thickness of the signal lines 133. Therefore, at positions corresponding to the positions of the signal lines 133, the thickness of the color filter layer 15 above the signal lines 133 can be increased accordingly, thereby improving the light shielding effect of the color filter layer 15 and reducing the risk of reduced stability of the thin film transistor 131 due to the influence of light.

[0064] Combination Figures 2 to 5 As shown, in the embodiment of the present application, the signal line 133 includes a data signal line 1331, a scan line 1332 and a power line 1333. The data signal line 1331 is electrically connected to the source and drain layer of the thin film transistor 131, and the scan line 1332 and the power line 1333 are electrically connected to the gate layer of the thin film transistor 131 to control the opening and closing of the thin film transistor 131.

[0065] It should be noted that the position of the groove opened on the interlayer dielectric layer 132 and / or the buffer layer 12 can correspond to the position of the data signal line 1331 in the signal line 133, or can correspond to the position of the scan line 1332 and the power line 1333 in the signal line 133, which can be determined according to actual conditions.

[0066] In a specific embodiment, Figure 3As shown, the signal line 133 includes a data signal line 1331, and the data signal line 1331 is arranged in the same layer as the source and drain electrode layer and is electrically connected. The data signal line 1331 is arranged in the same layer as the source and drain electrode layer, which means that the data signal line 1331 and the source and drain electrode layer are formed by the same patterning process, which is conducive to reducing production costs. At a position corresponding to the position of the data signal line 1331, a first groove 101 is opened on the interlayer dielectric layer 132, and the data signal line 1331 is located in the first groove 101. By opening the first groove 101 at a position corresponding to the position of the data signal line 1331 on the interlayer dielectric layer 132, the data signal line 1331 can be partially or completely located in the first groove 101, thereby reducing the space occupied by the data signal line 1331 in the film layer of the display substrate 10 along the first direction, and the thickness of the color filter layer 15 at the position corresponding to the position of the data signal line 1331 can be increased, thereby improving the light shielding performance of the color filter layer 15.

[0067] It should be noted that in the direction from the substrate 11 to the switching device layer ( Figure 3 The depth of the first groove can be determined according to actual conditions. Figure 3 As shown, in the embodiment of the present application, the first groove 101 penetrates the interlayer dielectric layer 132 and extends to the surface of the buffer layer 12. Thus, the depth of the first groove 101 can be maximized, which is conducive to increasing the portion of the data signal line 1331 located in the first groove 101, so as to further reduce the step difference above the data signal line 1331, and increase the thickness of the color filter layer 15 at the position corresponding to the position of the data signal line 1331.

[0068] like Figure 4 As shown, in a specific embodiment, the buffer layer 12 is provided with a second groove 102 at a position corresponding to the position of the first groove 101, the first groove 101 is connected to the second groove 102, and the orthographic projection area of ​​the second groove 102 on the substrate 11 is greater than or equal to the orthographic projection area of ​​the first groove 101 on the substrate 11. By providing the second groove 102 on the buffer layer 12 and making the second groove 102 connected to the first groove 101, the portion of the data signal line 1331 located in the groove 100 can be further increased, so as to reduce the space occupied by the data signal line 1331 in the film layer of the display substrate 10 along the first direction, and further increase the thickness of the color filter layer 15 at the position corresponding to the data signal line 1331.

[0069] In order to further reduce the step difference above the signal line 133, the thickness of the color filter layer 15 at the position corresponding to the position of the signal line 133 is increased, such as Figure 5As shown, in a specific embodiment, the signal line 133 further includes a scan line 1332 and a power line 1333, the scan line 1332 and the power line 1333 are stacked, the scan line 1332 is arranged in the same layer as the gate layer 1312 and is electrically connected, and the power line 1333 is arranged in the same layer as the source and drain layer 1313. The scan line 1332 and the gate layer 1312 are arranged in the same layer, which means that the scan line 1332 and the gate layer 1312 are formed by the same patterning process, so the manufacturing cost of the display substrate 10 can be reduced. At a position corresponding to the position of the scan line 1332 and the power line 1333, the buffer layer 12 is provided with a third groove 103, and at least part of the scan line 1332 is located in the third groove 103. By opening the third groove 103 on the buffer layer 12, part or all of the scan line 1332 can be located in the third groove 103, thereby reducing the space occupied by the power line 1333 and the scan line 1332 in the film layer of the display substrate 10 along the first direction, and the thickness of the color filter layer 15 at the position corresponding to the position of the power line 1333 and the scan line 1332 can be increased, thereby further improving the light shielding performance of the color filter layer 15.

[0070] It should be noted that in the direction from the substrate 11 to the switching device layer ( Figure 5 The depth of the third groove 103 can be determined according to actual conditions. Optionally, in the embodiment of the present application, the third groove 103 penetrates the buffer layer 12 and extends to the surface of the substrate 11. In this way, the depth of the third groove 103 can be maximized, which is conducive to increasing the portion of the scan line 1332 located in the third groove 103, so as to further reduce the step difference above the scan line 1332 and increase the thickness of the color filter layer 15 at the position corresponding to the position of the scan line 1332.

[0071] At the position corresponding to the signal line 133, the thickness of the color filter layer 15 and the specific position of the color filter layer 15 where the thickness is increased can be determined according to actual conditions. Figure 5 As shown, in a specific embodiment, the display substrate 10 further includes a color filter layer 15 disposed on a side of the source and drain electrode layer away from the substrate 11; the color filter layer 15 includes a first color filter layer 151 and a second color filter layer 152, the first color filter layer 151 and the second color filter layer 152 are adjacent to each other, and the orthographic projections of the first color filter layer 151 and the second color filter layer 152 on the substrate 11 overlap with the orthographic projections of the data signal line 1331 on the substrate 11; in the direction from the substrate 11 to the buffer layer 12 ( Figure 5 In the first direction, the first color filter layer 151 and the second color filter layer 152 have a first thickness W1 near the adjacent portion thereof, and the first color filter layer 151 and the second color filter layer 152 have a second thickness W2 away from the adjacent portion thereof, the first thickness W1 is greater than the second thickness W2, and the difference between the first thickness W1 and the second thickness W2 is greater than or equal to 1 micron.

[0072] Specifically, in the embodiment of the present application, the first color filter layer 151 is a blue color filter layer, the second color filter layer 152 is a red color filter layer, and the first color filter layer 151 and the second color filter layer 152 correspond to the positions of the data signal line 1331. The color filter layer 15 also includes a third color filter layer 153, the third color filter layer 153 is a green color filter layer, and the third color filter layer 153 corresponds to the positions of the power line 1333 and the scan line 1332. It should be noted that the colors of the first color filter layer 151, the second color filter layer 152, and the third color filter layer 153 can be determined according to actual conditions and are not limited here.

[0073] Near the junction of the first color filter layer 151 and the second color filter layer 152 (the central area of ​​the first color filter layer 151 and the second color filter layer 152 in the figure), the thickness of the first color filter layer 151 and the second color filter layer 152 is relatively large, and compared with the position away from the junction of the first color filter layer 151 and the second color filter layer 152 (the two end areas of the first color filter layer 151 and the second color filter layer 152 in the figure), the thickness is increased by more than 1 micron. It can be understood that the greater the thickness of the color filter layer 15, the better the improvement in light shielding performance. However, the increased thickness of the color filter layer 15 is limited by the step difference between different film layers and the overall thickness of the display substrate 10, and can be determined according to actual conditions. Figure 5 As shown, in the embodiment of the present application, the thickness of the first color filter layer 151 and the second color filter layer 152 near the junction thereof is larger because the junction of the first color filter layer 151 and the second color filter layer 152 corresponds to the position of the data signal line 1331, that is, the orthographic projection of the junction of the two color filter layers 15 on the substrate 11 falls within the orthographic projection of the data signal line on the substrate 11. Since the data signal line 1331 is located in the first groove 101 and the second groove 102, it is equivalent to sinking the data signal line 1331, so the thickness of the first color filter layer 151 and the second color filter layer 152 at the position corresponding to the position of the data signal line 1331 can be increased.

[0074] Based on the same inventive concept, the embodiment of the present application also provides a display device, which includes the display substrate 10 provided in the embodiment of the present application. Since the display device includes the display substrate 10 provided in the embodiment of the present application, the display device has the same beneficial effects as the display substrate 10, which will not be described in detail here.

[0075] Based on the same inventive concept, the present application also provides a method for manufacturing a display substrate 10, such as Figure 6 As shown, the production method includes:

[0076] S101, providing a substrate;

[0077] S102, forming a buffer layer on one side of the substrate;

[0078] S103. A switching device layer is manufactured on a side of the buffer layer away from the substrate, wherein the switching device layer includes a thin film transistor, an interlayer dielectric layer and a signal line, wherein the thin film transistor includes a gate layer and a source-drain layer, and the interlayer dielectric layer is located between the gate layer and the source-drain layer; wherein grooves are manufactured on the interlayer dielectric layer and / or the buffer layer at positions corresponding to positions of the signal lines, and at least part of the signal line is located in the grooves.

[0079] In the manufacturing method of the display substrate 10 provided in the embodiment of the present application, by providing a groove on the interlayer dielectric layer 132 and / or the buffer layer 12 at a position corresponding to the position of the signal line 133, the signal line 133 can be partially or completely located in the groove when routing, so as to reduce the step difference caused by the thickness of the signal line 133. Therefore, at the position corresponding to the position of the signal line 133, the thickness of the color filter layer 15 above the signal line 133 can be increased accordingly, thereby improving the light shielding effect of the color filter layer 15 and reducing the risk of reduced stability caused by the thin film transistor 131 being affected by light.

[0080] Specifically, in the embodiment of the present application, the signal line 133 includes a data signal line 1331, a scan line 1332 and a power line 1333, a buffer layer 12 is manufactured on one side of the substrate 11, and a switching device layer 13 is manufactured on a side of the buffer layer 12 away from the substrate 11, including:

[0081] A buffer layer is formed on one side of the substrate, and a second groove penetrating the buffer layer is formed at a position corresponding to the position of the data signal line, and a third groove penetrating the buffer layer is formed at a position corresponding to the position of the power line and the scanning line by a patterning process;

[0082] A gate layer, a scanning line and an interlayer dielectric layer are sequentially formed on a side of the buffer layer away from the substrate, and a first groove penetrating the interlayer dielectric layer is formed at a position corresponding to the position of the data signal line by a patterning process, and at least part of the scanning line is located in the third groove;

[0083] A source-drain layer, a data signal line and a power line are fabricated on the side of the interlayer dielectric layer away from the substrate. The data signal line is located in the first groove. The orthographic projection of the power line on the substrate overlaps with the orthographic projection of the scan line on the substrate 11 .

[0084] Specifically, the patterning process in the embodiments of the present application includes the coating, exposure, development, etching of photoresist and partial or all processes of removing the photoresist.

[0085] The specific process of manufacturing the display substrate 10 in the embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0086] like Figure 7aAs shown, a substrate 11 is first provided, and a light shielding layer 19 is made on one side of the substrate 11. Specifically, the material of the substrate 11 includes Corning glass and quartz glass, and the thickness thereof is between 50 microns and 1000 microns; when making the light shielding layer 19, metal can be first deposited on the substrate 11 by magnetron sputtering, and then a patterning process is performed to form a pattern of the light shielding layer 19, and the material of the light shielding layer 19 includes metal or other materials with good light shielding performance.

[0087] like Figure 7b As shown, then, a buffer layer 12 is deposited on one side of the substrate 11 so that the buffer layer 12 covers the light shielding layer 19. Specifically, the deposition can be carried out by plasma enhanced chemical vapor deposition (PECVD). The material of the buffer layer 12 can be one or more of silicon nitride (SiNx), silicon oxide (SiOx) or silicon oxynitride (SiOxNy). The thickness of the buffer layer 12 is 150 nanometers to 500 nanometers. Then, a second groove 102, a third groove 103 and a via 200 are formed on the buffer layer 12 by a patterning process. The position of the second groove 102 corresponds to the position where the data signal line 1331 needs to be made later, the position of the third groove 103 corresponds to the position where the scan line 1332 and the power line 1333 need to be made later, and the via 200 corresponds to the position where the source and drain layer 1313 needs to be made later.

[0088] like Figure 7c As shown, next, an active layer 1311 of a thin film transistor is manufactured on a side of the buffer layer 12 away from the substrate 11 by a patterning process. The material of the active layer 1311 includes a metal oxide semiconductor such as indium gallium zinc oxide (IGZO).

[0089] like Figure 7d As shown, then, a gate insulating layer 1314, a gate layer 1312 and a scanning line 1332 are formed on the side of the active layer 1311 away from the substrate 11 by a patterning process. The scanning line 1332 is located in the third groove 103 and is arranged in the same layer as the gate layer 1312 (the scanning line 1332 and the gate layer 1312 are formed by a single patterning process). The materials of the gate layer 1312 and the scanning line 1332 include metal materials such as copper or aluminum. Specifically, the gate insulating layer is first deposited by chemical vapor deposition, and then a gate metal layer is deposited on the gate insulating layer by magnetron sputtering. The thickness of the metal layer is 200 nanometers to 1000 nanometers. Then, a gate pattern is formed by a patterning process, and the photoresist is retained without being stripped. The photoresist on the gate layer is used as a mask, and dry etching is performed to form a pattern of the gate insulating layer.

[0090] like Figure 7eAs shown, then, an interlayer dielectric layer 132 is deposited on the side of the buffer layer 12 away from the substrate 11, and the interlayer dielectric layer 132 covers the active layer 1311, the gate insulating layer 1314 and the gate layer 1312. Then, a first groove 101 and a via 200 are formed on the interlayer dielectric layer 132 by a patterning process, the first groove 101 corresponds to the position of the second groove 102, and the second groove 102 is connected to the first groove 101, and the via 200 is used to realize the electrical connection between the source and drain layer and the active layer, and to realize the electrical connection between the scan line and the power line. Optionally, before depositing the interlayer dielectric layer 132, any one of ammonia (NH3), N2 (nitrogen) and hydrogen (H2) is used to first conduct the active layer exposed to the outside to reduce the ohmic contact resistance between the active layer and the source and drain layer.

[0091] like Figure 7f As shown, then, on the side of the interlayer dielectric layer 132 away from the substrate 11, a source-drain layer 1313, a data signal line 1331 and a power line 1333 are manufactured by a patterning process, the data signal line 1331 is located in the first groove 101 and the second groove 102, the power line 1333 corresponds to the position of the scan line 1332 and is electrically connected to the scan line 1332 through the via 200; the source-drain layer 1313, the data signal line 1331 and the power line 1333 are arranged in the same layer (formed by a single patterning process), and the thickness of the source-drain layer 1313 is 200 nanometers to 1000 nanometers.

[0092] like Figure 7g As shown, next, a passivation layer 14 is deposited on the side of the source and drain electrode layer 1313 away from the substrate 11 . The material of the passivation layer 14 includes a material with good insulation properties such as silicon oxide.

[0093] like Figure 7h As shown, next, a color filter layer 15 is formed on the side of the passivation layer 14 away from the substrate 11 by a patterning process, and then a planarization layer 16 is deposited on the side of the color filter layer 15 away from the substrate 11. The materials of the color filter layer 15 and the planarization layer 16 include organic materials, and the thickness is between 2 microns and 3.5 microns. The orthographic projection of the color filter layer 15 on the substrate 11 overlaps with the orthographic projection of the signal line 133 on the substrate 11. The manufacturing process of the color filter layer 15 and the planarization layer 16 includes a first drying, exposure, development and a second drying. During the second drying, the water and organic solvent are removed by 230°.

[0094] like Figure 7i As shown, next, an anode layer 17 is formed on a side of the planarization layer 16 away from the substrate 11 by a patterning process. The material of the anode layer 17 includes transparent indium tin oxide, and the thickness is 40 nanometers to 150 nanometers.

[0095] like Figure 7jAs shown, finally, a pixel defining layer 18 is formed on the side of the anode layer 17 away from the substrate 11 by a patterning process to complete the manufacture of the display substrate 10. The material of the pixel defining layer 18 includes an organic material. The spacing area (i.e., the display area 111) between two adjacent pixel defining layers 18 is staggered with the position of the signal line 133. The manufacturing process of the pixel defining layer 18 includes a first drying, exposure, development and a second drying. During the second drying, the moisture and organic solvent are removed by 230°.

[0096] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0097] 1. The display substrate 10 in the embodiment of the present application includes a substrate 11, a buffer layer 12 arranged on one side of the substrate 11, and a switching device layer 13 arranged on a side of the buffer layer 12 away from the substrate 11, the switching device layer 13 includes a thin film transistor 131, an interlayer dielectric layer 132 and a signal line 133, the thin film transistor 131 includes a gate layer and a source-drain layer, the gate layer is close to the buffer layer 12, the source-drain layer is located on the side of the gate layer away from the buffer layer 12, the interlayer dielectric layer 132 is located between the gate layer and the source-drain layer, and the signal line 133 is located in the non-display area 110; by providing a groove on the interlayer dielectric layer 132 and / or the buffer layer 12 at a position corresponding to the position of the signal line 133, and making at least part of the signal line 133 located in the groove, the thickness of the color filter layer 15 corresponding to the position of the signal line 133 can be increased in the subsequent process of manufacturing the color filter layer 15, thereby improving the light shielding ability of the color filter layer 15 and reducing the risk of reduced stability of the thin film transistor 131 after being exposed to external light.

[0098] 2. In some embodiments of the present application, the signal line 133 includes a data signal line 1331, which is disposed in the same layer as the source and drain electrode layer and is electrically connected. A first groove is provided on the interlayer dielectric layer 132 at a position corresponding to the position of the data signal line 1331, and the data signal line 1331 is located in the first groove. By providing the first groove at a position corresponding to the position of the data signal line 1331 on the interlayer dielectric layer 132, the data signal line 1331 can be partially or completely located in the first groove, thereby reducing the space occupied by the data signal line 1331 in the film layer of the display substrate 10 along the first direction, and the thickness of the color filter layer 15 at the position corresponding to the position of the data signal line 1331 can be increased, thereby improving the light shielding performance of the color filter layer 15.

[0099] 3. By making the first groove penetrate the interlayer dielectric layer 132 and extend to the surface of the buffer layer 12, the depth of the first groove is maximized, which is beneficial to increase the portion of the data signal line 1331 located in the first groove, so as to further reduce the step difference above the data signal line 1331 and increase the thickness of the color filter layer 15 at the position corresponding to the position of the data signal line 1331.

[0100] 4. In some embodiments of the present application, a second groove is provided on the buffer layer 12 at a position corresponding to the position of the first groove, the first groove is connected to the second groove, and the orthographic projection area of ​​the second groove on the substrate 11 is greater than or equal to the orthographic projection area of ​​the first groove on the substrate 11. By providing the second groove on the buffer layer 12 and connecting the second groove to the first groove, the portion of the data signal line 1331 located in the groove can be further increased, so as to reduce the space occupied by the data signal line 1331 in the film layer of the display substrate 10 along the first direction, and increase the thickness of the color filter layer 15 at the position corresponding to the data signal line 1331.

[0101] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0102] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0103] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0104] The above description is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A display substrate, characterized in that: include: substrate; A buffer layer is disposed on one side of the substrate; a switching device layer, arranged on a side of the buffer layer away from the substrate, comprising a thin film transistor, an interlayer dielectric layer and a signal line, wherein the thin film transistor comprises a gate layer and a source-drain layer, the gate layer is close to the buffer layer, the source-drain layer is located on a side of the gate layer away from the buffer layer, the interlayer dielectric layer is located between the gate layer and the source-drain layer, and the signal line is located in a non-display area; Wherein, at a position corresponding to the position of the signal line, a groove is provided on the interlayer dielectric layer and / or the buffer layer, at least part of the signal line is located in the groove, and at a position corresponding to the position of the signal line, the thickness of the color filter layer above the signal line increases accordingly; The signal line includes a data signal line, and the display substrate further includes a color filter layer arranged on a side of the source and drain electrode layer away from the substrate; The color filter layer comprises a first color filter layer and a second color filter layer, the first color filter layer and the second color filter layer are adjacent to each other, and the orthographic projections of the first color filter layer and the second color filter layer on the substrate overlap with the orthographic projections of the data signal line on the substrate; In the direction from the substrate to the buffer layer, the first color filter layer and the second color filter layer have a first thickness near the junction therebetween, and the first color filter layer and the second color filter layer have a second thickness away from the junction therebetween, the first thickness is greater than the second thickness, and the difference between the first thickness and the second thickness is greater than or equal to 1 micron.

2. The display substrate according to claim 1, characterized in that: The data signal line is arranged in the same layer as the source and drain electrode layer and is electrically connected; The interlayer dielectric layer is provided with a first groove at a position corresponding to the position of the data signal line, and the data signal line is located in the first groove.

3. The display substrate according to claim 2, characterized in that: The first groove penetrates the interlayer dielectric layer and extends to the surface of the buffer layer.

4. The display substrate according to claim 2, characterized in that: The buffer layer has a second groove at a position corresponding to the first groove, the first groove is connected to the second groove, and the orthographic projection area of ​​the second groove on the substrate is greater than or equal to the orthographic projection area of ​​the first groove on the substrate.

5. The display substrate according to any one of claims 2 to 4, characterized in that: The signal line further comprises a power line and a scan line, the power line and the scan line are stacked, the scan line is arranged in the same layer as the gate layer and is electrically connected, and the power line is arranged in the same layer as the source and drain layer; The buffer layer is provided with a third groove at a position corresponding to the positions of the power line and the scan line, and at least a part of the scan line is located in the third groove.

6. The display substrate according to claim 5, characterized in that: The third groove penetrates the buffer layer and extends to the surface of the substrate.

7. A display device, characterized in that: The display device comprises the display substrate according to any one of claims 1 to 6.

8. A method for manufacturing a display substrate, characterized in that: include: providing a substrate; Making a buffer layer on one side of the substrate; A switching device layer is formed on a side of the buffer layer away from the substrate, the switching device layer includes a thin film transistor, an interlayer dielectric layer and a signal line, the thin film transistor includes a gate layer and a source-drain electrode layer, and the interlayer dielectric layer is located between the gate layer and the source-drain electrode layer; wherein, at a position corresponding to the position of the signal line, a groove is formed on the interlayer dielectric layer and / or the buffer layer, at least part of the signal line is located in the groove, and at a position corresponding to the position of the signal line, the thickness of the color filter layer above the signal line is increased accordingly; The signal line includes a data signal line, and the display substrate further includes a color filter layer arranged on a side of the source and drain electrode layer away from the substrate; The color filter layer comprises a first color filter layer and a second color filter layer, the first color filter layer and the second color filter layer are adjacent to each other, and the orthographic projections of the first color filter layer and the second color filter layer on the substrate overlap with the orthographic projections of the data signal line on the substrate; In the direction from the substrate to the buffer layer, the first color filter layer and the second color filter layer have a first thickness near the junction therebetween, and the first color filter layer and the second color filter layer have a second thickness away from the junction therebetween, the first thickness is greater than the second thickness, and the difference between the first thickness and the second thickness is greater than or equal to 1 micron.

9. The manufacturing method according to claim 8, characterized in that: The signal line also includes a power line and a scan line; A buffer layer is formed on one side of the substrate, and a switch device layer is formed on a side of the buffer layer away from the substrate, comprising: A buffer layer is fabricated on one side of the substrate, and a second groove penetrating the buffer layer is formed at a position corresponding to the position of the data signal line, and a third groove penetrating the buffer layer is formed at a position corresponding to the position of the power line and the scanning line by a patterning process; A gate layer, a scan line and an interlayer dielectric layer are sequentially formed on a side of the buffer layer away from the substrate, and a first groove penetrating the interlayer dielectric layer is formed at a position corresponding to the position of the data signal line by a patterning process, and at least part of the scan line is located in the third groove; A source-drain layer, a data signal line and a power line are fabricated on a side of the interlayer dielectric layer away from the substrate. The data signal line is located in the first groove. The orthographic projection of the power line on the substrate overlaps with the orthographic projection of the scan line on the substrate.

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