Semiconductor device

Abstract

Provided is a semiconductor device that appropriately adjusts the withstand voltage in an active region. The semiconductor device includes an active region and a peripheral region, and includes: a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided above the drift region; a first collector region of the second conductivity type provided below the drift region in the active region; and a second collector region of the second conductivity type provided below the drift region in the peripheral region, the doping concentration of the first collector region being greater than the doping concentration of the second collector region, and the area of the first collector region being the same as or greater than the area of the second collector region when viewed from above.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] Previously, semiconductor devices such as insulated gate bipolar transistors (IGBTs) have active regions and edge regions (terminal structures) (for example, see Patent Document 1 or 2).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-133493

[0006] Patent Document 2: Japanese Patent Application Publication No. 2019-12725 Summary of the Invention

[0007] Technical issues

[0008] In semiconductor devices, the withstand voltage includes the withstand voltage of the active region and the withstand voltage of the edge region. In terms of the withstand voltage during switching operation, it is preferable that the edge region has a higher withstand voltage than the active region.

[0009] Technical solution

[0010] In one aspect of the present invention, a semiconductor device is provided, the semiconductor device having an active region and an edge region, and comprising: a drift region of a first conductivity type disposed on a semiconductor substrate; a base region of a second conductivity type disposed above the drift region; a first collector region of the second conductivity type disposed in the active region below the drift region; and a second collector region of the second conductivity type disposed in the edge region below the drift region, wherein the doping concentration of the first collector region is greater than the doping concentration of the second collector region, and in a top view, the area of ​​the first collector region is the same as or greater than the area of ​​the second collector region.

[0011] The doping concentration of the first collector region can be 1E16cm. -3 Above and 5E18cm -3 the following.

[0012] The doping concentration of the second collector region can be 1E16cm. -3 Above and 5E18cm -3 the following.

[0013] The semiconductor device may have an intermediate region located between the active region and the edge region when viewed from above. The first collector region may be configured to extend from the active region to the intermediate region when viewed from above.

[0014] The first collector area can be located inside the active area when viewed from above.

[0015] The semiconductor device may include: an emitter electrode disposed above a semiconductor substrate and electrically connected to the front side of the semiconductor substrate; and a gate metal layer disposed above the semiconductor substrate and configured as a gate potential. The width B, which is the distance from the outer periphery of the semiconductor substrate to the end of the second collector region, may be greater than the width A, which is the distance from the outer periphery of the semiconductor substrate to the end of the gate metal layer.

[0016] The doping concentration of the second collector region can be less than 0.85 times that of the first collector region.

[0017] The difference between width B and width A can be greater than 10μm.

[0018] The doping concentration of the second collector region can be more than 0.85 times and less than 0.9 times that of the first collector region.

[0019] When 0.1 < α < 0.5, the thickness T in the depth direction of the semiconductor substrate can satisfy BA < αT.

[0020] The semiconductor device may include: a second conductivity type of guard ring portion disposed above the drift region in the edge region; and a channel cut-off region disposed above the drift region in the edge region at a position closer to the outer peripheral end of the semiconductor substrate than the guard ring portion.

[0021] The above summary of the invention does not list all the features of the invention. Sub-combinations of these features can also constitute inventions. Attached Figure Description

[0022] Figure 1A An example of a top view showing a semiconductor device 100.

[0023] Figure 1B An example of a top view of a semiconductor device 100.

[0024] Figure 1C It means Figure 1B A diagram of an example of section a-a' in the figure.

[0025] Figure 2 This is a cross-sectional view showing an example of the configuration of the semiconductor device 100.

[0026] Figure 3A This indicates the region where the first collector region 61 is formed when viewed from above the semiconductor device 100.

[0027] Figure 3B This indicates the region where the first collector region 61 is formed when viewed from above the semiconductor device 100.

[0028] Figure 3CThis indicates the region where the first collector region 61 is formed when viewed from above the semiconductor device 100.

[0029] Figure 4A This indicates the relationship between the lead-out length (D) and temperature.

[0030] Figure 4B An example of the simulation results of semiconductor device 100.

[0031] Figure 4C This is an example of the simulation results for a comparative semiconductor device.

[0032] Figure 5A An example illustrating the characteristics of semiconductor device 100.

[0033] Figure 5B An example illustrating the characteristics of a comparative semiconductor device.

[0034] Symbol Explanation

[0035] 10…Semiconductor substrate, 11…Outer periphery, 12…Emitter region, 14…Base region, 15…Contact region, 16…Accumulation region, 17…Well region, 18…Drift region, 20…Buffer zone, 21…Front side, 23…Back side, 24…Collector electrode, 25…Connection portion, 28…Upper part, 29…End, 30…Dummy trench portion, 31…Extension portion, 32…Dummy insulating film, 34…Dummy conductive portion, 38…Interlayer insulating film, 40…Gate trench portion, 41…Extension portion, 42…Gate insulating film, 43…Connection portion, 44…Gate conductive portion 50…Gate metal layer, 52…Emitter electrode, 53…Barrier metal layer, 54…Contact hole, 55…Contact hole, 56…Contact hole, 57…Plug, 61…First collector region, 62…Second collector region, 71…Mesa section, 80…Field plate electrode, 82…Channel cutoff electrode, 84…Connection, 86…Insulating film, 88…Protective film, 92…Guard ring, 94…Channel cutoff region, 100…Semiconductor device, 110…Active region, 120…Non-active region, 122…Edge region, 124…Intermediate region, 140…Gate pad Detailed Implementation

[0036] The present invention will now be described through embodiments thereof; however, these embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the inventive solution.

[0037] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "front" or "upper," and the other side is referred to as "back" or "lower." One of the two main surfaces of a substrate, layer, or other component is referred to as the upper surface, and the other as the lower surface. The directions of "front," "upper," "back," and "lower" are not limited to the direction of gravity or the direction when mounting the semiconductor device.

[0038] In this specification, orthogonal coordinate axes of X, Y, and Z are sometimes used to illustrate technical matters. Orthogonal coordinate axes merely determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis is not limited to representing the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is not specified as positive or negative, it refers to a direction parallel to both the +Z-axis and -Z-axis. Furthermore, in this specification, the view viewed from the +Z-axis direction is sometimes referred to as a top view.

[0039] In the context of this specification, the terms "same" or "equal" may also include cases with errors due to manufacturing deviations, etc. Such errors may be, for example, within 10%.

[0040] In this specification, the conductivity type of the doped regions containing impurities is described as P-type or N-type. However, the conductivity types of each doped region can also be of opposite polarities. Furthermore, in this specification, P+ or N+ type refers to a doping concentration higher than P-type or N-type, while P- or N- type refers to a doping concentration lower than P-type or N-type.

[0041] In this specification, doping concentration refers to the concentration of impurities activated as donors or acceptors. In this specification, the concentration difference between donors and acceptors is sometimes used as the concentration of the majority of donors or acceptors. This concentration difference can be measured using the voltage-capacitance method (CV method). Alternatively, the carrier concentration measured by the diffusion resistance method (SR) can be used as the donor or acceptor concentration. Furthermore, if the donor or acceptor concentration distribution has a peak, that peak can be used as the donor or acceptor concentration in that region. If the donor or acceptor concentration is substantially uniform in the region where donors or acceptors exist, the average value of the donor or acceptor concentration in that region can be used as the donor or acceptor concentration.

[0042] Figure 1A This is an example of a top view of a semiconductor device 100. The semiconductor device 100 is a semiconductor chip having a transistor section. The semiconductor device 100 includes a semiconductor substrate 10 having an active region 110 and an active region 120 formed thereon.

[0043] The semiconductor substrate 10 is a substrate formed from semiconductor materials such as silicon, silicon carbide, or gallium nitride. The semiconductor substrate 10 may include portions formed by epitaxial growth or the like. In this example, the semiconductor substrate 10 is a silicon substrate.

[0044] The active region 110 is the region where the main current flows between the front side 21 and the back side 23 of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in a conducting state. That is, the active region 110 is the region where current flows along the depth direction inside the semiconductor substrate 10 from the front side 21 to the back side 23 or from the back side 23 to the front side 21. In this example, an IGBT is formed in the active region 110.

[0045] When viewed from above, the non-active region 120 is the area between the active region 110 and the outer peripheral end 11 of the semiconductor substrate 10. The non-active region 120 includes an edge region 122 and a middle region 124. One or more metal pads may be configured in the non-active region 120 for connecting the semiconductor device 100 to external devices using leads or the like.

[0046] Edge region 122 is the region between active region 110 and the outer peripheral end 11 of semiconductor substrate 10. When viewed from above, edge region 122 is configured to surround active region 110. It should be noted that edge region 122 may have an edge termination structure. The edge termination structure mitigates the electric field concentration on the upper surface side of semiconductor substrate 10. The specific structure of edge region 122 will be described later.

[0047] The intermediate region 124 is disposed between the active region 110 and the edge region 122 when viewed from above. In this example, the intermediate region 124 surrounds the outer periphery of the active region 110 when viewed from above. The intermediate region 124 has the gate metal layer 50 described later.

[0048] The gate pad 140 is electrically connected to the gate conductivity portion of the active region 110 via the gate metal layer 50. The gate pad 140 may also contact the gate metal layer 50. The gate pad 140 is set to the gate potential. In this example, the gate pad 140 is rectangular when viewed from above.

[0049] Figure 1B This is an example of a top view of a semiconductor device 100. In this example, it indicates that... Figure 1A The image is obtained by magnifying the region X.

[0050] In this example, the semiconductor device 100 has a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front side of the semiconductor substrate 10. In addition, the semiconductor device 100 in this example has an emitter electrode 52 and a gate metal layer 50 disposed on the upper part of the front side of the semiconductor substrate 10.

[0051] The emitter electrode 52 is disposed above the gate trench, the dummy trench, the emitter region, the base region, the contact region 15, and the well region 17. The emitter electrode 52 can be connected to an external electrode of the semiconductor device 100 via wire bonding or the like. The external electrode of the semiconductor device 100 can be, for example, an anode electrode of a diode or an electrode of an integrated circuit arranged adjacent to the semiconductor device 100, an electrode disposed on a substrate on which the semiconductor device 100 is mounted, or an external terminal disposed on a resin housing on which the substrate on which the semiconductor device 100 is mounted.

[0052] A gate metal layer 50 is disposed above the gate trench portion 40 and the well region 17. The gate metal layer 50 is electrically connected to the gate conductive portion of the active region 110, supplying a gate voltage. The gate metal layer 50 is electrically connected to the gate pad 140. In top view, the gate metal layer 50 is configured to surround the outer periphery of the active region 110. The gate metal layer 50 may be disposed along the intermediate region 124 between the active region 110 and the edge region 122.

[0053] The emitter electrode 52 and the gate metal layer 50 are formed of a metal-containing material. For example, at least a portion of the emitter electrode 52 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium and / or titanium compounds beneath the regions formed of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are disposed separately from each other.

[0054] The emitter electrode 52 and the gate metal layer 50 are disposed above the semiconductor substrate 10, separated by an interlayer insulating film 38. The interlayer insulating film 38... Figure 1B The middle part is omitted. Contact holes 55 and 56 are provided through the interlayer insulating film 38.

[0055] The contact hole 55 connects the gate metal layer 50 to the gate conductive portion within the active region 110. Inside the contact hole 55, a plug 57, made of tungsten or the like (described later), can be formed with the barrier metal layer 53 in between.

[0056] The contact hole 56 connects the emitting electrode 52 to the dummy conductive part within the dummy trench portion 30. Inside the contact hole 56, a plug 57 made of tungsten or the like can be formed with a barrier metal layer 53 in between.

[0057] The connection portion 25 electrically connects the front-side electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is disposed between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also disposed between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. Here, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is disposed above the front side of the semiconductor substrate 10 through an insulating film such as an oxide film.

[0058] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (X-axis direction in this example). The gate trench portions 40 in this example may have two extension portions 41 extending along an extension direction (Y-axis direction in this example) that is parallel to the front side of the semiconductor substrate 10 and perpendicular to the arrangement direction.

[0059] The connection portion 43 preferably has at least a portion formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, the electric field concentration at the ends of the extension portions 41 can be mitigated. In the connection portion 43 of the gate trench portion 40, the gate metal layer 50 can be connected to the gate conductive portion.

[0060] The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. The dummy trench portions 30, like the gate trench portions 40, are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). In this example, the dummy trench portion 30 has an extension portion 31 extending along the extension direction. It should be noted that the dummy trench portion 30 may have a U-shape on the front side of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connecting portion connecting the two extension portions 31.

[0061] The semiconductor device 100 in this example has a structure in which two gate trench portions 40 and one dummy trench portion 30 are repeatedly arranged. That is, the semiconductor device 100 in this example has gate trench portions 40 and dummy trench portions 30 in a 2:1 ratio. For example, the semiconductor device 100 has an extension portion 31 between two extension portions 41.

[0062] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 to the dummy trench portion 30 can be 1:1 or 1:2. Alternatively, the semiconductor device 100 may be entirely composed of gate trench portions 40 without providing dummy trench portions 30.

[0063] Well region 17 is a region of the second conductivity type located closer to the front side of semiconductor substrate 10 than drift region 18 (described later). Well region 17 is an example of a well region located on the non-active region 120 side of semiconductor device 100. The doping concentration of well region 17 can be higher than that of base region 14. As an example, well region 17 is P+ type. Well region 17 is formed from the end of active region 110 on the side where gate metal layer 50 is provided to non-active region 120 within a predetermined range. The diffusion depth of well region 17 can be deeper than the depth of gate trench portion 40 and dummy trench portion 30. A portion of gate trench portion 40 and dummy trench portion 30 located on the gate metal layer 50 side is formed in well region 17. The bottom of the ends of the extending direction of gate trench portion 40 and dummy trench portion 30 can be covered by well region 17.

[0064] Contact holes 54 are formed on the mesa 71 above each region of the emitter region 12 and the contact region 15. Contact holes 54 are not located above the well regions 17 located at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 can be configured to extend along the extension direction.

[0065] The mesa 71 is a region disposed adjacent to the trench portion in a plane parallel to the front side of the semiconductor substrate 10. The mesa 71 may be a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and is the portion extending from the front side of the semiconductor substrate 10 to the deepest bottom of each trench portion. An extension portion of each trench portion may be considered as a single trench portion. That is, the region sandwiched between two extension portions may be considered as the mesa 71. The mesa 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front side of the semiconductor substrate 10. In the mesa 71, the emitter region 12 and the contact region 15 are alternately disposed in the extending direction.

[0066] Base region 14 is a region of the second conductivity type disposed on the front side of semiconductor substrate 10. As an example, base region 14 is P-type. Base region 14 can be disposed at both ends of the mesa 71 on the front side of semiconductor substrate 10 in the Y-axis direction. It should be noted that... Figure 1B Only one end of the base region 14 in the Y-axis direction is shown.

[0067] Emitter region 12 is a region of the first conductivity type with a doping concentration higher than that of drift region 18. As an example, emitter region 12 in this example is N+ type. An example of the dopant for emitter region 12 is arsenic (As). Emitter region 12 is disposed on the front side of mesa 71 in contact with gate trench portion 40. Emitter region 12 can be configured to extend along the X-axis from one of the two trench portions sandwiching mesa 71 to the other. Emitter region 12 is also disposed below contact hole 54. Furthermore, emitter region 12 may or may not contact dummy trench portion 30. In this example, emitter region 12 contacts dummy trench portion 30.

[0068] Contact region 15 is a region of the second conductivity type with a higher doping concentration than the base region 14. As an example, contact region 15 in this example is P+ type. In this example, contact region 15 is located on the front side of the mesa 71. Contact region 15 can be configured to run along the X-axis from one of the two trench portions sandwiching the mesa 71 to the other. Contact region 15 may or may not contact the gate trench portion 40. Additionally, contact region 15 may or may not contact the dummy trench portion 30. In this example, contact region 15 contacts both the dummy trench portion 30 and the gate trench portion 40. Contact region 15 is also located below contact hole 54.

[0069] The active region 110 comprises an area formed by the repeated arrangement of the emitter region 12 and the contact region 15. Additionally, the active region 110 includes a dummy trench portion 30 and a gate trench portion 40. The end of the active region 110 in the Y-axis direction is the end of the region where the emitter electrode 52 is connected to the semiconductor substrate 10 via a contact hole 54. In this example, the end of the contact hole 54 is located above the contact region 15.

[0070] When viewed from above, edge region 122 is the region closer to the outer periphery 11 of the gate metal layer 50. In this example, the boundary between edge region 122 and the middle region 124 is the end of the gate metal layer 50 on the negative side of the Y-axis direction. The more specific structure of edge region 122 will be described later.

[0071] The intermediate region 124, when viewed from above, is the region between the active region 110 and the edge region 122. In the intermediate region 124, the emitter electrode 52 may not be electrically connected to the semiconductor substrate 10. However, in the intermediate region 124, the emitter electrode 52 may be electrically connected to the dummy conductive portion of the dummy trench portion 30.

[0072] Figure 1C It means Figure 1BThe figure shows an example of the a-a' section. The a-a' section is the XZ plane passing through the contact area 15 in the mesa 71. In this example, the semiconductor device 100 has a semiconductor substrate, an interlayer insulating film, an emitter electrode 52, and a collector electrode 24 in the a-a' section. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0073] Drift region 18 is a region of the first conductivity type disposed on semiconductor substrate 10. As an example, drift region 18 in this example is N-type. Drift region 18 can be a region remaining in semiconductor substrate 10 where no other doped regions have been formed. That is, the doping concentration of drift region 18 can be the doping concentration of semiconductor substrate 10. Emitter region 12, contact region 15, and accumulation region 16 are disposed above drift region 18. Buffer region 20 and first collector region 61 are disposed below drift region 18.

[0074] Buffer 20 is a region of the first conductivity type disposed below drift region 18. As an example, buffer 20 in this example is N-type. The doping concentration of buffer 20 is higher than that of drift region 18. Buffer 20 can function as a field cutoff layer to prevent the depletion layer extending from the lower surface side of base region 14 from reaching the first collector region 61 of the second conductivity type.

[0075] The first collector region 61 is a region of the second conductivity type located below the drift region 18 in the active region 110. For example, the first collector region 61 is P+ type. For instance, the doping concentration of the first collector region 61 is 1E16cm⁻¹. -3 Above and 5E18cm -3 Below. In one example, the doping concentration of the first collector region 61 is 8E17cm. -3 It should be noted that E refers to powers of 10, for example, 8E17cm. -3 It refers to 8×10 17 cm -3 The first collector area 61 is located below the buffer zone 20.

[0076] The collector electrode 24 is formed on the back side 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal. The collector electrode 24 is in contact with the first collector region 61.

[0077] The accumulation region 16 is a region of the first conductivity type located closer to the front side 21 of the semiconductor substrate 10 than the drift region 18. As an example, the accumulation region 16 in this example is N+ type. In this example, the accumulation region 16 is disposed in contact with the gate trench portion 40. The doping concentration of the accumulation region 16 is higher than that of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) is improved, thereby reducing the on-state voltage of the active region 110.

[0078] The gate trench portion 40 has a gate trench formed on the front side 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench at a position closer to the inside than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front side 21 by an interlayer insulating film 38.

[0079] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that sandwiches the gate insulating film 42 and faces the base region 14 adjacent to the mesa 71 side. If a predetermined voltage is applied to the gate conductive portion 44, electrons accumulate on the surface layer of the interface in the base region 14 that contacts the gate trench, forming a channel composed of an N-type inversion layer, and current flows through it.

[0080] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front side 21. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is located closer to the inner side than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front side 21 by an interlayer insulating film 38.

[0081] An interlayer insulating film 38 is disposed on the front side 21. An emitter electrode 52 is disposed above the interlayer insulating film 38. One or more contact holes 54 are provided on the interlayer insulating film 38 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be configured to penetrate the interlayer insulating film 38.

[0082] Figure 2 This is a cross-sectional view showing an example of the configuration of the semiconductor device 100. In this example, the plane parallel to the upper surface of the semiconductor substrate 10 is designated as the XY plane, and the depth direction of the semiconductor substrate 10 is designated as the Z-axis. Figure 2 A partial cross-sectional view is shown, including a portion of the active region 110 and an edge region 122 between that portion of the active region 110 and the outer peripheral end 11 of the semiconductor substrate 10. As an example, the active region 110 has a width greater than the edge region 122 in both the X and Y axes, and is surrounded by the edge region 122 in the XY plane. The end portion 29 on the outer peripheral end 11 side of the gate metal layer 50 is disposed along the boundary between the edge region 122 and the intermediate region 124.

[0083] A portion of the first collector region 61, when viewed from above, can be configured to extend from the active region 110 to the intermediate region 124. A portion of the first collector region 61, when viewed from above, can also be configured to extend from the active region 110 to the edge region 122. In one example, the first collector region 61 can be configured to extend more than 10 μm from the active region 110 to the non-active region 120, or it can be configured to extend more than 20 μm. The distance by which the first collector region 61 extends into the non-active region 120 can be within 40 μm.

[0084] The second collector region 62 is a region of the second conductivity type disposed below the drift region 18. The second collector region 62 is disposed below the buffer zone 20. At least a portion of the second collector region 62 is disposed in the edge region 122. When viewed from above, the second collector region 62 is positioned closer to the outer peripheral end 11 than the first collector region 61. For example, the doping concentration of the second collector region 62 is 1E16cm. -3 Above and 5E18cm -3 the following.

[0085] The doping concentration of the first collector region 61 is greater than that of the second collector region 62. In one example, the doping concentration of the second collector region 62 is less than 0.85 times that of the first collector region 61. It should be noted that the concentration difference between the first collector region 61 and the second collector region 62 is formed by ion implantation on the back surface 23 of the semiconductor substrate 10. As a formation method, ion implantation of a P-type dopant such as boron is performed on the entire surface of the first collector region 61. Subsequently, the second collector region 62 is covered with a photoresist or the like, and ion implantation of a P-type dopant is performed again. This allows the doping concentration of the first collector region 61 to be greater than that of the second collector region 62.

[0086] Position X1 is the boundary between the active region 110 and the non-active region 120 along the X-axis. Position X1 is also the location of the end where the emitter electrode 52 is electrically connected to the front side 21 of the semiconductor substrate 10. In this example, the boundary between the first collector region 61 and the second collector region 62 may differ from position X1.

[0087] Position X2 is the boundary position between the edge region 122 and the middle region 124 in the X-axis direction. Position X2 is the end position of the negative side of the gate metal layer 50 in the X-axis direction. Position X2 is located closer to the outer peripheral end 11 of the semiconductor substrate 10 than position X1.

[0088] Position X3 is the boundary position between the first collector region 61 and the second collector region 62 in the X-axis direction. Position X3 is located between position X1 and position X2 in the X-axis direction. The boundary position between the active region 110 and the non-active region 120 can also coincide with the boundary position between the first collector region 61 and the second collector region 62. In this case, position X1 becomes the same position as position X3.

[0089] The guard ring 92 is a region of the second conductivity type disposed above the drift region 18 in the edge region 122. In this example, the guard ring 92 is formed with the same doping concentration as the second collector region 62. The guard ring 92 is formed to surround the intermediate region 124 when viewed from above. The guard ring 92 serves to extend the depletion layer from the intermediate region 124 along the X-axis direction. Furthermore, by arranging multiple guard rings 92, the depletion layer can be further extended along the X-axis direction. Thus, by providing multiple guard rings 92, the breakdown voltage of the edge region 122 can be determined. The multiple guard rings 92 can be disposed separately from each other. In this example, the edge region 122 has four guard rings 92-1 to 92-4.

[0090] The field plate electrode 80 can be disposed above the guard ring portion 92. Multiple field plate electrodes 80 and multiple connection portions 84 can be formed above the semiconductor substrate 10 in the edge region 122. Four field plate electrodes 80-1 to 80-4 and four connection portions 84-1 to 84-4 are respectively disposed above the guard ring portions 92-1 to 92-4. The connection portions 84 can be configured to extend beyond the corresponding guard ring portion 92 in the X-axis direction, and the connection portions 84 can also extend beyond the field plate electrode 80. In this example, the field plate electrode 80 is electrically connected to the guard ring portion 92 via the barrier metal layer 53 and the connection portion 84. The field plate electrode 80 can be formed in the same process as the gate metal layer 50 and the emitter electrode 52. Furthermore, the connection portion 84 can be formed of polysilicon and is formed in the same process as the gate conductive portion 44 of the gate trench portion 40 and the dummy conductive portion 34 of the dummy trench portion 30.

[0091] The connecting portion 84 is covered by an insulating film 86. The insulating film 86 is provided with contact holes for connecting the connecting portion 84 to the protective ring portion 92 and for connecting the field plate electrode 80 to the connecting portion 84.

[0092] The barrier metal layer 53 electrically connects the field plate electrode 80 and the guard ring portion 92 in the contact hole. The barrier metal layer 53 is formed of titanium or titanium compounds. For example, the barrier metal layer 53 is a laminated film of Ti and TiN. It should be noted that a tungsten plug 57 may also be provided in the contact hole through the barrier metal layer 53.

[0093] The channel cutoff region 94 is located above the drift region 18 in the edge region 122, closer to the outer peripheral end 11 of the semiconductor substrate 10 than the protective ring portion 92. The channel cutoff region 94 is an N+ type or P+ type region. A channel cutoff electrode 82 can be formed above the channel cutoff region 94 with an insulating film 86 in between.

[0094] A channel cutoff electrode 82 is disposed above the channel cutoff region 94. The channel cutoff electrode 82 is electrically connected to the channel cutoff region 94 via a contact hole disposed in the insulating film 86. Alternatively, the channel cutoff electrode 82 can be electrically connected to the channel cutoff region 94 via a barrier metal layer 53. Furthermore, a tungsten plug 57, etc., can be provided in the contact hole across the barrier metal layer 53 to electrically connect the channel cutoff electrode 82 to the channel cutoff region 94. The channel cutoff electrode 82 can be configured to extend from the outer peripheral end 11 to the region where the channel cutoff region 94 is not disposed in the X-axis direction. The channel cutoff electrode 82 can be formed in the same process as the gate metal layer 50 and the emitter electrode 52.

[0095] A protective film 88 covers the field plate electrode, the channel cutoff electrode, the insulating film 86, and the emitter electrode 52 above the semiconductor substrate 10. For connection with bonding wires, a portion of the emitter electrode 52 can be exposed from the protective film 88. Additionally, regarding the upper portion 28 on the outer peripheral end 11 side of the semiconductor substrate 10, the channel cutoff region 94 is exposed from the protective film 88.

[0096] Here, the doping concentration of the first collector region 61 is greater than that of the second collector region 62. If the doping concentration of the second collector region 62 is greater than that of the first collector region 61, the number of holes increases, leading to an increase in electrons and a rise in the concentration of the drift region 18. Therefore, the breakdown voltage decreases compared to a configuration where the doping concentration of the second collector region 62 is less than that of the first collector region 61. The breakdown voltage of the active region 110 is relatively lower than that of the edge region 122. Here, breakdown voltage refers to the voltage value calculated based on the integral value of the electric field that causes avalanche breakdown when the semiconductor device is in the off state and a voltage is applied to the semiconductor device with the pn junction of the base region 14 and the drift region 18 reverse biased. As a result, the active region 110 can avalanche break down before the edge region 122.

[0097] When the doping concentration of the first collector region 61 is greater than the doping concentration of the second collector region 62, as described later... Figure 4B As shown, in the active region 110, the electric field at the bottom of the gate trench 40 and the dummy trench 30 becomes stronger, thus avalanche current is generated at the bottom of the gate trench 40 and the dummy trench 30. If the avalanche current reaches the first collector region 61, holes are generated due to conductivity modulation. The generated holes can be extracted in the extraction region of the front side 21.

[0098] At this point, avalanche currents at the bottom of the gate trench 40 and the dummy trench 30 become more likely to occur in regions where the width and / or depth of the trenches in the gate trench 40 and the dummy trench 30 are locally slightly different. For the regions where avalanche currents occur, the temperature increases, and the resistance of the drift region 18 increases. Thus, the avalanche current is suppressed, and the withstand voltage increases.

[0099] It should be noted that in other regions where the avalanche current does not flow in the active region 110, the temperature is low and the withstand voltage is reduced because the avalanche current does not flow.

[0100] Avalanche current moves towards regions of lower temperature, and the temperature rises in the regions where the avalanche current moves. This movement of avalanche current flow within the active region 110 is repeated. Therefore, because the avalanche current continuously moves at the bottom of the gate trench 40 and the dummy trench 30, the temperature rise of the active region 110 is suppressed, making it difficult for device damage due to overvoltage to occur.

[0101] On the other hand, when the doping concentration of the first collector region 61 is less than that of the second collector region 62, an avalanche current is generated at the corner of the guard ring portion 92 of the well region 17 in the edge region 122. If the avalanche current reaches the second collector region 62, a hole is generated. This hole can be extracted from the emitter electrode 52 of the active region 110 through the well region 17. Heat is generated according to the distance the hole travels from the well region 17 to the emitter electrode 52, and the temperature rises. As a result, the device is damaged before the avalanche current generation region moves. As a result, when the doping concentration of the first collector region 61 is greater than that of the second collector region 62, the shutdown tolerance (i.e., the damage tolerance during dynamic avalanche) is increased.

[0102] In particular, if the semiconductor device 100 is miniaturized and the spacing of the trenches is reduced, the breakdown voltage of the active region 110 increases. In this case, if the area of ​​the edge region 122 is reduced to relatively reduce costs, or the thickness of the semiconductor substrate 10 is thinned to improve characteristics, the breakdown voltage of the edge region 122 becomes relatively low, and therefore, the edge region 122 becomes more susceptible to avalanche breakdown. As a result, the shutdown withstand capability (i.e., the damage withstand capability during dynamic avalanche) of the semiconductor device 100 decreases.

[0103] In the semiconductor device 100 of this example, since the first collector region 61 has a higher doping concentration than the second collector region 62, even if the area of ​​the edge region 122 is reduced or the thickness of the semiconductor substrate 10 is reduced, the avalanche tolerance can be improved because the breakdown voltage of the active region 110 is relatively lower than that of the non-active region 120.

[0104] It should be noted that by providing the accumulation region 16, the carrier concentration below the accumulation region 16 can be increased, thereby reducing the on-state voltage. Furthermore, by providing the accumulation region 16, the withstand voltage of the active region 110 can be relatively reduced compared to the case where the accumulation region 16 is not provided, further improving the turn-off withstand capability (i.e., the withstand capability during dynamic avalanche). However, the semiconductor device 100 may also be without the accumulation region 16.

[0105] Width A is the distance from the outer periphery 11 of the semiconductor substrate 10 to the end of the gate metal layer 50. The size of width A can be increased by increasing the number of guard rings 92, thereby extending the depletion layer in the X direction from the well region 17 of the intermediate region 124. However, if width A is too large, the area of ​​the semiconductor device 100 itself increases, the number of semiconductor devices 100 disposed on a single semiconductor wafer decreases, and the cost increases. Therefore, in this example, width A is set to 120 μm or more and 300 μm or less.

[0106] Width B is the distance from the outer periphery 11 of the semiconductor substrate 10 to position X3 at the end of the second collector region 62. Width B can be greater than width A. When width B is greater than width A, the difference BA represents the lead-out length of the second collector region 62 from the edge region 122. For example, the lead-out length can be set to 10 μm or more. Avalanche current in the edge region 122 is generated from position X1 of the well region 17 in the intermediate region 124. Therefore, when the difference BA becomes smaller (i.e., position X3 is closer to the edge region 122), the breakdown voltage of the edge region 122 and the active region 110 is determined by the position X3 of the first collector region 61. The smaller the difference BA becomes (i.e., the closer position X3 is to the edge region 122), the higher the breakdown voltage of the edge region 122 becomes compared to the breakdown voltage of the active region 110. As a result, the breakdown voltage of the semiconductor device 100 becomes the breakdown voltage of the edge region 122, and the turn-off withstand capability (i.e., the damage withstand capability during dynamic avalanche) becomes lower.

[0107] Width C is the distance from the outer peripheral end 11 of the semiconductor substrate 10 to the end of the contact hole used to electrically connect the emitter electrode 52 to the front surface 21 of the semiconductor substrate 10.

[0108] The lead-out length D is the length by which the first collector region 61 extends beyond the active region 110 into the non-active region 120. The lead-out length D is the difference between the width C and the width B. By increasing the lead-out length D, it becomes easier to relatively reduce the withstand voltage of the active region 110, thereby increasing the withstand capacity.

[0109] The doping concentration of the second collector region 62 can be more than 0.85 times and less than 0.9 times that of the first collector region 61. In this case, by making the width B larger than the width A and making the difference between the width B and the width A greater than 10 μm, the breakdown voltage of the edge region 122 is unlikely to become lower than that of the active region 110.

[0110] Furthermore, when α is set to 0.1 < α < 0.5, the thickness T of the semiconductor substrate 10 in the Z-axis direction (i.e., the depth direction) satisfies BA < αT. For example, the thickness T of the semiconductor substrate 10 in the depth direction can be 50 μm or more, or 60 μm or more. Alternatively, the thickness T of the semiconductor substrate 10 in the depth direction can be 650 μm or less.

[0111] Figure 3A This indicates the region where the first collector region 61 is formed when viewed from above the semiconductor device 100. In this example, the first collector region 61 is located inside the gate metal layer 50. The first collector region 61 is disposed along the gate metal layer 50. The gate pad 140 contacts the gate metal layer 50 and extends from the intermediate region 124 to the active region 110. In this example, the first collector region 61 is also disposed in a portion of the lower part of the gate pad 140. When viewed from above, the area S1 of the first collector region 61 is the same as or larger than the area S2 of the second collector region 62. As a result, it becomes easier to relatively reduce the breakdown voltage of the active region 110 and improve its withstand voltage.

[0112] Figure 3B This indicates the region where the first collector region 61 is formed when viewed from above the semiconductor device 100. In this example, the first collector region 61 is located inside the active region 110 when viewed from above. Although the first collector region 61 in this example has a rectangular shape when viewed from above, it is not limited to this. In this example, the first collector region 61 is not located in the non-active region 120. Even in this case, when viewed from above, the area S1 of the first collector region 61 is the same as or larger than the area S2 of the second collector region 62.

[0113] Figure 3C This indicates the region where the first collector region 61 is formed when the semiconductor device 100 is viewed from above. In this example, the first collector region 61 is located inside the active region 110 when viewed from above. In this example, the first collector region 61 is located along the active region 110. The first collector region 61 is located in the region inside the gate metal layer 50, outside the region where the gate pad 140 is located. Even in this case, when viewed from above, the area S1 of the first collector region 61 is the same as or larger than the area S2 of the second collector region 62.

[0114] Figure 4A This chart shows the relationship between the lead-out length D and temperature. The vertical axis represents the maximum temperature inside the semiconductor device 100 when the voltage is clamped, and the horizontal axis represents the lead-out length D of the first collector region 61. In the various charts, the concentration ratio of the first collector region 61 and the second collector region 62 is different.

[0115] The concentration ratio R represents the ratio of the doping concentration of the second collector region 62 to the doping concentration of the first collector region 61. When R = 0.92, the doping concentration of the second collector region 62 is 0.92 times that of the first collector region 61. The same applies for R = 0.85 and R = 0.6.

[0116] Region E1 is the region with the lowest maximum temperature during clamping, and it is the temperature region within the active region 110 that defines the avalanche current. Region E2 is the region with the highest maximum temperature during clamping that is higher than that of region E1, and it is the temperature region within the edge region 122 that defines the avalanche current. Clamping refers to the temperature region described later. Figure 5A When the circuit is turned off, the collector voltage VCE rises and reaches a constant state.

[0117] Figure 4B This is an example of the simulation results for semiconductor device 100. It shows that the doping concentration of the first collector region 61 is set to 8E17cm. -3 The doping concentration of the second collector region 62 is set to 6E17cm. -3 The internal state under certain circumstances.

[0118] By making the doping concentration of the first collector region 61 higher than that of the second collector region 62, it becomes easier to generate avalanche current in the active region 110. As a result, the breakdown voltage in the active region 110 becomes the breakdown voltage of the semiconductor device 100. This is because the temperature at which avalanche current is generated becomes... Figure 4A In region E1, the temperature does not rise sharply, making component damage unlikely. However, if the avalanche current eventually moves to the edge and the temperature rises to region E2, damage to the semiconductor device 100 may occur.

[0119] Figure 4C This is an example of simulation results for a comparative semiconductor device. It shows that the doping concentration of both the first collector region 61 and the second collector region 62 is set to 6E17cm. -3 The internal state under certain circumstances.

[0120] By setting the doping concentrations of the first collector region 61 and the second collector region 62 to the same level, it becomes easier to generate avalanche current in the edge region 122. As a result, the breakdown voltage of the edge region 122 becomes the breakdown voltage of the semiconductor device in the comparative example. The avalanche current is generated at the corner of the guard ring portion 92 side of the well region 17. The temperature rises sharply when the avalanche current is generated. Figure 4A The region is E2. Therefore, if an avalanche current flows, the temperature rises sharply, causing damage to the semiconductor device.

[0121] Figure 4AThe conditions for R and the lead-out length D shown are as follows. When R = 0.92, the lead-out length D of the first collector region 61 is set to 10 μm or more. Furthermore, when R = 0.85, the lead-out length D of the first collector region 61 is set to 40 μm or less.

[0122] Figure 5A This is an example illustrating the characteristics of the semiconductor device 100. The graphs in this example show the waveforms of the gate voltage VGE, collector voltage VCE, and collector current ICE when a wiring inductance of approximately 10–20 μH is connected. If the semiconductor device 100 in this example has a first collector region 61 with a higher doping concentration than the second collector region 62, the clamping time is extended. Therefore, it becomes less likely for device damage due to overvoltage to occur.

[0123] In this example, the semiconductor device 100 increases the hole density on the back side 23 and the electron density from the front side 21 by making the doping concentration of the first collector region 61 greater than that of the second collector region 62. Therefore, in the active region 110, due to the... Figure 5A The waveform of the collector voltage VCE shown is clamped to a constant state, which increases the electron density in the drift region 18, thus suppressing the expansion of the depletion layer and reducing the breakdown voltage during clamping. As a result, it becomes easier to generate avalanche current in the active region 110, thereby improving the breakdown voltage.

[0124] Figure 5B This illustrates an example of the characteristics of a comparative semiconductor device. In this comparative semiconductor device, the doping concentration is constant rather than gradient in the collector region. Therefore, in this comparative semiconductor device, if an avalanche current is generated in the edge region, the semiconductor device 100 will be damaged due to temperature rise. Figure 5B If the wiring inductance is further increased, the semiconductor device 100 will be damaged.

[0125] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. As can be seen from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

Claims

1. A semiconductor device, characterized in that, It has an active region and an edge region, and also has: The drift region of the first conductivity type is disposed on the semiconductor substrate; The base region of the second conductivity type is disposed above the drift region; The first collector region of the second conductivity type is disposed below the drift region in the active region; The second collector region of the second conductivity type is disposed below the drift region in the edge region; The emitting electrode is disposed above the semiconductor substrate and electrically connected to the front side of the semiconductor substrate; as well as A gate metal layer, disposed above the semiconductor substrate, is used to set the gate potential. The doping concentration of the first collector region is greater than the doping concentration of the second collector region. When viewed from above, the area of ​​the first collector region is the same as the area of ​​the second collector region, or the area of ​​the first collector region is larger than the area of ​​the second collector region. The width B, which is the distance from the outer periphery of the semiconductor substrate to the end of the second collector region near the active region, is greater than the width A, which is the distance from the outer periphery of the semiconductor substrate to the end of the gate metal layer near the outer periphery.

2. The semiconductor device according to claim 1, characterized in that, The doping concentration of the first collector region is 1E16cm. -3 Above and 5E18cm -3 the following.

3. The semiconductor device according to claim 1, characterized in that, The doping concentration of the second collector region is 1E16cm. -3 Above and 5E18cm -3 the following.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device includes an intermediate region disposed between the active region and the edge region when viewed from above. The first collector area is configured to extend from the active area to the intermediate area when viewed from above.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first collector region is located inside the active region when viewed from above.

6. The semiconductor device according to claim 1, characterized in that, The doping concentration of the second collector region is less than 0.85 times that of the first collector region.

7. The semiconductor device according to claim 1, characterized in that, The difference between width B and width A is greater than 10. μ m.

8. The semiconductor device according to claim 7, characterized in that, The doping concentration of the second collector region is more than 0.85 times and less than 0.9 times that of the first collector region.

9. The semiconductor device according to any one of claims 6 to 8, characterized in that, Set to 0.1 < α When the thickness T of the semiconductor substrate is less than 0.5, the thickness T in the depth direction satisfies BA < α T.

10. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device includes: The second type of conductive protective ring is disposed above the drift region in the edge region; as well as The channel cut-off region is located above the drift region in the edge region, at a position closer to the outer peripheral end of the semiconductor substrate than the protective ring portion.

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