A diamond-based SiC PIN diode and a method for manufacturing the same

Abstract

The present invention provides a diamond-based SiC PIN diode and a manufacturing method thereof, wherein the diode comprises: an N-type ohmic electrode; an N-type heavily doped semiconductor transmission layer, wherein the lower side of the N-type heavily doped semiconductor transmission layer is connected to the upper side of the N-type ohmic electrode; an N-type doped diamond voltage-resistant improvement layer, wherein the lower side of the N-type doped diamond voltage-resistant improvement layer is connected to the upper side of the N-type heavily doped semiconductor transmission layer; an N-type intrinsic layer, wherein the lower side of the N-type intrinsic layer is connected to the upper side of the N-type doped diamond voltage-resistant improvement layer; a P-type heavily doped semiconductor transmission layer, wherein the lower side of the P-type heavily doped semiconductor transmission layer is connected to the upper side of the N-type intrinsic layer; and a P-type ohmic electrode, wherein the lower side of the P-type ohmic electrode is connected to the upper side of the P-type heavily doped semiconductor transmission layer, thereby greatly improving the voltage and current resistance capabilities of the diode.

Description

Technical Field

[0001] The present invention relates to a diamond-based SiC PIN diode and a method for manufacturing the same. Background Art

[0002] SiC DevicesSiC materials have attracted extensive attention and research due to their superior physical properties. Their high-temperature, high-power electronic devices have the advantages of high input impedance, fast switching speed, high operating frequency, high temperature and high pressure resistance, and have been widely used in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.

[0003] However, due to the limitations of material properties, its bandgap width is certain, and current capability must be sacrificed when achieving a higher withstand voltage. Therefore, the current capability of high-voltage-rated SiC PIN diodes is relatively small. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a diamond-based SiC PIN diode and a manufacturing method thereof, so as to improve the current capability and voltage capability of the SiC PIN diode.

[0005] One of the present inventions is implemented as follows: a diamond-based SiC PIN diode with withstand voltage and current, comprising:

[0006] An N-type ohmic electrode;

[0007] an N-type heavily doped semiconductor transmission layer, wherein the lower side of the N-type heavily doped semiconductor transmission layer is connected to the upper side of the N-type ohmic electrode;

[0008] an N-type doped diamond voltage-resistant improving layer, wherein the lower side of the N-type doped diamond voltage-resistant improving layer is connected to the upper side of the N-type heavily doped semiconductor transmission layer;

[0009] An N-type intrinsic layer, the lower side of the N-type intrinsic layer is connected to the upper side of the N-type doped diamond withstand voltage improvement layer;

[0010] a P-type heavily doped semiconductor transmission layer, wherein the lower side of the P-type heavily doped semiconductor transmission layer is connected to the upper side of the N-type intrinsic layer;

[0011] and, a P-type ohmic electrode, the lower side of the P-type ohmic electrode being connected to the upper side of the P-type heavily doped semiconductor transmission layer;

[0012] The doping concentration of the N-type doped diamond voltage-enhancing layer is 4 times that of the N-type intrinsic layer.

[0013] Furthermore, the thickness of the N-type doped diamond voltage-enhancing layer is 1.2 to 3 microns, and the thickness of the N-type intrinsic layer is 3 microns.

[0014] Furthermore, the doping concentration of the N-type doped diamond voltage-enhancing layer is 4*10 17 cm -3 .

[0015] Furthermore, the N-type doped diamond voltage-resistant enhancement layer is N-type diamond.

[0016] The second aspect of the present invention is achieved as follows: a method for manufacturing a diamond-based SiC PIN diode, specifically comprising the following steps:

[0017] Step 1: Processing the SiC epitaxial wafer to remove foreign matter on the surface and form a substrate;

[0018] Step 2, epitaxially growing an N-type heavily doped semiconductor transmission layer on the surface of the substrate;

[0019] Step 3, epitaxially growing an N-type doped diamond voltage-enhancing layer on the N-type heavily doped semiconductor transport layer;

[0020] Step 4, epitaxially growing an N-type SiC intrinsic layer on the N-type doped diamond voltage-enhancing layer;

[0021] Step 5, epitaxially growing a P-type heavily doped semiconductor transmission layer on the N-type SiC intrinsic layer;

[0022] Step 6: removing the substrate obtained according to the above steps through a substrate removal process;

[0023] Step 7: evaporate and photolithograph on the N-type heavily doped semiconductor transmission layer to produce an N-type ohmic electrode, and then evaporate and photolithograph on the P-type heavily doped semiconductor transmission layer to produce a P-type ohmic electrode.

[0024] Furthermore, the step 1 is further specified as follows: rinse the surface of the SiC epitaxial wafer with deionized water, and then soak it in a heated mixed washing solution for 1 minute to further remove foreign matter on the surface of the SiC epitaxial wafer to form a substrate; the mixed washing solution includes ammonia water, hydrogen peroxide and deionized water.

[0025] Furthermore, the thickness of the N-type doped diamond voltage-enhancing layer is 1.2 to 3 microns, and the thickness of the N-type intrinsic layer is 3 microns.

[0026] Furthermore, the doping concentration of the N-type doped diamond voltage-enhancing layer is 4*10 17 cm -3 .

[0027] Furthermore, the N-type doped diamond voltage-resistant enhancement layer is N-type diamond.

[0028] Furthermore, the thickness of the N-type heavily doped semiconductor transmission layer is 6 microns.

[0029] The advantages of the present invention are as follows: in the present invention, the diamond layer is below the N-type intrinsic layer, and the structure does not affect the withstand voltage characteristics of the PN junction formed by the original PN structure. Simply adding a layer of doped diamond can reduce the thickness of the PIN diode, and on the premise of ensuring the withstand voltage of the SiC PIN diode, the current withstand capacity is improved, and its current capacity is increased by 4 times. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0031] Figure 1 A flowchart of a method for manufacturing a diamond-based SiC PIN diode according to the present invention;

[0032] Figure 2 A schematic diagram of a method for manufacturing a diamond-based SiC PIN diode according to the present invention Figure 1 ;

[0033] Figure 3 A schematic diagram of a method for manufacturing a diamond-based SiC PIN diode according to the present invention Figure 2 ;

[0034] Figure 4 A schematic diagram of a method for manufacturing a diamond-based SiC PIN diode according to the present invention Figure 3 ;

[0035] Figure 5 A schematic diagram of a method for manufacturing a diamond-based SiC PIN diode according to the present invention Figure 4 ;

[0036] Figure 6 A schematic diagram of a method for manufacturing a diamond-based SiC PIN diode according to the present invention Figure 5 ;

[0037] Figure 7 A schematic diagram of a method for manufacturing a diamond-based SiC PIN diode according to the present invention Figure 6 ;

[0038] Figure 8 A schematic diagram of a diode manufactured by a method for manufacturing a diamond-based SiC PIN diode according to the present invention;

[0039] Fig. 9 Schematic diagram of the space charge region during the working process of the diode of the present invention Figure 1 ;

[0040] Fig.10Schematic diagram of the space charge region during the working process of the diode of the present invention Figure 2 . DETAILED DESCRIPTION

[0041] like Figures 1 to 8 As shown, the present invention provides a method for manufacturing a diamond-based SiC PIN diode, which specifically includes the following steps:

[0042] Step 1, washing the surface of the SiC epitaxial wafer with deionized water, and then soaking it in a heated mixed washing solution for 1 minute to further remove foreign matter on the surface of the SiC epitaxial wafer to form a substrate; the mixed washing solution includes ammonia water, hydrogen peroxide and deionized water;

[0043] Step 2, epitaxially growing an N-type heavily doped semiconductor transmission layer on the surface of the substrate;

[0044] Step 3: epitaxially grow an N-type doped diamond voltage-resistant improving layer on the N-type heavily doped semiconductor transport layer, wherein the thickness of the N-type doped diamond voltage-resistant improving layer is 3 microns, the N-type doped diamond voltage-resistant improving layer is N-type diamond, and the doping concentration of the N-type doped diamond voltage-resistant improving layer is 4*10 17 cm -3 ;

[0045] Step 4, epitaxially growing an N-type SiC intrinsic layer on the N-type doped diamond withstand voltage enhancement layer, wherein the thickness of the N-type intrinsic layer is 3 microns;

[0046] Step 5, epitaxially growing a P-type heavily doped semiconductor transmission layer on the N-type SiC intrinsic layer, wherein the thickness of the N-type heavily doped semiconductor transmission layer is 6 microns;

[0047] Step 6: removing the substrate obtained according to the above steps through a substrate removal process;

[0048] Step 7: evaporate and photolithograph on the N-type heavily doped semiconductor transmission layer to produce an N-type ohmic electrode, and then evaporate and photolithograph on the P-type heavily doped semiconductor transmission layer to produce a P-type ohmic electrode.

[0049] like Figure 8 As shown, the present invention is a diamond-based SiC PIN diode, comprising:

[0050] An N-type ohmic electrode;

[0051] an N-type heavily doped semiconductor transmission layer, wherein the lower side of the N-type heavily doped semiconductor transmission layer is connected to the upper side of the N-type ohmic electrode;

[0052] an N-type doped diamond voltage-resistant improving layer, wherein the lower side of the N-type doped diamond voltage-resistant improving layer is connected to the upper side of the N-type heavily doped semiconductor transmission layer;

[0053] an N-type intrinsic layer, the lower side of the N-type intrinsic layer is connected to the upper side of the N-type doped diamond withstand voltage improvement layer, the thickness of the N-type intrinsic layer is 3 microns (the thickness of the N-type intrinsic layer in the prior art is 6 microns), and the material of the N-type intrinsic layer is SiC;

[0054] a P-type heavily doped semiconductor transmission layer, wherein the lower side of the P-type heavily doped semiconductor transmission layer is connected to the upper side of the N-type intrinsic layer;

[0055] and, a P-type ohmic electrode, wherein the lower side of the P-type ohmic electrode is connected to the upper side of the P-type heavily doped semiconductor transmission layer.

[0056] The thickness of the N-type doped diamond voltage-enhancing layer is 1.2 to 3 microns.

[0057] The doping concentration of the N-type doped diamond voltage-enhancing layer is 4*10 17 cm -3 .

[0058] The N-type doped diamond pressure-resistant improving layer is N-type diamond

[0059] The diode has a vertical structure and is a bipolar device.

[0060] Under the same withstand voltage level, the diode has a reduced device thickness.

[0061] The diode adds a diamond voltage-resistant improvement layer above the N-type heavily doped semiconductor transmission layer on the original basis.

[0062] The thickness of the N-type doped diamond pressure-resistant improving layer is 3 microns, and the doping concentration of the N-type doped diamond pressure-resistant improving layer is 4*10 17 cm -3 The N-type doped diamond voltage-enhancing layer is made of N-type diamond, and the doping concentration of the N-type doped diamond voltage-enhancing layer is 4 times that of the N-type intrinsic layer.

[0063] The diamond withstand voltage improvement layer can improve the withstand voltage level of the diode because a space charge region is formed when the PIN diode is reversely pressurized, and the space charge region diffuses from the N-type intrinsic layer to the N-type doped diamond withstand voltage improvement layer.

[0064] like Fig. 9 and Fig.10 As shown in the figure, at low voltage, the space charge region diffuses to the N-type intrinsic withstand voltage region. When the voltage is gradually increased, the space charge region diffuses to the diamond region. However, since the doping concentration of the N-type doped diamond withstand voltage enhancement layer is 4 times that of the N-type intrinsic layer, the diffusion depth is one-fourth at the same voltage. Therefore, under the same thickness, the withstand voltage level is 2.5 times the original.

[0065] When the thickness of the PIN diode remains unchanged, that is, the diamond voltage-resistant enhancement layer is 3 microns and the N-type intrinsic layer is 3 microns, the voltage resistance is increased by 2.5 times and the current is increased by 4 times; when the diamond voltage-resistant enhancement layer is 1.2 microns and the N-type intrinsic layer is 3 microns, the voltage resistance can be achieved The same as the prior art, but the thickness is reduced by 1.8 microns, further reducing the thickness of the PIN diode and reducing the volume of the PIN diode.

[0066] The present invention replaces part of the material of the N-type intrinsic layer on the basis of the SiC PIN diode. The structure does not change the pn junction of the basic SiC PIN diode, that is, the basic structure of the PIN diode is not changed. The improvement of its withstand voltage characteristics is mainly due to the extension of the same type of doping space charge region, thereby improving the withstand voltage characteristics, rather than relying on heterojunction characteristics to improve the withstand voltage capability.

[0067] This structure relies on the material's inherent withstand voltage characteristics to achieve a smaller space charge region that meets the reverse withstand voltage characteristics. It is an extension of the pn junction space charge region and an extension of the basic working principle of PIN.

[0068] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A diamond-based SiC PIN diode with high voltage and current resistance, characterized in that: include: An N-type ohmic electrode; an N-type heavily doped semiconductor transmission layer, wherein the lower side of the N-type heavily doped semiconductor transmission layer is connected to the upper side of the N-type ohmic electrode; an N-type doped diamond voltage-resistant improving layer, wherein the lower side of the N-type doped diamond voltage-resistant improving layer is connected to the upper side of the N-type heavily doped semiconductor transmission layer; An N-type intrinsic layer, the lower side of the N-type intrinsic layer is connected to the upper side of the N-type doped diamond withstand voltage improvement layer; a P-type heavily doped semiconductor transmission layer, wherein the lower side of the P-type heavily doped semiconductor transmission layer is connected to the upper side of the N-type intrinsic layer; and, a P-type ohmic electrode, the lower side of the P-type ohmic electrode being connected to the upper side of the P-type heavily doped semiconductor transmission layer; The doping concentration of the N-type doped diamond voltage-enhancing layer is 4 times that of the N-type intrinsic layer.

2. A diamond-based SiC PIN diode with withstand voltage and current according to claim 1, characterized in that: The thickness of the N-type doped diamond voltage-enhancing layer is 1.2 to 3 microns, and the thickness of the N-type intrinsic layer is 3 microns.

3. The diamond-based SiC PIN diode with withstand voltage and current according to claim 1, characterized in that: The doping concentration of the N-type doped diamond voltage-enhancing layer is 4*10 17 cm -3 .

4. The diamond-based SiC PIN diode with withstand voltage and current according to claim 1, characterized in that: The N-type doped diamond voltage-resistant improving layer is N-type diamond.

5. A method for manufacturing a diamond-based SiC PIN diode, characterized in that: The specific steps include: Step 1: Processing the SiC epitaxial wafer to remove foreign matter on the surface and form a substrate; Step 2, epitaxially growing an N-type heavily doped semiconductor transmission layer on the surface of the substrate; Step 3, epitaxially growing an N-type doped diamond voltage-enhancing layer on the N-type heavily doped semiconductor transport layer; Step 4, epitaxially growing an N-type SiC intrinsic layer on the N-type doped diamond voltage-enhancing layer; Step 5, epitaxially growing a P-type heavily doped semiconductor transmission layer on the N-type SiC intrinsic layer; Step 6: removing the substrate obtained according to the above steps through a substrate removal process; Step 7: evaporate and photolithograph on the N-type heavily doped semiconductor transmission layer to produce an N-type ohmic electrode, and then evaporate and photolithograph on the P-type heavily doped semiconductor transmission layer to produce a P-type ohmic electrode.

6. The method for manufacturing a diamond-based SiC PIN diode according to claim 5, characterized in that: The step 1 is further specifically as follows: rinse the surface of the SiC epitaxial wafer with deionized water, and then soak it in a heated mixed washing solution for 1 minute to further remove foreign matter on the surface of the SiC epitaxial wafer to form a substrate; the mixed washing solution includes ammonia water, hydrogen peroxide and deionized water.

7. The method for manufacturing a diamond-based SiC PIN diode according to claim 6, characterized in that: The thickness of the N-type doped diamond voltage-enhancing layer is 1.2 to 3 microns, and the thickness of the N-type SiC intrinsic layer is 3 microns.

8. The method for manufacturing a diamond-based SiC PIN diode according to claim 6, characterized in that: The doping concentration of the N-type doped diamond voltage-enhancing layer is 4*10 17 cm -3 .

9. The method for manufacturing a diamond-based SiC PIN diode according to claim 6, characterized in that: The N-type doped diamond voltage-resistant improving layer is N-type diamond.

10. The method for manufacturing a diamond-based SiC PIN diode according to claim 6, characterized in that: The thickness of the N-type heavily doped semiconductor transmission layer is 6 microns.

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