A LDMOS device with double-side superjunction trench gate

Abstract

The present invention relates to an LDMOS device with a double-sided superjunction groove gate, belonging to the field of semiconductor technology. The device is composed of a double-sided superjunction groove gate region and an LDMOS conductive region, and a silicon dioxide isolation layer is used to separate the double-sided superjunction groove gate region and the LDMOS conductive region. The double-sided superjunction groove gate region is composed of a groove gate P+ contact region, a P-type auxiliary depletion region, a drain N-buffer region, a drain N+ region, and a drain P+ region. The LDMOS conductive region is composed of a source P+ region, a source N+ region, a P-body, a drift region, a drain N-buffer region, and a drain N+ region. The present invention uses a double-sided superjunction groove gate technology on a traditional LDMOS device structure, and can greatly reduce the specific on-resistance of the device and increase the transconductance of the device while ensuring a higher breakdown voltage, and ultimately improves the Baliga figure of merit FOM of the device, and breaks the silicon limit.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to an LDMOS device with double-side super-junction groove gates. Background Art

[0002] As the core components of chips such as consumer electronics, industrial control circuits, and drive circuits, power semiconductor devices are the cornerstone and key link for achieving energy conservation and emission reduction. SOI technology can achieve dielectric isolation of power integrated circuits by introducing a dielectric layer into the device. Compared with bulk silicon technology, SOI technology has higher integration, smaller parasitic capacitance, and better isolation performance. SOI technology can improve the reliability of integrated circuits and will become a key technology in the future process of manufacturing high-integration, high-reliability, high-speed, and low-power chips, especially for power integrated circuits. Compared with most other new active devices such as HEMT and HBT, LDMOS devices based on silicon-on-insulator technology have better CMOS process compatibility and convenient integration. They also have high power, high gain, high linearity, high switching characteristics, good isolation performance, superior radiation resistance, and reliability. Therefore, they have attracted widespread attention from industry workers, so the research on SOI LDMOS is of special significance. SOI LDMOS is mainly used in: Smart Power Integrated Circuit (SPIC), Radio Frequency Integrated Circuit (RFIC), and High Voltage Integrated Circuit (HVIC).

[0003] The voltage withstand capability of SOI lateral power devices is determined by the smaller of the lateral breakdown voltage and the longitudinal breakdown voltage. Generally, increasing the lateral length of the device and reducing the doping concentration of the drift region can improve the lateral voltage withstand capability of the device, but at the same time it will increase the on-resistance of the device, thereby increasing the forward conduction loss of the device. However, since the buried oxide layer and the top silicon of the SOI device cannot be too thick, if the thickness of the buried oxide layer and the top silicon is too thick, it will increase the difficulty of the device manufacturing process and aggravate the self-heating phenomenon of the device, as well as heat dissipation problems. Therefore, the buried oxide layer and the top silicon of the SOI device cannot be too thick. When the buried oxide layer and the top silicon of the SOI device are too thin, the longitudinal voltage withstand capability of the device will be reduced, because the buried oxide layer will prevent the depletion region of the device from extending to the substrate, so that the substrate will not withstand the voltage. The main contradiction of this device is the on-resistance R on,sp and breakdown voltage BV: R on,sp ∝BV 2.5Reducing the on-resistance will also reduce the breakdown voltage of the device; increasing the breakdown voltage of the device will also increase the on-resistance of the device. In order to better measure the comprehensive performance indicators of the device, using the Baliga figure of merit to evaluate the device's figure of merit FOM (figure of merit) has become a very important performance indicator, that is, FOM = BV 2 / R on,sp .

[0004] Therefore, in order to resolve this contradictory relationship, a new LDMOS device is urgently needed. Summary of the invention

[0005] In view of this, the object of the present invention is to provide an LDMOS device with double-sided superjunction trench gate, which can significantly reduce the device's specific on-resistance R by using double-sided superjunction trench gate and polysilicon assisted depletion effect while ensuring a high breakdown voltage. on,sp , ultimately improving the device's Baliga figure of merit FOM, thereby reducing the device's conduction loss.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] A LDMOS device with double-side super-junction trench gate mainly includes: source P+ region 1, source N+ region 2, P-body 3, drift region 6, drain N+ region 7, drain N-buffer region 8, drain P+ region 9, P-type auxiliary depletion region 10, trench gate P+ contact region 11 and silicon dioxide isolation layer 12; wherein the source P+ region 1, source N+ region 2, P-body 3, drift region 6, drain N-buffer region 8 and drain N+ region 7 are arranged from left to right to form an LDMOS conductive region. The trench gate P+ contact region 11, P-type auxiliary depletion region 10, drain N-buffer region 8, drain N+ region 7 and drain P+ region 9 are arranged from left to right to form a double-side super-junction trench gate region. The silicon dioxide isolation layer 12 is used to separate the double-sided super junction trench gate region and the LDMOS conductive region. The LDMOS conductive region is located inside the silicon dioxide isolation layer 12 , and the double-sided super junction trench gate region is located outside the silicon dioxide isolation layer 12 .

[0008] The bottom of the device is composed of a buried oxide layer 4 and a substrate 5; the buried oxide layer 4 is located below the double-sided super junction trench gate region and the LDMOS conductive region, and is also located above the substrate 5. The substrate 5 is located below the buried oxide layer 4.

[0009] Preferably, the drift region 6 includes a drift region I 6 - 1 and a drift region II 6 - 2 which are arranged on the left and right; wherein the doping concentration of the drift region I 6 - 1 is greater than the doping concentration of the drift region II 6 - 2.

[0010] Preferably, the P-type auxiliary depletion region 10 includes a P-type auxiliary depletion region I 10 - 1 and a P-type auxiliary depletion region II 10 - 2 arranged left and right; wherein the doping concentration of the P-type auxiliary depletion region I 10 - 1 is less than the doping concentration of the P-type auxiliary depletion region II 10 - 2.

[0011] Preferably, the doping type of the drift region 6 can be changed from N-type to P-type.

[0012] Preferably, the LDMOS device can be changed from N-type to P-type.

[0013] Preferably, the device structure is suitable for a lateral diode or a LIGBT.

[0014] Preferably, the thickness of the silicon dioxide isolation layer 12 can be changed as needed.

[0015] Preferably, the doping concentration of the drain N-buffer region 8 can be changed as needed.

[0016] Preferably, the doping concentration of the P-type auxiliary depletion region 10 can be changed as needed.

[0017] The beneficial effect of the present invention is that: on the basis of the traditional LDMOS device, the present invention introduces a double-sided super-junction groove gate structure outside a drift region, and the silicon dioxide isolation layer separates the double-sided super-junction groove gate region and the LDMOS conductive region. The device is mainly composed of a double-sided super-junction groove gate region and a conductive region, which are respectively located on the outside and inside of the device. When forward conduction occurs, a positive voltage is applied to the groove gate P+ contact region of the double-sided super-junction groove gate region. At this time, the polysilicon P-type auxiliary depletion region of the double-sided super-junction groove gate region forms a reverse-biased PN junction with the drain N-buffer region, so that the voltage on the P-type auxiliary depletion region of the double-sided super-junction groove gate region of the device is almost exactly the same as the voltage on the gate, so that the device generates a high-concentration charge accumulation layer in the drift region, further improving the conductive majority carrier concentration in the drift region, and finally obtaining a very small specific on-resistance R on,sp When turned off, the polysilicon P-type auxiliary depletion region in the double-sided superjunction groove gate region can assist in depleting the drift region, thereby optimizing the electric field distribution in the drift region, and finally the device obtains a higher breakdown voltage BV. Therefore, the present invention solves the contradictory relationship between the specific on-resistance and breakdown voltage of the traditional LDMOS, breaks the silicon limit, greatly improves the Baliga figure of merit FOM of the device, and thus reduces the conduction loss of the device.

[0018] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 is a schematic structural diagram of the LDMOS device of Example 1;

[0021] Figure 2 for Figure 1 Interface diagrams of three different cross sections a, b, and c.

[0022] Figure 3 is a schematic structural diagram of an LDMOS device according to Embodiment 2;

[0023] Figure 4 is a schematic structural diagram of an LDMOS device according to Embodiment 3;

[0024] Figure 5 The distribution diagram of the electric potential of the double-sided super junction trench gate region of the LDMOS device of Example 1 along the Y axis;

[0025] Figure 6 For Example 1, V GS =10V, V DS =1V, the drift region doping concentration is 4.0×10 16 cm -3 The doping concentration of the CON-SJLDMOS and drift region is 4.0×10 16 cm -3 The electron current density distribution in the drift region of the new structure LDMOS device along the Y-axis direction;

[0026] Figure 7 For Example 1, V GS =10V, V DS =1V and Y = 6.0μm, X = 0.1μm, the drift region doping concentration is 4.0×10 16 cm -3 The doping concentration of CON-SJ LDMOS and drift region is 4.0×10 16 cm -3 The electron density distribution in the drift region of the new structure LDMOS device;

[0027] Figure 8For Example 1, V GS =10V, V DS = 0V, the drift region doping concentration is 4.0×10 16 cm -3 The doping concentration of the CON-SJLDMOS and drift region is 4.0×10 16 cm -3 The current density distribution of the new structure LDMOS device along the section a;

[0028] Fig. 9 For Example 1, when V g =10V, V d =1V, the doping concentration in the drift region is 4.0×10 16 cm -3 The doping concentration of the CON-SJLDMOS and drift region is 4.0×10 16 cm -3 In the case of the new structure LDMOS device, the transfer characteristic curves and transconductance comparison diagram of the two devices;

[0029] Fig.10 is a comparison diagram of the relationship between the drain voltage and the drain current of the LDMOS device of Example 1 and the conventional CON-SJ LDMOS device, and when the gate voltage is 6V, 8V, and 10V respectively;

[0030] Fig.11 A comparison diagram of the relationship between the specific on-resistance of the LDMOS device of Example 1 and the traditional CON-SJ LDMOS device as the gate voltage and the thickness of the silicon dioxide isolation layer change;

[0031] Fig.12 1 is a potential distribution diagram of the LDMOS device of Example 1 and the traditional CON-SJ LDMOS device under avalanche breakdown;

[0032] Fig.13 A comparison diagram of the breakdown voltage and specific on-resistance of the LDMOS device of Example 1 and the traditional CON-SJ LDMOS device under different charge compensation effects;

[0033] Fig.14 is a silicon limit comparison diagram of the LDMOS device of Example 1;

[0034] Fig.15 A switching performance comparison diagram of the LDMOS device of Example 1 and a conventional CON-SJ LDMOS device;

[0035] Fig.16 It is a schematic diagram of the main process flow of the LDMOS device of Example 1;

[0036] Figure symbols: 1-source P+ region, 2-source N+ region, 3-P-body, 4-buried oxide layer, 5-substrate, 6-drift region, 7-drain N+ region, 8-drain N-buffer region, 9-drain P+ region, 10-P-type auxiliary depletion region, 11-trench gate P+ contact region, 12-silicon dioxide isolation layer, 6-1-drift region I, 6-2-drift region II, 10-1-P-type auxiliary depletion region I, 10-2-P-type auxiliary depletion region II. DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0038] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0039] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "back" and the like indicate directions or positional relationships, they are based on the directions or positional relationships shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0040] Embodiment 1:

[0041] like Figure 1 and Figure 2As shown, this embodiment designs a double-side super-junction trench gate LDMOS device, which mainly includes a source P+ region 1, a source N+ region 2, a P-body 3, a buried oxide layer 4, a substrate 5, a drift region 6, a drain N+ region 7, a drain N-buffer region 8, a drain P+ region 9, a P-type auxiliary depletion region 10, a trench gate P+ contact region 11 and a silicon dioxide isolation layer 12.

[0042] The silicon dioxide isolation layer 12 separates the double-sided super junction trench gate region and the LDMOS conductive region, the LDMOS conductive region is located inside the silicon dioxide isolation layer 12, and the double-sided super junction trench gate region is located outside the silicon dioxide isolation layer 12. The thickness of the silicon dioxide isolation layer 12 is 0.5 μm.

[0043] The LDMOS conductive region mainly includes the source P+ region 1, the source N+ region 2, the P-body 3, the drift region 6, the drain N-buffer region 8, and the drain N+ region 7; from left to right, the source P+ region 1, the source N+ region 2, the P-body 3, the drift region 6, the drain N-buffer region 8, and the drain N+ region 7.

[0044] The double-sided super junction trench gate region is mainly composed of the trench gate P+ contact region 11, the P-type auxiliary depletion region 10, the drain N-buffer region 8, the drain N+ region 7, and the drain P+ region 9; from left to right are the trench gate P+ contact region 11, the P-type auxiliary depletion region 10, the drain N-buffer region 8, the drain N+ region 7, and the drain P+ region 9.

[0045] The bottom of the device is composed of a buried oxide layer 4 and a substrate 5; the buried oxide layer 4 is located below the double-sided super junction trench gate region and the LDMOS conductive region, and is also located above the substrate 5. The substrate 5 is located below the buried oxide layer 4.

[0046] Embodiment 2:

[0047] like Figure 3 As shown, this embodiment designs a double-side super-junction trench gate LDMOS device, which mainly includes a source P+ region 1, a source N+ region 2, a P-body 3, a buried oxide layer 4, a substrate 5, a drain N+ region 7, a drain N-buffer region 8, a drain P+ region 9, a P-type auxiliary depletion region 10, a trench gate P+ contact region 11 and a silicon dioxide isolation layer 12, a drift region I 6-1, and a drift region II 6-2.

[0048] On the basis of the structure of Example 1, the drift region 6 is divided into two parts: drift region I 6 - 1 and drift region II 6 - 2 , wherein the doping concentration of drift region I 6 - 1 is greater than the doping concentration of drift region II 6 - 2 .

[0049] Embodiment 3:

[0050] like Figure 4As shown, this embodiment designs a double-side super-junction trench gate LDMOS device, which mainly includes a source P+ region 1, a source N+ region 2, a P-body 3, a buried oxide layer 4, a substrate 5, a drift region 6, a drain N+ region 7, a drain N-buffer region 8, a drain P+ region 9, a trench gate P+ contact region 11 and a silicon dioxide isolation layer 12, a P-type auxiliary depletion region I 10-1, and a P-type auxiliary depletion region II 10-2.

[0051] Based on the structure of Example 1, the original P-type auxiliary depletion region 10 is divided into two parts: P-type auxiliary depletion region I 10-1 and P-type auxiliary depletion region II 10-2, wherein the doping concentration of P-type auxiliary depletion region I 10-1 is less than the doping concentration of P-type auxiliary depletion region II 10-2.

[0052] Figure 5 The distribution diagram of the electric potential of the double-sided superjunction trench gate region along the Y axis of the LDMOS device of Example 1. As can be seen from Figure 5, the electric potential of the trench gate P+ contact region and the P-type auxiliary depletion region are substantially equal, and in particular, the electric potential of the P-type auxiliary depletion region is equal to 10V, which enables a large amount of electrons to accumulate in the drift region of the device when the device is turned on, thereby increasing the concentration of conductive carriers and ultimately reducing the device specific on-resistance.

[0053] Figure 6 In Example 1 of the present invention, V GS =10V, V DS =1V, the drift region doping concentration is 4.0×10 16 cm -3 The doping concentration of CON-SJ LDMOS and drift region is 4.0×10 16 cm -3 The electron current density distribution in the drift region of the new structure LDMOS device along the Y-axis direction. Figure 6 It can be seen that the electron density in the drift region of the new structure LDMOS device close to the inner side of the chemical isolation layer is 5.0×10 18 cm -3 , the electron density in the drift region of CON-SJ LDMOS is 4.0×10 16 cm -3 ,Therefore, the electron concentration in the drift region of the new structure LDMOS device is much greater than the electron density in the drift region of the CON-SJ LDMOS.

[0054] Figure 7 In Example 1 of the present invention, V GS =10V, V DS =1V and Y = 6.0μm, X = 0.1μm, the drift region doping concentration is 4.0×10 16 cm -3The doping concentration of CON-SJ LDMOS and drift region is 4.0×10 16 cm -3 The electron density distribution in the drift region of the new structure LDMOS device. Figure 7 It can be seen that the electron density in the drift region of the new structure LDMOS device is much greater than that in the drift region of the CON-SJ LDMOS.

[0055] Figure 8 In Example 1 of the present invention, V GS =10V, V DS = 0V, the drift region doping concentration is 4.0×10 16 cm -3 The doping concentration of CON-SJ LDMOS and drift region is 4.0×10 16 cm -3 The current density distribution of the new structure LDMOS device along the section a. Figure 8 As shown, the electron current density in the drift region of the new structure LDMOS device is much greater than the electron current density in the drift region of the CON-SJ LDMOS.

[0056] Fig. 9 For Example 1 of the present invention, when V g =10V, V d =1V, the doping concentration in the drift region is 4.0×10 16 cm -3 The doping concentration of CON-SJ LDMOS and drift region is 4.0×10 16 cm -3 In the case of the new structure LDMOS device, the transfer characteristic curves and transconductance comparison diagram of the two devices. Fig. 9 It can be seen that the drain current I of the new structure LDMOS DS and the maximum transconductance g m Much larger than CON-SJ LDMOS.

[0057] Fig.10 The new structure LDMOS device provided in Example 1 of the present invention and the traditional CON-SJ LDMOS device, as well as the relationship between the drain voltage and the drain current when the gate voltage is 6V, 8V, and 10V respectively. Fig.10 As shown, the drain current I DS Both are greater than CON-SJ LDMOS. Therefore, the forward conduction performance of the new structure LDMOS device is better than that of CON-SJ LDMOS.

[0058] Fig.11This is a comparison chart of the relationship between the specific on-resistance of the new structure LDMOS device provided in Example 1 of the present invention and the traditional CON-SJ LDMOS device as the gate voltage and the thickness of the silicon dioxide isolation layer change. Fig.11 It can be seen that the specific on-resistance R of the new structure LDMOS device on,sp Much smaller than the traditional CON-SJ LDMOS device; In addition, the specific on-resistance R on,sp It decreases as the thickness of the silicon dioxide isolation layer decreases.

[0059] Fig.12 The potential distribution diagram of the new structure LDMOS device provided in Example 1 of the present invention and the traditional CON-SJ LDMOS device under avalanche breakdown. Fig.12 As shown, although the breakdown voltage of the new structure LDMOS device is slightly lower than that of the traditional CON-SJ LDMOS device, the potential distributions of the two devices are basically the same.

[0060] Fig.13 The comparison diagram of the breakdown voltage and specific on-resistance of the new structure LDMOS device provided in Example 1 of the present invention and the traditional CON-SJ LDMOS device under different charge compensation effects. Fig.13 It can be seen that the breakdown voltage BV of the two devices increases with Q N / Q P First increase and then decrease, when Q N / Q P When the breakdown voltage BV of the two devices reaches the maximum value, the specific on-resistance R on,sp The geometry remains unchanged, and the specific on-resistance R on,sp With Q N / Q P The ratio increases and decreases continuously.

[0061] Fig.14 A comparison diagram of the silicon limit of the new structure LDMOS device provided in Example 1 of the present invention. As can be seen from Figure 14, the new structure LDMOS device successfully breaks the RESURF silicon limit because the new structure LDMOS device well solves the silicon limit contradiction existing in the traditional LDMOS device. Under the same withstand voltage, the new structure LDMOS device has a smaller specific on-resistance, which indicates that the new structure LDMOS device has a better compromise relationship between breakdown voltage and specific on-resistance.

[0062] Fig.15 This is a comparison chart of the switching performance of the new structure LDMOS device provided in Example 1 of the present invention and the traditional CON-SJ LDMOS device. Fig.15It can be seen that the switching performance of the new structure LDMOS device is slightly worse than that of the traditional CON-SJ LDMOS device because the new structure LDMOS device has a larger Miller capacitance.

[0063] The LDMOS device with double-side superjunction trench gates proposed in Embodiment 1 of the present invention is shown as an example. Figure 1 For example, its main process flow is as follows Fig.16 As shown. Its main processes include: ion implantation, diffusion, etching, oxidation, deposition, polycrystalline filling and annealing to form double-sided super junction gate region, LDMOS conductive region, silicon dioxide isolation layer. Finally, metal electrodes are deposited to form source, gate and drain.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A LDMOS device with double-side superjunction trench gate, characterized in that: The device comprises: a source P+ region (1), a source N+ region (2), a P-body (3), a drift region (6), a drain N+ region (7), a drain N-buffer region (8), a drain P+ region (9), a P-type auxiliary depletion region (10), a trench gate P+ contact region (11) and a silicon dioxide isolation layer (12); wherein the source P+ region (1), the source N+ region (2), the P-body (3), the drift region (6), the drain N-buffer region (8) and the drain N+ region (7) are arranged from left to right. The trench gate P+ contact region (11), the P-type auxiliary depletion region (10), the drain N-buffer region (8), the drain N+ region (7) and the drain P+ region (9) are arranged from left to right to form a double-sided super junction trench gate region; the silicon dioxide isolation layer (12) is used to separate the double-sided super junction trench gate region and the LDMOS conductive region, the LDMOS conductive region is located on the inner side of the silicon dioxide isolation layer (12), and the double-sided super junction trench gate region is located on the outer side of the silicon dioxide isolation layer (12).

2. The LDMOS device with double-side superjunction trench gate according to claim 1, characterized in that: The drift region (6) comprises a drift region I (6-1) and a drift region II (6-2) arranged on the left and right; wherein the doping concentration of the drift region I (6-1) is greater than the doping concentration of the drift region II (6-2).

3. The LDMOS device with double-side superjunction trench gate according to claim 1, characterized in that: The P-type auxiliary depletion region (10) comprises a P-type auxiliary depletion region I (10-1) and a P-type auxiliary depletion region II (10-2) arranged on the left and right; wherein the doping concentration of the P-type auxiliary depletion region I (10-1) is lower than the doping concentration of the P-type auxiliary depletion region II (10-2).

4. The LDMOS device with double-side superjunction trench gate according to any one of claims 1 to 3, characterized in that: The device also includes a buried oxide layer (4) located under the double-sided super junction groove gate region and the LDMOS conductive region, and a substrate (5) located under the buried oxide layer (4).

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