Display device

Abstract

A display device is provided. The display device includes a driving controller that provides a first start signal and a second start signal corresponding to an operation mode to a scan driving circuit. The scan driving circuit includes a first scan driving circuit having a plurality of first dummy driving stages and a plurality of first driving stages that sequentially drive scan lines corresponding to a first display area among a plurality of scan lines in synchronization with the first start signal, and a second scan driving circuit having a plurality of second dummy driving stages and a plurality of second driving stages that sequentially drive scan lines corresponding to a second display area among the plurality of scan lines in synchronization with the second start signal. The first dummy driving stages are arranged on a first side surface of a display panel, and the second dummy driving stages are arranged on a second side surface of the display panel.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0086576, filed on July 14, 2020, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] This disclosure relates to display devices, and more specifically, to display devices capable of multi-frequency driving. Background Technology

[0004] In display devices, organic light-emitting diodes (OLEDs) use organic light-emitting diodes (OLEDs) to generate light through the recombination of electrons and holes to display images. Such OLEDs offer advantages such as fast response times and low power consumption.

[0005] Organic light-emitting display devices are provided with pixels connected to data lines and scan lines. A pixel typically includes an organic light-emitting diode (OLED) and a circuit unit for controlling the amount of current flowing into the OLED. The circuit unit controls the amount of current flowing through the OLED from a first driving voltage to a second driving voltage in response to a data signal. At this time, light with a predetermined brightness is generated in response to the amount of current flowing through the OLED.

[0006] Display devices are used in various fields. Therefore, multiple different types of images can be displayed on a single display device. Furthermore, there is research into technologies to reduce the power consumption of display devices that display multiple images. Summary of the Invention

[0007] This disclosure also provides a display device capable of reducing power consumption.

[0008] An embodiment of the present invention provides a display device comprising: a display panel, a first display area and a second display area defined within the display panel, and the display panel including a plurality of pixels each connected to one of a plurality of data lines and at least one of a plurality of scan lines; a data driving circuit for driving the plurality of data lines; a scan driving circuit for driving the plurality of scan lines; and a drive controller for receiving image signals and control signals and controlling the data driving circuit and the scan driving circuit according to an operating mode. In an embodiment, the drive controller provides a first start signal and a second start signal corresponding to an operating mode to the scan driving circuit. The scan driving circuit includes: a first scan driving circuit having a plurality of first dummy driving stages and a plurality of first driving stages, the plurality of first dummy driving stages and the plurality of first driving stages being synchronized with a first start signal to sequentially drive a scan line among a plurality of scan lines corresponding to a first display area; and a second scan driving circuit having a plurality of second dummy driving stages and a plurality of second driving stages, the plurality of second dummy driving stages and the plurality of second driving stages being synchronized with a second start signal to sequentially drive a scan line among a plurality of scan lines corresponding to a second display area, wherein the first dummy driving stages are arranged on a first side surface of the display panel, and the second dummy driving stages are arranged on a second side surface of the display panel.

[0009] In an implementation, the plurality of scan lines may include a first scan line to an nth scan line, a first display area may correspond to the plurality of scan lines from the first scan line to the kth scan line, and a second display area may correspond to the plurality of scan lines from the (k+1)th scan line to the nth scan line, where n may be a natural number and k may be a natural number less than n.

[0010] In one implementation, the first scan driving circuit can sequentially drive from the first first scan line to the kth first scan line, and the second scan driving circuit can sequentially drive from the nth first scan line to the (k+1)th first scan line.

[0011] In an implementation, the plurality of scan lines may further include a first second scan line to an nth second scan line, wherein the plurality of first dummy drive levels may include a first first dummy drive level to a wth first dummy drive level, the first first dummy drive level to a wth first dummy drive level may be driven sequentially from the first first scan line to the wth (where w is a natural number less than k) first scan line, and the plurality of first drive levels may include a first first drive level to a kth first drive level, the first first drive level to a (kw)th first drive level may be driven sequentially from the (w+1)th first scan line to the kth first scan line, and the first first drive level to a kth first drive level may be driven sequentially from the first second scan line to the kth second scan line.

[0012] In the implementation, in response to a clock signal and a carry signal received from the drive controller, each of the plurality of first dummy drive stages outputs a first scan signal and a dummy second scan signal, and each of the first drive stage to the (kW)th drive stage outputs a first scan signal and a second scan signal.

[0013] In an implementation, the dummy second scan signal output from the j-th (where j is natural) first dummy driver stage can be provided as the carry signal of the (j+1)-th first dummy driver stage, and the second scan signal output from the j-th first driver stage can be provided as the carry signal of the (j+1)-th first driver stage.

[0014] In the implementation, the first dummy driver stage can receive a first start signal as a carry signal, and the first dummy driver stage can receive a dummy second scan signal from the wth dummy driver stage as a carry signal.

[0015] In an implementation, the plurality of second dummy driving stages may include a first second dummy driving stage to the wth second dummy driving stage, the first second dummy driving stage to the wth second dummy driving stage may be driven sequentially from the nth first scan line to the (n-w+1)th first scan line, and the plurality of second driving stages may include the (k+1)th second driving stage to the nth second driving stage, the nth second driving stage to the (k+w+1)th second driving stage may be driven sequentially from the (nw)th first scan line to the (k+1)th first scan line, and the nth second driving stage to the (k+1)th second driving stage may be driven sequentially from the nth second scan line to the (k+1)th second scan line.

[0016] In the implementation, in response to the clock signal and carry signal received from the drive controller, each of the plurality of second dummy drive stages outputs a first scan signal and a dummy second scan signal, and each of the nth second drive stage to the (k+w+1)th second drive stage outputs a first scan signal and a second scan signal.

[0017] In the implementation, the dummy second scan signal output from the j-th (where j is a natural number) second dummy driver stage can be provided as the carry signal of the (j+1)-th second dummy driver stage, and the second scan signal output from the j-th second driver stage can be provided as the carry signal of the (j-1)-th second driver stage.

[0018] In the implementation, the first and second dummy driver stages can receive the second start signal as a carry signal, and the nth second driver stage can receive the dummy second scan signal from the wth second dummy driver stage as a carry signal.

[0019] In the implementation, when the operating mode is normal frequency mode, the drive controller can provide the image data signal corresponding to the first display area and the second display area to the data drive circuit in each frame, and when the operating mode is multi-frequency mode, the drive controller can provide the image data signal corresponding to the first display area and the second display area to the data drive circuit during the first frame, and provide the image data signal corresponding to the first display area but not the second display area to the data drive circuit during the second frame.

[0020] In the implementation, when the operating mode is normal frequency mode, the drive controller can sequentially provide the data drive circuit with data signals from the first first scan line to the kth first scan line as image data signals, and can also sequentially provide the data drive circuit with data signals from the nth first scan line to the (k+1)th first scan line as image data signals.

[0021] In the implementation, when the operating mode is normal frequency mode, the frequency of each of the first start signal and the second start signal can be the first drive frequency, and when the operating mode is multi-frequency mode, the frequency of the first start signal can be the first drive frequency, and the frequency of the second start signal can be a second drive frequency lower than the first drive frequency.

[0022] In an embodiment of the present invention, the display device includes: a display panel defining a first non-folding region, a folding region, and a second non-folding region in a plan view, and including a plurality of pixels each connected to one of a plurality of data lines and at least one of a plurality of scan lines; a data driving circuit driving the plurality of data lines; a scan driving circuit driving the plurality of scan lines; and a driving controller receiving image signals and control signals and controlling the data driving circuit and the scan driving circuit according to an operating mode. In an embodiment, the driving controller provides a first start signal and a second start signal corresponding to the operating mode to the scan driving circuit. In an embodiment, the scan driving circuit includes: a first scan driving circuit having a plurality of first dummy driving stages and a plurality of first driving stages that sequentially drive the scan lines corresponding to a first display area among the plurality of scan lines in sync with the first start signal; and a second scan driving circuit having a second dummy driving stage and a plurality of second driving stages that sequentially drive the scan lines corresponding to a second display area among the plurality of scan lines in sync with the second start signal, wherein the first dummy driving stages are arranged on a first side surface of the display panel, and the second dummy driving stages are arranged on a second side surface of the display panel.

[0023] In the implementation, the first non-folded area may correspond to the first display area, the second non-folded area may correspond to the second display area, and the first part of the folded area may correspond to the first display area and the second part of the folded area may correspond to the second display area.

[0024] In an implementation, the plurality of scan lines may include a first scan line to an nth scan line, a first display area may correspond to the plurality of scan lines from the first scan line to the kth scan line, and a second display area may correspond to the plurality of scan lines from the (k+1)th scan line to the nth scan line, where n is a natural number and k is a natural number less than n.

[0025] In one implementation, the first scan driving circuit can sequentially drive from the first first scan line to the kth first scan line, and the second scan driving circuit can sequentially drive from the nth first scan line to the (k+1)th first scan line.

[0026] In the implementation, the plurality of scan lines may further include a first second scan line to an nth second scan line, and the plurality of first dummy drive levels may include a first first dummy drive level to a wth first dummy drive level. The first first dummy drive levels to the wth first dummy drive levels may be driven sequentially from the first first scan line to the wth (where w is a natural number less than k) first scan line, and the plurality of first drive levels may include a first first drive level to a kth first drive level. The first first drive level to the (kw)th first drive level may be driven sequentially from the (w+1)th first scan line to the kth first scan line, and the first first drive level to the kth first drive level may be driven sequentially from the first second scan line to the kth second scan line.

[0027] In the implementation, a plurality of second dummy driving stages can be sequentially driven from the nth first scan line to the (n-w+1)th first scan line, and a plurality of second driving stages can be sequentially driven from the (nw)th first scan line to the (k+1)th first scan line, and sequentially driven from the nth second scan line to the (k+1)th second scan line. Attached Figure Description

[0028] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0029] Figure 1A This is a perspective view of a display device according to an embodiment of the present invention;

[0030] Figure 1B This is a perspective view of a display device according to an embodiment of the present invention;

[0031] Figure 2 It is a view used to describe the operation of a display device in normal frequency mode;

[0032] Figure 3A and Figure 3B It is a view used to describe the operation of a display device in multi-frequency mode;

[0033] Figure 4 This is a block diagram of a display device according to an embodiment of the present invention;

[0034] Figure 5 This is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0035] Figure 6 It is used to describe Figure 5 Timing diagram of pixel operations;

[0036] Figure 7 This is a block diagram of a first scan drive circuit according to an embodiment of the present invention.

[0037] Figure 8 This is a block diagram of a second scan drive circuit according to an embodiment of the present invention.

[0038] Figure 9 This is an example illustrating the operation from the normal frequency mode, respectively. Figure 7 The first scan drive circuit shown in the figure and Figure 8 The signal timing diagram of the first scan signal and the second scan signal output by the second scan drive circuit shown in the figure;

[0039] Figure 10 This is an example illustrating how frequencies can be generated from different sources in multi-frequency mode. Figure 7 The first scan drive circuit shown in the figure and Figure 8 The signal timing diagram of the first scan signal and the second scan signal output by the second scan drive circuit shown in the figure;

[0040] Figure 11 This is an example illustrating the signal timing diagram of the second scan signal in multi-frequency mode;

[0041] Figure 12 This is an example illustrating the signal timing diagram of the image data signal output from the drive controller in normal frequency mode;

[0042] Figure 13 This is an example illustrating the signal timing diagram of the image data signal output from the drive controller in multi-frequency mode;

[0043] Figure 14AThis exemplarily illustrates the signal timing diagrams of the first and second start signals in normal frequency mode; and

[0044] Figures 14B to 14D This is an example illustrating the signal timing diagram of the first and second start signals in a multi-frequency mode. Detailed Implementation

[0045] In this disclosure, when an element (or region, layer, portion, etc.) is referred to as being “on”, “connected to”, or “linked to” another element, it means that the element may be directly arranged on, directly connected to, or directly linked to the other element, or that a third element may be arranged between them.

[0046] The same reference numerals refer to the same elements. Furthermore, in the drawings, the thickness, scale, and dimensions of the elements are exaggerated for the sake of effective description of the technical content. The term "and / or" includes all combinations that can define one or more of the associated configurations.

[0047] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of exemplary embodiments of the inventive concept, and similarly, a second element may be referred to as a first element. Unless the context clearly indicates otherwise, singular terms may include plural forms.

[0048] Additionally, terms such as "below," "down," "above," and "up" are used to describe the relationships of the configurations shown in the accompanying drawings. These terms are used as relative concepts and are described with reference to the directions indicated in the drawings.

[0049] It should be understood that the terms “comprising” or “having” are intended to describe the presence of features, integers, steps, operations, elements, components or combinations thereof stated in this disclosure, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or combinations thereof.

[0050] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It shall also be understood that terms defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly rigid sense unless expressly defined herein.

[0051] In the following description, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0052] Figure 1A This is a perspective view of a display device according to an embodiment of the present invention. Figure 1B This is a perspective view of a display device according to an embodiment of the present invention. Figure 1A The display device DD in its unfolded state is shown, and Figure 1B The display device DD in its folded state is shown.

[0053] exist Figure 1A and Figure 1B In this embodiment, the display device DD is exemplarily shown as a mobile phone. However, the embodiments of the inventive concept are not limited thereto. In another embodiment, the display device DD may include a tablet PC, a smartphone, a personal digital assistant (“PDA”), a portable multimedia player (“PMP”), a game console, a watch-type electronic device, etc. The inventive concept can be applied to large electronic devices such as televisions or outdoor billboards, and also to small and medium-sized electronic devices such as personal computers, laptop computers, kiosks, car navigation system units, and cameras. It should be understood that these are merely exemplary embodiments and can be used in other electronic devices without departing from the inventive concept.

[0054] The display device DD includes a display area DA and a non-display area NDA. The display device DD can display images through the display area DA. When the display device DD is in an unfolded state, the display area DA may include a plane defined by a first direction DR1 and a second direction DR2. The thickness direction of the display device DD may be parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. Therefore, the front (or upper) surface and rear (or lower) surface of the components constituting the display device DD may be defined based on the third direction DR3. The non-display area NDA may be referred to as a border area. As an example, the display area DA may have a quadrilateral shape. The non-display area NDA surrounds the display area DA.

[0055] The display area DA may include a first non-foldable area NFA1, a foldable area FA, and a second non-foldable area NFA2. The foldable area FA may be bent based on a folding axis FX extending along a first direction DR1.

[0056] When the display device DD is folded, the first non-folded region NFA1 and the second non-folded region NFA2 can face each other. Therefore, in the fully folded state, the display area DA is not exposed to the outside, which can be referred to as "inward folding". However, this is only exemplary. The operation of the display device DD of the present invention is not limited to this.

[0057] For example, in another embodiment of the present invention, when the display device DD is folded, the first non-folded region NFA1 and the second non-folded region NFA2 may not face each other and may face outwards relative to each other. Therefore, in the folded state, the first non-folded region NFA1 may be exposed to the outside, which may be referred to as "outward folding".

[0058] In one embodiment, the display device DD may perform only one of the inward folding and outward folding operations. Alternatively, in another embodiment, the display device DD may perform both inward folding and outward folding operations. In this case, the same area of ​​the display device DD, for example, the folding area FA, may be folded inward and outward. Alternatively, in yet another embodiment, some areas of the display device DD may be folded inward, while other areas may be folded outward.

[0059] exist Figure 1A and Figure 1B The illustration exemplarily shows one folded region and two non-folded regions. However, the number of folded and non-folded regions conceived in this invention is not limited thereto. In another embodiment, for example, the display device DD may include more than two non-folded regions and multiple folded regions arranged between adjacent non-folded regions.

[0060] exist Figure 1A and Figure 1B In this embodiment, the folding axis FX is exemplarily shown as a short axis (i.e., a horizontal axis) parallel to the first direction DR1 of the display device DD, but the inventive concept is not limited thereto. In another embodiment, for example, the folding axis FX may extend along the long axis (i.e., the vertical axis) of the display device DD, for example, in a direction parallel to the second direction DR2. In this case, the first non-folding region NFA1, the folding region FA, and the second non-folding region NFA2 may be arranged sequentially along the first direction DR1.

[0061] In the display area DA of the display device DD, multiple display areas DA1 and DA2 can be defined. Figure 1A The example shows two display areas DA1 and DA2. However, the number of display areas DA1 and DA2 in this invention is not limited to this.

[0062] Multiple display areas DA1 and DA2 may include a first display area DA1 and a second display area DA2. For example, the first display area DA1 may be the area displaying a first image IM1, and the second display area DA2 may be the area displaying a second image IM2. However, embodiments of the present invention are not limited thereto. For example, the first image IM1 may be a moving image, and the second image IM2 may be a still image or an image (text information, etc.) that does not change over a relatively long period of time compared to the moving image.

[0063] The display device DD according to the embodiment can operate differently depending on the operating mode. The operating mode may include a normal frequency mode and a multi-frequency mode. In normal frequency mode, the display device DD can drive both the first display area DA1 and the second display area DA2 at a normal frequency. In multi-frequency mode, the display device DD according to the embodiment can drive the first display area DA1, which displays the first image IM1, at a first driving frequency, and can drive the second display area DA2, which displays the second image IM2, at a second driving frequency lower than the normal frequency. In the embodiment, the first driving frequency may be the same as the normal frequency.

[0064] The size of each of the first display area DA1 and the second display area DA2 may be predetermined, but can be changed by the application. In an embodiment, the first display area DA1 may correspond to the first non-folding area NFA1, and the second display area DA2 may correspond to the second non-folding area NFA2. Additionally, a first portion of the folding area FA may correspond to the first display area DA1, and a second portion of the folding area FA may correspond to the second display area DA2.

[0065] In another embodiment, the folded area FA may correspond entirely to either the first display area DA1 or the second display area DA2.

[0066] In another embodiment, the first display area DA1 may correspond to a first portion of the first non-foldable area NFA1, and the second display area DA2 may correspond to a second portion of the first non-foldable area NFA1, the foldable area FA, and the second non-foldable area NFA2. That is, the area of ​​the first display area DA1 may be smaller than the area of ​​the second display area DA2.

[0067] In another embodiment, the first display area DA1 may correspond to a first non-folded area NFA1, a folded area FA, and a first portion of the second non-folded area NFA2, and the second display area DA2 may correspond to a second portion of the second non-folded area NFA2. That is, the area of ​​the second display area DA2 may be smaller than the area of ​​the first display area DA1.

[0068] like Figure 1B As shown, when the folded area FA is in a folded state (i.e., the state where it is folded in the middle), the first display area DA1 can correspond to the first non-folded area NFA1, and the second display area DA2 can correspond to the second non-folded area NFA2.

[0069] exist Figure 1A and Figure 1BIn the illustration, a foldable display device DD is shown as an example of a display device. However, the embodiments of the inventive concept are not limited thereto. In another embodiment, for example, the inventive concept can be applied to unfoldable display devices, display devices having two or more folding regions, rollable display devices, slidable display devices, etc.

[0070] Figure 2 It is a view used to describe the operation of a display device in normal frequency mode.

[0071] First, refer to Figure 2 The first image IM1 displayed in the first display area DA1 and the second image IM2 displayed in the second display area DA2 can both be moving images. Figure 2 The first image IM1 displayed in the first display area DA1 and the second image IM2 displayed in the second display area DA2 shown are merely exemplary. Various images may be displayed in the display device DD.

[0072] In Normal Frequency Mode (NFM), the driving frequency of the first display area DA1 and the second display area DA2 of the display device DD is the normal frequency. For example, the normal frequency could be 60 Hz. In Normal Frequency Mode (NFM), the images from the first frame F1 to the sixtieth frame F60 can be displayed for one second in the first display area DA1 and the second display area DA2 of the display device DD.

[0073] Figure 3A and Figure 3B It is a view used to describe the operation of a display device in multi-frequency mode.

[0074] Reference Figure 3A In multi-frequency mode (MFM), the display device DD can set the driving frequency of the first display area DA1, in which a first image IM1 is displayed as a moving image, to a first driving frequency, and can set the driving frequency of the second display area DA2, in which a second image IM2 is displayed as a still image, to a second driving frequency lower than the first driving frequency. When the normal frequency is 60Hz, the first driving frequency can be 60Hz, and the second driving frequency can be 30Hz.

[0075] In implementation methods, for example, such as Figure 3AAs shown, when the first driving frequency is 60Hz and the second driving frequency is 30Hz in multi-frequency mode MFM, for one second, in the first display area of ​​the display device DD, the first image IM1 can be displayed during each period from the first frame F1 to the sixtieth frame F60, and in the second display area DA2 of the display device DD, the second image IM2 can be displayed only during odd-numbered frames F1, F3, F5, ..., F59. That is, in multi-frequency mode MFM, for one second, the first image IM1 corresponding to 60 frames is displayed in the first display area DA1, and the second image IM2 corresponding to 30 frames is displayed in the second display area DA2. Since no image for the second display area DA2 is generated during the even-numbered frames F2, F4, F6, ..., F60 of multi-frequency mode MFM, power consumption can be reduced.

[0076] Reference Figure 3B In the multi-frequency mode (MFM), the display device DD can set the driving frequency of the first display area DA1, in which a second image IM2, which is displayed as a still image, is a second driving frequency lower than the normal frequency, and can set the driving frequency of the second display area DA2, in which the first image IM1, which is displayed as a moving image, is a first driving frequency higher than the second driving frequency.

[0077] Figure 4 This is a block diagram of a display device according to an embodiment of the present invention.

[0078] Reference Figure 4 The display device DD includes a display panel DP, a drive controller 100, a data drive circuit 200, and a voltage generator 300.

[0079] The drive controller 100 receives the image signal RGB and the control signal CTRL. The drive controller 100 generates an image data signal DATA obtained by converting the data format of the image signal RGB to meet the interface specifications of the data drive circuit 200. The drive controller 100 can output a first scan control signal SCS1, a second scan control signal SCS2, a third scan control signal SCS3, a data control signal DCS, and a light emission control signal ECS.

[0080] The data drive circuit 200 receives the data control signal DCS and the image data signal DATA from the drive controller 100. The data drive circuit 200 converts the image data signal DATA into a data signal and outputs the data signal to multiple data lines DL1 to DLm (described later). Here, m is a natural number. The data signal is an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0081] Voltage generator 300 generates voltages for the operation of display panel DP. In this embodiment, voltage generator 300 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2.

[0082] The display panel DP includes first scan lines GIL1 to GILn, second scan lines GCL1 to GCLn, third scan lines GWL1 to GWLn+1, light emission control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX. Here, n is a natural number. The display panel DP may also include a scan driving circuit and a light emission driving circuit EDC. In an embodiment, the scan driving circuit may include a first scan driving circuit SD1, a second scan driving circuit SD2, and a third scan driving circuit SD3. In an embodiment, the first scan driving circuit SD1, the second scan driving circuit SD2, and the third scan driving circuit SD3 are arranged on the third side surface of the display panel DP (i.e., Figure 4 The light emission drive circuit (EDC) is arranged on the fourth side surface of the display panel DP (i.e., on the left side of the display panel DP). Figure 4 On the right side of the display panel DP. In other words, the first scan drive circuit SD1, the second scan drive circuit SD2, and the third scan drive circuit SD3 can be arranged to face the light emission drive circuit EDC on the first direction DR1, with the pixel PX between them.

[0083] The first scan lines GIL1 to GILk and the second scan lines GCL1 to GCLk extend from the first scan drive circuit SD1 in the first direction DR1. The first scan lines GILk+1 to GILn and the second scan lines GCLk+1 to GCLn extend from the second scan drive circuit SD2 in the first direction DR1. Here, k is a natural number less than n. The third scan lines GWL1 to GWLn+1 extend from the third scan drive circuit SD3 in the first direction DR1. The light emission control lines EML1 to EMLn extend from the light emission drive circuit EDC in the opposite direction to the first direction DR1.

[0084] The first scan lines GIL1 to GILn, the second scan lines GCL1 to GCLn, the third scan lines GWL1 to GWLn+1, and the light emission control lines EML1 to EMLn are arranged spaced apart from each other on the second direction DR2. The data lines DL1 to DLm extend from the data drive circuit 200 in the opposite direction to the second direction DR2 and are arranged spaced apart from each other on the first direction DR1.

[0085] The first scan driving circuit SD1 may correspond to the first display area DA1, and the second scan driving circuit SD2 may correspond to the second display area DA2. For example, the pixel PX in the first display area DA1 is connected to the first scan lines GIL1 to GILk, the second scan lines GCL1 to GCLk, the third scan lines GWL1 to GWLk+1, and the light emission control lines EML1 to EMLk. The pixel PX in the second display area DA2 is connected to the first scan lines GILk+1 to GILn, the second scan lines GCLk+1 to GCLn, the third scan lines GWLk+1 to GWLn+1, and the light emission control lines EMLk+1 to EMLn.

[0086] Each of the multiple pixels PX is electrically connected to one of the first scan lines GIL1 to GILn, one of the second scan lines GCL1 to GCLn, two of the third scan lines GWL1 to GWLn+1, one of the light emission control lines EML1 to EMLn, and one of the data lines DL1 to DLm. Each of the multiple pixels PX can be electrically connected to at least one of the multiple scan lines.

[0087] In an implementation, for example, pixels PX in the first row of the first display area DA1 can be connected to scan lines GIL1, GCL1, GWL1, and GWL2. Pixels PX in the second row can be connected to scan lines GIL2, GCL2, GWL2, and GWL3. Pixels PX in the k-th row of the first display area DA1 can be connected to scan lines GILk, GCLk, GWLk, and GWLk+1.

[0088] In an implementation, for example, pixels PX in the (k+1)th row of the second display area DA2 can be connected to scan lines GILk+1, GCLk+1, GWLk+1, and GWLk+2. Pixels PX in the nth row can be connected to scan lines GILn, GCLn, GWLn, and GWLn+1.

[0089] Each of the multiple pixels in a PX includes an organic light-emitting diode (ED) (see Figure 5 ) and the pixel circuit unit PXC (see) that controls the light emission of the light-emitting diode ED. Figure 5 The pixel circuit unit (PXC) may include multiple transistors and capacitors. At least any one of the first scan drive circuit SD1, the second scan drive circuit SD2, and the third scan drive circuit SD3, as well as the light emission drive circuit EDC, may include transistors formed using the same manufacturing process as that used to form the pixel circuit unit (PXC).

[0090] Each of the multiple pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2.

[0091] The first scan drive circuit SD1 receives a first scan control signal SCS1 from the drive controller 100. In response to the first scan control signal SCS1, the first scan drive circuit SD1 can output a first scan signal to the first scan lines GIL1 to GILk, and can output a second scan signal to the second scan lines GCL1 to GCLk.

[0092] The second scan drive circuit SD2 receives the second scan control signal SCS2 from the drive controller 100. In response to the second scan control signal SCS2, the second scan drive circuit SD2 can output the first scan signal to the first scan lines GILk+1 to GILn, and can output the second scan signal to the second scan lines GCLk+1 to GCLn.

[0093] The third scan drive circuit SD3 receives the third scan control signal SCS3 from the drive controller 100. In response to the third scan control signal SCS3, the third scan drive circuit SD3 outputs the third scan signal to the third scan lines GWL1 to GWLn+1.

[0094] The circuit configuration and operation of the first scan drive circuit SD1 and the second scan drive circuit SD2 will be described in detail later.

[0095] The optical emission driver circuit EDC receives the optical emission control signal ECS from the driver controller 100. In response to the optical emission control signal ECS, the optical emission driver circuit EDC can output the optical emission control signal to the optical emission control lines EML1 to EMLn.

[0096] exist Figure 4 In the diagram, the first scan drive circuit SD1, the second scan drive circuit SD2, and the third scan drive circuit SD3 are shown arranged only on the third side surface of the display panel DP (i.e., Figure 4 The display panel (DP) is located on the left side of the display panel (DP) in the present invention, but the embodiments of the present invention are not limited thereto.

[0097] According to the embodiment, the first scan drive circuit SD1 can respond to the first scan control signal SCS1 to drive the first scan lines GIL1 to GILk and the second scan lines GCL1 to GCLk at any one of the normal frequency, the first drive frequency and the second drive frequency.

[0098] According to the embodiment, the second scan drive circuit SD2 can respond to the second scan control signal SCS2 to drive the first scan lines GILk+1 to GILn and the second scan lines GCLk+1 to GCLn at any one of the normal frequency, the first drive frequency and the second drive frequency.

[0099] According to the embodiment, the third scan drive circuit SD3 can sequentially drive the third scan lines GWL1 to GWLn+1 in response to the third scan control signal SCS3. Although Figure 4 A third scan drive circuit SD3 is shown, but as with the first scan drive circuit SD1 and the second scan drive circuit SD2, two third scan drive circuits SD3 corresponding to the first display area DA1 and the second display area DA2 can be independently configured in another embodiment.

[0100] Figure 5 This is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0101] Figure 5 An example shows the connection to Figure 4 The diagram shows the equivalent circuit diagram of pixel PXij for the following data lines: the i-th data line DL1 to DLm, the j-th first scan line GILj among the first scan lines GIL1 to GILn, the j-th second scan line GCLj among the second scan lines GCL1 to GCLn, the j-th third scan line GWLj and the (j+1)-th third scan line GWLj+1 among the third scan lines GWL1 to GWLn, and the j-th light emission control line EMLj among the light emission control lines EML1 to EMLn. Here, i is a natural number equal to or less than m, and j is a natural number equal to or less than n.

[0102] Figure 4 Each of the plurality of pixels PX shown may have the same as Figure 5 The circuit configuration shown in the equivalent circuit diagram of pixel PXij is the same as that shown in the diagram. In this embodiment, the pixel circuit unit PXC of pixel PXij includes a first transistor T1 to a seventh transistor T7 and a capacitor Cst. Furthermore, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be a P-type transistor having a low-temperature polycrystalline silicon (“LTPS”) semiconductor layer, and each of the third transistor T3 and the fourth transistor T4 can be an N-type transistor with an oxide semiconductor layer. However, the embodiments of the present invention are not limited to this. In another embodiment, at least one of the first transistors T1 to the seventh transistor T7 can be an N-type transistor, and the remaining transistors can be P-type transistors. Moreover, the circuit configuration of the pixel according to the present invention is not limited to... Figure 5 The configuration shown. Figure 5 The pixel circuit unit PXC shown is merely exemplary, and the configuration of the pixel circuit unit PXC can be modified and implemented.

[0103] Reference Figure 5 According to an embodiment, the pixel PXij of the display device DD includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a capacitor Cst, and at least one light-emitting diode ED. In this embodiment, a pixel PXij including one light-emitting diode ED will be described as an example.

[0104] For ease of explanation, the j-th first scan line GILj, the j-th second scan line GCLj, the j-th third scan line GWLj, the (j+1)-th third scan line GWLj+1, and the j-th light emission control line EMLj are respectively referred to as the first scan line GILj, the second scan line GCLj, the third scan line GWLj, the fourth scan line GWLj+1, and the light emission control line EMLj.

[0105] The first scan line GILj, the second scan line GCLj, the third scan line GWLj, and the fourth scan line GWLj+1 can transmit the first scan signal GIj, the second scan signal GCj, the third scan signal GWj, and the fourth scan signal GWj+1, respectively. The first scan signal GIj can be turned on / off as the fourth transistor T4 of the N-type transistor group. The second scan signal GCj can be turned on / off as the third transistor T3 of the N-type transistor group. The third scan signal GWj can be turned on / off as the second transistor T2 of the P-type transistor group. The fourth scan signal GWj+1 can be turned on / off as the seventh transistor T7 of the P-type transistor group.

[0106] The light emission control line EMLj transmits a light emission control signal EMj that controls the light emission of the light-emitting diodes ED included in pixel PXij. The light emission control signal EMj transmitted by the light emission control line EMLj may have a different waveform than the scan signals GIj, GCj, GWj, and GWj+1 transmitted by the first scan line GILj, the second scan line GCLj, the third scan line GWLj, and the fourth scan line GWLj+1. The data line DL1 transmits a data signal Di. The data signal Di may have a waveform different from the input to the drive controller 100 (see...). Figure 4The image signal RGB corresponds to the voltage level. The first driving voltage line VL1, the second driving voltage line VL2, the third driving voltage line VL3, and the fourth driving voltage line VL4 can respectively transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT1, and the second initialization voltage VINT2. The first initialization voltage VINT1 and the second initialization voltage VINT2 can have different voltage levels. In another embodiment, the first initialization voltage VINT1 and the second initialization voltage VINT2 can have the same voltage level.

[0107] The first transistor T1 includes a first electrode connected to the first drive voltage line VL1 via a fifth transistor T5, a second electrode electrically connected to the anode of the light-emitting diode ED via a sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 can receive the data signal Di transmitted via the data line DLi and supply the drive current Id to the light-emitting diode ED according to the switching operation of the second transistor T2.

[0108] The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the third scan line GWLj. The second transistor T2 can be turned on according to the third scan signal GWj received through the third scan line GWLj, so as to transmit the data signal Di transmitted from the data line DLi to the first electrode of the first transistor T1.

[0109] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the second scan line GCLj. The third transistor T3 can be turned on according to the second scan signal GCj received through the second scan line GCLj to connect the gate electrode and the second electrode of the first transistor T1, thereby connecting the first transistor T1 in the form of a diode.

[0110] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third drive voltage line VL3 that transmits the first initialization voltage VINT1, and a gate electrode connected to the first scan line GILj. The fourth transistor T4 can be turned on according to the first scan signal GIj received through the first scan line GILj to transmit the first initialization voltage VINT1 to the gate electrode of the first transistor T1, thereby performing an initialization operation to initialize the voltage of the gate electrode of the first transistor T1.

[0111] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the light emission control line EMLj.

[0112] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting diode ED, and a gate electrode connected to the light emission control line EMLj.

[0113] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light emission control signal EMj received through the light emission control line EMLj, so that the first driving voltage ELVDD can be compensated by the first transistor T1 connected in the form of a diode and transmitted to the light-emitting diode ED.

[0114] The seventh transistor T7 includes a first electrode connected to the fourth drive voltage line VL4, a second electrode connected to the second electrode of the sixth transistor T6, and a gate electrode connected to the fourth scan line GWLj+1. In another embodiment, the first electrode of the seventh transistor T7 may be connected to the third drive voltage line VL3 instead of the fourth drive voltage line VL4.

[0115] As described above, one end of capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end of capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light-emitting diode ED can be connected to the second driving voltage line VL2 for transmitting the second driving voltage ELVSS. The structure of pixel PXij according to the embodiment is not limited to... Figure 5 The structure shown can be modified in various ways, including the number of transistors and capacitors included in a pixel PXij, as well as the connections between them.

[0116] Figure 6 It is used to describe Figure 5 The timing diagram for pixel operations. (Refer to...) Figure 5 and Figure 6 The operation of the display device according to the embodiments will be described.

[0117] Reference Figure 5 and Figure 6 During the initialization period within a frame F, a high-level first scan signal GIj is supplied via the first scan line GILj. In response to the high-level first scan signal GIj, the fourth transistor T4 is turned on, and through the fourth transistor T4, the first initialization voltage VINT1 is transmitted to the gate electrode of the first transistor T1 to initialize the first transistor T1.

[0118] Next, when a high-level second scan signal GCj is supplied via the second scan line GCLj during the data programming and compensation period, the third transistor T3 is turned on. The first transistor T1 is connected in diode form through the turned-on third transistor T3 and is forward biased. The pulse width of each of the first scan signal GIj and the second scan signal GCj can be five horizontal segments 5H. The horizontal segments H are the display panel DP (see...). Figure 4 The time when pixel PX in a row on the first direction DR1 is driven.

[0119] When a low-level third scan signal GWj is supplied through the third scan line GWLj, the second transistor T2 is turned on. Then, a compensation voltage Di-Vth, which is equal to the voltage obtained by subtracting the threshold voltage Vth of the first transistor T1 from the data signal Di, is applied to the gate electrode of the first transistor T1. That is, the gate voltage applied to the gate electrode of the first transistor T1 can be the compensation voltage Di-Vth.

[0120] A first driving voltage ELVDD and a compensation voltage Di-Vth are applied to the two ends of the capacitor Cst, and the capacitor Cst can store a charge corresponding to the voltage difference between the two ends.

[0121] The seventh transistor T7 is turned on by being supplied with a low-level fourth scan signal GWj+1 through the fourth scan line GWLj+1. A portion of the drive current Id (i.e., the bypass current Ibp) can be discharged to the fourth drive voltage line VL4 through the seventh transistor T7.

[0122] If the light-emitting diode ED emits light even when the minimum current of the first transistor T1 used to display a black image flows as the drive current Id, the black image is not displayed correctly. Accordingly, the seventh transistor T7 in the pixel PXij of the embodiment of the present invention can divert a portion of the minimum current of the first transistor T1 as a bypass current Ibp into a current path other than the current path on the side of the organic light-emitting diode. Here, the minimum current of the first transistor T1 refers to the current under the condition that the first transistor T1 is turned off because the gate-source voltage of the first transistor T1 is less than the threshold voltage Vth. In this way, the minimum drive current (e.g., 10 picoamperes (pA) or less) under the condition that the first transistor T1 is turned off is transmitted to the light-emitting diode ED and displayed as an image of black brightness. When the minimum drive current used to display a black image flows, the effect of the bypass transmission of the bypass current Ibp is significant. However, when the large drive current Id used to display an image (such as a normal image or a white image) flows, the effect of the bypass current Ibp is small. Accordingly, when the drive current Id for displaying a black image flows, the light-emitting current Ied of the LED ED, which reduces the amount of bypass current Ibp discharged through the seventh transistor T7, can have a minimum current amount sufficient to reliably display a black image. Consequently, the seventh transistor T7 can be used to achieve an image with correct black brightness, thereby improving contrast. In this embodiment, the bypass signal is the low-level fourth scan signal GWj+1, but embodiments of the present invention are not necessarily limited to this.

[0123] Next, during the light emission period, the light emission control signal EMj supplied from the light emission control line EMLj changes from a high level to a low level. During the light emission period, the fifth transistor T5 and the sixth transistor T6 are turned on by the low-level light emission control signal EMj. Then, a drive current Id is generated corresponding to the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD, and the drive current Id is supplied to the light-emitting diode ED through the sixth transistor T6, so that the light emission current Ied flows in the light-emitting diode ED. During the light emission period, the gate-source voltage of the first transistor T1 is maintained at a value of "(Di-Vth)-ELVDD" through the capacitor Cst, and according to the current-voltage relationship of the first transistor T1, the drive current Id can be expressed as the square of the value obtained by subtracting the threshold voltage Vth from the drive gate-source voltage, which is "(Di-ELVDD"). 2 "Proportional. Accordingly, the drive current Id can be determined independently of the threshold voltage Vth of the first transistor T1."

[0124] Figure 7 This is a block diagram of the first scan drive circuit SD1 according to an embodiment of the present invention.

[0125] Reference Figure 7 The first scan drive circuit SD1 includes first dummy drive stages DST11 to DST15 and first drive stages STA1 to STAk.

[0126] Each of the first drive stages STA1 to STAk from Figure 4 The drive controller 100 shown receives a first scan control signal SCS1. The first scan control signal SCS1 includes a first start signal FLM1, a first clock signal CLK1, and a second clock signal CLK2. Each of the first drive stages STA1 to STAk receives a first voltage VGL and a second voltage VGH. The first voltage VGL and the second voltage VGH can be obtained from... Figure 4 The voltage generator 300 shown is provided.

[0127] In this implementation, the first dummy driver stages DST11 to DST15 output first scan signals GI1 to GI5 and dummy second scan signals DGC11 to DGC15, respectively. The first driver stages STA1 to STAk-5 output first scan signals GI6 to GIk and second scan signals GC1 to GCk-5, respectively. The first driver stages STA1k-4 to STAk output second scan signals GCk-4 to GCk, respectively.

[0128] The first scan signals GI1 to GIk can be provided respectively to Figure 4 The first scan lines GIL1 to GILk shown, and the second scan signals GC1 to GCk can be provided respectively to Figure 4 The second scan lines GCL1 to GCLk are shown in the diagram.

[0129] The first dummy driver stage DST11 can receive a first start signal FLM1 as a first carry signal. Each of the first dummy driver stages DST12 to DST15 can receive a dummy second scan signal output from the previous driver stage as a carry signal. The first driver stage STA1 can receive a dummy second scan signal DGC15 output from the first dummy driver stage DST15 as a carry signal. Each of the first driver stages STA2 to STAk can receive a second scan signal output from the previous driver stage as a carry signal.

[0130] Figure 8 This is a block diagram of the second scan drive circuit SD2 according to an embodiment of the present invention.

[0131] Reference Figure 8 The second scan drive circuit SD2 includes second dummy drive stages DST21 to DST25 and second drive stages STBk+1 to STBn.

[0132] Each of the second drive stages STBk+1 to STBn from Figure 4 The drive controller 100 shown receives a second scan control signal SCS2. The second scan control signal SCS2 includes a second start signal FLM2, a first clock signal CLK1, and a second clock signal CLK2. Each of the second drive stages STBk+1 to STBn receives a first voltage VGL and a second voltage VGH. The first voltage VGL and the second voltage VGH can be obtained from... Figure 4 The voltage generator 300 shown is provided. In an embodiment, Figure 7 The first clock signal CLK1, the second clock signal CLK2, the first voltage VGL, and the second voltage VGH provided to the first dummy drive stages DST11 to DST15 and the first drive stages STA1 to STAk, as shown, can be the same as the first clock signal CLK1, the second clock signal CLK2, the first voltage VGL, and the second voltage VGH provided to the second dummy drive stages DST21 to DST25 and the second drive stages STBk+1 to STBn.

[0133] In the implementation, the second dummy driver stages DST21 to DST25 can respectively output first scan signals GIn to GIn-4 and dummy second scan signals DGC21 to DGC25. The second driver stages STBk+6 to STBn respectively output first scan signals GIk+1 to GIn-5 and second scan signals GCk+6 to GCn. The second driver stages STBk+1 to STBk+5 respectively output second scan signals GCk+1 to GCk+5.

[0134] The first scan signals GIk+1 to GIn can be provided respectively to Figure 4 The first scan lines GILk+1 to GILn shown are provided respectively, and the second scan signals GCk+1 to GCn can be provided to... Figure 4 The second scan lines GCLk+1 to GCLn are shown in the diagram.

[0135] The second dummy driver stage DST21 can receive the second start signal FLM2 as the first carry signal. Each of the second dummy driver stages DST22 to DST25 can receive the dummy second scan signal output from the previous driver stage as the carry signal. The second driver stage STBn can receive the dummy second scan signal DGC25 output from the second dummy driver stage DST25 as the carry signal. Each of the second driver stages STBn-1 to STBk+1 can receive the second scan signal output from the previous driver stage as the carry signal.

[0136] Figure 9 This is an example illustrating the operation from the normal frequency mode, respectively. Figure 7 The first scan drive circuit SD1 shown is Figure 8The timing diagram of the first scan signals GI1 to GIn and the second scan signals GC1 to GCn output by the second scan drive circuit SD2 shown in the figure.

[0137] Reference Figure 7 , Figure 8 and Figure 9 In the normal frequency mode NFM, synchronized with the first start signal FLM1, the first clock signal CLK1 and the second clock signal CLK2, the first scan drive circuit SD1 can sequentially activate the first scan signals GI1 to GIk to a high level, and can sequentially activate the second scan signals GC1 to GCk to a high level.

[0138] In normal frequency mode NFM, synchronized with the second start signal FLM2, the first clock signal CLK1 and the second clock signal CLK2, the second scan drive circuit SD2 can sequentially activate the first scan signals GIn to GIk+1 to high level and can sequentially activate the second scan signals GCn to GCk+1 to high level.

[0139] After the first start signal FLM1 is activated to a high level and then after a first delay time t1, the second start signal FLM2 can be activated to a high level. The first delay time t1 can be determined based on the start position of the second display area DA2 (i.e., the position of the (k+1)th first scan line GILk+1).

[0140] During each period of the first frame F1 and the second frame F2 in the normal frequency mode NFM, the first scan signals GI1 to GIk and GIn to GIk+1 can be sequentially activated to a high level, and the second scan signals GC1 to GCk and GCn to GCk+1 can be sequentially activated. Therefore, as Figure 9 As shown, during each of the first frame F1 and the second frame F2, the first image IM can be displayed in the first display area DA1, and the second image IM can be displayed in the second display area DA2.

[0141] Figure 10 This is an example illustrating how frequencies can be generated from different sources in multi-frequency mode. Figure 7 The first scan drive circuit SD1 shown is Figure 8 The timing diagram of the first scan signals GI1 to GIn and the second scan signals GC1 to GCn output by the second scan drive circuit SD2 shown in the figure.

[0142] Reference Figure 7 , Figure 8 and Figure 10In the multi-frequency mode MFM, synchronized with the first start signal FLM1, the first clock signal CLK1 and the second clock signal CLK2, the first scan drive circuit SD1 can sequentially activate the first scan signals GI1 to GIk to a high level, and can sequentially activate the second scan signals GC1 to GCk to a high level.

[0143] In the multi-frequency mode MFM, synchronized with the second start signal FLM2, the first clock signal CLK1 and the second clock signal CLK2, the second scan drive circuit SD2 can sequentially activate the first scan signals GIn to GIk+1 to a high level, and can sequentially activate the second scan signals GCn to GCk+1 to a high level.

[0144] After the first start signal FLM1 is activated to a high level and then after a first delay time t1, the second start signal FLM2 can be activated to a high level. The first delay time t1 can be determined based on the start position of the second display area DA2 (i.e., the position of the (k+1)th first scan line GILk+1).

[0145] During the first frame F1 of the multi-frequency mode MFM, the first scan signals GI1 to GIk and GIn to GIk+1 can be sequentially activated to a high level, and the second scan signals GC1 to GCk and GCn to GCk+1 can be sequentially activated.

[0146] During the second frame F2 of the multi-frequency mode MFM, the first start signal FLM1 can be activated to a high level, while the second start signal FLM2 may not be activated to a high level. In this case, during the second frame F2, the first scan signals GI1 to GIk and the second scan signals GC1 to GCk are sequentially activated, but the first scan signals GIn to GIk+1 and the second scan signals GCn to GCk+1 remain low. Because the first scan signals GIn to GIk+1 and the second scan signals GCn to GCk+1 remain low, the pixels arranged in the second display area DA2 do not display an image. Since the second scan drive circuit SD2 and the pixels in the second display area DA2 are not working during the second frame F2, power consumption is reduced.

[0147] like Figure 9 and Figure 10 As shown, the pulse width of each of the first scan signals GI1 to GIn and the second scan signals GC1 to GCn can be five horizontal segments 5H. For example, as Figure 6 As shown, after the j-th first scan signal GIj is activated to a high level and then passes through five horizontal segments 5H, the j-th second scan signal GCj can be activated to a high level.

[0148] When using a delay of 5H across five horizontal segments between the j-th first scan signal GIj and the j-th second scan signal GCj, as... Figure 7 and Figure 8 As shown, five first dummy driver levels DST11 to DST15 and five second dummy driver levels DST21 to DST25 are required.

[0149] The first dummy driver stages DST11 to DST15 can be arranged on the first side surface of the display panel DP (e.g., Figure 4 The second dummy driver stages DST21 to DST25 may be arranged on the second side surface of the display panel DP (e.g., on the upper side of the display panel DP), and the second dummy driver stages DST21 to DST25 may be arranged on the second side surface of the display panel DP (e.g., on the upper side of the display panel DP). Figure 4 On the lower side of the display panel DP in the middle. In other words, the first dummy drive stages DST11 to DST15 can be arranged in the second direction DR2, facing the second dummy drive stages DST21 to DST25, with the first drive stages STA1 to STAk and the second drive stages STBk+1 to STBn between them. If the second dummy drive stages DST21 to DST25 are arranged between the first display area DA1 and the second display area DA2, then a dead zone may exist in the folded area FA.

[0150] In an embodiment of the present invention, the second dummy driving levels DST21 to DST25 are arranged on one side of the second display area DA2 (e.g., Figure 1A (The lower side of the second display area DA2) can minimize the dead zone shown in the middle of the display area DA.

[0151] Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 The diagram shows that the pulse width of each of the first scan signals GI1 to GIn and the second scan signals GC1 to GCn is five horizontal segments 5H. However, embodiments of the present invention are not limited to this. In another embodiment, for example, the pulse width of each of the first scan signals GI1 to GIn and the second scan signals GC1 to GCn can be w horizontal segments wH or greater (where w is a natural number). Furthermore, the number of the first dummy drive stages and the number of the second dummy drive stages can vary according to the pulse width of each of the first scan signals GI1 to GIn and the second scan signals GC1 to GCn.

[0152] Figure 11 This is an example illustrating the signal timing diagram of the second scan signal in multi-frequency mode.

[0153] Figure 11 An example is shown when the display device DD (see Figure 4This includes 3840 second scan signals GC1 to GC3840 when there are 3840 second scan lines GCL1 to GCL3840. That is, the number of second scan lines is 3840.

[0154] First display area DA1 (see...) Figure 4 This can correspond to the second scan lines GCL1 to GCL1920, and the second display area DA2 (see...) Figure 4 This can correspond to the second scan lines GCL1921 to GCL3840.

[0155] In multi-frequency mode (MFM), when the second scan lines GCL1 to GCL1920 corresponding to the first display area DA1 are driven at 120Hz, the period of the second scan lines GCL1 to GCL1920 is 8.33 milliseconds (ms).

[0156] In multi-frequency mode (MFM), when the second scan lines GCL1921 to GCL3840 corresponding to the second display area DA2 are driven at 1Hz, the period of the second scan lines GCL1921 to GCL3840 is 1 second (s).

[0157] Figure 12 This is an example illustrating the signal timing diagram of the image data signal DATA output from the drive controller in normal frequency mode.

[0158] Reference Figure 4 and Figure 12 The drive controller 100 provides image data signals DATA to the data drive circuit 200. During a predetermined frame F in the normal frequency mode NFM, the drive controller 100 may sequentially provide data signals D1 to D1920 and D3840 to D1921 to the data drive circuit 200. Each of the data signals D1 to D1920 and D3840 to D1921 is a signal provided to a data line connected to a pixel PX in a row. For example, data signal D1 is a signal provided to data lines DL1 to DLm connected to a pixel PX in the first row. Data signal D1921 is a signal provided to data lines DL1 to DLm connected to a pixel PX in the 1921st row.

[0159] like Figure 11 As shown, since the second scan lines GCL1 to GCL1920 are driven sequentially and then the second scan lines GCL3840 to GCL1921 are driven sequentially, the drive controller 100 can sequentially provide data signals D1 to D1920 to the data drive circuit 200 and then sequentially provide data signals D3840 to D1921 to the data drive circuit 200.

[0160] Figure 13This is an example illustrating the signal timing diagram of the image data signal DATA output from the drive controller in multi-frequency mode.

[0161] Reference Figure 4 and Figure 13 Since the second scan lines GCL1 to GCL1920 are driven sequentially during a predetermined frame F in the multi-frequency mode MFM, the drive controller 100 can sequentially provide data signals D1 to D1920 to the data drive circuit 200. The predetermined frame F of the multi-frequency mode MFM can be... Figure 10 The second frame, F2, is shown in the image.

[0162] Since the second scan lines GCL1921 to GCL3840 remain low during the second frame F2 of the multi-frequency mode MFM, the drive controller 100 does not provide any data signal to the data drive circuit 200.

[0163] Figure 14A This is an example illustrating the signal timing diagram of the first and second start signals in normal frequency mode. Figures 14B to 14D This is an example illustrating the signal timing diagram of the first and second start signals in a multi-frequency mode.

[0164] First, refer to Figure 4 and Figure 14A The display device DD can drive the first display area DA1 and the second display area DA2 at a first driving frequency in normal frequency mode NFM. The first driving frequency can be 120Hz.

[0165] In normal frequency mode NFM, each of the first start signal FLM1 and the second start signal FLM2 is 120Hz, and one period is 8.33ms. After the first start signal FLM1 is activated to a high level and then after a first delay time t1, the second start signal FLM2 can be activated to a high level.

[0166] Reference Figure 4 and Figure 14B In multi-frequency mode (MFM), the display device DD can drive the first display area DA1 with a first driving frequency and drive the second display area DA2 with a second driving frequency. The first driving frequency can be 120Hz and the second driving frequency can be 60Hz.

[0167] In Multi-Frequency Mode (MFM), the first drive frequency of the first start signal FLM1 is 120Hz, and one period is 8.33ms. In the same MFM mode, the second drive frequency of the second start signal FLM2 is 60Hz, and one period is 16.66ms. That is, the first start signal FLM1 can be activated high in every frame. The second start signal FLM2 can be activated high during odd-numbered frames F1, F3, F5, ..., F119, and remains low during even-numbered frames F2, F4, F6, ..., F120.

[0168] Reference Figure 4 and Figure 14C In multi-frequency mode (MFM), the display device DD can drive the first display area DA1 with a first driving frequency and drive the second display area DA2 with a second driving frequency. The first driving frequency can be 120Hz, and the second driving frequency can be 1Hz.

[0169] In Multi-Frequency Mode (MFM), the first drive frequency of the first start signal FLM1 is 120Hz, and one period is 8.33ms. In MFM, the second drive frequency of the second start signal FLM2 is 1Hz, and one period is 1 second (s). That is, the first start signal FLM1 can be activated high in each frame. The second start signal FLM2 can be activated high during the first frame F1 and can remain low during the remaining frames F2 to F120.

[0170] Since the second driving frequency of the second start signal FLM2 corresponding to the second display area DA2 is reduced in the multi-frequency mode MFM, the power consumption of the display device DD can be further reduced.

[0171] Reference Figure 4 and Figure 14D In multi-frequency mode (MFM), the display device DD can drive the first display area DA1 with a second driving frequency, and can drive the second display area DA2 with a first driving frequency. The first driving frequency can be 120Hz, and the second driving frequency can be 1Hz.

[0172] In Multi-Frequency Mode (MFM), the second drive frequency of the first start signal FLM1 is 1 Hz, and one period is 1 second (s). In MFM, the first drive frequency of the second start signal FLM2 is 120 Hz, and one period is 8.33 ms. That is, the second start signal FLM2 can be activated high in every frame. The first start signal FLM1 can be activated high during the first frame F1 and can remain low during the remaining frames F2 to F120.

[0173] When a moving image is displayed in the first display area and a still image is displayed in the second display area, the display device with the above configuration can reduce power consumption by making the driving frequency of the second display area lower than that of the first display area. Specifically, a first scan drive circuit driving the first display area and a second scan drive circuit driving the second display area are independently configured so that the operation of either the first scan drive circuit or the second scan drive circuit can be stopped.

[0174] Although the inventive concept has been described with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as set forth in the appended claims. Furthermore, the embodiments disclosed in the inventive concept are not intended to limit the technical spirit of the inventive concept, and all technical concepts falling within the scope of the appended claims and their equivalents shall be construed as being included within the scope of the inventive concept.

Claims

1. A display device, comprising: The display panel defines a first display area and a second display area and includes a plurality of pixels, each of which is connected to one of a plurality of data lines and at least one of a plurality of scan lines; Data driving circuit, driving the plurality of data lines; The scan driving circuit drives the plurality of scan lines; as well as The drive controller receives image signals and control signals, and controls the data drive circuit and the scan drive circuit according to the operating mode. The drive controller provides a first start signal and a second start signal corresponding to the operating mode to the scan drive circuit, and The first display area corresponds to the first scan line to the kth scan line among the plurality of scan lines. The second display area corresponds to the (k+1)th first scan line to the nth first scan line among the plurality of scan lines, where n is a natural number and k is a natural number less than n. The scanning drive circuit includes: A first scan driving circuit includes a plurality of first dummy driving stages and a plurality of first driving stages, wherein the plurality of first dummy driving stages and the plurality of first driving stages are synchronized with a first start signal to sequentially drive the first first scan line corresponding to the first display area to the kth first scan line; and The second scan driving circuit includes multiple second dummy driving stages and multiple second driving stages, which are synchronized with the second start signal to sequentially drive the nth first scan line to the (k+1)th first scan line corresponding to the second display area. Wherein, the plurality of first dummy driver levels sequentially drive the first first scan line to the w-th first scan line, where w is a natural number less than k, and The plurality of second dummy driving levels sequentially drive the nth first scan line to the (n-w+1)th first scan line.

2. The display device according to claim 1, wherein, The plurality of first dummy driver stages are arranged on the first side surface of the display panel, and the plurality of second dummy driver stages are arranged on the second side surface of the display panel.

3. The display device according to claim 1, wherein, The plurality of scan lines also includes the first second scan line to the nth second scan line. The plurality of first dummy driver levels include a first first dummy driver level to a w-th first dummy driver level, wherein the first first dummy driver level to the w-th first dummy driver level are respectively driven sequentially from the first first scan line to the w-th first scan line, where w is a natural number less than k, and The plurality of first driving stages include a first driving stage to a kth first driving stage, the first driving stage to a (kw)th first driving stage being driven sequentially from a (w+1)th first scan line to the kth first scan line, and the first driving stage to a kth first driving stage being driven sequentially from a first second scan line to a kth second scan line.

4. The display device according to claim 3, wherein, In response to a clock signal and a carry signal received from the drive controller, each of the plurality of first dummy drive stages outputs a first scan signal and a dummy second scan signal, and each of the first first drive stage to the (kW) first drive stage outputs the first scan signal and the second scan signal.

5. The display device according to claim 4, wherein, The dummy second scan signal output from the j-th first dummy driver stage is provided as the carry signal of the (j+1)-th first dummy driver stage, where j is a natural number, and the second scan signal output from the j-th first driver stage is provided as the carry signal of the (j+1)-th first driver stage.

6. The display device according to claim 5, wherein, The first dummy driver stage receives the first start signal as the carry signal, and the first dummy driver stage receives the dummy second scan signal from the wth dummy driver stage as the carry signal.

7. The display device according to claim 3, wherein, The plurality of second dummy drive stages include a first second dummy drive stage to the wth second dummy drive stage, wherein the first second dummy drive stage to the wth second dummy drive stage are sequentially driven from the nth first scan line to the (n-w+1)th first scan line, and the plurality of second drive stages include a (k+1)th second drive stage to the nth second drive stage, wherein the nth second drive stage to the (k+w+1)th second drive stage are sequentially driven from the (nw)th first scan line to the (k+1)th first scan line, and the nth second drive stage to the (k+1)th second drive stage are sequentially driven from the nth second scan line to the (k+1)th second scan line.

8. The display device according to claim 7, wherein, In response to a clock signal and a carry signal received from the drive controller, each of the plurality of second dummy drive stages outputs a first scan signal and a dummy second scan signal, and each of the nth second drive stage to the (k+w+1)th second drive stage outputs the first scan signal and the second scan signal.

9. The display device according to claim 8, wherein, The dummy second scan signal output from the j-th second dummy driver stage is provided as the carry signal of the (j+1)-th second dummy driver stage, where j is a natural number, and the second scan signal output from the j-th second driver stage is provided as the carry signal of the (j-1)-th second driver stage.

10. The display device according to claim 9, wherein, The first and second dummy driver stages receive the second start signal as the carry signal, and the nth second driver stage receives the dummy second scan signal from the wth second dummy driver stage as the carry signal.

11. The display device according to claim 1, wherein, When the operating mode is normal frequency mode, the drive controller provides the image data signal corresponding to the first display area and the second display area to the data drive circuit in each frame, and When the operating mode is multi-frequency mode, the drive controller provides image data signals corresponding to the first display area and the second display area to the data drive circuit during the first frame, and provides image data signals corresponding to the first display area but not the second display area to the data drive circuit during the second frame.

12. The display device according to claim 11, wherein, When the operating mode is the normal frequency mode, the drive controller sequentially provides the data signal corresponding to the first scan line to the data signal corresponding to the kth scan line as the image data signal to the data drive circuit, and sequentially provides the data signal corresponding to the nth scan line to the data signal corresponding to the (k+1)th scan line as the image data signal to the data drive circuit.

13. The display device according to claim 1, wherein, When the operating mode is the normal frequency mode, the frequency of each of the first start signal and the second start signal is the first drive frequency, and When the operating mode is multi-frequency mode, the frequency of the first start signal is the first drive frequency, and the frequency of the second start signal is a second drive frequency lower than the first drive frequency.

14. A display device, comprising: The display panel defines a first non-foldable area, a foldable area, and a second non-foldable area in a plan view, and includes a plurality of pixels, each of which is connected to one of a plurality of data lines and at least one of a plurality of scan lines; Data driving circuit, driving the plurality of data lines; The scan driving circuit drives the plurality of scan lines; as well as The drive controller receives image signals and control signals and controls the data drive circuit and the scan drive circuit according to the operating mode. The drive controller provides a first start signal and a second start signal corresponding to the operating mode to the scan drive circuit. The first non-folded region corresponds to the first scan line to the kth scan line among the plurality of scan lines. The second non-folded region corresponds to the (k+1)th first scan line to the nth first scan line among the plurality of scan lines, where n is a natural number and k is a natural number less than n. The scanning drive circuit includes: A first scan driving circuit includes a plurality of first dummy driving stages and a plurality of first driving stages, wherein the plurality of first dummy driving stages and the plurality of first driving stages are synchronized with a first start signal to sequentially drive the first first scan line corresponding to the first non-folded region to the kth first scan line; and The second scan driving circuit includes multiple second dummy driving stages and multiple second driving stages, which are synchronized with the second start signal to sequentially drive the nth first scan line to the (k+1)th first scan line corresponding to the second non-folded region. Among them, the plurality of first dummy driver levels sequentially drive from the first first scan line to the wth first scan line, where w is a natural number less than k, and The plurality of second dummy driver levels sequentially drive the first scan line from the nth first scan line to the (n-w+1)th first scan line.

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