Semiconductor structure and method for manufacturing the same

Abstract

The present disclosure relates to the field of semiconductor technology, and discloses a semiconductor structure and a preparation method thereof; the semiconductor structure includes a substrate layer, a device layer, and a stress propagation layer; the device layer is located above the substrate layer, the device layer includes a first dielectric layer and a device structure, the first dielectric layer fills the device layer and isolates the device structure; the stress propagation layer is located above the device layer, the stress propagation layer includes a second dielectric layer and a plurality of stress propagation patterns arranged at intervals, the second dielectric layer fills the stress propagation layer and isolates the stress propagation patterns. The plurality of stress propagation patterns can prevent the cutting area from extending to the chip area, thereby reducing the difficulty of cutting and improving the qualified rate of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the semiconductor structure. Background Art

[0002] In the semiconductor manufacturing process, wafers need to be cut into individual chips, and then these chips are made into different semiconductor packaging structures. In the prior art, wafer cutting is not only a key process in the semiconductor packaging process, but also a production bottleneck process in the entire semiconductor packaging process.

[0003] With the development of semiconductor technology, the integration of chips is getting higher and higher, while the corresponding chip size is getting smaller and smaller, the slit width is getting smaller and smaller, and the cutting road is getting narrower and narrower; therefore, compared with the wide cutting road, it becomes more difficult to separate chips.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to overcome the disadvantages of the prior art that it is difficult to cut, and to provide a semiconductor structure that is easier to cut and a method for preparing the semiconductor structure.

[0006] According to one aspect of the present disclosure, there is provided a semiconductor structure, comprising:

[0007] Basal layer;

[0008] A device layer, located above the base layer, the device layer comprising a first dielectric layer and a device structure, the first dielectric layer filling the device layer and isolating the device structure;

[0009] The stress propagation layer is located above the device layer, and includes a second dielectric layer and a plurality of stress propagation patterns arranged at intervals, wherein the second dielectric layer fills the stress propagation layer and isolates the stress propagation patterns.

[0010] In an exemplary embodiment of the present disclosure, the semiconductor structure has a plurality of chip regions, a cutting path is arranged between two adjacent chip regions, and the device layer and the stress propagation layer are at least arranged in the cutting path.

[0011] In an exemplary embodiment of the present disclosure, a plurality of the stress propagation patterns are arranged in an array within the scribe line.

[0012] In an exemplary embodiment of the present disclosure, the stress propagation patterns in one scribe line are arranged in at least two rows along the scribe direction.

[0013] In an exemplary embodiment of the present disclosure, the hardness of the first dielectric layer is smaller than the hardness of the second dielectric layer.

[0014] In an exemplary embodiment of the present disclosure, in a direction parallel to the base layer, the cross-sectional shape of the stress propagation pattern is one or more of a rectangular shape, a circular shape, and an elliptical shape.

[0015] In an exemplary embodiment of the present disclosure, the material of the stress spreading pattern is metal aluminum.

[0016] In an exemplary embodiment of the present disclosure, the material of the first dielectric layer is a low-k dielectric material.

[0017] In an exemplary embodiment of the present disclosure, the device structure includes a test structure.

[0018] According to another aspect of the present disclosure, there is provided a method for preparing a semiconductor structure, comprising:

[0019] Provides a base layer;

[0020] forming a device layer above the base layer, wherein the device layer comprises a first dielectric layer and a device structure, wherein the first dielectric layer fills the device layer and isolates the device structure;

[0021] A stress propagation layer is formed above the device layer. The stress propagation layer includes a second dielectric layer and a plurality of stress propagation patterns arranged at intervals. The second dielectric layer fills the stress propagation layer and isolates the stress propagation patterns.

[0022] In an exemplary embodiment of the present disclosure, the hardness of the first dielectric layer is smaller than the hardness of the second dielectric layer.

[0023] In an exemplary embodiment of the present disclosure, the semiconductor structure has a plurality of chip regions, a cutting path is arranged between two adjacent chip regions, and the device layer and the stress propagation layer are at least formed in the cutting path.

[0024] In an exemplary embodiment of the present disclosure, the preparation method further comprises:

[0025] The semiconductor structure is cut along the cutting path.

[0026] In an exemplary embodiment of the present disclosure, the semiconductor structure is cut along the scribe line by laser or a rotating blade to separate the chip regions.

[0027] In an exemplary embodiment of the present disclosure, the stress propagation patterns are arranged in at least two rows along the cutting direction in one cutting street;

[0028] The cutting of the semiconductor structure along the scribe line includes cutting along a region between two columns of the stress propagation patterns.

[0029] The semiconductor structure disclosed in the present invention has a device layer arranged above the base layer, the device layer includes a first dielectric layer and a device structure, the first dielectric layer fills the device layer and isolates the device structure; a stress propagation layer is arranged above the device layer, the stress propagation layer includes a second dielectric layer and a plurality of stress propagation patterns arranged at intervals, the second dielectric layer fills the stress propagation layer and isolates the stress propagation patterns. Since the plurality of stress propagation patterns are arranged at intervals in the second dielectric layer, stress dispersion can be effectively avoided, thereby ensuring that the cutting stress is concentratedly transferred from the first dielectric layer to the second dielectric layer, thereby ensuring that the chips after cutting are completely separated; at the same time, since the stress propagation patterns are arranged at intervals, the lateral diffusion of stress when cutting the chip is avoided, thereby preventing the cutting area from extending to the chip area, thereby improving the chip cutting yield and ensuring the structural integrity of the chip.

[0030] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0032] Figure 1 It is a structural schematic diagram of a semiconductor structure.

[0033] Figure 2 for Figure 1 The part indicated by I is a local enlarged schematic diagram showing defects during cutting.

[0034] Figure 3 A schematic structural diagram of an exemplary embodiment of a semiconductor structure disclosed herein.

[0035] Figure 4 for Figure 3 Schematic top view of the semiconductor structure in .

[0036] Figure 5 for Figure 4 Schematic diagram of the structure when the semiconductor structure is cut.

[0037] Figure 6 FIG. 4 is a schematic top view of another exemplary embodiment of the semiconductor structure disclosed herein.

[0038] Figure 7 FIG. 4 is a schematic structural diagram of yet another exemplary embodiment of the semiconductor structure disclosed herein.

[0039] Figure 8 The present invention is a schematic block diagram of a process of an exemplary embodiment of a method for preparing a semiconductor structure disclosed in the present invention.

[0040] Description of reference numerals:

[0041] 1. base layer; 11. substrate; 12. storage device;

[0042] 2. device layer; 21. device structure; 211. first device structure; 212. second device structure; 22. first dielectric layer; 221. first sub-dielectric layer; 222. second sub-dielectric layer;

[0043] 3. stress propagation layer; 31. second dielectric layer; 32. stress propagation pattern;

[0044] 4. Chip area; 5. Cutting road; 6. Cutting area; 7. Crack; 8. Semiconductor structure. DETAILED DESCRIPTION

[0045] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0046] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0047] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0048] Reference Figure 1 The semiconductor structure 8, such as a wafer, has a plurality of chip regions 4, and a cutting path 5 is provided between adjacent chip regions 4. The wafer is cut along the cutting path 5 to separate adjacent chips. As the integration of semiconductor devices increases, the width of the cutting path 5 becomes narrower and narrower, resulting in increasing stress on the dielectric layer near the cutting path 5. The cracks 7 generated when the wafer is cut will extend to the adjacent chip regions 4. Figure 2 The defect shown causes the interconnection structure in the chip area 4 to be damaged, the plug layer in the interconnection structure to be broken, the signal transmission channel to be disconnected, causing chip failure, and ultimately causing certain functions of the chip to not work properly or the performance of the chip to fail to meet the design requirements, resulting in a decrease in the cutting yield.

[0049] like Figure 3 As shown, a semiconductor structure is provided in an embodiment of the present disclosure, including: a base layer 1, a device layer 2 and a stress propagation layer 3. The base layer 1 includes a substrate 11 and a memory device 12. In some embodiments, the substrate 11 may be germanium, silicon germanium, gallium arsenide or silicon on insulator. A person skilled in the art may select the material of the substrate 11 as needed, which is not limited here. The memory device 12 includes transistors, resistors, capacitors, inductors, etc. The above-mentioned memory devices 12 can be used to constitute volatile storage (Dram, Sdram, etc.), non-volatile storage (Nand, Nor, Flash, etc.), and a person skilled in the art may form the corresponding type of memory device 12 as needed, which is not limited here.

[0050] The device layer 2 is located above the base layer 1, and the device layer 2 includes a first dielectric layer 22 and a device structure 21, wherein the first dielectric layer 22 fills the device layer 2 and isolates the device structure 21. In some embodiments, the device structure 21 includes a test structure, which may be an alignment mark for alignment, a test pad for testing chip performance, and other device structures 21.

[0051] The stress propagation layer 3 is located above the device layer 2 . The stress propagation layer 3 includes a second dielectric layer 31 and a plurality of stress propagation patterns 32 arranged at intervals. The second dielectric layer 31 fills the stress propagation layer 3 and isolates the stress propagation patterns 32 .

[0052] Specifically, a plurality of stress propagation patterns 32 are arranged on a side of the first dielectric layer 22 away from the base layer 1 , adjacent stress propagation patterns 32 are arranged at intervals, and the second dielectric layer 31 fills the stress propagation layer 3 , isolates the stress propagation patterns 32 , and covers the first dielectric layer 22 .

[0053] Since the multiple stress propagation patterns 32 are arranged at intervals in the second dielectric layer 31, stress dispersion can be effectively avoided, thereby ensuring that the cutting stress is concentratedly transferred from the first dielectric layer 22 to the second dielectric layer 31, thereby ensuring complete chip separation after cutting; at the same time, since the stress propagation patterns 32 are arranged at intervals, lateral diffusion of stress when cutting the chip is avoided, thereby preventing the cutting area 6 from extending to the chip area 4, thereby improving the chip cutting yield and ensuring the structural integrity of the chip.

[0054] In some embodiments, the hardness of the second dielectric layer 31 is greater than that of the first dielectric layer 22, that is, the second dielectric layer 31 is more brittle. When the cutting stress propagates to the second dielectric layer 31, even if the stress decreases at this time, it can ensure that the second dielectric layer 31 is completely cut, thereby improving the cutting yield.

[0055] In some embodiments, the material of the first dielectric layer 22 can be a low-k dielectric material, which is beneficial to reducing the coupling capacitance between the device structures 21. The low-k dielectric material can include doped silicon oxide, organic polymers or porous materials, and can specifically be fluorinated silicate glass (Fluorinated Silicate Glass; FSG), carbon-doped glass (Carbon Doped Glass), organo silicate glass (Organo Silicate Glass; OSG), hydrogen-doped glass (Hydrogen Doped Glass), porous carbon-doped glass, porous silicon dioxide (Silicon Dioxide); the second dielectric layer 31 is a general dielectric material or a high-k dielectric material, such as silicon oxide, silicon nitride, and silicon oxynitride. The hardness of the above materials is greater than that of the low-k dielectric material, so that when the stress diffuses to the second dielectric layer 31, the second dielectric layer 31 is completely cut, and finally the chip is completely separated.

[0056] In some embodiments, reference Figure 4 The arrow in the figure indicates the cutting direction. The semiconductor structure has multiple chip areas 4. A cutting road 5 is arranged between two adjacent chip areas 4. The device layer 2 and the stress propagation layer 3 are at least arranged in the cutting road 5. The semiconductor structure is cut along the cutting road 5.

[0057] In some embodiments, reference Figure 4In one cutting road 5, at least two rows of stress propagation patterns 32 are arranged along the cutting direction, and the multiple stress propagation patterns 32 in the two rows are arranged at intervals, that is, in one cutting road 5, two stress propagation patterns 32 are arranged horizontally at intervals in a direction perpendicular to the cutting direction, and are arranged in an array of 2×N (N is the number of stress propagation patterns 32 along the cutting direction, and N is a positive integer greater than or equal to 2) in the cutting road 5.

[0058] In some embodiments, the semiconductor structure 8 can be cut along the cutting path 5 by laser or a rotating blade to separate adjacent chip regions 4. Figure 5 When cutting the semiconductor structure 8, the laser or rotating blade cuts along the area between the two columns of stress propagation patterns 32. Since the stress propagation patterns 32 are arranged at intervals, the lateral diffusion of stress when cutting the semiconductor structure 8 is avoided, and the cutting area 6 is prevented from extending to the chip area 4, thereby improving the chip cutting yield and ensuring the structural integrity of the chip.

[0059] In some embodiments, the stress propagation patterns 32 may be staggered, for example, the stress propagation patterns 32 in one column may be arranged opposite to the gap between two adjacent stress propagation patterns 32 in another column, so as to further improve the degree of blocking the stress.

[0060] In some embodiments, reference Figure 6 , three, four or more rows of stress propagation patterns 32 may be arranged along the cutting direction in one cutting street 5. Specifically, in one cutting street 5, a plurality of stress propagation patterns 32 may be arranged in an array of 3×N, 4×N or M×N, where N is the number of stress propagation patterns 32 along the cutting direction, and N is a positive integer greater than or equal to 2. In the above array arrangement, three, four or more rows of stress propagation patterns 32 may also be mutually staggered or partially staggered in one cutting street 5, and the above arrangement methods all fall within the scope of protection of the present disclosure.

[0061] In some embodiments, the number of columns of the stress propagation pattern 32 in different scribe lines 5 of the same semiconductor structure 8 may also be different, which is specifically reflected in the difference in size. When the size of the stress propagation pattern 32 is small, the number of corresponding arrangement arrays may be increased. In addition, according to the different settings of the chip area 4, the width of the scribe line 5 may also be different, so the number of columns of the stress propagation pattern 32 that can be set may also be different.

[0062] In some embodiments, the stress propagation pattern 32 may be provided not only in the dicing street 5, but also in the chip region 4. Specifically, a corresponding area may be reserved in the chip region 4. For example, when the dicing street 5 is very narrow, a blank area may be reserved at the edge of the chip region 4. By forming the stress propagation pattern 32 in the blank area, the stress generated during dicing may be prevented from extending to the chip region 4, thereby protecting the chip region 4.

[0063] In some embodiments, reference Figure 3 As shown, the device structure 21 may further include a first device structure 211 and a second device structure 212 , and the first dielectric layer 22 may include a first sub-dielectric layer 221 and a second sub-dielectric layer 222 .

[0064] Specifically, a plurality of first device structures 211 are formed at intervals above the base layer 1. A first sub-dielectric layer 221 fills the first device structures 211 and covers the base layer 1; a plurality of second device structures 212 are formed at intervals above the first sub-dielectric layer 221, and a second sub-dielectric layer 222 fills the second device structures 212 and covers the first sub-dielectric layer 221.

[0065] In some embodiments, a third device structure may be provided as required, and a dielectric layer may be filled accordingly, which is not limited here.

[0066] In some embodiments, reference Figure 7 As shown, the device layer 2 may also only include the first sub-dielectric layer 221 and the first device structure 211 , and there is no limit to the number thereof.

[0067] In some embodiments, reference Figure 4-6 As shown, in the direction parallel to the substrate layer 1, the cross-sectional shape of the stress propagation pattern 32 can be one or more of a rectangle, a circle, an ellipse, and a trapezoid. In addition, the stress propagation layer 3 of a semiconductor structure 8 can also include multiple first stress propagation patterns and multiple second stress propagation patterns. In the direction parallel to the substrate layer 1, the cross-sectional shape of the first stress propagation pattern is a circle, and the cross-sectional shape of the second stress propagation pattern is an ellipse, that is, the first stress propagation pattern and the second stress propagation pattern can be different; of course, a third stress propagation pattern can also be included. In the direction parallel to the substrate layer 1, the cross-sectional shape of the third stress propagation pattern can be a trapezoid. The cross-sectional shape of the stress propagation pattern 32 can also be other shapes, which will not be repeated here.

[0068] In some embodiments, the material of the stress propagation pattern 32 may be metal aluminum, or metal copper, tungsten, etc. The above materials are compatible with existing processes, that is, the stress propagation pattern 32 may be formed simultaneously when the metal wiring layer is formed.

[0069] Based on the same inventive concept, the exemplary embodiment of the present disclosure also provides a method for preparing a semiconductor structure, referring to Figure 8 A schematic flow chart of an exemplary embodiment of a method for preparing a semiconductor structure of the present disclosure is provided. The method for preparing a semiconductor structure may include the following steps:

[0070] Step S10, providing a base layer 1.

[0071] Step S20 , forming a device layer 2 on the base layer 1 , wherein the device layer 2 includes a first dielectric layer 22 and a device structure 21 , wherein the first dielectric layer 22 fills the device layer 2 and isolates the device structure 21 .

[0072] Step S30 , forming a stress propagation layer 3 on the device layer 2 , wherein the stress propagation layer 3 includes a second dielectric layer 31 and a plurality of stress propagation patterns 32 arranged at intervals, wherein the second dielectric layer 31 fills the stress propagation layer 3 and isolates the stress propagation patterns 32 .

[0073] The following is a detailed description of each step of the method for preparing the semiconductor structure.

[0074] Step S10, providing a base layer 1.

[0075] In some embodiments, the base layer 1 includes a substrate 11 and a memory device 12. Those skilled in the art can select the materials of the substrate 11 and the memory device 12 as needed, which have been described in detail in the aforementioned semiconductor structure and are not limited here.

[0076] Step S20 , forming a device layer 2 on the base layer 1 , wherein the device layer 2 includes a first dielectric layer 22 and a device structure 21 , wherein the first dielectric layer 22 fills the device layer 2 and isolates the device structure 21 .

[0077] In some embodiments, a first conductive material layer is formed on the base layer 1 by deposition or electroplating, and the first conductive material layer is patterned to form spaced first device structures 211 , which expose the base layer 1 .

[0078] A first sub-dielectric layer 221 is deposited above the first device structure 211 and the base layer 1 to cover the first device structure 211 and the base layer 1 , and the first sub-dielectric layer 221 is ground to smooth the upper surface of the first sub-dielectric layer 221 .

[0079] A second conductive material layer is formed on the first sub-dielectric layer 221 by deposition or electroplating, and the second conductive material layer is patterned to form spaced second device structures 212 . The spaced second device structures 212 expose the first sub-dielectric layer 221 .

[0080] A second sub-dielectric layer 222 is deposited over the second device structure 212 and the first sub-dielectric layer 221 to cover the first sub-dielectric layer 221 and the second device structure 212 . The second sub-dielectric layer 222 is ground to smooth the upper surface of the second sub-dielectric layer 222 .

[0081] The first sub-dielectric layer 221 and the second sub-dielectric layer 222 together form the first dielectric layer 22 , and the first device structure 211 and the second device structure 212 together constitute the device structure 21 .

[0082] Reference Figure 7 As shown, the device layer 2 may also only include the first sub-dielectric layer 221 and the first device structure 211 , and there is no limit to the number thereof.

[0083] Step S30 , forming a stress propagation layer 3 on the device layer 2 , wherein the stress propagation layer 3 includes a second dielectric layer 31 and a plurality of stress propagation patterns 32 arranged at intervals, wherein the second dielectric layer 31 fills the stress propagation layer 3 and isolates the stress propagation patterns 32 .

[0084] In some embodiments, a stress propagation material layer is formed on the first dielectric layer 22 by deposition or electroplating, and the stress propagation material layer is patterned to form a plurality of stress propagation patterns 32 disposed at intervals, and the stress propagation patterns 32 disposed at intervals expose the first dielectric layer 22 .

[0085] A second dielectric layer 31 is deposited on the plurality of stress propagation patterns 32 disposed at intervals and the first dielectric layer 22 , and the second dielectric layer 31 covers the plurality of stress propagation patterns 32 disposed at intervals and the first dielectric layer 22 .

[0086] It should be noted that the deposition processes involved in the above processes may specifically include plasma vapor deposition (PVD), chemical vapor deposition (CVD), and electroplating. The grinding process may include chemical mechanical grinding (CMP). The patterning process may be achieved by photolithography, wet etching, dry etching, etc., and the mask layer used in the patterning process may include a spin-on hard mask, a photoresist, etc. The above processes all adopt existing processes and will not be repeated here.

[0087] In some embodiments, the hardness of the first dielectric layer 22 is less than the hardness of the second dielectric layer 31. The specific materials of the first dielectric layer 22 and the second dielectric layer 31 have been described in detail above, and therefore, will not be described again here.

[0088] In some embodiments, the semiconductor structure 8 has a plurality of chip regions 4, a scribe line 5 is provided between two adjacent chip regions 4, and the device layer 2 and the stress propagation layer 3 are at least formed in the scribe line 5. The specific arrangement of the stress propagation pattern 32 has been described in detail above and will not be repeated here.

[0089] In some embodiments, the semiconductor structure 8 can be cut along the dicing path 5 to form a plurality of chips. Specifically, the semiconductor structure can be cut along the dicing path 5 by laser or a rotating blade to separate the chip region 4. The rotating blade cutting can include mechanical sawing, scribing and then breaking. The cut chips are picked out from the dicing tape by a chip selection device (such as a chip bonder or a chip sorter) to form separate chips.

[0090] In some embodiments, the stress propagation patterns 32 are arranged in two rows along the cutting direction in one scribe line 5 , and the laser or the rotating blade cuts along the area between the two rows of stress propagation patterns 32 .

[0091] In addition, when the stress propagation patterns 32 in a cutting road 5 are arranged in three columns along the cutting direction, the laser or rotating blade can cut along the middle column of stress propagation patterns 32, or along any one of the two gaps between the three columns of stress propagation patterns 32.

[0092] After the dicing process, the individual chips are packaged into packages for manufacturing electronic devices such as computers. The chips are integrated into lead-frame packages, directly placed on the substrate of a personal computer baseboard, or packaged using solder bumping technology.

[0093] It should be noted that, although the steps of the method for preparing a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0094] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: basal layer; A device layer, located above the base layer, the device layer comprising a first dielectric layer and a device structure, the first dielectric layer filling the device layer and isolating the device structure; A stress propagation layer, located above the device layer, the stress propagation layer comprising a second dielectric layer and a plurality of stress propagation patterns arranged at intervals, the second dielectric layer filling the stress propagation layer and isolating the stress propagation patterns; The hardness of the first dielectric layer is smaller than the hardness of the second dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure has a plurality of chip regions, a cutting path is arranged between two adjacent chip regions, and the device layer and the stress propagation layer are at least arranged in the cutting path.

3. The semiconductor structure according to claim 2, characterized in that: A plurality of the stress propagation patterns are arranged in an array within the scribe line.

4. The semiconductor structure according to claim 2, characterized in that: The stress propagation patterns in one scribe line are arranged in at least two rows along a scribe direction.

5. The semiconductor structure according to claim 1, characterized in that: In a direction parallel to the base layer, the cross-sectional shape of the stress propagation pattern is one or more of a rectangular shape, a circular shape, and an elliptical shape.

6. The semiconductor structure according to claim 1, characterized in that The material of the stress propagation pattern is metal aluminum.

7. The semiconductor structure according to claim 1, characterized in that: The material of the first dielectric layer is a low-k dielectric material.

8. The semiconductor structure according to claim 1, characterized in that: The device structure includes a test structure.

9. A method for preparing a semiconductor structure, characterized in that: include: Provides a base layer; forming a device layer above the base layer, wherein the device layer comprises a first dielectric layer and a device structure, wherein the first dielectric layer fills the device layer and isolates the device structure; forming a stress propagation layer above the device layer, wherein the stress propagation layer comprises a second dielectric layer and a plurality of stress propagation patterns arranged at intervals, wherein the second dielectric layer fills the stress propagation layer and isolates the stress propagation patterns; The hardness of the first dielectric layer is smaller than the hardness of the second dielectric layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The semiconductor structure has a plurality of chip regions, a cutting path is arranged between two adjacent chip regions, and the device layer and the stress propagation layer are at least formed in the cutting path.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: The preparation method further comprises: The semiconductor structure is cut along the cutting path.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that: The semiconductor structure is cut along the scribe lines by laser or a rotating blade to separate the chip regions.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that: The stress propagation patterns in one cutting street are arranged in at least two rows along the cutting direction; The cutting of the semiconductor structure along the scribe line includes cutting along a region between two columns of the stress propagation patterns.

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