Semiconductor package

Abstract

A semiconductor package is disclosed that includes a base film having a first surface and a second surface opposite the first surface; a plurality of input / output lines on the first surface of the base film; a semiconductor chip disposed on the first surface of the base film and connected to the input / output lines, and including a central portion and end portions on opposite sides of the central portion; and a heat dissipation pattern on the second surface of the base film. The heat dissipation pattern corresponds to the semiconductor chip and has a plurality of openings corresponding to and vertically overlapping the end portions of the semiconductor chip.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0086278, filed on July 13, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor packages, and more specifically, to semiconductor packages in which a semiconductor chip is attached to a film. Background Technology

[0004] To address the recent trend towards smaller, thinner, and lighter electronic products, chip-on-film (COF) packaging technology has been developed to utilize flexible film substrates. According to COF packaging technology, semiconductor chips can be directly flip-chip bonded to the film substrate and coupled to external circuitry via short leads. COF packages can be applied to portable terminal devices such as cellular phones, personal digital assistants (PDAs), laptops, or display panels. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide semiconductor packages with improved reliability.

[0006] The purpose of this invention is not limited to the benefits mentioned herein, and other purposes not mentioned herein will be clearly understood by those skilled in the art from the following description.

[0007] According to some exemplary embodiments of the present invention, a semiconductor package may include: a substrate film having a first surface and a second surface opposite to the first surface; a plurality of input / output lines located on the first surface of the substrate film; a semiconductor chip located on the first surface of the substrate film and connected to the input / output lines, the semiconductor chip including a central portion and ends located on opposite sides of the central portion; and a heat dissipation pattern located on the second surface of the substrate film, the heat dissipation pattern corresponding to the semiconductor chip and having a plurality of openings corresponding to the ends of the semiconductor chip and perpendicularly overlapping the ends of the semiconductor chip.

[0008] According to some exemplary embodiments of the present invention, a semiconductor package may include: a substrate film having a first surface and a second surface opposite to the first surface; a semiconductor chip located on the first surface of the substrate film, the semiconductor chip having a length in a first direction and a width in a second direction perpendicular to the first direction, the width being less than the length; and a heat dissipation pattern located on the second surface of the substrate film. The semiconductor chip may include: a plurality of first chip pads adjacent to a first edge of the semiconductor chip parallel to the second direction; and a plurality of second chip pads adjacent to a second edge of the semiconductor chip opposite to the first edge. The heat dissipation pattern may have: a first opening perpendicularly overlapping the first chip pads of the semiconductor chip; and a second opening perpendicularly overlapping the second chip pads of the semiconductor chip. Both the first and second openings may have an opening length in the second direction. The opening length may be greater than the width of the semiconductor chip.

[0009] According to some exemplary embodiments of the present invention, a semiconductor package may include: a substrate film having a first surface and a second surface opposite to the first surface; a plurality of input / output lines located on the first surface of the substrate film; a semiconductor chip located on the first surface of the substrate film and connected to the input / output lines, the semiconductor chip including: a first edge and a second edge opposite to each other; a third edge and a fourth edge perpendicular to the first edge and the second edge and opposite to each other, the first edge and the second edge being longer than the third edge and the fourth edge; and a heat sink located on the second surface of the substrate film, the heat sink corresponding to the semiconductor chip. The semiconductor chip may include: a plurality of first chip pads arranged adjacent to the first edge and the second edge; and a plurality of second chip pads arranged adjacent to the third edge and the fourth edge. The heat sink may have a first opening and a second opening, the first opening and the second opening partially exposing the substrate film. The first opening may perpendicularly overlap with the second chip pad adjacent to the third edge. The second opening may overlap perpendicularly with the second chip pad adjacent to the fourth edge.

[0010] Details of other example embodiments are included in the specification and drawings. Attached Figure Description

[0011] Figure 1A top view is shown illustrating some example embodiments of a semiconductor package according to a concept of the present invention.

[0012] Figure 2A It shows along Figure 1 The cross-sectional view taken by line I-I' shows a semiconductor package according to some exemplary embodiments of the present invention.

[0013] Figure 2B It shows along Figure 1 The cross-sectional view taken by line II-II' shows a semiconductor package according to some exemplary embodiments of the concept of the present invention.

[0014] Figure 3 A top view showing a heat dissipation pattern of a semiconductor package according to some example embodiments of the concept of the present invention is shown.

[0015] Figure 4 , Figure 5 and Figure 6 It shows along Figure 1 The cross-sectional view taken by line I-I' shows a semiconductor package according to some exemplary embodiments of the present invention.

[0016] Figure 7 A top view is shown illustrating some example embodiments of a semiconductor package according to a concept of the present invention.

[0017] Figure 8 It shows along Figure 7 The cross-sectional view taken from line III-III'.

[0018] Figures 9 to 16 A top view is shown illustrating some example embodiments of a semiconductor package according to a concept of the present invention.

[0019] Figure 17 A perspective view of a display device including a semiconductor package, illustrating some example embodiments of a concept according to the present invention, is shown. Detailed Implementation

[0020] Semiconductor packages based on some exemplary embodiments of the present invention will be discussed in conjunction with the accompanying drawings.

[0021] Figure 1 A top view is shown illustrating some example embodiments of a semiconductor package according to a concept of the present invention. Figure 2A It shows along Figure 1 The cross-sectional view taken by line I-I' shows a semiconductor package according to some exemplary embodiments of the present invention. Figure 2B It shows along Figure 1The cross-sectional view taken by line II-II' shows a semiconductor package according to some exemplary embodiments of the concept of the present invention. Figure 3 A top view showing a heat dissipation pattern of a semiconductor package according to some example embodiments of the concept of the present invention is shown.

[0022] Reference Figure 1 , Figure 2A and Figure 2B The semiconductor package 100 may include a substrate film 110, input / output lines 120a and 120b, a semiconductor chip 130, a connection terminal 160, and a heat dissipation pattern 140.

[0023] The substrate film 110 may be an electrically insulating material (e.g., polyimide) having excellent durability and a low coefficient of thermal expansion (CTE), or a flexible film formed from an electrically insulating material (e.g., polyimide) having excellent durability and a low coefficient of thermal expansion (CTE). Alternatively, the substrate film 110 may include epoxy resin, acrylic resin, polyether nitrile resin, polyethersulfone resin, polyethylene terephthalate resin, polyethylene naphthalate resin, or any suitable synthetic resin.

[0024] The substrate film 110 may include guide holes 111 spaced apart from each other at regular intervals on opposite edges of the substrate film 110. The guide holes 111 may allow a winding reel (not shown) to wind the substrate film 110 onto or release the substrate film 110 from the reel.

[0025] The substrate film 110 may have a first surface 110a and a second surface 110b opposite to the first surface 110a. Input / output lines 120a and 120b may be disposed on the first surface 110a of the substrate film 110. Input / output lines 120a and 120b may comprise, for example, aluminum or copper. Input / output lines 120a and 120b may be formed, for example, by casting, lamination, or electroplating. Input / output lines 120a and 120b may be disposed only on the first surface 110a of the substrate film 110, or on both the first surface 110a and the second surface 110b of the substrate film 110. When input / output lines 120a and 120b are disposed on both the first surface 110a and the second surface 110b of the substrate film 110, one or more conductive paths (not shown) may be formed to penetrate the substrate film 110.

[0026] In one embodiment, input / output lines 120a are all input lines (which can be specifically described as input line 120a), and input / output lines 120b are all output lines (which can be specifically described as output line 120b). Regarding the semiconductor chip 130, the input lines 120a may extend in a direction opposite to the extension direction of the output lines 120b. For example, the input lines 120a may extend toward a first side or first edge of the semiconductor chip 130, while the output lines 120b may extend toward a second side or second edge of the semiconductor chip 130 opposite to the first side or first edge. The input lines 120a may be connected to a printed circuit board, and the output lines 120b may be connected to a display panel. The input lines 120a may provide the semiconductor chip 130 with signal voltages transmitted from the printed circuit board, and the output lines 120b may provide the display panel with image signals generated in the semiconductor chip 130.

[0027] The semiconductor chip 130 can be mounted on the first surface 110a of the substrate film 110. The semiconductor chip 130 can be a rectangular shape having a major axis and a minor axis. For example, the semiconductor chip 130 can include a first edge E1 and a second edge E2 that are opposite each other and parallel to the major axis, and can also include a third edge E3 and a fourth edge E4 that are opposite each other and perpendicular to the first edge E1 and the second edge E2. The third edge E3 and the fourth edge E4 can be parallel to the minor axis.

[0028] Semiconductor chip 130 may have a first length L1 in a first direction D1 (or the major axis direction) and a first width W1 in a second direction D2 (or the minor axis direction) perpendicular to the first direction D1. The first width W1 may be smaller than the first length L1. For example, semiconductor chip 130 may be configured such that the first length L1 in the first direction D1 (or the major axis direction) may be approximately 5 to 15 times the first width W1 in the second direction D2 (or the minor axis direction); however, in some embodiments, the first length L1 may be greater than 15 times the first width W1. For example, the first length L1 of semiconductor chip 130 may have a value in the first direction D1 ranging from approximately 15,000 μm to approximately 17,000 μm, and the first width W1 of semiconductor chip 130 may have a value in the second direction D2 ranging from approximately 900 μm to approximately 1,500 μm. Terms such as “about” or “approximately” can reflect a quantity, size, orientation, or layout that varies only in a relatively small way and / or in a way that does not significantly alter the operation, function, or structure of certain components. For example, a range of “about 0.1 to about 1” can encompass a range such as a deviation of 0%-5% from about 0.1 to about 0%-5% from about 1, especially when such deviation maintains the same effect as the range listed.

[0029] Semiconductor chip 130 may include an integrated circuit formed on a wafer and may include chip pads disposed on its bottom surface. The chip pads of semiconductor chip 130 may include a first chip pad 131 adjacent to a first edge E1, a second chip pad 132 adjacent to a second edge E2, a third chip pad 133 adjacent to a third edge E3, and a fourth chip pad 134 adjacent to a fourth edge E4. The first chip pad 131 may be arranged symmetrically with respect to a line extending in a first direction D1 along the center of semiconductor chip 130 in a second direction D2, and the third chip pad 133 may be arranged symmetrically with respect to a line extending in a second direction D2 along the center of semiconductor chip 130 in the first direction D1.

[0030] Semiconductor chip 130 may include a central portion and opposing ends located on opposite sides of the central portion. First chip pads 131 and second chip pads 132 may be disposed on the central portion of semiconductor chip 130, and third chip pads 133 and fourth chip pads 134 may be disposed on opposing ends of semiconductor chip 130. For example, in a first direction D1, first chip pads 131 and second chip pads 132 may be disposed inside semiconductor chip 130, and in the same first direction D1, third chip pads 133 and fourth chip pads 134 may be disposed on opposing ends located outside semiconductor chip 130. First chip pads 131 may include a plurality of chip pads (e.g., three or more chip pads) aligned in a row extending along the first direction D1, and second chip pads 132 may also include a plurality of chip pads (e.g., three or more chip pads) aligned in a row extending along the first direction D1. The third chip pad 133 may include a plurality of chip pads (e.g., three or more chip pads) aligned in rows extending along the second direction D2, and the fourth chip pad 134 may also include a plurality of chip pads (e.g., three or more chip pads) aligned in rows extending along the second direction D2. Each row of chip pads extending in the first direction D1 may include more chip pads than each row of chip pads extending in the second direction D2 (e.g., between approximately twice the number of chip pads and approximately eight times the number of chip pads). The first chip pad 131, the second chip pad 132, the third chip pad 133, and the fourth chip pad 134 of the semiconductor chip 130 may be connected to corresponding input / output lines 120a and 120b via connection terminals 160. For example, the semiconductor chip 130 may be flip-chip mounted on a substrate film 110. The first chip pad 131, the second chip pad 132, the third chip pad 133, and the fourth chip pad 134 of the semiconductor chip 130 can be physically connected to the input / output lines 120a and 120b via connection terminals 160. For example, the connection terminals 160 can be conductive bumps or solder balls. The connection terminals 160 can be described as external chip connection terminals because they are arranged on the outer surface of the semiconductor chip 130 and transmit signals and / or voltages from or to the outside of the semiconductor chip 130.

[0031] According to some example embodiments, semiconductor chip 130 may be a display driver integrated chip (IC) that drives a display panel. For example, semiconductor chip 130 may generate an image signal using data signals transmitted from a timing controller, and may output the image signal to the display panel. As another example, semiconductor chip 130 may be a timing controller connected to the display driver IC.

[0032] For example, when the semiconductor package 100 is combined with an electronic device other than a display device, the semiconductor chip 130 can be used to drive the electronic device.

[0033] A passivation layer 150 may be disposed on a first surface 110a of the substrate film 110. The passivation layer 150 may cover the input / output lines 120a and 120b. The passivation layer 150 may include, for example, a solder resist or a dry film resist, or optionally, an oxide-based or nitride-based dielectric layer.

[0034] The bottom filler layer 155 may be disposed along the bottom edge of the semiconductor chip 130 and may fill the space between the substrate film 110 and the semiconductor chip 130. The bottom filler layer 155 may partially cover the input / output lines 120a and 120b. The bottom filler layer 155 may include, for example, epoxy resin.

[0035] The heat dissipation pattern 140 can be disposed on the second surface 110b of the substrate film 110, and the adhesive layer 145 can be disposed between the heat dissipation pattern 140 and the second surface 110b of the substrate film 110. The adhesive layer 145 can be, for example, a polymer tape comprising a dielectric material, and therefore can be electrically insulating.

[0036] The heat dissipation pattern 140 can dissipate heat generated during the operation of the semiconductor chip 130. The heat dissipation pattern 140 can be formed of a material with a coefficient of thermal expansion greater than that of the substrate film 110. For example, the heat dissipation pattern 140 can be a metal strip such as copper (Cu), aluminum (Al), or alloys thereof. The heat dissipation pattern 140 can also be described as a heat sink, a heat dissipation film, a heat dissipation foil, or a heat dissipation material layer.

[0037] According to some example embodiments, the heat dissipation pattern 140 may have a first opening 141a corresponding to a first end of the semiconductor chip 130 and a second opening 141b corresponding to a second end of the semiconductor chip 130 opposite to the first end. The heat dissipation pattern 140 may include a central portion located between the first opening 141a and the second opening 141b. In some example embodiments, the first opening 141a and the second opening 141b may have substantially the same size and may be symmetrically arranged about each other about a line extending in the second direction D2 and passing through the center of the heat dissipation pattern 140 in the first direction D1. The heat dissipation pattern 140 may be configured such that the central portion between the first opening 141a and the second opening 141b may overlap with the first chip pad 131 and the second chip pad 132 of the semiconductor chip 130. Figure 1As seen in other example drawings illustrating embodiments of the heat dissipation pattern, the heat dissipation pattern 140 includes a central portion and outer portions. The central portion of the heat dissipation pattern 140 is continuous and covers the entire area of ​​the semiconductor chip 130 on the central portion. The outer portions of the heat dissipation pattern 140 are integrally connected to and formed integrally with the central portion, but are outside the area of ​​the semiconductor chip 130. The portion of the semiconductor chip 130 located outside the central portion of the heat dissipation pattern 140 is not covered by the heat dissipation pattern 140.

[0038] For example, refer to Figure 1 and Figure 3 The size of the heat dissipation pattern 140 can be determined by the size of the semiconductor chip 130. The heat dissipation pattern 140 can be a rectangular shape with a major axis and a minor axis. The heat dissipation pattern 140 can have a second length L2 in the first direction D1 (or the major axis direction) that is greater than the first length L1 of the semiconductor chip 130, and can also have a second width W2 in the second direction D2 (or the minor axis direction) that is greater than the first width W1 of the semiconductor chip 130. The second length L2 of the heat dissipation pattern 140 can be less than the length L3 of the substrate film 110 in the first direction D1, and the second width W2 of the heat dissipation pattern 140 can be less than the width W3 of the substrate film 110 in the second direction D2. The thickness of the heat dissipation pattern 140 can be less than the thickness of the semiconductor chip 130, and the heat dissipation pattern 140 can have a thickness in the range of approximately 15 μm to approximately 50 μm.

[0039] Both the first opening 141a and the second opening 141b of the heat dissipation pattern 140 can have an opening width OW in the first direction D1 and an opening length OL in the second direction D2. The opening width OW can be less than the opening length OL. The opening length OL can be greater than the first width W1 of the semiconductor chip 130 and less than the second width W2 of the heat dissipation pattern 140. For example, the opening width OW can be in the range of approximately 600 μm to approximately 4600 μm. The opening length OL can be in the range of approximately 1200 μm to approximately 9000 μm.

[0040] The first opening 141a and the second opening 141b of the heat dissipation pattern 140 may each have a first side surface S1 spaced apart from the first edge E1 of the semiconductor chip 130, a second side surface S2 spaced apart from the second edge E2 of the semiconductor chip 130, and a third side surface S3 and a fourth side surface S4 that are opposite to each other and spaced apart from the third edge E3 or the fourth edge E4 of the semiconductor chip 130.

[0041] Both the first opening 141a and the second opening 141b can be configured such that the first side surface S1 is spaced apart from the first edge E1 of the semiconductor chip 130 by a first distance G1, and the second side surface S2 is spaced apart from the second edge E2 of the semiconductor chip 130 by a second distance G2. For example, the first distance G1 can be substantially the same as the second distance G2. The first distance G1 and the second distance G2 can be in the range of approximately 1.0 μm to approximately 2.5 μm. As used herein, terms such as “same,” “equal,” “planar,” or “coplanar” cover “same” or include substantially the same, including variations that may occur due to manufacturing processes. Unless the context or other statement indicates otherwise, the term “substantially” is used herein to emphasize that meaning.

[0042] The third side surface S3 of the first opening 141a may be spaced apart from the third edge E3 of the semiconductor chip 130 by a third distance G3, and the fourth side surface S4 of the first opening 141a may be spaced apart from the third edge E3 of the semiconductor chip 130 by a fourth distance G4. The third distance G3 may be substantially equal to or less than the fourth distance G4. Both the third distance G3 and the fourth distance G4 may be in the range of approximately 1.0 μm to approximately 2.5 μm.

[0043] The third side S3 and the fourth side S4 of the second opening 141b can be spaced apart from the fourth edge E4 of the semiconductor chip 130. For example, the distance between the fourth side S4 of the second opening 141b and the fourth edge E4 of the semiconductor chip 130 can be given as approximately 1.0 μm to approximately 2.5 μm.

[0044] The first opening 141a of the heat dissipation pattern 140 can partially expose the second surface 110b of the substrate film 110 and can overlap with the third chip pad 133 disposed on the third edge E3 of the semiconductor chip 130. The second opening 141b of the heat dissipation pattern 140 can partially expose the second surface 110b of the substrate film 110 and can overlap perpendicularly with the fourth chip pad 134 disposed adjacent to the fourth edge E4 of the semiconductor chip 130.

[0045] For example, the heat dissipation pattern 140 may have its openings overlap with the connection portions of the input / output lines 120a and 120b that are connected to the connection terminals 160, which are adjacent to the third edge E3 and the fourth edge E4 of the semiconductor chip 130. In this case, the heat dissipation pattern 140 may not be present below the opposite ends of the semiconductor chip 130 where the third chip pad 133 and the fourth chip pad 134 are provided.

[0046] Because the heat dissipation pattern 140 does not overlap with the opposite end of the semiconductor chip 130, stress concentration caused by the expansion of the heat dissipation pattern 140 on the opposite end of the semiconductor chip 130 at the connection portion between the connection terminal 160 and the input / output lines 120a and 120b can be prevented. Therefore, damage to the connection terminal 160 and the input lines 120a and 120b can be avoided.

[0047] For the sake of brevity, in the following embodiments, the same components are assigned to... Figure 1 , Figure 2A , Figure 2B and Figure 3 The accompanying figures will use the same reference numerals, and their descriptions will be omitted while the differences will be described.

[0048] Figure 4 , Figure 5 and Figure 6 It shows along Figure 1 The cross-sectional view taken by line I-I' shows a semiconductor package according to some exemplary embodiments of the present invention.

[0049] Reference Figure 4 The lower passivation layer 170 can be disposed on the surface of the heat dissipation pattern 140. The lower passivation layer 170 can be a polyimide layer. The lower passivation layer 170 can have openings, the positions of which are substantially the same as the positions of the first opening 141a and the second opening 141b of the heat dissipation pattern 140.

[0050] Reference Figure 5 The lower passivation layer 170 can be disposed on the surface of the heat dissipation pattern 140, while covering the first opening 141a and the second opening 141b of the heat dissipation pattern 140. The lower passivation layer 170 and the substrate film 110 can have empty spaces therebetween corresponding to the first opening 141a and the second opening 141b of the heat dissipation pattern 140.

[0051] Reference Figure 6 An upper heat dissipation pattern 180 covering the semiconductor chip 130 may be formed on the first surface 110a of the substrate film 110. The upper heat dissipation pattern 180 can be attached to the first surface 110a of the substrate film 110 via an upper adhesive layer 185. The upper heat dissipation pattern 180 may have a uniform thickness and may cover the top surface of the semiconductor chip 130 and the top surface of the passivation layer 150. The upper heat dissipation pattern 180 may include a metallic material, such as aluminum or copper. Figures 4 to 6 The passivation layer described herein can be formed from an insulating material such as a solder resist or a dry film resist, or optionally from an oxide-based or nitride-based dielectric layer.

[0052] Figure 7A top view is shown illustrating some example embodiments of a semiconductor package according to a concept of the present invention. Figure 8 It shows along Figure 7 The cross-sectional view taken from line III-III'.

[0053] Reference Figure 7 and Figure 8 The heat dissipation pattern 140 may have a first opening 141a corresponding to a first end of the semiconductor chip 130 and a second opening 141b corresponding to a second end of the semiconductor chip 130. The heat dissipation pattern 140 may include a central portion located between the first opening 141a and the second opening 141b. (Referring to the above...) Figure 3 Both the first opening 141a and the second opening 141b discussed can have a first side surface S1, a second side surface S2, a third side surface S3 and a fourth side surface S4.

[0054] In this embodiment, the first opening 141a may have a first opening width OW1, and the second opening 141b may have a second opening width OW2. The first opening width OW1 may be different from the second opening width OW2. For example, the first opening width OW1 may be greater than the second opening width OW2, and the first opening 141a may overlap with one or more first chip pads 131 and one or more second chip pads 132 of the semiconductor chip 130. The first opening 141a and the second opening 141b may have substantially the same opening length in the second direction D2. Figure 7 and Figure 8 The characteristics of each of them can also be compared with Figure 4 , Figure 5 or Figure 6 The combination of features of each of them.

[0055] Figures 9 to 16 The diagram shows a top view illustrating some example embodiments of a semiconductor package according to the present invention, all of which can be compared with... Figure 4 , Figure 5 or Figure 6 The combination of features of each of them.

[0056] Reference Figure 9 The heat dissipation pattern 140 may have a first opening 141a and a second opening 141b, and as shown above. Figure 3 Both the first opening 141a and the second opening 141b discussed herein may have a first side surface S1, a second side surface S2, a third side surface S3, and a fourth side surface S4. The first side surface S1, the second side surface S2, the third side surface S3, and the fourth side surface S4 of the first opening 141a and the second opening 141b may be spaced apart from the first edge E1, the second edge E2, the third edge E3, and the fourth edge E4 of the semiconductor chip 130.

[0057] Both the first opening 141a and the second opening 141b can overlap with one or more first chip pads 131 and one or more second chip pads 132 of the semiconductor chip 130. The distance between the third edge E3 of the semiconductor chip 130 and the third side surface S3 of the first opening 141a can be less than the distance between the third edge E3 of the semiconductor chip 130 and the fourth side surface S4 of the first opening 141a. Furthermore, the distance between the fourth edge E4 of the semiconductor chip 130 and the fourth side surface S4 of the second opening 141b can be less than the distance between the fourth edge E4 of the semiconductor chip 130 and the third side surface S3 of the second opening 141b.

[0058] Reference Figure 10 Both the first opening 141a and the second opening 141b can be configured such that the first side surface S1 can be spaced apart from the first edge E1 of the semiconductor chip 130 by a first distance G1, and the second side surface S2 can be spaced apart from the second edge E2 of the semiconductor chip 130 by a second distance G2. The first distance G1 can be different from (e.g., less than) the second distance G2.

[0059] Reference Figure 11 The heat dissipation pattern 140 may have a generally rectangular shape and may have a first edge parallel to the first edge E1 of the semiconductor chip 130 and a second edge parallel to the second edge E2 of the semiconductor chip 130.

[0060] The distance d1 between the first edge of the heat dissipation pattern 140 and the first edge E1 of the semiconductor chip 130 can be different from the distance d2 between the second edge of the heat dissipation pattern 140 and the second edge E2 of the semiconductor chip 130. For example, the distance d1 can be less than the distance d2.

[0061] As described above, the heat dissipation pattern 140 may have a first opening 141a and a second opening 141b, and also has a first side S1, a second side S2, a third side S3 and a fourth side S4. The first opening 141a and the second opening 141b may have substantially the same size and may be symmetrical to each other about a line extending between them in the middle in the second direction D2.

[0062] The first distance G1 between the first edge E1 of the semiconductor chip 130 and the first side surface S1 of the first opening 141a and the second opening 141b can be substantially equal to the second distance G2 between the second edge E2 of the semiconductor chip 130 and the second side surface S2 of the first opening 141a and the second opening 141b.

[0063] The distance T1 between the first edge of the heat dissipation pattern 140 and the first side surface S1 of the first opening 141a and the second opening 141b can be different from the distance T2 between the second edge of the heat dissipation pattern 140 and the second side surface S2 of the first opening 141a and the second opening 141b. For example, the distance T1 can be less than the distance T2.

[0064] Reference Figure 12 The distance d1 between the first edge of the heat dissipation pattern 140 and the first edge E1 of the semiconductor chip 130 may be different from the distance d2 between the second edge of the heat dissipation pattern 140 and the second edge E2 of the semiconductor chip 130.

[0065] The heat dissipation pattern 140 may have a first opening 141a and a second opening 141b that are symmetrical to each other with respect to a line extending in the second direction D2 and located at the center of the heat dissipation pattern 140 in the first direction D1. Both the first opening 141a and the second opening 141b may be defined by three sides S2, S3, and S4. For example, the first opening 141a and the second opening 141b may open at a portion adjacent to the first edge E1 of the semiconductor chip 130. This is in contrast to the openings in the foregoing embodiments, which can be described as closed openings. Figure 12 The openings 141a and 141b can be described as open openings.

[0066] Reference Figure 13 The distance Ga between the third edge E3 of the semiconductor chip 130 and one side of the substrate film 110 may be different from the distance Gb between the fourth edge E4 of the semiconductor chip 130 and the other side of the substrate film 110.

[0067] The heat dissipation pattern 140 may have a third edge parallel to the third edge E3 of the semiconductor chip 130 and a fourth edge parallel to the fourth edge E4 of the semiconductor chip 130.

[0068] The distance Gc between one side of the substrate film 110 and the third edge of the heat dissipation pattern 140 can be substantially equal to the distance Gd between the other side of the substrate film 110 and the fourth edge of the heat dissipation pattern 140.

[0069] The heat dissipation pattern 140 may have a first opening 141a and a second opening 141b that are asymmetrical to each other. The first opening 141a of the heat dissipation pattern 140 may be defined by three sides, and therefore may be an open opening, while the second opening 141b of the heat dissipation pattern 140 may be defined by four sides, and therefore may be a closed opening. For example, the first opening 141a of the heat dissipation pattern 140 may be defined by a first side spaced apart from the first edge E1 of the semiconductor chip 130 (see...). Figure 3 S1), and the second side spaced apart from the second edge E2 of the semiconductor chip 130 (see S1). Figure 3S2) and the fourth side spaced apart from the third edge E3 of the semiconductor chip 130 (see S2) Figure 3 S4) is limited. See reference Figure 3 The second opening 141b of the heat dissipation pattern 140 discussed may be defined by the first side S1, the second side S2, the third side S3 and the fourth side S4.

[0070] Reference Figure 14 The distance Ga between the third edge E3 of the semiconductor chip 130 and one side of the substrate film 110 may be different from the distance Gb between the fourth edge E4 of the semiconductor chip 130 and the other side of the substrate film 110.

[0071] The heat dissipation pattern 140 may have a third edge parallel to the third edge E3 of the semiconductor chip 130 and a fourth edge parallel to the fourth edge E4 of the semiconductor chip 130.

[0072] The distance Gc between one side of the substrate film 110 and the third edge of the heat dissipation pattern 140 can be substantially equal to the distance Gd between the other side of the substrate film 110 and the fourth edge of the heat dissipation pattern 140.

[0073] The heat dissipation pattern 140 may have a first opening 141a and a second opening 141b of different sizes. The first opening 141a and the second opening 141b of the heat dissipation pattern 140 may be asymmetrical. For example, the width of the first opening 141a in the first direction D1 may be smaller than the width of the second opening 141b in the first direction D1. The first opening 141a may overlap with the third chip pad 133 of the semiconductor chip 130, and the third side of the first opening 141a (see...) Figure 3 The distance between S3 and the third edge E3 of the semiconductor chip 130 can be smaller than the first side of the first opening 141a (see S3). Figure 3 The distance between S1 and the first edge E1 of the semiconductor chip 130. For example, the third side of the first opening 141a (see Figure 3 S3 can be substantially aligned with the third edge E3 of the semiconductor chip 130.

[0074] Reference Figure 15 and Figure 16The heat dissipation pattern 140 may include first portions parallel to the first direction D1 and spaced apart from each other in the second direction D2, and may also include second portions located between the first portions. When viewed in the first direction D1, the first portions may have a second length L2 greater than the first length L1 of the semiconductor chip 130, and the second portions may have a fourth length L4 less than the second length L2. The second portions of the heat dissipation pattern 140 may overlap with the central portion of the semiconductor chip 130. When viewed in the second direction D2, the width of the heat dissipation pattern 140 may be greater than the width of the semiconductor chip 130.

[0075] As described above, the heat dissipation pattern 140 may have a first opening 141a and a second opening 141b corresponding to the end of the semiconductor chip 130.

[0076] The first opening 141a may have a first side surface S1 spaced apart from a first edge E1 of the semiconductor chip 130, a second side surface S2 spaced apart from a second edge E2 of the semiconductor chip 130, and a third side surface S3 spaced apart from a third edge E3 of the semiconductor chip 130. The second opening 141b may have a first side surface S1 spaced apart from a first edge E1 of the semiconductor chip 130, a second side surface S2 spaced apart from a second edge E2 of the semiconductor chip 130, and a third side surface S3 spaced apart from a fourth edge E4 of the semiconductor chip 130. The first opening 141a and the second opening 141b may also be described as a gap within a heat dissipation pattern 140.

[0077] like Figure 15 As shown, the first opening 141a can overlap with the third chip pad 133 of the semiconductor chip 130, and the second opening 141b can overlap with the fourth chip pad 134 of the semiconductor chip 130.

[0078] like Figure 16 As shown, the first opening 141a can overlap with the third chip pad 133 of the semiconductor chip 130, and can overlap with some (e.g., two, four or more) of the first chip pads 131 and the second chip pads 132 of the semiconductor chip 130. Similarly, the second opening 141b can overlap with the fourth chip pad 134 of the semiconductor chip 130, and can overlap with some (e.g., two, four or more) of the first chip pads 131 and the second chip pads 132 of the semiconductor chip 130.

[0079] Compared with the previous Figures 10 to 14 The embodiments shown are the same, in Figure 15 and Figure 16 The heat dissipation pattern 140 and semiconductor chip 130 shown can be configured to be misaligned with each other in either the first direction D1 or the second direction D2.

[0080] Figure 17 A perspective view of a display device including a semiconductor package, illustrating some example embodiments of a concept according to the present invention, is shown.

[0081] The display device 1000 may include at least one semiconductor package 100, a printed circuit board 200, and a display panel 300.

[0082] At least one semiconductor package 100 may be connected between the printed circuit board 200 and the display panel 300. The at least one semiconductor package 100 may receive signals output from the printed circuit board 200 and may transmit signals to the display panel 300. The at least one semiconductor package 100 may include the components described above. Figures 1 to 16 Semiconductor packages under discussion.

[0083] The printed circuit board 200 may include an interface capable of connecting to an external processing device, and may also include at least one driving component capable of simultaneously applying power and signals to at least one semiconductor package 100.

[0084] The display panel 300 may include a transparent substrate 310, a display area 320 formed on the transparent substrate 310, and multiple panel lines. The transparent substrate 310 may be, for example, a glass substrate or a transparent flexible substrate. The display area 320 may include multiple pixels connected to the multiple panel lines, and the multiple pixels may operate in response to signals output from the semiconductor package 100.

[0085] The display panel 300 may be, for example, a liquid crystal display (LCD) panel, a light-emitting diode (LED) panel, an organic LED panel, or a plasma display panel (PDP).

[0086] According to some exemplary embodiments of the present invention, because the heat dissipation pattern has openings corresponding to the opposite ends of the semiconductor chip, stress concentration caused by the expansion of the heat dissipation pattern at the opposite ends of the semiconductor chip can be prevented at the connection portions of the connection terminals to the input / output lines when the semiconductor chip is operating. Therefore, damage to the input / output lines and connection terminals can be avoided. As a result, the reliability of the semiconductor package can be improved.

[0087] Although the inventive concept has been described with reference to some exemplary embodiments shown in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and essential characteristics of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made without departing from the scope and spirit of the inventive concept.

[0088] Ordinal numbers such as "first," "second," and "third" can be simply used as labels to distinguish certain elements, steps, etc., from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term mentioned with a specific number (e.g., "first" in a particular claim) may be described elsewhere with a different number (e.g., "second" in the specification or another claim).

Claims

1. A semiconductor package, the semiconductor package comprising: A substrate film having a first surface and a second surface opposite to the first surface; Multiple input / output lines are located on the first surface of the substrate film; A semiconductor chip disposed on the first surface of the substrate film and connected to the input / output line, the semiconductor chip including a central portion and ends located on opposite sides of the central portion; and A heat dissipation pattern is located on the second surface of the substrate film. The heat dissipation pattern corresponds to the semiconductor chip and has multiple openings that correspond to the ends of the semiconductor chip and overlap perpendicularly with the ends of the semiconductor chip. The semiconductor chip includes a plurality of first chip pads located on the central portion and a plurality of second chip pads located on the ends. The second chip pad of the semiconductor chip overlaps perpendicularly with the opening of the heat dissipation pattern.

2. The semiconductor package according to claim 1, wherein the semiconductor package further comprises a plurality of connection terminals located between the input / output line and the first chip pad and the second chip pad.

3. The semiconductor package according to claim 1, in, The semiconductor chip has: The first and second edges that are opposite to each other; and The third and fourth edges, which are opposite to each other and perpendicular to the first and second edges, and Wherein, each of the openings has: A first side surface spaced apart from the first edge; The second side surface spaced apart from the second edge; and The third and fourth sides are opposite to each other and spaced apart from the third edge or the fourth edge.

4. The semiconductor package according to claim 3, wherein, For at least one of the openings, the first distance between the first side and the first edge and the second distance between the third side and the third edge are both in the range of 1.0 μm to 2.5 μm.

5. The semiconductor package according to claim 3, wherein, For at least one of the openings, the first distance between the first side and the first edge is different from the second distance between the third side and the third edge.

6. The semiconductor package according to claim 3, wherein, The first edge and the second edge of the semiconductor chip have a first length. The third and fourth edges of the semiconductor chip have a first width, and The first length is 5 to 15 times the first width.

7. The semiconductor package according to claim 1, wherein, When viewed in the first direction The substrate membrane has a first length. The semiconductor chip has a second length, and The heat dissipation pattern has a third length that is less than the first length and greater than the second length.

8. The semiconductor package according to claim 7, wherein, When viewed in a second direction perpendicular to the first direction The semiconductor chip has a first width, and The heat dissipation pattern has a second width that is greater than the first width.

9. The semiconductor package according to claim 1, wherein, The heat dissipation pattern is a sheet with a thickness ranging from 15 μm to 50 μm.

10. The semiconductor package according to claim 1, wherein, The heat dissipation pattern includes: A plurality of first portions having a first length in a first direction and spaced apart from each other in a second direction perpendicular to the first direction. A second portion located between the first portions and having a second length less than the first length. The second portion of the heat dissipation pattern overlaps with the central portion of the semiconductor chip.

11. The semiconductor package according to claim 1, in, The semiconductor chip has: The first and second edges that are opposite to each other; and The third and fourth edges, which are opposite to each other and perpendicular to the first and second edges, and Wherein, each of the openings has: A first side surface spaced apart from the first edge; The second side surface spaced apart from the second edge; and A third side surface spaced apart from the third edge or the fourth edge.

12. The semiconductor package according to claim 1, wherein, The semiconductor chip has: A first edge spaced apart from the first side surface of the substrate film by a first distance; and A second edge spaced apart from the second side surface of the substrate membrane by a second distance, the second distance being different from the first distance.

13. The semiconductor package according to claim 12, wherein, The heat dissipation pattern has the following characteristics: A third edge spaced a third distance from the first side surface of the substrate film; and The fourth edge, spaced a fourth distance from the second side surface of the substrate film. Wherein, the third distance is smaller than the first distance. Wherein, the fourth distance is less than the second distance, and The third distance is basically the same as the fourth distance.

14. A semiconductor package, the semiconductor package comprising: A substrate film having a first surface and a second surface opposite to the first surface; A semiconductor chip, the semiconductor chip being located on the first surface of the substrate film, the semiconductor chip having a length in a first direction and a width in a second direction perpendicular to the first direction, the width being less than the length; and A heat dissipation pattern is located on the second surface of the substrate film. The semiconductor chip includes: A plurality of first chip pads, the plurality of first chip pads being adjacent to a first edge of the semiconductor chip parallel to the second direction; and A plurality of second chip pads are provided, the plurality of second chip pads being adjacent to a second edge of the semiconductor chip opposite to the first edge. The heat dissipation pattern has the following characteristics: A first opening, the first opening perpendicularly overlapping the first chip pad of the semiconductor chip; and The second opening overlaps perpendicularly with the second chip pad of the semiconductor chip, and Both the first opening and the second opening have an opening length in the second direction, and the opening length is greater than the width of the semiconductor chip.

15. A semiconductor package, the semiconductor package comprising: A substrate film having a first surface and a second surface opposite to the first surface; Multiple input / output lines are located on the first surface of the substrate film; A semiconductor chip, located on the first surface of the substrate film and connected to the input / output line, includes: a first edge and a second edge opposite to each other; a third edge and a fourth edge perpendicular to the first edge and the second edge and opposite to each other, wherein the first edge and the second edge are longer than the third edge and the fourth edge; and A heat sink is located on the second surface of the substrate film and corresponds to the semiconductor chip. The semiconductor chip includes: a plurality of first chip pads arranged adjacent to the first edge and the second edge; and a plurality of second chip pads arranged adjacent to the third edge and the fourth edge. The heat sink has a first opening and a second opening, the first opening and the second opening partially exposing the substrate film. Wherein, the first opening perpendicularly overlaps with the second chip pad adjacent to the third edge, and The second opening overlaps perpendicularly with the second chip pad adjacent to the fourth edge.

16. The semiconductor package of claim 15, wherein, Both the first opening and the second opening have: A first side surface spaced apart from the first edge of the semiconductor chip; and A second side surface spaced apart from the third edge of the semiconductor chip.

17. The semiconductor package of claim 16, wherein, The first distance between the first side and the first edge, and the second distance between the second side and the third edge, are both within the range of 1.0 μm to 2.5 μm.

18. The semiconductor package of claim 15, wherein, When viewed in the first direction, The substrate membrane has a first length. The semiconductor chip has a second length, and The third length of the heat sink is less than the first length and greater than the second length.

19. The semiconductor package of claim 15, wherein, The first edge and the second edge have a first length The third edge and the fourth edge have a first width, and The first length is 5 to 15 times the first width.

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