Semiconductor device

Abstract

A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, a cell separation structure separating the first and second active patterns between the first and second epitaxial patterns and including a core separation pattern and a separation sidewall pattern on sidewalls of the core separation pattern, and a gate structure extending on the first active pattern in a second direction crossing the first direction. An upper surface of the gate structure is on a same plane as an upper surface of the core separation pattern. The separation sidewall pattern includes a high dielectric constant liner including a high dielectric constant dielectric film containing a metal.

Description

Technical Field

[0001] Exemplary embodiments of the present invention relate to semiconductor devices including element separation structures. Background Technology

[0002] One scaling technique used to increase the density of semiconductor devices is the use of multi-gate transistors, in which a multi-channel active pattern (or silicon body) with a fin shape or nanowire shape is formed on a substrate and the gate is formed on the surface of the multi-channel active pattern.

[0003] Because multi-gate transistors utilize a three-dimensional channel, scaling is easily implemented. Furthermore, current control capability can be improved even without increasing the gate length of the multi-gate transistor. Additionally, the short-channel effect (SCE), where the channel region potential is affected by the drain voltage, can be effectively suppressed. Summary of the Invention

[0004] According to an exemplary embodiment of the present invention, a semiconductor device includes: a first active pattern and a second active pattern, each extending in a first direction; a first epitaxial pattern disposed on the first active pattern and adjacent to the second active pattern; a second epitaxial pattern disposed on the second active pattern and adjacent to the first active pattern; an element separation structure separating the first active pattern and the second active pattern between the first epitaxial pattern and the second epitaxial pattern, wherein the element separation structure includes a core separation pattern and a separation sidewall pattern on the sidewall of the core separation pattern; and a gate structure extending on the first active pattern in a second direction intersecting the first direction. The upper surface of the gate structure is disposed on the same plane as the upper surface of the core separation pattern, and the separation sidewall pattern includes a high-dielectric-constant pad comprising a high-dielectric-constant dielectric film comprising a metal.

[0005] According to an exemplary embodiment of the present invention, a semiconductor device includes: an element separation structure including a first extended separation structure and a second extended separation structure extending in a first direction, and a third extended separation structure and a fourth extended separation structure extending in a second direction different from the first direction, wherein the element separation structure has a closed-loop shape; a first active pattern and a second active pattern, separated by the first extended separation structure and each extending in the second direction; a first gate structure extending in the first direction, including a gate electrode and disposed on the first active pattern; and a gate separation structure formed along the second direction and facing a first side of the gate electrode. The third extended separation structure is disposed on a portion of the gate separation structure.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes: a first active pattern and a second active pattern, each extending in a first direction; a first epitaxial pattern on the first active pattern; a second epitaxial pattern on the second active pattern; a first element separator structure separating the first active pattern and the second active pattern between the first epitaxial pattern and the second epitaxial pattern; a gate structure extending in a second direction intersecting the first direction on the first active pattern; a gate separator structure in contact with the first element separator structure; and a second element separator structure disposed on the gate separator structure and directly connected to the first element separator structure. The upper surface of the second element separator structure is disposed on the same plane as the upper surface of the gate structure and the upper surface of the first element separator structure.

[0007] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming a plurality of pre-gate structures separated by an interlayer insulating film, wherein the plurality of pre-gate structures are spaced apart in a first direction and extend in a second direction intersecting the first direction; forming a mask pattern on a portion of the plurality of pre-gate structures; forming a replacement pattern along the sidewalls of the mask pattern, wherein the replacement pattern has a closed-loop shape extending in the first and second directions; forming a filling mask pattern surrounding the replacement pattern; removing the replacement pattern to form an element separation trench; and forming a core separation pattern filling the element separation trench. Attached Figure Description

[0008] The above and other aspects and features of the present invention will become more apparent from the exemplary embodiments described in detail with reference to the accompanying drawings.

[0009] Figure 1 This is an exemplary layout diagram used to illustrate an exemplary embodiment of a semiconductor device according to the concept of the present invention.

[0010] Figures 2 to 6 This is along the exemplary embodiments of the concept of the present invention. Figure 1 The cross-sectional views are taken from lines AA, BB, CC, DD and EE.

[0011] Figures 7 to 9 This is one of the exemplary embodiments of the concept of the present invention. Figure 2 An exemplary view in which region P is magnified.

[0012] Figure 10 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0013] Figure 11 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0014] Figure 12 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0015] Figure 13 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0016] Figures 14 to 16 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0017] Figure 17 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0018] Figure 18 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0019] Figure 19 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0020] Figure 20 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0021] Figure 21 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0022] Figure 22 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0023] Figure 23 This is a layout diagram used to illustrate an exemplary embodiment of a semiconductor device according to the concept of the present invention.

[0024] Figure 24 and Figure 25 This is along the exemplary embodiments of the concept of the present invention. Figure 23 The cross-sectional view taken by lines AA and EE.

[0025] Figure 26 This is a layout diagram used to illustrate an exemplary embodiment of a semiconductor device according to the concept of the present invention.

[0026] Figure 27 This is along the exemplary embodiments of the concept of the present invention. Figure 26 The cross-sectional view taken from line AA.

[0027] Figure 28 This is a layout diagram used to illustrate an exemplary embodiment of a semiconductor device according to the concept of the present invention.

[0028] Figure 29 This is along the exemplary embodiments of the concept of the present invention. Figure 28 The cross-sectional view taken from line AA.

[0029] Figure 30 This is a layout diagram used to illustrate an exemplary embodiment of a semiconductor device according to the concept of the present invention.

[0030] Figure 31 This is a layout diagram used to illustrate an exemplary embodiment of a semiconductor device according to the concept of the present invention.

[0031] Figures 32 to 36 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention. Detailed Implementation

[0032] Exemplary embodiments of the present invention provide semiconductor devices in which the integration of components is improved and reliability and performance are enhanced.

[0033] Exemplary embodiments of the present invention also provide a method for manufacturing a semiconductor device in which the integration of components is improved and the reliability and performance are enhanced.

[0034] Exemplary embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings. Throughout this application, similar reference numerals may refer to similar elements.

[0035] Although the accompanying drawings of semiconductor devices according to exemplary embodiments of the present invention illustrate fin transistors (FinFETs) including fin-patterned channel regions and transistors including nanowires or nanosheets, the present invention is not limited thereto. The present invention can be applied to transistors based on two-dimensional materials (FETs based on 2D materials) and their heterostructures.

[0036] Furthermore, semiconductor devices according to exemplary embodiments of the present invention may include tunneling FETs or three-dimensional (3D) transistors. Semiconductor devices according to exemplary embodiments of the present invention may also include bipolar junction transistors, laterally diffused metal-oxide-semiconductor (LDMOS), etc.

[0037] Figures 1 to 9 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention.

[0038] Figure 1 This is an exemplary layout diagram used to illustrate an exemplary embodiment of a semiconductor device according to the concept of the present invention. Figures 2 to 6 This is along the exemplary embodiments of the concept of the present invention. Figure 1The cross-sectional views are taken from lines AA, BB, CC, DD and EE. Figures 7 to 9 This is one of the exemplary embodiments of the concept of the present invention. Figure 2 An exemplary view in which region P is magnified.

[0039] For ease of explanation, Figure 1 The interlayer insulating films 191 and 192, the source / drain contact 160, and the wiring structure 195 are not shown.

[0040] Reference Figures 1 to 9 A semiconductor device according to an exemplary embodiment of the present invention may include first to sixth active patterns AP1 to AP6, first to third gate structures GS1 to GS3, gate separation structure GCS and element separation structure DCS.

[0041] The substrate 100 may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate 100 may be a silicon substrate, or may be other materials including, but not limited to, silicon germanium, SGOI (silicon germanium-on-insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0042] The first to sixth active patterns AP1 to AP6 may each protrude from the substrate 100. Each of the first to sixth active patterns AP1 to AP6 may extend on the substrate 100 along a first direction D1. For example, each of the first to sixth active patterns AP1 to AP6 may include a long side extending in the first direction D1 and a short side extending in the second direction D2. Here, the first direction D1 may intersect with the second direction D2 and the third direction D3. In addition, the second direction D2 may intersect with the third direction D3.

[0043] The first to third active patterns AP1 to AP3 can be arranged in a row along the first direction D1. The second active pattern AP2 can be spaced apart from the first active pattern AP1 and the third active pattern AP3 along the first direction D1.

[0044] The first active pattern AP1 and the second active pattern AP2 can be separated by the component separation structure DCS described below, and the second active pattern AP2 and the third active pattern AP3 can be separated by the component separation structure DCS.

[0045] The fourth to sixth active patterns AP4 to AP6 can be arranged in a row along the first direction D1. The fifth active pattern AP5 can be spaced apart from the fourth active pattern AP4 and the sixth active pattern AP6 along the first direction D1.

[0046] The fourth active pattern AP4 and the fifth active pattern AP5 can be separated by the component separation structure DCS described below, and the fifth active pattern AP5 and the sixth active pattern AP6 can be separated by the component separation structure DCS.

[0047] The fourth active pattern AP4 can be spaced apart from the first active pattern AP1 in the second direction D2. The fifth active pattern AP5 can be spaced apart from the second active pattern AP2 in the second direction D2. The sixth active pattern AP6 can be spaced apart from the third active pattern AP3 in the second direction D2.

[0048] The first to third active patterns AP1 to AP3 can be placed in the active region defined by the deep trench DT. The fourth to sixth active patterns AP4 to AP6 can be placed in the active region defined by the deep trench DT. The deep trench DT can be formed between the first to third active patterns AP1 to AP3 and the fourth to sixth active patterns AP4 to AP6. In a semiconductor device according to an exemplary embodiment of the present invention, the deep trench DT can distinguish the active region in which the first to third active patterns AP1 to AP3 are placed from the active region in which the fourth to sixth active patterns AP4 to AP6 are placed.

[0049] The first to sixth active patterns AP1 to AP6 can be placed between the gate separation structures GCS described below.

[0050] The first to sixth active patterns AP1 to AP6 can be multi-channel active patterns. In a semiconductor device according to an exemplary embodiment of the present invention, each of the first to sixth active patterns AP1 to AP6 can be, for example, a fin pattern. Each of the first to sixth active patterns AP1 to AP6 can be used as a channel pattern for a transistor. Although two of each of the first to sixth active patterns AP1 to AP6 are shown, this is only for illustrative purposes, and the number is not limited thereto. Each of the first to sixth active patterns AP1 to AP6 can be one or more.

[0051] Each of the first to sixth active patterns AP1 to AP6 may be part of the substrate 100 and may include an epitaxial layer grown from the substrate 100. Each of the first to sixth active patterns AP1 to AP6 may include, for example, silicon or germanium as an elemental semiconductor material. In addition, each of the first to sixth active patterns AP1 to AP6 may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0052] Group IV-IV compound semiconductors can be, for example, binary or ternary compounds comprising at least two of group IV elements, such as carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds obtained by combining group IV elements.

[0053] III-V compound semiconductors can be, for example, binary, ternary, and quaternary compounds obtained by combining at least one of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, with one of phosphorus (P), arsenic (As), and antimony (Sb), which are group V elements.

[0054] As an example, the first to sixth active patterns AP1 to AP6 may include the same material. As another example, the first to third active patterns AP1 to AP3 may include different materials than the fourth to sixth active patterns AP4 to AP6.

[0055] A field insulating film 105 can be formed on a substrate 100. The field insulating film 105 can fill a deep trench DT.

[0056] The field insulating film 105 may be formed on a portion of the sidewall of the first to sixth active patterns AP1 to AP6. Each of the first to sixth active patterns AP1 to AP6 may protrude upward from the upper surface of the field insulating film 105. The field insulating film 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0057] Each of the first to third gate structures GS1 to GS3 can be placed on the field insulating film 105. Each of the first to third gate structures GS1 to GS3 can extend in the second direction D2. The second gate structure GS2 can be spaced apart from the first gate structure GS1 and the third gate structure GS3 in the first direction D1.

[0058] The first gate structure GS1 can be placed on the first active pattern AP1 and the fourth active pattern AP4. The first gate structure GS1 can intersect with the first active pattern AP1 and the fourth active pattern AP4. The second gate structure GS2 can be placed on the second active pattern AP2 and the fifth active pattern AP5.

[0059] The second gate structure GS2 can intersect with the second active pattern AP2 and the fifth active pattern AP5. The third gate structure GS3 can be placed on the third active pattern AP3 and the sixth active pattern AP6. The third gate structure GS3 can intersect with the third active pattern AP3 and the sixth active pattern AP6.

[0060] Each of the first to third gate structures GS1 to GS3 may include a gate electrode 120, a gate insulating film 130, a gate spacer 140, and a gate cover pattern 145.

[0061] Gate electrode 120 may be formed on the first to sixth active patterns AP1 to AP6. Gate electrode 120 may intersect with the first to sixth active patterns AP1 to AP6. Gate electrode 120 may surround the first to sixth active patterns AP1 to AP6 that protrude beyond the upper surface of the field insulating film 105. Gate electrode 120 may include a long side extending in the second direction D2 and a short side extending in the first direction D1.

[0062] The gate electrode 120 may include at least one of the following: titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbon Nitrides (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof.

[0063] Gate spacer 140 may be disposed on the sidewall of gate electrode 120. Gate spacer 140 may extend in the second direction D2. Gate spacer 140 may include at least one of the following: silicon nitride (SiN), silicon oxide nitride (SiON), silicon oxide (SiO2), silicon oxygen carbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxygen boron nitride (SiOBN), silicon oxygen carbide (SiOC), and combinations thereof.

[0064] The gate insulating film 130 may extend along the sidewalls and bottom surface of the gate electrode 120. The gate insulating film 130 may be placed between the gate electrode 120 and the first to sixth active patterns AP1 to AP6, and between the gate electrode 120 and the field insulating film 105. The gate insulating film 130 may be placed between the gate electrode 120 and the gate spacer 140.

[0065] The gate insulating film 130 may include silicon oxide, silicon nitride, silicon nitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, for example, one or more of the following: boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0066] The gate cover pattern 145 may be placed on the upper surface of the gate electrode 120 and the upper surface of the gate spacer 140. The gate cover pattern 145 may include at least one of the following: silicon nitride (SiN), silicon oxide nitride (SiON), silicon oxide (SiO2), silicon carbon nitride (SiCN), silicon oxygen carbon nitride (SiOCN), and combinations thereof.

[0067] Unlike the case shown, the gate cover pattern 145 can be placed between the gate spacers 140. In this case, the upper surface of the gate cover pattern 145 can be placed on the same plane as the upper surface of the gate spacers 140.

[0068] The first epitaxial pattern 150 can be placed on the first active pattern AP1. The second epitaxial pattern 250 can be placed on the second active pattern AP2. The third epitaxial pattern 350 can be placed on the third active pattern AP3.

[0069] The first epitaxial pattern 150 can be included in the source / drain of a transistor using the first active pattern AP1 as the channel region. The second epitaxial pattern 250 can be included in the source / drain of a transistor using the second active pattern AP2 as the channel region. The third epitaxial pattern 350 can be included in the source / drain of a transistor using the third active pattern AP3 as the channel region.

[0070] According to an exemplary embodiment of the invention, an etch stop film may be further formed on the first to third epitaxial patterns 150, 250 and 350.

[0071] According to an exemplary embodiment of the present invention, the epitaxial pattern may be placed on the fourth to sixth active patterns AP4 to AP6.

[0072] A gate separator structure GCS can be formed along a first direction D1. The gate separator structure GCS can separate each of the first to third gate structures GS1 to GS3. For example, the gate separator structure GCS separates the gate electrode 120 included in the gate structures GS1 to GS3. For example, the gate separator structure GCS can be placed on a field insulating film 105 that fills a deep trench DT.

[0073] Each of the first to third gate structures GS1 to GS3 can be placed between gate partition structures GCS that are spaced apart from each other in the second direction D2. The gate partition structure GCS can face the short side of the gate electrode 120 extending in the first direction D1. The short side of the gate electrode 120 can be referred to as the first side.

[0074] In a semiconductor device according to an exemplary embodiment of the present invention, the gate separator structure GCS may include a plurality of gate separator patterns GCP arranged and spaced apart from each other in a first direction D1, such as... Figure 4 As shown. A portion of the gate separator pattern GCP can be placed on the second direction D2 facing the gate electrode 120. Additionally, the remaining gate separator patterns GCP can be placed on the element separation structure DCS on the second direction D2 facing the first extended separation structures DB1 and DB2, which will be described below. The first interlayer insulating film 191 can be placed between the gate separator patterns GCP spaced apart from each other on the first direction D1.

[0075] Gate spacers 140 extending in the second direction D2 can be placed on the sidewalls of each gate separator pattern GCP. Gate spacers 140 placed on the sidewalls of the gate electrode 120 can extend in the second direction D2 and can be placed on the sidewalls of the gate separator pattern GCP. Additionally, gate spacers 140 placed on the sidewalls of the first extended separator structure DB1 and the first extended separator structure DB2 can extend in the second direction D2 and can be placed on the sidewalls of the gate separator pattern GCP. Alternatively, unlike the illustrated case, gate spacers 140 may not be placed on the sidewalls of each gate separator pattern GCP.

[0076] The upper surface of the gate separator structure GCS can be placed on the same plane as the upper surface 145µs of the gate cover pattern 145. In other words, the upper surface of the gate separator pattern GCP can be placed on the same plane as the upper surface 145µs of the gate cover pattern 145.

[0077] The bottom surface of the gate separator pattern GCP can be closer to the substrate 100 than the bottom surface of the gate spacer 140. In other words, the bottom surface of the gate separator pattern GCP can be lower than the upper surface of the field insulating film 105. Alternatively, unlike the case shown, the bottom surface of the gate separator pattern GCP can be located at the same level as the bottom surface of the gate spacer 140.

[0078] In a semiconductor device according to an exemplary embodiment of the present invention, a gate insulating film 130 may be disposed between the gate electrode 120 and the gate separator structure GCS. The gate insulating film 130 may extend along the sidewall of the gate separator structure GCS. The gate electrode 120 and the gate separator structure GCS may be separated by the gate insulating film 130.

[0079] The gate separator pattern (GCP) may include at least one of the following: silicon nitride (SiN), silicon oxide nitride (SiON), silicon oxide (SiO2), silicon oxide carbon nitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon oxide carbide (SiOC), aluminum oxide (AlO), and combinations thereof. Although each gate separator pattern (GCP) is shown as a single film, the inventive concept is not limited thereto.

[0080] The component partition structure DCS may include first extended partition structures DB1 and DB2 extending in the second direction D2, and second extended partition structures CDB1 and CDB2 extending in the first direction D1. For example, the first extended partition structures DB1 and DB2 may be connected to the second extended partition structures CDB1 and CDB2. For reference, the first extended partition structure DB1, DB2, CDB1, and CDB2 may be referred to as the first, second, third, and fourth extended partition structures, respectively.

[0081] In a semiconductor device according to an exemplary embodiment of the present invention, the element separation structure DCS may have a closed-loop shape.

[0082] In a semiconductor device according to an exemplary embodiment of the present invention, the first extended separator structure DB1 and the first extended separator structure DB2 can be directly connected to the second extended separator structure CDB1. Additionally, the first extended separator structure DB1 and the first extended separator structure DB2 can be directly connected to the second extended separator structure CDB2.

[0083] The first extended partition structure DB1 and the first extended partition structure DB2 may be spaced apart from each other in the first direction D1. The first extended partition structure DB1 and the first extended partition structure DB2 may be spaced apart from the gate structures GS1, GS2 and GS3 in the first direction D1.

[0084] The first extension separator DB1 can separate the first active pattern AP1 and the second active pattern AP2. The first extension separator DB1 can be placed between the first epitaxial pattern 150 and the second epitaxial pattern 250. The first extension separator DB1 can be placed between the first epitaxial pattern 150 that is closest to (e.g., adjacent to) the second active pattern AP2 and the second epitaxial pattern 250 that is closest to (e.g., adjacent to) the first active pattern AP1.

[0085] The first extended separator structure DB1 can contact the gate separator structure GCS. The short side of the first extended separator structure DB1 can contact the gate separator structure GCS. For example, the first extended separator structure DB1 can contact the side of the gate separator pattern GCP facing the second direction D2.

[0086] According to an exemplary embodiment of the present invention, the first extended separation structure DB1 can separate the fourth active pattern AP4 and the fifth active pattern AP5.

[0087] The first extension separator DB2 can separate the second active pattern AP2 and the third active pattern AP3. The first extension separator DB2 can be placed between the second epitaxial pattern 250 and the third epitaxial pattern 350. The first extension separator DB2 can be placed between the second epitaxial pattern 250 closest to the third active pattern AP3 and the third epitaxial pattern 350 closest to the second active pattern AP2.

[0088] The first extended separator structure DB2 can contact the gate separator structure GCS. The short side of the first extended separator structure DB2 can contact the gate separator structure GCS. For example, the first extended separator structure DB2 can contact the side of the gate separator pattern GCP facing the second direction D2.

[0089] According to an exemplary embodiment of the present invention, the first extended separation structure DB2 can separate the fourth active pattern AP4 and the fifth active pattern AP5.

[0090] The first extended partition structure DB1 and the first extended partition structure DB2 may each include a core partition pattern 170 and a partition sidewall pattern 175. The partition sidewall pattern 175 may be placed on the sidewall of the core partition pattern 170.

[0091] The core separator pattern 170 can extend in the second direction D2. The core separator pattern 170 of the first extended separator structure DB1 can separate the first active pattern AP1 and the second active pattern AP2. In addition, the core separator pattern 170 of the first extended separator structure DB2 can separate the second active pattern AP2 and the third active pattern AP3. Similarly, the core separator pattern 170 can separate the fourth to sixth active patterns AP4 to AP6.

[0092] exist Figure 2 and Figure 5 Although the depth from the upper surface of the second active pattern AP2 to the lowermost part of the core separator pattern 170 is shown as the same as the height of the first to third active patterns AP1 to AP3, the inventive concept is not limited thereto. Unlike the illustrated case, as an example, the depth from the upper surface of the second active pattern AP2 to the lowermost part of the core separator pattern 170 may be less than the height of the first to third active patterns AP1 to AP3. As another example, the depth from the upper surface of the second active pattern AP2 to the lowermost part of the core separator pattern 170 may be greater than the height of the first to third active patterns AP1 to AP3.

[0093] The bottom surface of the core separator pattern 170 may be defined by the field insulating film 105, the substrate 100, and the remaining active pattern RF. The remaining active pattern RF may be the portion remaining after the active pattern portion has been removed in the etching process used to form the core separator pattern 170. Alternatively, unlike the case shown, there may be no remaining active pattern RF.

[0094] During the etching process used to form the core separator pattern 170, a portion of the field insulating film 105 is removed, and the upper surface of the field insulating film 105 facing the bottom surface of the core separator pattern 170 can be lowered. For example, the upper surface of the field insulating film 105 facing the bottom surface of the core separator pattern 170 can be lower than the upper surface of the field insulating film 105 facing the bottom surface of the gate electrode 120.

[0095] The upper surface 170us of the core separator pattern 170 can be placed on the same plane as the upper surfaces of the gate structures GS1 to GS3. The upper surfaces of the gate structures GS1 to GS3 can be the upper surface 145us of the gate cover pattern 145. In other words, the upper surface 170us of the core separator pattern can be placed on the same plane as the upper surface 145us of the gate cover pattern 145.

[0096] The core separator pattern 170 may include at least one of the following: silicon nitride (SiN), silicon oxide nitride (SiON), silicon oxide (SiO2), silicon oxide carbon nitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon oxide carbide (SiOC), aluminum oxide (AlO), and combinations thereof.

[0097] The separating sidewall pattern 175 may include a high dielectric constant pad 176 and a conductive separating pad 177.

[0098] The conductive spacer 177 can be placed between the high dielectric constant spacer 176 and the core spacer pattern 170.

[0099] The high-dielectric-constant pad 176 may include a high-dielectric-constant dielectric film comprising metal. Considering the manufacturing process, since the high-dielectric-constant pad 176 is retained after the gate insulating film 130 is etched, the high-dielectric-constant pad 176 may include materials included in the gate insulating film 130.

[0100] Considering the manufacturing process, the conductive spacer 177 can be retained after the gate electrode 120 is etched. The conductive spacer 177 may include the material included in the gate electrode 120.

[0101] The core separator pattern 170 may include a first sidewall 170_s1 and a second sidewall 170_s2 that are opposite to each other. The separator sidewall pattern 175 may be placed on at least one of the first sidewall 170_s1 and the second sidewall 170_s2.

[0102] exist Figure 7 and Figure 8 In this configuration, the dividing sidewall pattern 175 can be placed on the first sidewall 170_s1 and the second sidewall 170_s2 of the core dividing pattern 170. In contrast, in Figure 9 In the middle, the dividing sidewall pattern 175 can be placed on the first sidewall 170_s1 of the core dividing pattern 170, but not on the second sidewall 170_s2 of the core dividing pattern 170.

[0103] exist Figures 7 to 9 In the core separation pattern 170, the separation sidewall pattern 175 on the first sidewall 170_s1 may include an L-shaped high dielectric constant pad 176. For example, the high dielectric constant pad 176 may include a bottom 176L extending in a first direction D1, which is the extension direction of the second active pattern AP2, and a vertical extension 176V extending in a third direction D3, which is the thickness direction of the substrate 100.

[0104] The bottom 176L of the high dielectric constant pad 176 may include a first end and a second end opposite to each other in a first direction D1. A vertical extension 176V of the high dielectric constant pad 176 may extend from the first end of the bottom 176L in a third direction D3. The second end of the bottom 176L of the high dielectric constant pad 176 may face the sidewall of the core separator pattern 170. The bottom 176L of the high dielectric constant pad 176 may be inserted between the second active pattern AP2 and the conductive separator pad 177.

[0105] exist Figure 7 In the process, an L-shaped high dielectric constant pad 176 can be placed on the first sidewall 170_s1 and the second sidewall 170_s2 of the core separator pattern 170.

[0106] exist Figure 8 In the process, an L-shaped high dielectric constant pad 176 can be placed on the first sidewall 170_s1 of the core separator pattern 170. On the other hand, a linear high dielectric constant pad 176, rather than an L-shaped high dielectric constant pad 176, is placed on the second sidewall 170_s2 of the core separator pattern 170.

[0107] exist Figure 5 In this process, a high dielectric constant pad 176 extending along the sidewall of the gate separator structure GCS can be placed between the core separator pattern 170 and the gate separator structure GCS.

[0108] Because the separator sidewall pattern 175 is retained after etching the gate electrode 120 and the gate insulating film 130, the separator sidewall pattern 175 can be placed on a portion of the sidewall of the core separator pattern 170. The upper surface of the separator sidewall pattern 175 is 170 μs lower than the upper surface of the core separator pattern 170.

[0109] Each of the first extended partition structure DB1 and the first extended partition structure DB2 can have selected from Figures 7 to 9 The shape of the first extended separator DB1. In other words, the shape of the first extended separator DB2 may be the same as or different from the shape of the first extended separator DB2.

[0110] Because the core separator pattern 170 is formed as a through-gate cover pattern 145, the cut gate cover pattern 145_c can be placed on the sidewall of the core separator pattern 170, such as... Figure 2 As shown. In addition, the gate spacer 140 can be placed on the first sidewall 170_s1 and the second sidewall 170_s2 of the core spacer pattern 170.

[0111] The second extended separator structure CDB1 and the second extended separator structure CDB2 can be spaced apart from each other in the second direction D2. The second extended separator structure CDB1 and the second extended separator structure CDB2 can be placed on the gate separator structure GCS.

[0112] The second extended separator structure CDB1 and the second extended separator structure CDB2 can be placed on a portion of the gate separator structure GCS formed in the first direction D1. The second extended separator structure CDB1 and the second extended separator structure CDB2 can be placed on some of a plurality of gate separator patterns GCP.

[0113] The second extended partition structure CDB1 and the second extended partition structure CDB2 may each have a linear shape extending in the first direction D1. Figure 4In this configuration, multiple gate separator patterns (GCPs) can protrude from the bottom surface of a second extended separator structure (CDB1) extending in the first direction (D1) toward the substrate 100. A first interlayer insulating film (191) is interposed between the second extended separator structure (CDB1) and the field insulating film (105).

[0114] In a semiconductor device according to an exemplary embodiment of the present invention, the width of the second extended separator structure CDB1 in the second direction D2 may be smaller than the width of the gate separator structure GCS in the second direction D2. The upper surface of the second extended separator structure CDB1 may be placed on the same plane as the upper surface of the gate separator structure GCS and the upper surface 145µs of the gate cover pattern 145. The upper surface of the second extended separator structure CDB1 may be placed on the same plane as the upper surface of the first extended separator structure DB1.

[0115] Unlike the first extended separator structures DB1 and DB2, the second extended separator structures CDB1 and CDB2 do not include the separator sidewall pattern 175. In a semiconductor device according to an exemplary embodiment of the present invention, the film structures of the first extended separator structures DB1 and DB2 are different from the film structures of the second extended separator structures CDB1 and CDB2.

[0116] On the other hand, since the second extended partition structure CDB1 and the second extended partition structure CDB2 are formed substantially simultaneously with the core partition pattern 170, each of the second extended partition structure CDB1 and the second extended partition structure CDB2 can have a membrane structure substantially the same as the core partition pattern 170. The core partition pattern 170 included in the second extended partition structure CDB1, the second extended partition structure CDB2, the first extended partition structure DB1, and the first extended partition structure DB2 can have a closed-loop shape.

[0117] Here, when the core separator pattern 170 is a single film, the core separator pattern 170 can be formed of the same material as the second extended separator structure CDB1 and the second extended separator structure CDB2. When the core separator pattern 170 is a multilayer film, the order of the stacked films included in the core separator pattern 170 can be the same as the order of the stacked films included in the second extended separator structure CDB1 and the second extended separator structure CDB2.

[0118] When the core separator pattern 170 and the gate separator structure GCS are formed from a single film and the core separator pattern 170 and the gate separator structure GCS are formed from the same material, the boundary between the second extended separator structure CDB1 and the gate separator structure GCS can be indistinguishable.

[0119] Although a single second gate structure GS2 is shown as being placed between the first extended separator structure DB1 and the first extended separator structure DB2, this is only for illustrative purposes and the inventive concept is not limited thereto.

[0120] Source / drain contacts 160 may be placed on epitaxial patterns 150, 250, and 350. According to an exemplary embodiment of the present invention, a metal silicide film may be placed between the source / drain contacts 160 and the epitaxial patterns 150, 250, and 350.

[0121] exist Figure 2 In this process, the upper surfaces of the source / drain contacts 160 can be different from each other. The upper surface of the source / drain contacts 160 of the wiring structure 195 connected to the BEOL (back-end process) is higher than the upper surface of the source / drain contacts 160 not connected to the wiring structure 195.

[0122] The first interlayer insulating film 191 can be placed on the field insulating film 105. The first interlayer insulating film 191 can surround the sidewalls of the gate structures GS1 to GS3. The upper surface of the first interlayer insulating film 191 can be placed on the same plane as the upper surface 145µs of the gate cover pattern 145.

[0123] The second interlayer insulating film 192 may be placed on the first interlayer insulating film 191. Each of the first interlayer insulating film 191 and the second interlayer insulating film 192 may include, for example, but not limited to, silicon oxide, silicon nitride, silicon nitride oxide, FOX (flowable oxide), TOSZ (Toron silazane), USG (undoped silicon glass), BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), PETEOS (plasma-enhanced tetraethyl orthosilicate), FSG (fluorinated silicate glass), CDO (carbon-doped silicon oxide), degel, aerogel, amorphous fluorinated carbon, OSG (organosilicate glass), parylene, BCB (bisbenzocyclobutene), SiLK, polyimide, porous polymeric materials, or combinations thereof.

[0124] Wiring structure 195 can be placed in the second interlayer insulating film 192. Wiring structure 195 may include a path 196 and a line wiring 197. Path 196 and line wiring 197 may include conductive material.

[0125] Figure 10 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention. Figure 11 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to the concept of the present invention. For ease of explanation, the main description will be based on references to... Figures 1 to 9 The components described are different components.

[0126] Reference Figure 10 In a semiconductor device according to an exemplary embodiment of the present invention, no high dielectric constant pad 176 is placed between the core separator pattern 170 and the gate separator structure GCS.

[0127] During the etching process that forms the core separator pattern 170, the gate insulating film extending along the sidewalls of the gate separator structure GCS can be completely removed. Figure 6 (of 130).

[0128] Reference Figure 11 In a semiconductor device according to an exemplary embodiment of the present invention, the first extended partition structure DB1 and the first extended partition structure DB2 may include an air gap AG_SEAM.

[0129] For example, the core separator pattern 170 may include an air gap AG_SEAM. The air gap AG_SEAM may be surrounded by the core separator pattern 170.

[0130] Figure 12 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention. Figure 13 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to the concept of the present invention. For ease of explanation, the main description will be based on references to... Figures 1 to 9 The components described are different components.

[0131] Reference Figure 12 In a semiconductor device according to an exemplary embodiment of the present invention, the separating sidewall pattern 175 may consist only of a high dielectric constant pad 176.

[0132] During the process of forming the core separator pattern 170, the gate electrode can be completely removed. Figure 2 (of 120).

[0133] The core separator pattern 170 may include a lower portion 170a, a width extension portion 170b, and an upper portion 170c. The width extension portion 170b may be disposed on the upper surface of the active pattern (e.g., the first active pattern AP1). The width extension portion 170b of the core separator pattern 170 may be placed on the lower portion 170a of the core separator pattern 170. The upper portion 170c of the core separator pattern 170 may be placed on the width extension portion 170b of the core separator pattern 170.

[0134] The lower surface of the width extension 170b of the core separator pattern 170 can contact the high dielectric constant pad 176. The upper surface of the width extension 170b of the core separator pattern can contact the diced gate cover pattern 145_c.

[0135] A portion of the width extension 170b of the core separator pattern 170 may be located at the bottom of the high dielectric constant pad 176 having an L-shape. Figure 7 Extending above 176L.

[0136] Reference Figure 13 In a semiconductor device according to an exemplary embodiment of the present invention, the first extended partition structure DB1 and the first extended partition structure DB2 may consist only of the core partition pattern 170.

[0137] During the process of forming the core separator pattern 170, the gate electrode can be removed ( Figure 2 120) and gate insulating film ( Figure 2 (130) Both.

[0138] The core separator pattern 170 may include a lower portion 170a, a width extension portion 170b, and an upper portion 170c. The width extension portion 170b of the core separator pattern 170 may be placed on the lower portion 170a of the core separator pattern 170. The upper portion 170c of the core separator pattern 170 may be placed on the width extension portion 170b of the core separator pattern 170.

[0139] At the boundary between the width extension 170b and the upper portion 170c, the width of the width extension 170b in the first direction D1 is greater than the width of the upper portion 170c in the first direction D1. Based on (e.g., relative to) the upper surface of the second active pattern AP2, the boundary between the width extension 170b and the upper portion 170c can have substantially the same height as the upper surface of the gate electrode 120. The upper surface of the width extension 170b can contact the diced gate overlay pattern 145_c.

[0140] Since the first extended partition structure DB1 and the first extended partition structure DB2 only include the core partition pattern 170, the membrane structure of the first extended partition structure DB1 and the first extended partition structure DB2 can be basically the same as the membrane structure of the second extended partition structure CDB1 and the second extended partition structure CDB2.

[0141] However, when the core separator pattern 170 includes an air gap (e.g., Figure 11 When AG_SEAM is used, the second extended partition structure CDB1 and the second extended partition structure CDB2 may not include an air gap.

[0142] Figures 14 to 16 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to the concept of the present invention. For ease of explanation, the main description will be based on references to... Figures 1 to 9 The components described are different components.

[0143] Reference Figures 14 to 16In a semiconductor device according to an exemplary embodiment of the present invention, the core separator pattern 170 may include a core separator pad 171 and a core fill pattern 172.

[0144] Core spacer 171 may be formed on substrate 100. Core spacer 171 may define a filling spacer trench 171R.

[0145] The core spacer 171 may extend to the upper surface 145u of the gate cover pattern 145. The uppermost surface of the core spacer 171 may be placed on the same plane as the upper surface 145u of the gate cover pattern 145.

[0146] The core fill pattern 172 can be placed on the core spacer pad 171. The core fill pattern 172 can fill the fill spacer trench 171R. The upper surface of the core fill pattern 172 can be placed on the same plane as the upper surface 145us of the gate cover pattern 145.

[0147] The first extended partition structure DB1, the first extended partition structure DB2, the second extended partition structure CDB1, and the second extended partition structure CDB2 all include a core partition pattern 170. Therefore, the first extended partition structure DB1, the first extended partition structure DB2, the second extended partition structure CDB1, and the second extended partition structure CDB2 may include a core partition liner 171 and a core fill pattern 172.

[0148] Because the component separation structure DCS has a closed-loop shape, the core filling pattern 172 can also have a closed-loop shape.

[0149] The core separator liner 171 and the core filling pattern 172 may include materials that are different from each other.

[0150] Although the core separator pattern 170 is shown as having a double-layer membrane structure, this is merely for illustrative purposes, and the inventive concept is not limited thereto. In other words, the core separator liner 171 may have a multilayer membrane structure.

[0151] Figure 17 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention. Figure 18 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention. Figure 19 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention. Figure 20 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention. Figure 21 This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention. Figure 22This is a diagram illustrating an exemplary embodiment of a semiconductor device according to a concept proposed in this invention. For ease of explanation, the main description will be based on references to... Figures 1 to 9 The components described are different components.

[0152] Reference Figure 17 In a semiconductor device according to an exemplary embodiment of the present invention, the bottom surface of the second extended partition structure CDB1 and the bottom surface of the second extended partition structure CDB2 may have unevenness.

[0153] For example, the upper surface of the second extended partition structure CDB1 can be placed on the same plane as the upper surface of the gate partition structure GCS and the upper surface of the first interlayer insulating film 191.

[0154] On the other hand, based on the upper surface of the field insulating film 105, the height of the bottom surface of the portion of the second extended partition structure CDB1 that overlaps with the gate partition pattern GCP may be different from the height of the bottom surface of the portion of the second extended partition structure CDB1 that overlaps with the first interlayer insulating film 191.

[0155] During the etching process used to form the second extended separator structure CDB1, the etching rates between the gate separator pattern GCP and the first interlayer insulating film 191 can be different. As a result, the bottom surface of the second extended separator structure CDB1 can have unevenness.

[0156] Alternatively, unlike the case shown, the height of the bottom surface of the portion of the second extended partition structure CDB1 that overlaps with the gate partition pattern GCP may be lower than the height of the bottom surface of the portion of the second extended partition structure CDB1 that overlaps with the first interlayer insulating film 191, based on the upper surface of the field insulating film 105.

[0157] Reference Figure 18 In a semiconductor device according to an exemplary embodiment of the present invention, the gate separation structure GCS may have a first orientation ( Figure 1 The elongated line on D1).

[0158] In the etching process that forms the gate separator structure (GCS), the portion corresponding to the gate and the portion corresponding to the first interlayer insulating film are etched. Figure 4 Both of the portions of 191) can form a linear trench extending in the first direction D1. The linear trench can be filled with an insulating material to form a gate separation structure GCS with a linear shape.

[0159] Reference Figure 19 In a semiconductor device according to an exemplary embodiment of the present invention, the gate insulating film 130 may not extend along the sidewall of the gate separation structure GCS.

[0160] No gate insulating film 130 is placed between the short side of the gate electrode 120 and the sidewall of the gate separation structure GCS.

[0161] In this case, such as Figure 10 As shown, high dielectric constant pad ( Figure 5 176) does not extend along the sidewall of the gate separator structure GCS between the first extended separator structure DB1 and the gate separator structure GCS.

[0162] Reference Figure 20 In a semiconductor device according to an exemplary embodiment of the present invention, the width of the second extended separator structure CDB1 in the second direction D2 may be greater than or equal to the width of the gate separator structure GCS in the second direction D2.

[0163] Reference Figure 21 In a semiconductor device according to an exemplary embodiment of the present invention, the wiring structure 195 does not include a path, but may only include linear line wiring.

[0164] This allows the wiring structure 195 to contact the gate cover pattern 145.

[0165] Reference Figure 22 A semiconductor device according to an exemplary embodiment of the present invention may include a protruding pattern DPF protruding from the substrate 100 between a first active pattern AP1 and a fourth active pattern AP4.

[0166] The height of the protruding pattern DPF is less than the height of the first active pattern AP1 and the fourth active pattern AP4. The height of the protruding pattern DPF is less than the height of the field insulating film 105 overlapping with the gate electrode 120. The protruding pattern DPF can, for example, be in the first direction ( Figure 1 It extends on D1, but is not limited to it.

[0167] The raised pattern DPF can also be placed below the gate separator structure GCS.

[0168] Figure 23 This is a layout diagram used to illustrate an exemplary embodiment of a semiconductor device according to the concept of the present invention. Figure 24 and Figure 25 This is along the exemplary embodiments of the concept of the present invention. Figure 23 The cross-sectional view is taken from lines AA and EE. For ease of explanation, the main descriptions and references will be provided. Figures 1 to 9 The components described are different components.

[0169] Reference Figures 23 to 25In a semiconductor device according to an exemplary embodiment of the present invention, the first to third active patterns AP1 to AP3 may respectively include the first to third lower patterns BP1 to BP3 and the first to third sheet patterns UP1 to UP3.

[0170] According to an exemplary embodiment of the present invention, each of the fourth to sixth active patterns AP4 to AP6 may also include a lower pattern and a sheet pattern. For example, the fourth active pattern AP4 may include a fourth lower pattern BP4 and a fourth sheet pattern UP4, such as... Figure 25 As shown.

[0171] The first to third lower patterns BP1 to BP3 can be arranged in a row along the first direction D1. The second lower pattern BP2 can be spaced apart from the first lower pattern BP1 and the third lower pattern BP3 along the first direction D1.

[0172] The first lower pattern BP1 and the second lower pattern BP2, as well as the second lower pattern BP2 and the third lower pattern BP3, can be separated by the first extended dividing structure DB1 and the first extended dividing structure DB2, respectively.

[0173] The first sheet pattern UP1 may be placed on top of the first lower pattern BP1, spaced apart from it. The first sheet pattern UP1 may include multiple sheet patterns. Although the number of first sheet patterns UP1 is shown as three, this is for illustrative purposes only, and the number is not limited thereto. The second and third sheet patterns UP2 and UP3 may be similar to the first sheet pattern UP1.

[0174] The first to third sheet patterns UP1 to UP3 can be connected to the first to third epitaxial patterns 150, 250, and 350, respectively. Each of the first to third sheet patterns UP1 to UP3 can be a channel pattern used as a channel region for a transistor. For example, each of the first to third sheet patterns UP1 to UP3 can be a nanosheet or a nanowire.

[0175] The descriptions of the fourth to sixth active patterns AP4 to AP6 are basically the same as those of the first to third active patterns AP1 to AP3, and therefore are omitted.

[0176] Although the two types of sheet patterns arranged on the second direction D2 (e.g., the sheet pattern of the first active pattern AP1 and the sheet pattern of the fourth active pattern AP4) are shown as being located between adjacent gate separation structures GCS on the second direction D2, this is only for the sake of illustration and their number is not limited thereto.

[0177] The first to third gate structures GS1 to GS3 can be placed on the lower pattern of the first to sixth active patterns AP1 to AP6. The gate insulating film 130 and gate electrode 120 of the first to third gate structures GS1 to GS3 can surround the first to third sheet patterns UP1 to UP3. According to an exemplary embodiment of the present invention, the gate insulating film 130 and gate electrode 120 of the first to third gate structures GS1 to GS3 can surround the sheet patterns of the fourth to sixth active patterns AP4 to AP6.

[0178] exist Figure 23 and Figure 24 Although the gate insulating film 130 located between the sheet patterns UP1 to UP3 adjacent to each other on the third direction D3 is shown to be in contact with the first to third epitaxial patterns 150, 250 and 350, the inventive concept is not limited thereto. Unlike the illustration, inner spacers may be placed between the gate insulating film 130 and the first to third epitaxial patterns 150, 250 and 350 and / or between the sheet patterns UP1 to UP3 adjacent to each other on the third direction D3.

[0179] The diced sheet pattern UP_R can be placed on the first sidewall 170_s1 and the second sidewall 170_s2 of the core separator pattern 170. The diced sheet pattern UP_R can be the pattern left after some of the sheet patterns UP1 to UP3 have been removed in the etching process used to form the element separator structure DCS.

[0180] A portion of the gate electrode 120 and the gate insulating film 130 may be interposed between adjacent cut-out patterns UP_R on the third direction D3.

[0181] Figure 26 This is a layout diagram used to illustrate an exemplary embodiment of a semiconductor device according to the concept of the present invention. Figure 27 This is along the exemplary embodiments of the concept of the present invention. Figure 26 The cross-sectional view taken from line AA. For ease of explanation, the main description and references will be... Figures 1 to 9 The components described are different components.

[0182] Reference Figure 26 and Figure 27 In a semiconductor device according to an exemplary embodiment of the present invention, no gate structure is placed between the first extended separator structure DB1 and the first extended separator structure DB2 (e.g., Figure 1 The second gate structure GS2).

[0183] No gate electrodes intersecting with the second active pattern AP2 and the fifth active pattern AP5 are placed on them.

[0184] Between the first extended separator DB1 and the first extended separator DB2, only one second epitaxial pattern 250 can be placed on the second active pattern AP2. Similarly, only one epitaxial pattern can be placed on the fifth active pattern AP5.

[0185] Figure 28 This is a layout diagram used to illustrate an exemplary embodiment of a semiconductor device according to the concept of the present invention. Figure 29 This is along the exemplary embodiments of the concept of the present invention. Figure 28 The cross-sectional view taken from line AA. For ease of explanation, the main description and references will be... Figures 1 to 9 The components described are different components.

[0186] Reference Figure 28 and Figure 29 In a semiconductor device according to an exemplary embodiment of the present invention, a first extended partition structure DB1 may be placed between a first gate structure GS1 and a second gate structure GS2, and a first extended partition structure DB2 may be placed between a second gate structure GS2 and a third gate structure GS3.

[0187] The first extended separator structures DB1 and DB2 can be placed by cutting the epitaxial pattern. Among the gate structure and epitaxial pattern placed on the active pattern, the gate structure, rather than the epitaxial pattern, can be closest to the first extended separator structures DB1 and DB2.

[0188] The etched epitaxial pattern EPI_R can be placed on both sides of the first extension separator DB1 and the first extension separator DB2.

[0189] Because the first extended partition structure DB1 and the first extended partition structure DB2 are not formed at the location where a portion of the gate structure is removed, each of the first extended partition structure DB1 and the first extended partition structure DB2 may consist only of the core partition pattern 170.

[0190] Figure 30 This is a layout diagram used to illustrate exemplary embodiments of semiconductor devices according to the present invention. For ease of explanation, the main description will be based on references to... Figures 1 to 9 The components described are different components.

[0191] For reference, along Figure 30 The cross-sectional view taken by line AA can be compared with Figure 2 The cross-sectional views are the same.

[0192] Reference Figure 30In a semiconductor device according to an exemplary embodiment of the present invention, the element separation structure DCS does not include a second extended separation structure CDB1 and a second extended separation structure CDB2 extending in the first direction D1.

[0193] The component separation structure DCS includes a first extended separation structure DB1 and a first extended separation structure DB2 that extend in the second direction D2 and are spaced apart from each other in the first direction D1.

[0194] In other words, in this example, the component separation structure DCS does not have a closed-loop shape.

[0195] Figure 31 This is a layout diagram illustrating an exemplary embodiment of a semiconductor device according to a concept proposed in this invention. For reference, Figure 31 Only the gate partition structure GCS extending in the first direction D1, the gate pattern GS between the gate partition structures GCS, and the element partition structure DCS are shown; other structures are not shown. Figure 1 The active patterns AP1 to AP6 in the diagram.

[0196] also, Figure 31 The gate pattern GS can correspond to Figure 1 The gate structures GS1 to GS3.

[0197] Reference Figure 31 In a semiconductor device according to an exemplary embodiment of the present invention, the component separation structure DCS may include a third extended separation structure DB3_1, a third extended separation structure DB3_2, and a third extended separation structure DB3_3 extending in the second direction D2. The component separation structure DCS may also include a fourth extended separation structure CDB3, a fourth extended separation structure CDB4, and a fourth extended separation structure CDB5 extending in the first direction D1.

[0198] The third extended partition structure DB3_1, the third extended partition structure DB3_2, and the third extended partition structure DB3_3 can be connected to the fourth extended partition structure CDB3, the fourth extended partition structure CDB4, and the fourth extended partition structure CDB5.

[0199] The third extended partition structure DB3_1, the third extended partition structure DB3_2 and the third extended partition structure DB3_3 can be aligned with the gate pattern GS extending in the second direction D2.

[0200] The fourth extended partition structure CDB3, the fourth extended partition structure CDB4 and the fourth extended partition structure CDB5 can overlap with the gate partition structure GCS on the third direction D3 on the gate partition structure GCS extending along the first direction D1.

[0201] The third extended partition structure DB3_1, the third extended partition structure DB3_2, and the third extended partition structure DB3_3 can correspond to Figure 1 One of the first extended partition structure DB1 and the first extended partition structure DB2.

[0202] The fourth extended partition structure CDB3, the fourth extended partition structure CDB4, and the fourth extended partition structure CDB5 can correspond to Figure 1 One of the second extended partition structure CDB1 and the second extended partition structure CDB2.

[0203] The element partition structure DCS can be placed between three or more gate partition structures GCS arranged in the second direction D2.

[0204] The closed-loop shape of the component partitioning structure DCS can vary widely depending on the layout of the semiconductor devices to be manufactured.

[0205] Figures 32 to 36 This is an intermediate stage diagram illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention. For reference, Figure 32 It is a layout diagram used to illustrate the method of manufacturing semiconductor devices. Figures 33 to 36 It is along Figure 32 The intermediate stage cross-section diagram taken from line AA.

[0206] Reference Figure 32 and Figure 33 The first pre-active pattern PAP1, the second pre-active pattern PAP2, and the pre-gate structure PGS can be placed between the gate separation structures GCS formed along the first direction D1.

[0207] The first pre-active pattern PAP1 and the second pre-active pattern PAP2 may extend in the first direction D1. The first pre-active pattern PAP1 and the second pre-active pattern PAP2 may be spaced apart from each other in the second direction D2.

[0208] The pre-gate structure PGS can extend in the second direction D2. The pre-gate structures PGS can be spaced apart from each other in the first direction D1. The pre-gate structure PGS may include a gate electrode 120, a gate insulating film 130, a gate spacer 140, and a gate cover pattern 145.

[0209] Source / drain epitaxial EPIs can be placed between pre-gate structures PGS that are adjacent to each other along the first direction D1. The source / drain epitaxial EPIs can be placed on a first pre-active pattern PAP1. According to an exemplary embodiment of the present invention, the source / drain epitaxial EPIs can be placed on a second pre-active pattern PAP2.

[0210] A first interlayer insulating film 191 is formed to cover the source / drain epitaxial EPI. The upper surface of the first interlayer insulating film 191 can be placed on the same plane as the upper surface of the gate cover pattern 145. The pregate structure PGS may include multiple pregate structures separated by the first interlayer insulating film 191.

[0211] A molded interlayer insulating film 193 can be formed on the first interlayer insulating film 191 and the pre-gate structure PGS.

[0212] A mask pattern with a polygonal shape can be formed on the die interlayer insulating film 193. The mask pattern can be formed on a portion of the pre-gate structure PGS (e.g., overlapping a portion of the pre-gate structure PGS). In other words, the die interlayer insulating film 193 is disposed between the mask pattern and the portion of the pre-gate structure PGS.

[0213] Next, a replacement pattern PR_PAT can be formed along the sidewalls of the mask pattern MASK. The replacement pattern PR_PAT can have a closed-loop shape in which the portions extending in the first direction D1 and the portions extending in the second direction D2 are connected.

[0214] The portion of the replacement pattern PR_PAT extending in the first direction D1 can be placed at the location where it overlaps with the gate separator structure GCS in the third direction D3. The portion of the replacement pattern PR_PAT extending in the second direction D2 can be placed at the location where it overlaps with the pre-gate structure PGS in the third direction D3.

[0215] Reference Figure 34 A filling mask pattern F_MASK can be formed on the interlayer insulating film 193 of the mold, surrounding the replacement pattern PR_PAT.

[0216] The fill mask pattern F_MASK covers the sidewalls of the replacement pattern PR_PAT, but does not cover the top surface of the replacement pattern PR_PAT.

[0217] The fill mask pattern F_MASK and the mask pattern MASK can include materials that have etch selectivity for the replacement pattern PR_PAT.

[0218] Reference Figure 35 By removing the replacement pattern PR_PAT, a component separation opening DB_OP can be formed between the fill mask pattern F_MASK and the mask pattern MASK.

[0219] The interlayer insulating film 193 of the mold can be exposed by the component separation opening DB_OP.

[0220] Reference Figure 36By using the filling mask pattern F_MASK and the mask pattern MASK as etching masks, the portions of the die interlayer insulating film 193, the gate cover pattern 145, the gate electrode 120, the gate insulating film 130, and the first pre-active pattern PAP1 that overlap with the element separation opening DB_OP can be removed.

[0221] It can be formed accordingly in the second direction ( Figure 32 The element-separating groove DB_H extends on D2).

[0222] According to an exemplary embodiment of the present invention, the element separation trench DB_H can also be formed in the gate separation structure ( Figure 32 In the GCS).

[0223] For example, by using the filling mask pattern F_MASK and the mask pattern MASK as an etching mask, the interlayer insulating film 193, the gate cover pattern 145 and the gate separation structure GCS can be partially removed until the gate electrode 120 is exposed.

[0224] After exposing the gate electrode 120, the gate electrode 120 and the gate insulating film 130 can be etched sequentially to expose the first pre-active pattern PAP1. The gate separator structure GCS may not be etched during the etching of the gate electrode 120 and the gate insulating film 130.

[0225] Next, by removing the exposed first pre-active pattern PAP1, first to third active patterns AP1 to AP3 that are adjacent to each other in the first direction D1 can be formed.

[0226] Next, the fill mask pattern F_MASK and the mask pattern MASK can be removed. Additionally, the core separator pattern for the fill element separator trench DB_H can be formed. Figure 2 (170).

[0227] By using the method described above to separate active patterns, active patterns can be stably separated in scaled-down semiconductor devices. For example, the position where the element separation trench DB_H is formed corresponds to the position where the replacement pattern PR_PAT is formed. When the width of the replacement pattern PR_PAT changes in the first direction D1, the corresponding width of the element separation trench DB_H in the first direction D1 also changes. Therefore, even when the gate pitch and other parameters decrease, active patterns can be stably separated using the aforementioned method.

[0228] Alternatively, unlike the aforementioned case, before forming the element separation opening DB_OP, the replacement pattern PR_PAT overlapping the gate separation structure GCS on the third-direction D3 can be removed. Figure 32 (the portion extending in the first direction D1).

[0229] Next, mask material can be filled at the location where the portion of the replacement pattern PR_PAT extending in the first direction D1 is removed. When the component separation opening DB_OP is formed after such a process, a structure like... Figure 30 The component separation structure DCS is shown.

[0230] While the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various modifications in form and detail may be made therein without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

[0231] This application claims priority to Korean Patent Application No. 10-2020-0085972, filed on July 13, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: The first active pattern and the second active pattern each extend in the first direction; The first epitaxial pattern is placed on the first active pattern and disposed adjacent to the second active pattern; The second epitaxial pattern is placed on the second active pattern and disposed adjacent to the first active pattern; A component separation structure separates a first active pattern and a second active pattern between a first epitaxial pattern and a second epitaxial pattern, wherein the component separation structure includes a core separation pattern and a separation sidewall pattern on the sidewall of the core separation pattern. as well as A gate structure extends in a second direction intersecting the first direction and is disposed on the first active pattern. The upper surface of the gate structure is placed on the same plane as the upper surface of the core separator pattern. The separator sidewall pattern includes a high-dielectric-constant pad and a conductive separator pad placed between the core separator pattern and the high-dielectric-constant pad, the conductive separator pad contacting the sidewall of the core separator pattern. The high dielectric constant liner includes a high dielectric constant dielectric film containing metal.

2. The semiconductor device of claim 1, wherein the high dielectric constant pad has an L-shape.

3. The semiconductor device of claim 2, wherein the high dielectric constant pad includes a bottom extending in the first direction and a vertical extension extending upward in a third direction intersecting the first and second directions. The bottom of the high dielectric constant pad has a first end and a second end. The vertical extension of the high dielectric constant pad extends upward from the first end of the bottom of the high dielectric constant pad on the third side, and The second end of the bottom of the high dielectric constant pad faces the sidewall of the core separator pattern.

4. The semiconductor device of claim 1, wherein the gate structure comprises a gate electrode, and The conductive spacer includes the material included in the gate electrode.

5. The semiconductor device of claim 1, wherein the core separator pattern comprises first sidewalls and second sidewalls opposite to each other, and The dividing sidewall pattern is placed on the first sidewall and the second sidewall of the core dividing pattern.

6. The semiconductor device of claim 1, wherein the upper surface of the separating sidewall pattern is lower than the upper surface of the core separating pattern.

7. The semiconductor device of claim 1, wherein the core separator pattern comprises a core separator pad and a core fill pattern, the core fill pattern being placed on the core separator pad and filling a fill separator trench defined by the core separator pad.

8. The semiconductor device of claim 1, wherein each of the first active pattern and the second active pattern is a fin pattern.

9. A semiconductor device, comprising: The component separation structure includes a first extended separation structure and a second extended separation structure extending in a first direction, and a third extended separation structure and a fourth extended separation structure extending in a second direction different from the first direction, wherein the component separation structure has a closed-loop shape. The first active pattern and the second active pattern are separated by the first extended dividing structure and each extends in the second direction; A first gate structure extends in the first direction, includes a gate electrode, and is disposed on the first active pattern; as well as A gate separation structure is formed along the second direction and faces the first side of the gate electrode. The third extended partition structure is placed on a portion of the gate partition structure.

10. The semiconductor device of claim 9, wherein the first extended partition structure and the second extended partition structure each comprise a core partition pattern and a partition sidewall pattern on the sidewall of the core partition pattern. The partition sidewall pattern includes a high dielectric constant pad, and The high dielectric constant liner includes a high dielectric constant dielectric film containing metal.

11. The semiconductor device of claim 10, wherein the spacer sidewall pattern further comprises a conductive spacer pad disposed between the core spacer pattern and the high dielectric constant pad, and The conductive spacer includes the material included in the gate electrode.

12. The semiconductor device of claim 10, wherein the first gate structure comprises a gate insulating film extending along the sidewalls and bottom surface of the gate electrode, and The high dielectric constant pad includes the material included in the gate insulating film.

13. The semiconductor device of claim 10, wherein the third extended partition structure and the fourth extended partition structure do not include the high dielectric constant pad.

14. The semiconductor device of claim 9, wherein the third extended separation structure includes a core separator pad and a core fill pattern, the core fill pattern being placed on the core separator pad and filling a fill separation trench defined by the core separator pad.

15. A semiconductor device, comprising: The first active pattern and the second active pattern each extend in the first direction; The first epitaxial pattern is on the first active pattern; The second epitaxial pattern is on the second active pattern; A first element separation structure separates the first active pattern and the second active pattern between the first epitaxial pattern and the second epitaxial pattern; A gate structure extends on the first active pattern in a second direction intersecting the first direction; The gate separation structure is in contact with the first element separation structure; as well as A second element separator structure is placed on the gate separator structure and directly connected to the first element separator structure. The upper surface of the second element separator structure is placed on the same plane as the upper surface of the gate structure and the upper surface of the first element separator structure.

16. The semiconductor device of claim 15, wherein the first element separation structure has a film structure substantially the same as the second element separation structure.

17. The semiconductor device of claim 16, wherein the first element separation structure includes a width extension disposed on the upper surface of the first active pattern and an upper portion disposed on the width extension of the first element separation structure. At the boundary between the width extension of the first element separator structure and the upper part of the first element separator structure, the width of the width extension of the first element separator structure is greater than the width of the upper part of the first element separator structure.

18. The semiconductor device of claim 15, wherein the first element separation structure comprises a core separation pattern and a separation sidewall pattern on the sidewall of the core separation pattern. The partition sidewall pattern includes a high dielectric constant pad, and The high dielectric constant liner includes a high dielectric constant dielectric film containing metal.

19. The semiconductor device of claim 18, wherein the core separator pattern has a film structure substantially the same as the second element separator structure.

20. The semiconductor device of claim 15, wherein the first active pattern and the second active pattern each comprise a nanosheet.

Images