Three-dimensional memory devices and methods for fabricating the same

Abstract

Embodiments of the present application disclose a three-dimensional memory device and a preparation method thereof. The three-dimensional memory device comprises a laminated structure, and a plurality of channel structures penetrating through the laminated structure, wherein the channel structure comprises at least a channel layer, and a material of the channel layer comprises silicon; and a connecting layer, which is in contact with the channel layer, and a material of the connecting layer comprises a metal silicide.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a three-dimensional memory device and its fabrication method. Background Technology

[0002] To achieve electrical connectivity between the channel layer in a 3D memory device and external circuitry, the following method is typically used: first, metal contact pillars are used to connect the channel layer to electrical lead pads, and then the electrical lead pads are connected to the external circuitry. A polysilicon layer is often placed between the channel layer and the metal contact pillars as an intermediate bridge. However, the direct connection between the polysilicon layer and the channel layer has a high resistance, resulting in high resistance between the channel layer and the external circuitry. Furthermore, directly connecting the polysilicon layer and the channel layer is difficult and results in a weak connection. Summary of the Invention

[0003] To address at least one of the existing technical problems, this invention proposes a three-dimensional storage device and its fabrication method.

[0004] A first aspect of the present invention provides a three-dimensional storage device, comprising: Layered structure; A plurality of channel structures running through the stacked structure, each channel structure comprising at least a channel layer; wherein the material of the channel layer comprises silicon; A connecting layer that contacts the channel layer; wherein the material of the connecting layer includes metal silicide.

[0005] In the above scheme, the connecting layer is used for electrical connection with the electrical lead-out pad.

[0006] In the above scheme, the three-dimensional storage device further includes a semiconductor layer covering the interconnect layer; the semiconductor layer is used to electrically connect the interconnect layer to the electrical lead-out pad.

[0007] In the above scheme, the material of the connecting layer includes nickel silicide.

[0008] In the above scheme, the connection layer includes a first part and a second part; wherein, The first portion extends into the channel layer, and the cross-sectional shape of the first portion parallel to the first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the layered structure; The second part covers the stacked structure and the channel structure.

[0009] In the above scheme, the connection layer includes a first part and a second part; wherein, The three-dimensional memory device further includes a substrate located between the stacked structure and the second portion; the channel structure extends through the substrate, and the substrate is made of silicon. The first portion extends into the channel layer, and the cross-sectional shape of the first portion parallel to the first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the layered structure; The second portion covers the substrate and the channel structure.

[0010] In the above scheme, the connection layer includes a first part and a second part; wherein, The first portion extends into the channel layer, and the cross-sectional shape of the first portion parallel to the first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the layered structure; The channel structure further includes a portion extending out of the stacked structure; the portion of the channel structure extending out of the stacked structure contacts the second portion; the second portion also covers the stacked structure.

[0011] In the above scheme, the connection layer includes a first part and a second part; wherein, The first portion extends into the channel layer, and the cross-sectional shape of the first portion parallel to the first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the layered structure; The second portion extends into the semiconductor layer, and the cross-sectional shape of the second portion parallel to the first plane is the same as the cross-sectional shape of the first portion.

[0012] In the above scheme, the three-dimensional storage device further includes: a metal contact post located above the connection layer, the metal contact post being used to connect the connection layer to the electrical lead-out pad.

[0013] A second aspect of this invention provides a method for fabricating a three-dimensional storage device, comprising: A semiconductor structure is provided; the semiconductor structure includes a substrate, a stacked structure covering the surface of the substrate, and a channel structure extending through the stacked structure and extending to the substrate; wherein the channel structure includes at least a channel layer; and the materials of the substrate and the channel layer include at least silicon. Remove at least a portion of the substrate to expose a portion of the channel layer; A connecting layer is formed in contact with the exposed portion of the channel layer; the material of the connecting layer includes metal silicides.

[0014] In the above scheme, the connecting layer is used for electrical connection with the electrical lead-out pad.

[0015] The method in the above scheme further includes: A semiconductor layer is formed on the interconnect layer; the interconnect layer is electrically connected to the electrical lead-out pad through the semiconductor layer.

[0016] In the above scheme, the material of the connecting layer includes nickel silicide.

[0017] In the above scheme, removing at least a portion of the substrate to expose a portion of the trench layer includes: The entire substrate is removed to expose a portion of the channel layer; wherein, when removing the substrate, the channel structure extending to the substrate is also removed.

[0018] In the above scheme, the method further includes: forming a sacrificial semiconductor layer covering the stacked structure and the channel structure before forming the interconnect layer; the material of the sacrificial semiconductor layer includes silicon; The connecting layer includes a first portion and a second portion; the connecting layer forming contact with the exposed portion of the channel layer includes: Form a metal layer covering the sacrificial semiconductor layer; At a first temperature, the metal layer and a portion of the channel layer are silicided to form a first portion of the interconnect layer in the portion of the channel layer, while a second portion of the interconnect layer is formed in the metal layer and the sacrificial semiconductor layer; wherein the cross-sectional shape of the first portion parallel to a first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the stacked structure; the second portion covers the stacked structure and the channel structure.

[0019] In the above scheme, removing at least a portion of the substrate to expose a portion of the trench layer includes: A portion of the substrate is removed to expose a portion of the channel layer; wherein, when removing the substrate, the channel structure extending into the substrate is also removed.

[0020] In the above scheme, the connecting layer includes a first portion and a second portion; the connecting layer that forms contact with the exposed portion of the channel layer includes: A metal layer is formed covering the remaining substrate and the exposed portion of the trench layer; At a first temperature, the metal layer and a portion of the channel layer are silicided to form a first portion of the interconnect layer in the portion of the channel layer, while a second portion of the interconnect layer is formed in the metal layer; wherein the cross-sectional shape of the first portion parallel to a first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the layered structure; the second portion covers the remaining substrate and the channel structure.

[0021] In the above scheme, the channel structure includes a channel hole and a gate dielectric layer, a charge storage layer, a tunneling layer and a channel layer arranged radially along the channel hole; The removal of at least a portion of the substrate to expose a portion of the trench layer includes: Remove all of the substrate to expose the channel structure and stacked structure extending into the substrate; Remove the gate dielectric layer, charge storage layer, and tunneling layer of the channel structure extending into the substrate to expose the channel layer of the channel structure extending into the substrate.

[0022] In the above scheme, the method further includes: forming a sacrificial semiconductor layer covering the stacked structure and the channel layer before forming the interconnect layer; the material of the sacrificial semiconductor layer includes silicon; The connecting layer includes a first portion and a second portion; the connecting layer forming contact with the exposed portion of the channel layer includes: Form a metal layer covering the sacrificial semiconductor layer; At a first temperature, the metal layer and a portion of the channel layer are silicided to form a first portion of the interconnect layer in the unexposed portion of the channel layer, while a second portion of the interconnect layer is formed in the metal layer and the exposed portion of the channel layer; wherein the cross-sectional shape of the first portion parallel to a first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the laminated structure; the second portion covers the laminated structure and the channel structure extending into the substrate.

[0023] In the above scheme, removing at least a portion of the substrate to expose a portion of the trench layer includes: The entire substrate is removed to expose a portion of the channel layer; wherein, when removing the substrate, the channel structure extending to the substrate is also removed.

[0024] In the above scheme, the connecting layer includes a first portion and a second portion; the connecting layer that forms contact with the exposed portion of the channel layer includes: A metal layer is formed to cover the exposed portion of the trench layer; At a first temperature, the metal layer and a portion of the channel layer are subjected to a silicide reaction to form a first portion of the interconnect layer, while a second portion of the interconnect layer is formed in the metal layer; wherein, the cross-sectional shape of the first portion parallel to a first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the laminated structure; the cross-sectional shape of the second portion parallel to the first plane is the same as the cross-sectional shape of the first portion.

[0025] The method in the above scheme further includes: Metal contact posts are formed above the connecting layer to electrically connect the connecting layer to the electrical lead-out pad.

[0026] This invention provides a three-dimensional memory device and its manufacturing method. The three-dimensional memory device includes: a stacked structure; multiple channel structures penetrating the stacked structure, each channel structure including at least a channel layer; wherein the channel layer is made of silicon; and a connecting layer in contact with the channel layers; wherein the connecting layer is made of metal silicide. In this invention, the connecting layer serves as an intermediate bridge connecting the channel layers to the external circuit. Since the connecting layer is made of metal silicide, its low resistance reduces the resistance between the channel layer and the external circuit. Furthermore, because metal silicides have good thermal stability, they do not decompose or detach during subsequent heat treatment processes, thus achieving a more robust connection. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of a three-dimensional storage device provided in an embodiment of the present invention; Figures 2a to 2l A cross-sectional schematic diagram of the fabrication process of a three-dimensional storage device provided in an embodiment of the present invention; Figures 3a to 3c Three structural schematic diagrams of another three-dimensional storage device provided in the embodiments of the present invention; Figure 4 A schematic diagram of another three-dimensional storage device structure including metal contact pillars provided for an embodiment of the present invention; Figures 5a to 5c Three structural schematic diagrams of another three-dimensional storage device provided in the embodiments of the present invention; Figure 6 A schematic diagram of another three-dimensional storage device structure including metal contact pillars provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of another three-dimensional storage device structure provided in an embodiment of the present invention; Figure 8 for Figure 7A partial schematic diagram of the area within the dashed box shown; Figure 9 A flowchart illustrating the fabrication method of a three-dimensional storage device provided in an embodiment of the present invention; Figure 10 A schematic diagram of the semiconductor structure provided in the embodiments of the present invention; Figures 11a to 11g A schematic cross-sectional structure of the fabrication process of another three-dimensional storage device provided in an embodiment of the present invention. Figure 1 ; Figures 12a to 12f A schematic diagram of the cross-sectional structure of another three-dimensional storage device fabrication process provided in an embodiment of the present invention; Figures 13a to 13f A schematic diagram of the cross-sectional structure of another three-dimensional storage device fabrication process provided in an embodiment of the present invention; Figures 14a to 14f A schematic cross-sectional structure of the fabrication process of another three-dimensional storage device provided in this embodiment of the invention. Figure 4 . Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0029] In the description of this invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and do not require that this invention be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0030] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0031] In three-dimensional storage devices, to reduce the resistance between the channel layer and the electrical lead pads in the channel structure, and to achieve better connectivity between the channel layer and the electrical lead pads, reference is made. Figure 1 In some embodiments, the approach is to place the channel layer 101 with the electrical lead-out pad (in Figure 1 In the process, a polysilicon layer 102 is added between the channel layer 101 and the three-dimensional storage device 10 (connected by metal contact post 103), and then a metal contact post 103 is placed on the polysilicon layer 102, thereby achieving electrical connection between the channel layer 101 and the electrical lead-out pad.

[0032] Combination Figures 2a to 2l The specific preparation method of the above structure is carried out according to the following steps: Provide such as Figure 2a The semiconductor structure shown; specifically, the semiconductor structure includes a substrate 1001 and a stacked structure 1002 located on the substrate 1001.

[0033] In some embodiments, the substrate 1001 can be any suitable semiconductor substrate, such as a single-crystal monolayer substrate, a polycrystalline silicon monolayer substrate, a multilayer substrate of polycrystalline silicon and metal, etc.

[0034] For the stacked structure 1002, multiple insulating layers and multiple gate layers can be formed alternately.

[0035] It should be noted that two alternately stacked first dielectric layers 1002a and second dielectric layers 1002b can be formed first, for example, the first dielectric layer 1002a is silicon oxide and the second dielectric layer 1002b is silicon nitride. In some embodiments, the second dielectric layer 1002b is replaced by a conductive layer in a subsequent process to form a gate layer; therefore, the second dielectric layer 1002b is also referred to as a sacrificial layer.

[0036] The first dielectric layer 1002a and the second dielectric layer 1002b may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition, physical vapor deposition, or atomic layer deposition or any combination thereof.

[0037] It should be noted that the first dielectric layer 1002a and / or the second dielectric layer 1002b may comprise any suitable oxide material and / or nitride material. For example, the elements of the oxide material and / or nitride material include, but are not limited to, tungsten, cobalt, copper, aluminum, doped silicon, silicides, or any combination thereof. In some embodiments, the first dielectric layer 1002a may be a silicon oxide layer, and the second dielectric layer 1002b may be a silicon nitride layer.

[0038] Next, combined Figure 2bA groove 1003 is formed, penetrating the stacked structure 1002 and extending to the substrate 1001. The groove 1003 can be formed by a series of processes including patterning photoresist, etching the stacked structure 1002 and part of the substrate 1001, and subsequent ashing and cleaning processes. The etching process used to form the groove 1003 can be wet etching, dry etching, or a combination thereof. The ashing process can be plasma ashing, and the cleaning process can be wet cleaning.

[0039] It should be noted that the lower part of the formed groove can be cylindrical or have an inverted arch shape.

[0040] Subsequently, combined Figure 2c A channel structure 1004 is formed in the groove 1003. Specifically, a gate dielectric layer 1004a, a charge storage layer 1004b, a tunneling layer 1004c, and a channel layer 1004d are sequentially deposited on the bottom and sidewalls of the groove 1003. The deposition here may include, but is not limited to, chemical vapor deposition, physical vapor deposition, or atomic layer deposition, or any combination thereof, as described above.

[0041] It should be noted that the gate dielectric layer 1004a, the charge storage layer 1004b, and the tunneling layer 1004c can be a combination of silicon oxide / silicon nitride / silicon oxide layers. The gate dielectric layer 1004a serves as a barrier; the charge storage layer 1004b serves to store charge, and the storage or removal of charge therein can affect the on / off state and / or conductivity of the semiconductor channel; electrons or holes from the channel layer 1004d can tunnel through the tunneling layer 1004c to the charge storage layer 1004b.

[0042] Furthermore, combined with Figure 2d A filling layer 1005 is formed on top of the channel structure 1004 formed in the groove 1003. The material of the filling layer 1005 can be an oxide layer, such as a silicon oxide layer. In practical applications, one or more air gaps (not shown in the figure) may exist in the filling layer 1005. In some embodiments, the filling layer 1005 can be formed by a deposition filling process or an etch-back process.

[0043] Next, combined Figure 2e Remove the portions of the channel structure 1004 and the filler layer 1005 located outside the channel holes. In some embodiments, this can be done by a chemical mechanical polishing process. In some embodiments, the top surfaces of the channel structure 1004 and the filler layer 1005 can be planarized to be flush with the top surface of the laminate structure 1002.

[0044] Furthermore, firstly Figure 2e The structure in the image is inverted; the inverted structure is referenced. Figure 2fSubsequently, the entire substrate 1001 is removed by selective etching, at which point the channel structure 1004 located above the stacked structure 1002 is at least partially exposed, such as... Figure 2g As shown.

[0045] Further, the portion of the channel structure 1004 above the stacked structure 1002, excluding the channel layer 1004d, is removed; specifically, the gate dielectric layer 1004a, charge storage layer 1004b, and tunneling layer 1004c located above the stacked structure 1002 are removed. Specifically, a step-by-step wet etching process can be used to sequentially remove the portion of the gate dielectric layer 1004a, charge storage layer 1004b, and tunneling layer 1004c located above the stacked structure 1002, thereby obtaining the following... Figure 2h The structure shown has only exposed cross sections of the channel layer 1004d, gate dielectric layer 1004a, charge storage layer 1004b, and tunneling layer 1004c above the stacked structure 1002.

[0046] Subsequently, a polycrystalline silicon layer 1006 is formed on the basis of the above structure. The polycrystalline silicon layer 1006 can be formed by the deposition method described above.

[0047] Furthermore, the top surface of the polysilicon layer 1006 is made planar using a planarization method. The resulting structure is as follows. Figure 2j As shown. In some embodiments, this can be performed using a chemical mechanical polishing process.

[0048] Since the polysilicon layer 1006 needs to be connected to the metal contact pillars in subsequent processes, in order to improve electrical connectivity, the polysilicon layer 1006 undergoes low-temperature undoped polysilicon deposition, high-dose ion implantation, and finally shallow surface ion activation through nanosecond laser annealing, thereby obtaining the processed polysilicon layer 1006'. Figure 2k As shown.

[0049] Next, a series of processes, such as forming a dielectric layer, patterning photoresist, and etching the dielectric layer, are used to form a hole structure, and metal contact pillars 1009 are formed in this hole structure. The formation of the dielectric layer, the patterning photoresist, and the etching of the dielectric layer can be performed using the methods described above, while the formation of the metal contact pillars can be performed using methods such as physical vapor deposition and chemical vapor deposition. In some embodiments, the material of the metal contact pillars includes tungsten.

[0050] Through the above process steps, the following is prepared: Figure 2l The three-dimensional storage device structure is shown. It should be noted that... Figure 2l The structure of three-dimensional storage devices and Figure 1 The structures shown are essentially the same, because in the preparation of such Figure 2bWhen the groove 1003 is shown, the shape of the formed groove depends on the process of forming the groove structure 1003 that accommodates the filling layer 1005. Depending on different process conditions, the protrusion extending to the substrate 1001 can be in the shape of a "bamboo shoot" or have a flat top, depending on the process of forming the groove structure that accommodates the insulating layer 205d.

[0051] exist Figure 1 (or Figure 2l In the structure shown, the polycrystalline silicon layer 102 (or 1006') Figure 2l ) and channel layer 101 (1004d, Figure 2l The direct resistance of the ) is relatively large, and it is difficult to form a robust structure.

[0052] To address at least one of these problems, embodiments of the present invention provide a three-dimensional memory device and a method for fabricating the same. Specifically, a connecting layer is introduced between the channel layer and the electrical lead pad. The material of this connecting layer includes metal silicide, thereby reducing the resistance between the channel layer and the electrical lead pad in the three-dimensional memory device. Simultaneously, since metal silicide has good thermal stability, it remains undecomposed and does not detach during subsequent heat treatment processes, thus achieving a more robust connection.

[0053] The following will describe in detail the three-dimensional storage device of the present invention and its fabrication method with reference to the accompanying drawings.

[0054] According to a first aspect of the embodiments of the present invention, in conjunction with the appendix Figures 3a to 3c Three-dimensional storage devices 20a, 20b and 20c are provided.

[0055] refer to Figure 3a The three-dimensional storage device 20a of this embodiment includes: Layered structure 203a; A plurality of channel structures 204a penetrate the stacked structure 203a, wherein the channel structure 204a includes at least a channel layer 204ad; wherein the material of the channel layer 204ad comprises silicon. A connecting layer 201a is in contact with a channel layer 204ad; wherein the material of the connecting layer 201a includes metal silicide.

[0056] In some embodiments, the connection layer 201a is used for electrical connection with an electrical lead-out pad (not shown).

[0057] In practical applications, the stacked structure 203a includes multiple insulating layers 203aa and multiple gate layers 203ab stacked alternately. In practical applications, the number of these multiple insulating layers 203aa and multiple gate layers 203ab can be, for example, 32 layers, 64 layers, etc. For ease of understanding, the number of stacked structures in the accompanying drawings is exemplary.

[0058] Multiple channel structures 204a extend through the stacked structure 203a. In some embodiments, the channel structure 204a includes at least a channel layer 204ad. In some typical memory structures, the channel structure 304a radially comprises a gate dielectric layer 204aa, a charge storage layer 204ab, a tunneling layer 204ac, and a channel layer 204ad. In some embodiments, the gate dielectric layer 204aa, the charge storage layer 204ab, the tunneling layer 204ac, and the channel layer 204ad are made of silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively.

[0059] It should be noted that the middle portion surrounded by the channel layer 204ad is usually filled with a filler structure 205a, also known as an insulating layer, to support the three-dimensional storage structure and maintain reasonable stress. Since the filler structure 205a is usually filled by a deposition method, in some cases, there may be one or more air gaps 206a in the filler structure 205a.

[0060] Here, the connecting layer 201a serves as an intermediate layer, and its material is a metal silicide, which has low electrical resistance. In practical applications, the metal silicide may include nickel silicide, titanium silicide, tungsten silicide, cobalt silicide, etc.

[0061] In some embodiments, the material of the connecting layer 201a includes nickel silicide.

[0062] It is understood that the material of the interconnect layer 201a includes metal silicide. Because metal silicide has low resistance, a lower contact resistance can be obtained when the channel layer is connected to the electrical lead-out pad via the metal silicide, thereby facilitating electrical lead-out of the channel layer. Compared to the previous embodiment, where the channel layer is directly connected to the polysilicon layer before being connected to the electrical lead-out pad, the contact resistance during the channel layer lead-out process is greatly reduced, thus optimizing the electrical performance of the three-dimensional memory device.

[0063] The following will describe several specific structural methods of the interconnect layer. In the three-dimensional storage device 20a of this embodiment, the interconnect layer 201a includes a first part 201aa and a second part 201ab; wherein, the first part 201aa extends into the channel layer 204ad, and the cross-sectional shape of the first part 201aa parallel to the first plane is the same as the cross-sectional shape of the channel layer 204bd parallel to the first plane; here, since the first plane is perpendicular to the stacking direction of the stacked structure, the stacking direction of the stacked structure can be defined as the Z direction, such as... Figure 3a As shown, the first plane is a plane perpendicular to the Z direction, which can be denoted as the XY plane; at the same time, the second part 201ab covers the stacked structure 203a and the channel structure 204a.

[0064] As can be seen from the above structure, since the material of the connecting layer 201a in this embodiment of the invention includes metal silicide, compared to Figure 1 The corresponding trench layer in the embodiment ( Figure 1 (101) and semiconductor layer ( Figure 1 In this embodiment of the invention, the metal silicide acts as a bridge connecting the channel layer 204ad and the external circuit (not shown in the figure). This provides two advantages: firstly, it results in lower resistance between the channel layer and the external circuit, leading to better conductivity; secondly, the metal silicide exhibits good thermal stability, preventing decomposition and detachment during subsequent heat treatment processes, thus achieving a more robust connection.

[0065] The following combination Figure 3b This invention describes a variation 20b of the three-dimensional storage device 20a according to an embodiment of the present invention.

[0066] refer to Figure 3b The three-dimensional memory device 20b also includes a substrate 207 located between a second portion 201bb of the stacked structure 203b and the interconnect layer 201b; a channel structure 204b extends through the substrate 207, wherein the material of the substrate 207 includes silicon; the interconnect layer 201b includes a first portion 201ba and a second portion 201bb; wherein the first portion 201ba extends into the channel layer 204bd, and the cross-sectional shape of the first portion 201ba parallel to a first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is as defined above; meanwhile, the second portion 201bb covers the substrate 207 and the channel structure 204b.

[0067] It is understood that in this embodiment, the three-dimensional memory device 20b also has a substrate 207, while the other structures are similar to those in the previous embodiment. Therefore, the three-dimensional memory device 20b can also achieve lower resistance and a more robust connection between the channel layer and the external circuitry.

[0068] The following combination Figure 3c This invention describes another variation 20c of the three-dimensional storage device 20a in this embodiment.

[0069] refer to Figure 3c The connection layer 201c in the three-dimensional storage device 20c includes a first portion 201ca and a second portion 201cb; wherein the first portion 201ca extends into the channel layer 204cd, and the cross-sectional shape of the first portion 201ca parallel to the first plane is the same as the cross-sectional shape of the channel layer 204cd parallel to the first plane; the first plane is as defined above.

[0070] The channel structure 204c also includes a portion extending into the stacked structure 203c; the portion of the channel structure 204c extending into the stacked structure 203c contacts the second portion 201cb; wherein the second portion 201cb also covers the stacked structure 203c.

[0071] It should be noted that the second part 201cb of the connecting layer 201c covers a portion of the channel structure 204c extending into the stacked structure 203c. This portion of the channel structure 204c may only include the filling structure 205c. Figure 3c (As shown in the diagram); the channel structure 204c may further include a filling structure 205c and a partial channel layer covering the filling structure 205c. Furthermore, the extended protruding portion is not limited to... Figure 3c The "bamboo shoot" shape shown can also have a flat-topped shape, depending on the process used to form the groove structure that accommodates the insulating layer 205c. In this case, the connection layer 201c of the three-dimensional storage device 20c has the same effect as the connection layers 201a / 201b of the three-dimensional storage devices 20a / 20b, which will not be described further here.

[0072] In some embodiments, the three-dimensional storage device further includes metal contact posts located above the connection layer, the metal contact posts being used to connect the connection layer to the electrical lead-out pad. For example, in the structures of the three-dimensional storage devices 20a, 20b, and 20c described above, metal contact posts are also included, see reference. Figure 4 , Figure 4 In the case of a three-dimensional storage device 20a', a metal contact post 210 is provided above the three-dimensional storage device 20a for connecting the connection layer 201a to the electrical lead pad, thereby connecting to an external circuit. The process of forming the metal contact post 210 includes a series of processes as described above, such as forming a dielectric layer, patterning photoresist, and etching the dielectric layer to form a hole structure, and forming the metal contact post 210 in the hole structure, which will not be described in detail here. The material of the formed metal contact post 210 may include tungsten, etc.

[0073] For the three-dimensional storage devices 20b and 20c, metal contact pillars can also be formed above their respective connection layers, which will not be elaborated here.

[0074] According to a second aspect of the embodiments of the present invention, in conjunction with the appendix Figures 5a to 5c Three-dimensional storage devices 30a, 30b and 30c are provided.

[0075] For the three-dimensional storage device 30a, and with reference to Figure 3a and Figure 5a ,and Figure 3a Compared to the three-dimensional storage device 20a shown, Figure 5a The three-dimensional memory device 30a further comprises a semiconductor layer 302a covering the interconnect layer 301a above the interconnect layer 301a; wherein the semiconductor layer 302a is used to electrically connect the interconnect layer 301a to the electrical lead-out pad. In some embodiments, the material of the semiconductor layer 302a includes polycrystalline silicon.

[0076] It should be noted that the silicon of semiconductor layer 302a is typically deposited at a low temperature below 420°C. This is to avoid the risk of short circuits or discharges caused by the diffusion of copper that may be present in the memory device at high temperatures. Furthermore, to achieve better electrical interconnect performance, the silicon of semiconductor layer 302a may undergo at least high-dose ion implantation and nanosecond laser annealing to perform shallow surface ion activation, thereby increasing the conductivity of semiconductor layer 302a.

[0077] For the three-dimensional storage device 30b, and with reference to Figure 3b and Figure 5b ,and Figure 3b Compared to the three-dimensional storage device 20b shown, Figure 5b The three-dimensional memory device 30b further comprises a semiconductor layer 302b covering the interconnect layer 301b above the interconnect layer 301b; wherein the semiconductor layer 302b is used to electrically connect the interconnect layer 301b to the electrical lead-out pad. In some embodiments, the material of the semiconductor layer 302b includes polycrystalline silicon.

[0078] It should be noted that the semiconductor layer 302b and the semiconductor layer 302a in the three-dimensional memory device 30a have the same structure and function, which will not be elaborated here.

[0079] For the three-dimensional storage device 30c, and with reference to Figure 3c and Figure 5c ,and Figure 3c Compared to the three-dimensional storage device 20c shown, Figure 5cThe three-dimensional memory device 30c further comprises a semiconductor layer 302c covering the interconnect layer 301c above the interconnect layer 301c; wherein the semiconductor layer 302c is used to electrically connect the interconnect layer 301c to the electrical lead-out pad. In some embodiments, the material of the semiconductor layer 302c includes polycrystalline silicon.

[0080] It should be noted that the semiconductor layer 302c and the semiconductor layer 302a in the three-dimensional memory device 30a have the same structure and function, which will not be elaborated here.

[0081] Similarly, for the three-dimensional memory devices 30a, 30b and 30c, it is ultimately necessary to bring the channel layer out to the circuit outside the three-dimensional memory device. Therefore, taking the three-dimensional memory device 30a' as an example, the three-dimensional memory device 30a may also include a metal contact post located above the semiconductor layer 302a, the metal contact post being used to connect the semiconductor layer to the electrical lead-out pad.

[0082] In some embodiments, the three-dimensional memory device further includes metal contact pillars located above the semiconductor layer, the metal contact pillars serving to connect the semiconductor layer to the electrical lead-out pad. For example, in the structures of the three-dimensional memory devices 20a, 20b, and 20c described above, metal contact pillars are also included, see reference. Figure 6 , Figure 6 In the case of a three-dimensional memory device 30a', a metal contact post 310 is provided above the three-dimensional memory device 30a for connecting the semiconductor layer 302a to the electrical lead pad, thereby connecting to an external circuit. The process of forming the metal contact post 310 includes a series of processes as described above, such as forming a dielectric layer, patterning photoresist, and etching the dielectric layer to form a hole structure, and forming the metal contact post 310 in the hole structure, which will not be described in detail here. The material of the formed metal contact post 310 may include tungsten, etc.

[0083] According to a third aspect of the embodiments of the present invention, in conjunction with the appendix Figure 7 and Figure 8 It provides a three-dimensional storage device 40, such as Figure 7 As shown. Figure 8 This is a partial enlarged view of the connection layer 201 of the three-dimensional storage device 40.

[0084] The three-dimensional storage device 40 is similar to the three-dimensional storage device 20a' or the three-dimensional storage device 30a', except that the shape of the connecting layer 401 is different, which includes a first part 401a and a second part 401b; wherein, the first part 401a extends into the channel layer 404d, and the cross-sectional shape of the first part 401a parallel to the first plane is the same as the cross-sectional shape of the channel layer 404d parallel to the first plane; with the stacking direction being the Z direction, the first plane is perpendicular to the stacking direction Z of the stacked structure 403.

[0085] The second part 401b extends into the semiconductor layer 402, and the cross-sectional shape of the second part 401b parallel to the first plane is the same as the cross-sectional shape of the first part 401a.

[0086] Understandably, from Figure 8 As shown in the enlarged view, the connection layer 401 can be a ring structure, which can be divided into two parts. One part can be embedded in the channel layer, and the other part can be embedded in the semiconductor layer.

[0087] It should be noted that, precisely because the connecting layer 401 in the above embodiment is a ring structure, the surface area of ​​the portion located at the top of the stacked structure is relatively small. Therefore, it is not suitable to directly connect to the subsequently provided metal contact pillars. A preferred approach is to use the semiconductor layer 402 provided in this embodiment as an intermediate bridge. In this case, the channel layer 404d is connected to the metal contact pillars sequentially through the connecting layer 401 and the semiconductor layer 402, thereby achieving electrical connection with the external circuit.

[0088] The following will describe in detail the fabrication method of the three-dimensional storage device of the present invention.

[0089] Figure 9 This is a flowchart illustrating a method for fabricating a three-dimensional storage device according to an embodiment of the present invention.

[0090] For the fabrication of three-dimensional storage devices, combined with Figure 9 The fabrication method of the three-dimensional storage device includes the following steps: S101: Provide a semiconductor structure, the semiconductor structure including a substrate, a stacked structure above the substrate, and a channel structure extending through the stacked structure and extending to the substrate, wherein the channel structure includes at least a channel layer; the material of the substrate or the channel layer includes at least silicon; S102: Remove at least a portion of the substrate to expose a portion of the channel layer; S103: A connecting layer is formed in contact with the exposed portion of the channel layer; the material of the connecting layer includes metal silicide.

[0091] In some embodiments, the connecting layer is used for electrical connection with the electrical lead-out pad.

[0092] The above method is a method for fabricating the three-dimensional storage device of the present invention by directly connecting the connecting layer with the metal contact pillars prepared by subsequent processes.

[0093] Since the preliminary steps in fabricating a three-dimensional memory device are essentially the same, step S101 begins with the provided semiconductor structure including a substrate, a stacked structure above the substrate, and a channel structure penetrating the stacked structure and extending to the substrate. The above steps have been described in detail, as follows: Figures 2a to 2f As shown, it will not be described again here. The cross-sectional structural diagram of the semiconductor structure provided in step S101 is shown below. Figure 10 As shown.

[0094] In step S102, the main process involves removing a portion or all of the substrate 1001 to expose a portion of the cross-section of the channel layer 1004d. Removing at least a portion of the substrate 1001 in step S102 includes various scenarios; for example, it may include removing all of the substrate or removing only a portion of it. It will be understood that the exposed portion of the channel layer will depend on the portion or manner in which the substrate is removed. These different scenarios will be described in detail below.

[0095] After exposing a portion of the channel layer, step S103 is performed to form a connecting layer in contact with the exposed portion of the channel layer; the material of the connecting layer includes metal silicide.

[0096] Given the various structures of the interconnect layer, the manufacturing methods also correspond to different ways of removing the substrate (S102) and forming the corresponding interconnect layer (S103).

[0097] Method 1: In some embodiments, removing at least a portion of the substrate to expose a portion of the trench layer includes: The entire substrate is removed to expose a portion of the channel layer; wherein, when removing the substrate, the channel structure extending to the substrate is also removed.

[0098] In some embodiments, the method further includes: forming a sacrificial semiconductor layer covering the stacked structure and the channel structure before forming the interconnect layer; the material of the sacrificial semiconductor layer includes silicon; The connecting layer includes a first portion and a second portion; the connecting layer forming contact with the exposed portion of the channel layer includes: Form a metal layer covering the sacrificial semiconductor layer; At a first temperature, the metal layer and a portion of the channel layer are silicided to form a first portion of the interconnect layer in the portion of the channel layer, while a second portion of the interconnect layer is formed in the metal layer and the sacrificial semiconductor layer; wherein, the cross-sectional shape of the first portion parallel to a first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the layered structure; the second portion covers the layered structure and the channel structure. Here, it is... Figure 10 Starting with the structure shown, combined Figures 11a to 11g A detailed explanation of Method 1 follows.

[0099] like Figure 11a As shown, at least a portion of the substrate 1001 is removed, specifically the portion above section AA. The removed portion includes the entire substrate 1001 above section AA, as well as the channel structure 1004 and the filling layer 1005 extending to the substrate 1001. In this case, the portion above section AA can be removed by planarization, for example, by chemical mechanical polishing.

[0100] In this case, the flattened structure is as follows Figure 11b As shown.

[0101] Subsequently, a connection layer is formed; here, refer to the back. Figure 3a The connecting layer 201a includes a first portion 201aa and a second portion 201ab; the forming of the connecting layer 201a, which contacts the exposed portion of the channel layer 204ad, specifically includes the following steps: like Figure 11c As shown, a sacrificial semiconductor layer 1006 is formed covering the stacked structure and the exposed portion of the channel structure; the material of the sacrificial semiconductor layer 1006 includes silicon, thereby increasing the amount of silicon that reacts with the deposited metal, thus compensating for insufficient silicon reacting with the metal in the channel layer. (Continue to refer to...) Figure 11d A metal layer 1007 is formed covering the sacrificial semiconductor layer 1006.

[0102] Here, the deposited metal can be nickel, tungsten, cobalt, titanium, etc. In some embodiments, the deposited metal is nickel. Here, since other copper wiring materials may be present in the storage device, to avoid the risk of short circuits or discharges caused by copper diffusion at high temperatures (e.g., above 420°C), nickel and silicon can form stable and robust nickel silicide at temperatures below the aforementioned levels. In some embodiments, the first temperature is less than 420°C.

[0103] Continue to refer to Figure 11eAt a first temperature, the metal layer 1007 and a portion of the channel layer 1004d are subjected to a silicide reaction to form the interconnect layer 1100, wherein the interconnect layer 1100 includes a first portion (equivalent to...) Figure 3a (201ab in the middle), while forming the second part of the connecting layer in the metal layer 1007 (equivalent to 201ab in the middle), Figure 3a (201ab in the middle).

[0104] It can be understood that in this way, a metal layer 1007 is deposited on top of the channel structure 1004, so that the metal of the metal layer 1007 is in contact with the channel layer 1004d in the channel structure 1004, and at a certain temperature, the two undergo a silicide reaction to form a metal silicide.

[0105] Next, the metal layer 1007 that did not undergo the silanization reaction is removed. The resulting structure is as follows. Figure 11f As shown. In practical applications, the metal layer that has not undergone silanization can be removed by wet etching. In this step, the metal of the metal layer 1007 reacts with the channel layer 1004d in the channel structure 1004 to form the interconnect layer 1100. The resulting structure corresponds to Figure 3a The three-dimensional storage structure 20a.

[0106] Subsequently, a semiconductor layer can be selectively formed over the interconnect layer. For example... Figure 12f As shown, a semiconductor 1200 is formed above the aforementioned interconnect layer 1100.

[0107] It is understandable that, without forming a semiconductor layer, the three-dimensional memory device fabricated according to the above method can, for example, be as follows: Figure 3a The three-dimensional memory device 20a shown; when forming the semiconductor layer, the three-dimensional memory device prepared according to the above method can, for example, be as follows: Figure 5a The three-dimensional storage device 30a shown.

[0108] It should be noted that, in combination Figure 11g In the subsequent process, the semiconductor layer 1200 in the obtained three-dimensional memory device needs to be connected to the metal contact pillar. Therefore, in order to increase the electrical connection performance, the semiconductor layer 1200 undergoes undoped polysilicon deposition at low temperature, high-dose ion implantation, and finally shallow surface ion activation by annealing with nanosecond laser.

[0109] In some embodiments, for Figure 3a The three-dimensional storage device 20a shown may have metal contact pillars formed above the connection layer to electrically connect the connection layer to the electrical lead-out pad.

[0110] for Figure 3aThe three-dimensional storage device 20a shown can be exemplified as follows: Figure 4 As shown, the metal contact post 210 is connected to the connecting layer 201. In some embodiments, for Figure 5a The three-dimensional storage device 30a shown may have metal contact pillars formed above the semiconductor layer to connect the semiconductor layer to the electrical lead-out pad.

[0111] for Figure 5a The three-dimensional storage device 30a shown can be exemplified as follows: Figure 6 As shown, the metal contact post 310 is connected to the connecting layer 201.

[0112] Method 2: In some embodiments, removing at least a portion of the substrate to expose a portion of the trench layer includes: A portion of the substrate is removed to expose a portion of the channel layer; wherein, when removing the substrate, the channel structure extending into the substrate is also removed.

[0113] In some embodiments, the connection layer includes a first portion and a second portion; the connection layer forming contact with the exposed portion of the channel layer includes: A metal layer is formed covering the remaining substrate and the exposed portion of the trench layer; At a first temperature, the metal layer and a portion of the channel layer are silicided to form a first portion of the interconnect layer in the portion of the channel layer, while a second portion of the interconnect layer is formed in the metal layer; wherein the cross-sectional shape of the first portion parallel to a first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the layered structure; the second portion covers the remaining substrate and the channel structure.

[0114] Here, with Figure 10 Starting with the structure shown, combined Figures 12a to 12f The second method will be explained in detail.

[0115] like Figure 12a As shown, at least a portion of the substrate 1001 is removed, specifically the portion above the cross-section BB. The removed portion includes the portion of the substrate 1001 above the cross-section BB, as well as the channel structure 1004 and the filling layer 1005 extending to the substrate 1001. In this case, the portion above the cross-section BB can be removed by planarization, for example, by chemical mechanical polishing.

[0116] In this case, the flattened structure is as follows Figure 12b As shown.

[0117] Subsequently, a connection layer is formed; here, refer to the back. Figure 3b The connecting layer 201a includes a first portion 201ba and a second portion 201bb; the connecting layer 201b, which forms contact with the exposed portion of the channel layer 204bd, specifically includes the following steps in forming the connecting layer: like Figure 12c As shown, a substrate 1001 forms the covering portion, and a metal layer 1007 extends to the substrate 1001, including a channel structure 1004 and a filling layer 1005.

[0118] The deposited metal has already been described in detail above, and will not be repeated here.

[0119] Continue to refer to Figure 12d At a first temperature, the metal layer 1007 undergoes a silicide reaction with a portion of the channel layer 1004d, while simultaneously, the metal layer 1007 reacts with silicon in a portion of the substrate 1001 it contacts to form the interconnect layer 1100, wherein the interconnect layer 1100 includes a first portion (equivalent to...) Figure 3b 201ba), while simultaneously forming the second part of the connecting layer in the metal layer 1007 (equivalent to 201ba), Figure 3b (201bb in the middle).

[0120] It can be understood that in this way, a metal layer 1007 is deposited above the channel layer 1004, so that the metal of the metal layer 1007 is in contact with the channel layer 1004d in the channel structure 1004 and with the polysilicon in the remaining substrate layer, and at a certain temperature, the two undergo a silicide reaction to form a metal silicide.

[0121] Next, the metal layer 1007 that did not undergo the silanization reaction is removed. The resulting structure is as follows. Figure 12e As shown. In practical applications, the metal layer that has not undergone silanization can be removed by wet etching. In this step, the metal of the metal layer 1007 reacts with the channel layer 1004d in the channel structure 1004 and the polysilicon in the remaining substrate to form the interconnect layer 1100. The resulting structure corresponds to Figure 3b The three-dimensional storage structure 20b.

[0122] Subsequently, a semiconductor layer can be selectively formed over the interconnect layer. For example... Figure 12f As shown, a semiconductor 1200 is formed above the aforementioned interconnect layer 1100.

[0123] It is understandable that, without forming a semiconductor layer, the three-dimensional memory device fabricated according to the above method can, for example, be as follows: Figure 3bThe three-dimensional memory device 20b shown; when forming the semiconductor layer, the three-dimensional memory device prepared according to the above method can, for example, be as follows: Figure 5b The three-dimensional storage device 30b shown.

[0124] It should be noted that, in combination Figure 12f In the subsequent process, the semiconductor layer 1200 in the obtained three-dimensional memory device needs to be connected to the metal contact pillar. Therefore, in order to increase the electrical connection performance, the semiconductor layer 1200 undergoes undoped polysilicon deposition at low temperature, high-dose ion implantation, and finally shallow surface ion activation by annealing with nanosecond laser.

[0125] In some embodiments, for Figure 3b The three-dimensional storage device 20b shown may have metal contact pillars formed above the connection layer to electrically connect the connection layer to the electrical lead-out pad.

[0126] for Figure 3b The three-dimensional storage device 20b shown is a specific example similar to that shown below. Figure 4 As shown, the difference lies in that, in this method, the metal contact post 210 is connected to the connecting layer 201b. In some embodiments, for Figure 5b The three-dimensional storage device 30b shown may have metal contact pillars formed above the semiconductor layer to connect the semiconductor layer to the electrical lead-out pad.

[0127] for Figure 5b The three-dimensional storage device 30b shown is a specific example similar to that shown below. Figure 6 The structure shown differs in that the metal contact post 310 is connected to the semiconductor layer 302b.

[0128] Method 3: In some embodiments, removing at least a portion of the substrate to expose a portion of the trench layer includes: Remove all of the substrate to expose the channel structure and stacked structure extending into the substrate; Remove the gate dielectric layer, charge storage layer, and tunneling layer of the channel structure extending into the substrate to expose the channel layer of the channel structure extending into the substrate.

[0129] In some embodiments, the method further includes: forming a sacrificial semiconductor layer covering the stacked structure and the channel layer before forming the interconnect layer; the material of the sacrificial semiconductor layer includes silicon; The channel structure includes a channel hole and a gate dielectric layer, a charge storage layer, a tunneling layer and a channel layer arranged radially along the channel hole; The connecting layer includes a first portion and a second portion; the connecting layer forming contact with the exposed portion of the channel layer includes: Form a metal layer covering the sacrificial semiconductor layer; At a first temperature, the metal layer and a portion of the channel layer are silicided to form a first portion of the interconnect layer in the unexposed portion of the channel layer, while a second portion of the interconnect layer is formed in the metal layer and the sacrificial semiconductor layer; wherein the cross-sectional shape of the first portion parallel to a first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the stacked structure; the second portion covers the stacked structure and the channel structure extending into the substrate.

[0130] Here, with Figure 10 Starting with the structure shown, combined Figures 13a to 13f The third method will be explained in detail.

[0131] like Figure 13a As shown, the entire substrate 1001 is removed to expose the channel junction layer 1004d and the stacked structure 1002 extending into the substrate. In this case, the entire substrate 1001, the portion of the gate dielectric layer 1004a located above the stacked structure 1002, the charge storage layer 1004b, and the tunneling layer 1004c can be removed sequentially by a stepwise wet selective etching process, thereby obtaining the following... Figure 13a The structure shown.

[0132] Continue to refer to Figures 13b to 13c A metal layer 1007 is formed covering the sacrificial semiconductor layer 1006. Because the channel layer 1004d in the channel structure 1004 has a small thickness and is easily damaged during the above process, Figure 13a A sacrificial semiconductor layer is formed on the structure, the material of which is silicon. This increases the amount of silicon that reacts with the deposited metal, thereby compensating for the lack of silicon that reacts with the metal in the channel layer.

[0133] The deposited metal has already been described in detail above, and will not be repeated here.

[0134] Continue to refer to Figure 13c At a first temperature, the metal layer 1007 and a portion of the channel layer 1004d undergo a silicide reaction, and simultaneously, the metal layer 1007 and the silicon in the sacrificial semiconductor layer 1006 undergo a silicide reaction to form the interconnect layer 1100, wherein the interconnect layer 1100 includes a first portion (equivalent to...) Figure 3c 201ca in the middle), while forming the second part of the connecting layer in the metal layer 1007 (equivalent to 201ca), and at the same time forming the second part of the connecting layer in the metal layer 1007 (equivalent to 201ca). Figure 3c(201cb in the middle).

[0135] It can be understood that in this way, a sacrificial semiconductor layer is first formed above the channel layer 1004d, and then a metal layer 1007 is deposited, so that the metal of the metal layer 1007 is in contact with the silicon of the sacrificial semiconductor layer, and at the same time, at a certain temperature, the two undergo a silicide reaction to form a metal silicide.

[0136] Next, remove the portion of the metal layer 1007 that did not undergo the silicide reaction (e.g. Figure 13d (As shown). The resulting structure is as follows. Figure 13e As shown. In practical applications, the metal layer 1007 that has not undergone silanization can be removed by wet etching. In this step, the metal of the metal layer 1007 reacts with the silicon of the sacrificial material layer to form the interconnect layer 1100. The resulting structure corresponds to Figure 3c The three-dimensional storage structure 20c.

[0137] Subsequently, a semiconductor layer may be selectively formed over the interconnect layer 1100. For example... Figure 13f As shown, a semiconductor 1200 is formed above the aforementioned interconnect layer 1100.

[0138] It is understandable that, without forming a semiconductor layer, the three-dimensional memory device fabricated according to the above method can, for example, be as follows: Figure 3c The three-dimensional memory device 20c shown; when forming the semiconductor layer, the three-dimensional memory device prepared according to the above method can, for example, be as follows: Figure 5c The three-dimensional storage device 30c shown.

[0139] It should be noted that, in combination Figure 13f In the subsequent process, the semiconductor layer 1200 in the obtained three-dimensional memory device needs to be connected to the metal contact pillar. Therefore, in order to increase the electrical connection performance, the semiconductor layer 1200 undergoes undoped polysilicon deposition at low temperature, high-dose ion implantation, and finally shallow surface ion activation by annealing with nanosecond laser.

[0140] In some embodiments, for Figure 3c The three-dimensional storage device 20a shown may have metal contact pillars formed above the connection layer to electrically connect the connection layer to the electrical lead-out pad.

[0141] for Figure 3c The three-dimensional storage device 20c shown is a specific example similar to... Figure 4 As shown, the difference lies in that, in this method, the metal contact post 210 is connected to the connecting layer 201c. In some embodiments, for Figure 5cThe three-dimensional storage device 30c shown may have metal contact pillars formed above the semiconductor layer to connect the semiconductor layer to the electrical lead-out pad.

[0142] for Figure 5c The three-dimensional storage device 30c shown is a specific example similar to... Figure 6 The structure shown differs in that, in this method, the metal contact post 310 is connected to the semiconductor layer 302c.

[0143] Method 4: In some embodiments, removing at least a portion of the substrate to expose a portion of the trench layer includes: The entire substrate is removed to expose a portion of the channel layer; wherein, when removing the substrate, the channel structure extending to the substrate is also removed.

[0144] In some embodiments, the connection layer includes a first portion and a second portion; the connection layer forming contact with the exposed portion of the channel layer includes: A metal layer is formed to cover the exposed portion of the trench layer; At a first temperature, the metal layer and a portion of the channel layer are subjected to a silicide reaction to form a first portion of the interconnect layer, while a second portion of the interconnect layer is formed in the metal layer; wherein, the cross-sectional shape of the first portion parallel to a first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the laminated structure; the cross-sectional shape of the second portion parallel to the first plane is the same as the cross-sectional shape of the first portion.

[0145] Here, with Figure 10 Starting with the structure shown, combined Figures 14a to 14f Method four will be explained in detail.

[0146] like Figure 14a As shown, at least a portion of the substrate 1001 is removed, specifically the portion above section AA. The removed portion includes the entire substrate 1001 above section AA, as well as the channel structure 1004 and the filling layer 1005 extending to the substrate 1001. In this case, the portion above section AA can be removed by planarization, for example, by chemical mechanical polishing.

[0147] In this case, the flattened structure is as follows Figure 14b As shown.

[0148] Subsequently, a connection layer is formed; here, refer to the back. Figure 7 and Figure 8The connecting layer 401 includes a first portion 401a and a second portion 401b; the connecting layer 401, which forms contact with the exposed portion of the channel layer 4014d, specifically includes the following steps: refer to Figure 14c A metal layer 1007 is formed covering the stacked structure and the exposed partial channel structure.

[0149] The deposited metal has already been described in detail above, and will not be repeated here.

[0150] Continue to refer to Figure 14d At a first temperature, the metal layer 1007 undergoes a silicide reaction with a portion of the channel layer 1004d, while simultaneously, the metal layer 1007 reacts with silicon in a portion of the substrate 1001 it contacts to form the interconnect layer 1100, wherein the interconnect layer 1100 includes a first portion (equivalent to...) Figure 8 (401a in the text), while simultaneously forming the second portion of the connecting layer in the metal layer 1007 (equivalent to 401a in the text). Figure 8 (401b in the middle).

[0151] It can be understood that in this way, a metal layer 1007 is deposited above the channel layer 1004, so that the metal of the metal layer 1007 is in contact with the channel layer 1004d in the channel structure 1004, and at a certain temperature, the two undergo a silicide reaction to form a metal silicide.

[0152] Next, the metal layer 1007 that did not undergo the silanization reaction is removed. The resulting structure is as follows. Figure 14e As shown. In practical applications, the metal layer that has not undergone silanization can be removed by wet etching. In this step, the metal of the metal layer 1007 reacts with the polysilicon in the channel layer 1004d of the channel structure 1004 to form the interconnect layer 1100. The resulting structure corresponds to Figure 7 The three-dimensional storage structure 40.

[0153] It is understood that the connection layer 1100 formed in the above manner is a ring structure, and therefore the surface area of ​​the portion located at the top of the stacked structure is relatively small. Therefore, it is not suitable for direct connection to subsequently installed metal contact pillars. Therefore, the method of this approach also includes forming a semiconductor layer 1200 to obtain... Figure 14f The structure shown.

[0154] It should be noted that, in combination Figure 14fIn the subsequent process, the semiconductor layer 1200 in the obtained three-dimensional memory device needs to be connected to the metal contact pillar. Therefore, in order to increase the electrical connection performance, the semiconductor layer 1200 undergoes undoped polysilicon deposition at low temperature, high-dose ion implantation, and finally shallow surface ion activation by annealing with nanosecond laser.

[0155] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A three-dimensional storage device, characterized in that, include: Layered structure; A plurality of channel structures running through the stacked structure, each channel structure comprising at least a channel layer; wherein the material of the channel layer comprises silicon; A connecting layer is provided, which is in contact with the channel layer; wherein the material of the connecting layer includes metal silicide. The connecting layer includes a first portion and a second portion; wherein the first portion extends into the channel layer, and the cross-sectional shape of the first portion parallel to a first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the layered structure; the second portion covers the channel structure; A semiconductor layer is provided for electrically connecting the interconnect layer to an electrical lead-out pad, the interconnect layer being located between the semiconductor layer and the stacked structure.

2. The three-dimensional storage device according to claim 1, characterized in that, The material of the connecting layer includes nickel silicide.

3. The three-dimensional storage device according to claim 1, characterized in that, The second part also covers the stacked structure.

4. The three-dimensional storage device according to claim 1, characterized in that, The three-dimensional memory device further includes a substrate located between the stacked structure and the second portion; the channel structure extends through the substrate, and the substrate is made of silicon; the second portion also covers the substrate.

5. The three-dimensional storage device according to claim 1, characterized in that, The channel structure further includes a portion extending out of the stacked structure; the portion extending out of the stacked structure contacts the second portion; the second portion also covers the stacked structure.

6. The three-dimensional storage device according to claim 1, characterized in that, The second portion extends into the semiconductor layer, and the cross-sectional shape of the second portion parallel to the first plane is the same as the cross-sectional shape of the first portion.

7. The three-dimensional storage device according to claim 1, characterized in that, The three-dimensional storage device further includes: a metal contact post located above the connection layer, the metal contact post being used to connect the connection layer to the electrical lead-out pad.

8. A method for fabricating a three-dimensional storage device, characterized in that, include: A semiconductor structure is provided; the semiconductor structure includes a substrate, a stacked structure covering the surface of the substrate, and a channel structure extending through the stacked structure and extending to the substrate; wherein the channel structure includes at least a channel layer; and the materials of the substrate and the channel layer include at least silicon. Remove at least a portion of the substrate to expose a portion of the channel layer; A connecting layer is formed in contact with the exposed portion of the channel layer; the material of the connecting layer includes metal silicide; the connecting layer includes a first portion and a second portion; wherein the first portion extends into the channel layer, and the cross-sectional shape of the first portion parallel to a first plane is the same as the cross-sectional shape of the channel layer parallel to the first plane; the first plane is perpendicular to the stacking direction of the laminated structure; the second portion covers the channel structure; A semiconductor layer is formed on the interconnect layer; the interconnect layer is electrically connected to an electrical lead-out pad through the semiconductor layer, and the interconnect layer is located between the semiconductor layer and the stacked structure.

9. The method according to claim 8, characterized in that, The material of the connecting layer includes nickel silicide.

10. The method according to claim 8, characterized in that, The removal of at least a portion of the substrate to expose a portion of the trench layer includes: The entire substrate is removed to expose a portion of the channel layer; wherein, when removing the substrate, the channel structure extending to the substrate is also removed.

11. The method according to claim 10, characterized in that, The method further includes: forming a sacrificial semiconductor layer covering the stacked structure and the channel structure before forming the interconnect layer; the material of the sacrificial semiconductor layer includes silicon; The connecting layer that forms and contacts the exposed portion of the channel layer includes: Form a metal layer covering the sacrificial semiconductor layer; At a first temperature, the metal layer is silicided with a portion of the channel layer to form a first portion of the interconnect layer in the portion of the channel layer, while a second portion of the interconnect layer is formed in the metal layer and the sacrificial semiconductor layer; wherein the second portion also covers the stacked structure.

12. The method according to claim 8, characterized in that, The removal of at least a portion of the substrate to expose a portion of the trench layer includes: A portion of the substrate is removed to expose a portion of the channel layer; wherein, when removing a portion of the substrate, the channel structure extending into that portion of the substrate is also removed.

13. The method according to claim 12, characterized in that, The connecting layer that forms and contacts the exposed portion of the channel layer includes: A metal layer is formed covering the remaining substrate and the exposed portion of the channel layer; At a first temperature, the metal layer is silicided with a portion of the channel layer to form a first portion of the interconnect layer in the portion of the channel layer, while a second portion of the interconnect layer is formed in the metal layer; wherein the second portion further covers the remainder of the substrate.

14. The method according to claim 8, characterized in that, The channel structure includes a channel hole and a gate dielectric layer, a charge storage layer, a tunneling layer and a channel layer arranged radially along the channel hole; The removal of at least a portion of the substrate to expose a portion of the trench layer includes: Remove all of the substrate to expose the channel structure and the stacked structure extending into the substrate; Remove the gate dielectric layer, the charge storage layer, and the tunneling layer of the channel structure extending into the substrate to expose the channel layer of the channel structure extending into the substrate.

15. The method according to claim 14, characterized in that, The method further includes: forming a sacrificial semiconductor layer covering the stacked structure and the channel layer before forming the interconnect layer; the material of the sacrificial semiconductor layer includes silicon; The connecting layer that forms and contacts the exposed portion of the channel layer includes: Form a metal layer covering the sacrificial semiconductor layer; At a first temperature, the metal layer is silicided with a portion of the channel layer to form a first portion of the interconnect layer in the unexposed portion of the channel layer, while a second portion of the interconnect layer is formed in the metal layer and the exposed portion of the channel layer; wherein the second portion further covers the stacked structure and the channel structure extending into the substrate.

16. The method according to claim 8, characterized in that, The removal of at least a portion of the substrate to expose a portion of the trench layer includes: The entire substrate is removed to expose a portion of the channel layer; wherein, when removing the substrate, the channel structure extending to the substrate is also removed.

17. The method according to claim 16, characterized in that, The connecting layer that forms and contacts the exposed portion of the channel layer includes: Form a metal layer covering the exposed portion of the trench layer; At a first temperature, the metal layer and a portion of the channel layer are subjected to a silicide reaction to form the first portion of the interconnect layer, while the second portion of the interconnect layer is formed in the metal layer; wherein the cross-sectional shape of the second portion parallel to the first plane is the same as the cross-sectional shape of the first portion.

18. The method according to claim 8, characterized in that, The method further includes: Metal contact posts are formed above the connecting layer to electrically connect the connecting layer to the electrical lead-out pad.

Images