Semiconductor device

Abstract

The present application provides a semiconductor device, when forming a contact trench portion, there is a silicon defect of a semiconductor substrate to reduce the element characteristics. A semiconductor device is provided, which has: a drift region of a first conductivity type provided in a semiconductor substrate; a base region of a second conductivity type provided in the semiconductor substrate; an emitter region of the first conductivity type provided on a front surface of the semiconductor substrate; a contact region of the second conductivity type provided on a front surface of the base region, and a doping concentration higher than a doping concentration of the base region; a contact trench portion provided on the front surface of the semiconductor substrate; a first barrier layer provided on a side wall and a bottom surface of the contact trench portion; and a second barrier layer provided on the side wall of the contact trench portion in contact with the contact region.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Technical Background

[0002] Previously, semiconductor devices having contact trenches were known (for example, see Patent Documents 1 to 4).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2014-158013

[0004] Patent Document 2: Japanese Patent Application Publication No. 2013-065724

[0005] Patent Document 3: International Publication No. 2018 / 052099

[0006] Patent Document 4: Japanese Patent Application Publication No. 2016-225512 Summary of the Invention

[0007] Technical issues

[0008] When forming contact trenches, there is a problem of silicon defects in the semiconductor substrate reducing device characteristics.

[0009] Technical solution

[0010] In a first embodiment of the present invention, a semiconductor device is provided, comprising: a drift region of a first conductivity type disposed on a semiconductor substrate; a base region of a second conductivity type disposed on the semiconductor substrate; an emitter region of the first conductivity type disposed on the front side of the semiconductor substrate; a contact region of the second conductivity type disposed on the front side of the base region, and having a doping concentration higher than that of the base region; a contact trench portion disposed on the front side of the semiconductor substrate; a first barrier layer disposed on the sidewall and bottom surface of the contact trench portion; and a second barrier layer disposed in contact with the contact region on the sidewall of the contact trench portion.

[0011] The first barrier layer can be installed on the sidewall of the contact trench and in contact with the launch area.

[0012] The second barrier layer can be installed in contact with the launch area on the sidewall of the contact groove.

[0013] The second barrier layer can be a silicon oxide film.

[0014] The contact resistance between the second barrier layer and the emission area can be below 100Ω.

[0015] The thickness of the second barrier layer can be above 1 nm and below 50 nm.

[0016] The conductivity of the second barrier layer can be the same as or lower than that of the first barrier layer.

[0017] The first barrier layer may contain at least one of Ti, TiN, Ta, and TaN.

[0018] The first barrier layer may have a silicide region formed by siliconization on the bottom surface of the contact trench.

[0019] The contact trenches can be arranged in a stripe pattern between multiple trenches arranged in a predetermined arrangement direction on the front side of the semiconductor substrate.

[0020] The contact trenches can be arranged in a matrix among multiple trenches arranged in a grid pattern on the front side of the semiconductor substrate.

[0021] The contact trenches can be arranged in a matrix between multiple trenches on the front side of the semiconductor substrate, and configured in a grid pattern along the multiple trenches.

[0022] It should be noted that the above description of the invention does not list all the features of the invention. Furthermore, sub-combinations of these feature groups can also constitute other inventions. Attached Figure Description

[0023] Figure 1 An example top view of a semiconductor device 100 according to an embodiment is shown.

[0024] Figure 2 It is shown Figure 1 A magnified view of an example of region A.

[0025] Figure 3A It is shown Figure 2 A diagram of an example of the a-a' section.

[0026] Figure 3B It is shown Figure 2 A diagram of an example of the b-b' section.

[0027] Figure 4A It is shown Figure 3A A magnified view of an example of region S in the image.

[0028] Figure 4B It is shown Figure 3B A magnified view of an example of region T in the image.

[0029] Figure 5 It is shown Figure 3A A magnified view of another example of region S.

[0030] Figure 6 It is shown Figure 3B A magnified view of another example of region T.

[0031] Figure 7This is a diagram illustrating an example of a method for manufacturing the first barrier layer 64 and the second barrier layer 66.

[0032] Figure 8 It is shown Figure 1 A magnified view of an example of region B in the image.

[0033] Figure 9A An example top view of a semiconductor device 1100 according to an embodiment is shown.

[0034] Figure 9B It is shown Figure 9A A magnified view of an example of region C in the image.

[0035] Symbol Explanation

[0036] 10…Semiconductor substrate, 12…Emitter region, 14…Base region, 15…Contact region, 16…Accumulation region, 17…Well region, 18…Drift region, 19…Contact layer, 21…Front side, 22…Collector region, 23…Back side, 24…Collector, 25…Connection portion, 30…Dummy trench portion, 31…Extension portion, 32…Dummy insulating film, 33…Connection portion, 34…Dummy conductive portion, 38…Interlayer insulating film, 40…Gate trench portion, 41…Extension portion, 42…Gate insulating film, 43…Connection portion, 44…Gate conductive portion, 50…Gate metal layer, 51… 52…Emitter electrode, 54…Contact hole, 55…Contact hole, 56…Contact hole, 60…Contact trench, 61…Bottom surface, 62…Sidewall, 63…Bottom of sidewall, 64…First barrier layer, 65…Silicide region, 66…Second barrier layer, 68…Terminal portion, 70…Transistor portion, 71…Mesa portion, 80…Diode portion, 81…Mesa portion, 82…Cathode region, 90…Boundary portion, 91…Mesa portion, 100…Semiconductor device, 102…Edge edge, 160…Active region, 162…Edge terminal structure portion, 1100…Semiconductor device Detailed Implementation

[0037] The present invention will now be described through embodiments thereof, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the solution of the invention.

[0038] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other as the lower surface. The directions of "upper," "lower," "positive," and "negative" are not limited to the direction of gravity or the actual mounting direction towards the substrate when mounting a semiconductor device.

[0039] In this specification, rectangular coordinate axes of X, Y, and Z are sometimes used to illustrate technical matters. In this specification, the surface parallel to the front side of the semiconductor substrate is designated as the XY plane, and the depth direction of the semiconductor substrate is designated as the Z-axis. It should be noted that in this specification, the view of the semiconductor substrate along the Z-axis is referred to as a top view.

[0040] In each embodiment, although an example is shown where the first conductivity type is N-type and the second conductivity type is P-type, it is also possible to use the first conductivity type as P-type and the second conductivity type as N-type. In this case, the conductivity types of the substrate, layer, region, etc., in each embodiment become their respective opposite polarities.

[0041] In this specification, layers and / or regions marked with N or P represent electrons or holes as the majority carriers, respectively. Furthermore, a "+" sign for N or P indicates a higher doping concentration than layers and / or regions without a "+" sign, a "-" sign for N and / or P indicates a lower doping concentration than layers and / or regions without a "-" sign, "++" indicates a higher doping concentration than "+", and "--" indicates a lower doping concentration than "-".

[0042] In this specification, doping concentration refers to the concentration of donor or acceptor dopant. Therefore, its unit is / cm². 3 In this specification, the concentration difference between donors and acceptors (i.e., net doping concentration) is sometimes used as the doping concentration. In this case, the doping concentration can be determined using the SR method. Alternatively, the chemical concentration of donors and / or acceptors can also be used as the doping concentration. In this case, the doping concentration can be determined using the SIMS method. Unless otherwise specified, any of the above-mentioned doping concentrations can be used as the doping concentration. Unless otherwise specified, the peak value of the doping concentration distribution in the doped region can be used as the doping concentration of that doped region.

[0043] Furthermore, in this specification, dosage refers to the number of ions implanted per unit area of ​​the wafer during ion implantation. Therefore, its unit is / cm². 2 It should be noted that the dose in the semiconductor region can be set as the integrated concentration obtained by integrating the doping concentration along the depth direction of the semiconductor region. The unit of this integrated concentration is / cm. 2 Therefore, the dose and integrated concentration can be considered the same. The integrated concentration can be the integral value up to the half-width, which can be derived by excluding the influence of other semiconductor regions when their spectra overlap with those of other semiconductor regions.

[0044] Therefore, in this specification, the level of doping concentration can be referred to as the level of dose. That is, when the doping concentration in one region is higher than the doping concentration in other regions, it can be understood that the dose in that region is higher than the dose in other regions.

[0045] Figure 1 An example top view of a semiconductor device 100 according to an embodiment is shown. Figure 1 The image shows the positions obtained by projecting each component onto the front surface of the semiconductor substrate 10. Figure 1 The diagram shows only a portion of the components of the semiconductor device 100, with some components omitted.

[0046] Semiconductor device 100 includes semiconductor substrate 10. Viewed from above, semiconductor substrate 10 has end edges 102. In this specification, "viewed from above" means viewed from the front side of semiconductor substrate 10. In this example, semiconductor substrate 10 has two sets of end edges 102 facing each other when viewed from above. Figure 1 In the diagram, the X and Y axes are parallel to one end edge 102. Additionally, the Z axis is perpendicular to the front surface of the semiconductor substrate 10.

[0047] An active region 160 is provided on the semiconductor substrate 10. The active region 160 is a region where, when the semiconductor device 100 is operated, the main current flows along the depth direction between the front and back surfaces of the semiconductor substrate 10. Although an emitter electrode is provided above the active region 160, Figure 1 omitted.

[0048] The active region 160 is provided with a transistor section 70 including transistor elements such as IGBTs and a diode section 80 including diode elements such as freewheeling diodes (FWDs). For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). It should be noted that the semiconductor device 100 can be an IGBT or a MOS transistor.

[0049] exist Figure 1 In this example, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the front side of the semiconductor substrate 10. In other examples, the active section 160 may contain only one of the transistor section 70 and the diode section 80.

[0050] exist Figure 1 In this specification, the area where the transistor section 70 is arranged is marked with the symbol "I", and the area where the diode section 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction when viewed from above is sometimes referred to as the extension direction (in...). Figure 1(The middle direction is the Y-axis direction). The transistor section 70 and the diode section 80 may each have a long side in the extending direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending direction of the transistor section 70 and the diode section 80 may be the same as the long side direction of each trench section described later.

[0051] exist Figure 1 In this configuration, the Y-axis end of the transistor section 70 is located further towards the end edge 102 than the Y-axis end of the diode section 80. Furthermore, the X-axis width of the transistor section 70 is greater than the X-axis width of the diode section 80.

[0052] The diode section 80 has an N+ type cathode region in the area that contacts the back side of the semiconductor substrate 10. In this specification, the area where the cathode region is provided is referred to as the diode section 80. That is, the diode section 80 is the area that overlaps with the cathode region when viewed from above. On the back side of the semiconductor substrate 10, a P+ type collector region may be provided in an area other than the cathode region.

[0053] The transistor section 70 has a P+ type collector region in the area that contacts the back side of the semiconductor substrate 10. In addition, the transistor section 70 has an N-type emitter region, a P-type base region, and a gate trench having a gate conductive portion and a gate insulating film periodically arranged on the front side of the semiconductor substrate 10.

[0054] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. As an example, the semiconductor device 100 may have pads such as a gate pad, an anode pad, a cathode pad, and a current sensing pad. Each pad is located near the edge 102. "Near the edge 102" refers to the area between the edge 102 and the emitter electrode when viewed from above. In actual installation of the semiconductor device 100, each pad can be connected to an external circuit via wiring such as wires.

[0055] Viewed from above, the gate metal layer 50 is disposed between the active region 160 and the end edge 102 of the semiconductor substrate 10. The gate metal layer 50 connects the gate trench and the gate pad. Viewed from above, in this example, the gate metal layer 50 surrounds the active region 160. Viewed from above, the area surrounded by the gate metal layer 50 can be considered as the active region 160.

[0056] In this example, the semiconductor device 100 has an edge termination structure 162 between the active region 160 and the edge 102. The edge termination structure 162 is disposed between the gate metal layer 50 and the edge 102. The edge termination structure 162 mitigates electric field concentration on the front side of the semiconductor substrate 10. The edge termination structure 162 may have multiple guard rings. Each guard ring is a P-type region connected to the front side of the semiconductor substrate 10. By providing multiple guard rings, the depletion layer on the upper surface of the active region 160 can extend outward, improving the withstand voltage of the semiconductor device 100. The edge termination structure 162 may include at least one of a field plate arranged in a ring shape surrounding the active region 160 and a surface electric field reduction mechanism.

[0057] Figure 2 It is shown Figure 1 An enlarged view of an example of region A. Viewed from above, region A shows the boundary periphery of the transistor section 70 and the diode section 80 at the edge side of the negative Y-axis direction of the semiconductor device 100.

[0058] The transistor section 70 is the area obtained by projecting the collector region 22, which is provided on the back side of the semiconductor substrate 10, onto the front side of the semiconductor substrate 10. As an example, the collector region 22 in this example is P+ type. The transistor section 70 includes transistors such as IGBTs. The transistor section 70 includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80. The boundary section 90 is a mesa-shaped area provided within the transistor section 70 adjacent to the diode section 80 and does not function as a transistor.

[0059] The diode section 80 is a region obtained by projecting the cathode region 82, which is disposed on the back side of the semiconductor substrate 10, onto the front side of the semiconductor substrate 10. As an example, the cathode region 82 in this example is N+ type. The diode section 80 includes diodes such as freewheeling diodes disposed adjacent to the transistor section 70 on the front side of the semiconductor substrate 10.

[0060] The semiconductor substrate 10 can be a silicon substrate, a silicon carbide substrate, or a gallium nitride or other nitride semiconductor substrate. In this example, the semiconductor substrate 10 is a silicon substrate.

[0061] In this example, the semiconductor device 100 has a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front side 21 of the semiconductor substrate 10. In addition, the semiconductor device 100 in this example has an emitter electrode 52 and a gate metal layer 50 disposed on the upper part of the front side 21 of the semiconductor substrate 10.

[0062] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. Additionally, the gate metal layer 50 is disposed above the gate trench portion 40 and the well region 17.

[0063] The emitter electrode 52 and the gate metal layer 50 are formed of a metal-containing material. At least a portion of the emitter electrode 52 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium and / or titanium compounds beneath the regions formed of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are disposed separately from each other.

[0064] The emitter electrode 52 and the gate metal layer 50 are sandwiched by an interlayer insulating film 38, which is disposed above the semiconductor substrate 10. The interlayer insulating film 38... Figure 2 The middle part is omitted. Contact holes 54, 55 and 56 are provided through the interlayer insulating film 38.

[0065] The contact hole 55 is connected to the gate conductive portion and the gate metal layer 50 within the gate trench portion 40 of the transistor portion 70. A plug made of tungsten or the like may be formed inside the contact hole 55.

[0066] The contact hole 56 connects the dummy conductive portion and the emitter electrode 52 provided in the dummy trench portion 30 of the transistor portion 70 and the diode portion 80. A plug made of tungsten or the like may be formed inside the contact hole 56.

[0067] The connection portion 25 electrically connects the front-side electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is provided in the region including the contact hole 55 between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided in the region including the contact hole 56 between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material such as a metal like tungsten and / or polycrystalline silicon doped with impurities. Alternatively, the connection portion 25 may be a barrier metal such as titanium nitride. Here, the connection portion 25 is polycrystalline silicon (N+) doped with N-type impurities. The connection portion 25 is disposed above the front side 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0068] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). In this example, the gate trench portions 40 may have two extension portions 41 extending along an extension direction (the Y-axis direction in this example) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction. The connection portion 43 connects the two extension portions 41.

[0069] At least a portion of the connection portion 43 is preferably formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, the electric field concentration at the ends of the extension portions 41 can be mitigated. In the connection portion 43 of the gate trench portion 40, the gate metal layer 50 can be connected to the gate conductive portion.

[0070] The dummy trench portion 30 is a trench portion in which a dummy conductive portion is electrically connected to the emitter electrode 52. Like the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). In this example, the dummy trench portion 30, like the gate trench portion 40, can have a U-shape on the front side 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 can have two extension portions 31 extending along the extension direction and a connecting portion 33 connecting the two extension portions 31.

[0071] The transistor section 70 in this example has a structure consisting of two gate trench sections 40 and three dummy trench sections 30 arranged in a repetitive pattern. That is, the transistor section 70 in this example has gate trench sections 40 and dummy trench sections 30 in a 2:3 ratio. For example, the transistor section 70 has an extension section 31 between two extension sections 41. In addition, the transistor section 70 has two extension sections 31 adjacent to the gate trench sections 40.

[0072] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 to the dummy trench portion 30 can be 1:1 or 2:4. Alternatively, a so-called full-gate structure can be constructed in which the dummy trench portion 30 is not provided in the transistor portion 70, but is entirely provided as gate trench portions 40.

[0073] Well region 17 is located further towards the front side 21 of semiconductor substrate 10 than drift region 18, which will be described later. Well region 17 is an example of a well region located on the edge side of semiconductor device 100. As an example, well region 17 is P+ type. Well region 17 is formed from the end of the active region on the side where gate metal layer 50 is located within a predetermined range. The diffusion depth of well region 17 can be deeper than the depth of gate trench portion 40 and dummy trench portion 30. A portion of the gate trench portion 40 and dummy trench portion 30 on the side adjacent to gate metal layer 50 is formed in well region 17. The bottom of the extending end of gate trench portion 40 and dummy trench portion 30 can cover well region 17.

[0074] Contact holes 54 are formed in the transistor section 70 above each region of the emitter region 12 and the contact region 15. Contact holes 54 are also formed in the boundary section 90 above the contact region 15. Contact holes 54 are also formed in the diode section 80 above the base region 14. No contact hole 54 is formed above the well region 17, which is located at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 can be provided extending in the extension direction.

[0075] The contact trench portion 60 electrically connects the emitter electrode 52 and the semiconductor substrate 10. The contact trench portion 60 is provided in the contact hole 54. The contact trench portion 60 is provided extending in the extending direction. That is, the contact trench portion 60 is arranged in a stripe shape along the gate trench portion 40 and the dummy trench portion 30.

[0076] Terminal portion 68 is the end portion extending in the contact groove portion 60. In tabletop portion 71 and tabletop portion 91, terminal portion 68 may be provided in the region where the contact area 15 is formed on the front surface 21. In tabletop portion 81, terminal portion 68 may be provided in the region where the base area 14 is formed on the front surface 21. Tabletop portion 71, tabletop portion 81, and tabletop portion 91 will be described later.

[0077] The boundary portion 90 is a region disposed in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact area 15. Alternatively, the boundary portion 90 may not have a contact area 15. In this example, the boundary portion 90 does not have an emitter area 12. In one example, the trench portion of the boundary portion 90 is a dummy trench portion 30. In this example, the boundary portion 90 is configured such that both ends in the X-axis direction are dummy trench portions 30.

[0078] Mesa-faces 71, 81, and 91 are mesa-faces disposed adjacent to the trench portions in a plane parallel to the front surface 21 of the semiconductor substrate 10. A mesa-face can refer to the region of the semiconductor substrate 10 sandwiched between two adjacent trench portions, extending from the front surface 21 of the semiconductor substrate 10 to the deepest bottom of each trench portion. An extension of each trench portion can be considered as a single trench portion. That is, the region sandwiched between two extension portions can be considered as a mesa-face.

[0079] The mesa portion 71 is disposed adjacent to at least one of the dummy trench portion 30 and the gate trench portion 40 in the transistor portion 70. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front side 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are alternately disposed in the extending direction.

[0080] A mesa 91 is provided at the boundary 90. The mesa 91 has a contact area 15 on the front side 21 of the semiconductor substrate 10. In this example, the mesa 91 has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0081] The mesa portion 81 is located in the diode portion 80, in the area sandwiched by the adjacent dummy trench portion 30. In this example, the mesa portion 81 has a base region 14 on the front side 21 of the semiconductor substrate 10 and a well region 17 on the negative side in the Y-axis direction. In the mesa portion 81, a contact region 15, similar to that of the boundary portion 90, may be provided on the front side 21 of the base region 14.

[0082] The base region 14 is a region disposed on the front side 21 of the semiconductor substrate 10 in the transistor section 70 and the diode section 80. As an example, the base region 14 is P-type. The base region 14 on the front side 21 of the semiconductor substrate 10 can be disposed at both ends in the Y-axis direction of the mesa 71 and mesa 91. It should be noted that... Figure 2 Only the negative end of the base region 14 in the Y-axis direction is shown.

[0083] Emitter region 12 is a region with the same conductivity type as drift region 18 but a higher doping concentration. As an example, emitter region 12 in this example is N+ type. An example of a dopant for emitter region 12 is arsenic (As). Emitter region 12 is disposed in contact with gate trench portion 40 on the front side 21 of mesa portion 71. Emitter region 12 can extend from one side of the two trench portions sandwiching mesa portion 71 along the X-axis to the other side. Emitter region 12 is also disposed below contact hole 54.

[0084] Furthermore, the emission area 12 may or may not contact the dummy groove portion 30. In this example, the emission area 12 contacts the dummy groove portion 30. The emission area 12 may not be provided on the platform surface 81 and platform surface 91.

[0085] Contact region 15 is a region with the same conductivity type as base region 14 but a higher doping concentration. As an example, contact region 15 in this example is P+ type. In this example, contact region 15 is located on the front surface 21 of mesa 71 and mesa 91. Contact region 15 can be located from one side of the two trench portions sandwiching mesa 71 or mesa 91 along the X-axis to the other side. Contact region 15 may or may not contact gate trench portion 40. Additionally, contact region 15 may or may not contact dummy trench portion 30. In this example, contact region 15 contacts both dummy trench portion 30 and gate trench portion 40. Contact region 15 is also located below contact hole 54.

[0086] Figure 3A It is shown Figure 2A diagram showing an example of the a-a' cross-section. The a-a' cross-section is the XZ plane passing through the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' cross-section. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0087] Drift region 18 is a region disposed on semiconductor substrate 10. As an example, drift region 18 in this example is N-type. Drift region 18 can be a region remaining in semiconductor substrate 10 where no other doped regions have been formed. That is, the doping concentration of drift region 18 can be the doping concentration of semiconductor substrate 10.

[0088] Buffer 20 is a region located below drift region 18. In this example, buffer 20 has the same conductivity type as drift region 18, which is N-type for example. The doping concentration of buffer 20 is higher than that of drift region 18. Buffer 20 functions as a field cutoff layer to prevent the depletion layer extending from the lower surface side of base region 14 from reaching collector region 22 and cathode region 82.

[0089] The collector region 22 is a region in the transistor section 70 located below the buffer zone 20 and having a different conductivity type than the drift region 18. The cathode region 82 is a region in the diode section 80 located below the buffer zone 20 and having the same conductivity type as the drift region 18. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80.

[0090] Collector 24 is formed on the back side 23 of semiconductor substrate 10. Collector 24 is formed of a conductive material such as metal.

[0091] The base region 14 is a region disposed above the drift region 18 in the mesa 71, mesa 81, and mesa 91, and has a different conductivity type than the drift region 18. As an example, the base region 14 in this example is P-type. The base region 14 is disposed in contact with the gate trench portion 40. The base region 14 may be disposed in contact with the dummy trench portion 30.

[0092] The emitter region 12 is disposed between the base region 14 and the front surface 21. In this example, the emitter region 12 is disposed on the mesa 71, but not on the mesa 81 and mesa 91. The emitter region 12 is disposed in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0093] The contact area 15 is located in the table surface 91 and is disposed on the front side of the base area 14. The contact area 15 is disposed in contact with the dummy groove portion 30 in the table surface 91. In other cross-sections, the contact area 15 may be disposed on the front side 21 of the table surface 71.

[0094] The contact trench portion 60 has a conductive material filling the contact hole 54. The contact trench portion 60 is disposed between two adjacent trench portions in a plurality of trench portions. The contact trench portion 60 is disposed in contact with the contact layer 19 on the front side 21. In this example, the contact trench portion 60 is disposed from the front side 21 through the emitting region 12 and contacts the contact layer 19 on the bottom surface. The contact trench portion 60 may have the same material as the emitting electrode 52.

[0095] The lower end of the contact trench 60 is deeper than the lower end of the emitter region 12. By providing the contact trench 60, the resistance of the base region 14 is reduced, making it easier to extract minority carriers (e.g., holes). As a result, the latch-up withstand capability and other breakdown withstand capability caused by minority carriers can be improved.

[0096] The contact groove portion 60 has a generally planar bottom surface. The bottom surface of the contact groove portion 60 is covered by the contact layer 19. In this example, the contact groove portion 60 has a tapered shape with inclined sidewalls. However, the sidewalls of the contact groove portion 60 can be configured to be generally perpendicular to the front surface 21.

[0097] A contact layer 19 is disposed below the contact trench portion 60. The contact layer 19 is a region with the same conductivity type as the base region 14 but a higher doping concentration. As an example, the contact layer 19 in this example is P+ type. For example, the contact layer 19 is formed by ion implantation of boron (B+) or boron fluoride (BF2+). The doping concentration of the contact layer 19 can be the same as the doping concentration of the contact region 15. The contact layer 19 suppresses latch-up by extracting minority carriers.

[0098] Contact layer 19 is provided on the sidewall and bottom surface of contact groove portion 60. In this example, contact layer 19 is provided on table surface 71, table surface 81 and table surface 91 respectively. Contact layer 19 can be provided extending in the Y-axis direction.

[0099] On the sidewall of the contact trench portion 60, the emitter region 12 is in contact with the contact layer 19. In this example, the sidewall of the contact trench portion 60 is covered by the emitter region 12 and the contact layer 19. That is, in the transistor portion 70, the contact trench portion 60 is not in contact with the base region 14.

[0100] In this example, by making the emitter region 12 contact with the contact layer 19, the injection of charge carriers from the emitter region 12 is suppressed, thereby improving the breakdown withstand capability. In addition, even when a large current flows through the semiconductor device 100, the minority carrier extraction efficiency can be increased through the contact layer 19, thereby stabilizing the potential of the base region 14.

[0101] The accumulation region 16 is a region located on the front side 21 of the semiconductor substrate 10, further away from the drift region 18. In this example, the conductivity type of the accumulation region 16 is the same as that of the drift region 18; for example, it is N+ type. The accumulation region 16 is provided in both the transistor section 70 and the diode section 80. However, the accumulation region 16 may not be provided.

[0102] Additionally, the accumulation region 16 is disposed in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than that of the drift region 18. The ion implantation dose of the accumulation region 16 can be 1E12cm. -2 Above and 1E13cm -2 Below. Additionally, the ion implantation dose in accumulation region 16 can also be 3E12cm. -2 Above and 6E12cm -2 The following describes how, by setting the accumulation region 16, the carrier injection enhancement effect (IE effect) can be improved, and the turn-on voltage of the transistor section 70 can be reduced. It should be noted that E means a power of 10, for example, 1E12cm. -2 It means 1×10 12 cm -2 .

[0103] One or more gate trench portions 40 and one or more dummy trench portions 30 are disposed on the front side 21. Each trench portion extends from the front side 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and accumulation region 16 is disposed, each trench portion also extends through these regions to reach the drift region 18. The trench portion extending through the doped region is not limited to the manufacturing sequence of forming the trench portion after forming the doped region. The sequence of forming the doped region between the trench portions after forming the trench portion is also included in the method of trench portion extending through the doped region.

[0104] The gate trench portion 40 has a gate trench formed on the front side 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed by covering the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench at a position further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front side 21 by an interlayer insulating film 38.

[0105] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces the base region 14 adjacent to the mesa 71 side, separated by the gate insulating film 42. If a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in the base region 14 that contacts the gate trench portion.

[0106] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 disposed on the front side 21. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed at a position further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front side 21 by an interlayer insulating film 38.

[0107] An interlayer insulating film 38 is disposed on the front side 21. An emitter electrode 52 is disposed above the interlayer insulating film 38. One or more contact holes 54 are provided on the interlayer insulating film 38 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be disposed through the interlayer insulating film 38.

[0108] Figure 3B It is shown Figure 2 A diagram showing an example of the b-b' section. The b-b' section is the XZ plane of the contact region 15 in the transistor section 70.

[0109] In section b-b', the platform surface 71 has a base region 14, a contact region 15, an accumulation region 16, and a contact layer 19. Similarly, in section a-a', the platform surface 91 has a contact region 15, an accumulation region 16, and a contact layer 19. In section b-b', the platform surface 71 has the same structure as the platform surface 91. Similarly, in section a-a', the platform surface 81 has a base region 14, an accumulation region 16, and a contact layer 19.

[0110] Figure 4A It is shown Figure 3A An enlarged view of an example of region S in the diagram. Here, the description will focus on the contact trench 60 and the first barrier layer 64 of the mesa 71 located between the dummy trench 30 and the gate trench 40.

[0111] The contact groove portion 60 has a bottom surface 61 and a sidewall 62. In this example, the concave bottom surface 61 of the contact groove portion 60 is recessed from the bottom 63 of the sidewall at the end of the sidewall 62, which is the positive side of the Z-axis, toward the center of the contact groove portion 60. The bottom surface 61 of the contact groove portion 60 may also be concave in an arc shape. The concave bottom surface 61 of the contact groove portion 60 is formed by etching for forming the contact hole 54. The bottom surface 61 may also be a straight shape other than concave.

[0112] A contact layer 19 is provided on a portion of the sidewall 62 and the bottom surface 61 of the contact groove portion 60. The contact layer 19 extends in the Z-axis direction towards the front surface 21 further than the lower end of the emission area 12 and is disposed in contact with the emission area 12. However, this structure is not necessary, and the contact layer 19 may also be disposed separately from the emission area 12.

[0113] A first barrier layer 64 is provided on the sidewall 62 and bottom surface 61 of the contact trench portion 60. As an example, the contact trench portion 60 is a tungsten (W) film formed using a CVD method employing WF6 gas or the like. In this case, the fluorine component of the WF6 gas may react with the silicon in the semiconductor substrate, causing defects in the semiconductor substrate. By providing the first barrier layer 64 between the contact trench portion 60 and the semiconductor substrate 10, the resistance to silicon defects caused by WF6 gas is improved.

[0114] The first barrier layer 64 contacts the emitter region 12 on the sidewall 62 of the contact trench portion 60. Furthermore, the first barrier layer 64 is conductive. In this example, the first barrier layer 64 comprises at least one of Ti, TiN, Ta, and TaN. Thus, the first barrier layer 64 forms a pathway on the sidewall 62 of the contact trench portion 60 for current to flow from the contact trench portion 60 to the emitter region 12.

[0115] Furthermore, the first barrier layer 64 contacts the contact layer 19 at the bottom surface 61 of the contact trench portion 60. Thus, the first barrier layer 64 forms a path for current to flow from the contact layer 19 to the contact trench portion 60.

[0116] Figure 4B It is shown Figure 3B An enlarged view of an example of region T in the diagram. Here, while the description focuses primarily on the contact trench 60, the first barrier layer 64, and the second barrier layer 66 of the mesa 71 located between the dummy trench 30 and the gate trench 40, mesa 81 or mesa 91 also has the same structure. Furthermore, all regions of mesa 71, mesa 81, and mesa 91 may have the same structure, or only a portion of the regions may have the same structure.

[0117] A contact layer 19 is provided on a portion of the sidewall 62 and bottom surface 61 of the contact groove portion 60. The contact layer 19 may be provided separately from the contact area 15 in the sidewall of the contact groove portion 60.

[0118] The first barrier layer 64 is provided on the entire surface of the sidewall 62 and bottom surface 61 of the contact groove portion 60. In contrast, the second barrier layer 66 is provided on the sidewall 62 of the contact groove portion 60. In addition, the second barrier layer 66 is provided on the sidewall 62 of the contact groove portion 60 adjacent to the contact area 15 at a position closer to the contact area 15 than the first barrier layer 64.

[0119] In this example, the second barrier layer 66 is disposed in contact with the contact area 15 on the side wall 62 of the contact groove portion 60. In addition, in this example, the second barrier layer 66 is not disposed on the bottom surface 61 of the contact groove portion 60, and the first barrier layer 64 is in contact with the contact layer 19 on the bottom surface 61 of the contact groove portion 60.

[0120] In this example, the second barrier layer 66 can be an oxide film, or, as an example, a silicon oxide (SiOx) film. The second barrier layer 66 can be a silicon oxide film containing boron, phosphorus, etc., or a silicon oxide film that has been imparted conductivity through oxygen vacancies, etc. Furthermore, the conductivity of the second barrier layer 66 is the same as, or lower than, the conductivity of the first barrier layer 64.

[0121] As an example, the first barrier layer 64 is formed by sputtering. Because sputtering uses a lower pressure gas than CVD, it is difficult to control the film thickness on the sidewalls 62 of the contact trench 60, and the resistance to silicon defects may be reduced in the thinner parts of the film.

[0122] In this example, the semiconductor device 100 has a dual barrier layer, namely a first barrier layer 64 and a second barrier layer 66, in the sidewall 62 of the contact trench portion 60 adjacent to the contact region 15, thereby improving resistance to silicon defects. It should be noted that the second barrier layer 66 may or may not be disposed in the portion that contacts the interlayer insulating film 38.

[0123] Furthermore, in this example, the second barrier layer 66 is disposed on the sidewall 62 of the contact trench portion 60 in the region adjacent to the contact area 15, but not in the region adjacent to the emitter area 12. However, on the front side 21 of the semiconductor substrate 10, since the area of ​​the contact area 15 is much larger than the area of ​​the emitter area 12, the area of ​​the sidewall 62 of the contact trench portion 60 adjacent to the contact area 15 is much larger than the area adjacent to the emitter area 12.

[0124] Therefore, in this example, the semiconductor device 100 selectively provides a second barrier layer 66 in the area adjacent to the contact region 15 on the sidewall 62 of the contact trench portion 60, thereby maintaining the current path of the first barrier layer 64. Thus, the semiconductor device 100 in this example can function as a device and also improve its resistance to silicon defects.

[0125] Figure 5 It is shown Figure 3A A magnified view of another example of region S in [the image]. Here, [the image is] compared to... Figure 4A The explanation will focus on the differences.

[0126] In this example, the second barrier layer 66 is disposed in contact with the emission region 12 on the sidewall 62 of the contact groove portion 60 adjacent to the emission region 12. On the other hand, the second barrier layer 66 is disposed in contact with the emission region 12 on the sidewall 62 of the contact groove portion 60 adjacent to the contact region 15. Figure 3B It is similarly set to the contact area 15.

[0127] That is, in this example, the first barrier layer 64 is provided on the entire surface of the sidewall 62 and bottom surface 61 of the contact groove portion 60. Although the second barrier layer 66 is not provided on the bottom surface 61 of the contact groove portion 60, it is provided on the entire surface of the sidewall 62 of the contact groove portion 60. The second barrier layer 66 is located on the sidewall 62 of the contact groove portion 60, closer to the emitter area 12 and the contact area 15 than the first barrier layer 64.

[0128] For the second barrier layer 66, an oxide film containing impurities is cited as an example. In this example, the second barrier layer 66 could also be a silicon oxide film containing boron, phosphorus, etc. Although the conductivity of the second barrier layer 66 is lower than that of the first barrier layer 64, it is at least conductive. The conductivity of the second barrier layer 66 could also be the same as that of the first barrier layer 64.

[0129] Regarding the contact resistance between the second barrier layer 66 and the contact area 15 in this example, in this embodiment, it can be approximately 100Ω or less, and preferably approximately 10Ω or less. It should be noted that the contact resistance depends on the design specifications of the component and is not necessarily limited to the above range.

[0130] The second barrier layer 66 preferably has a film thickness that provides resistance to silicon defects caused by WF6 gas, and this thickness can be 1 nm or more, preferably around 5 nm or more. Furthermore, while the upper limit of the film thickness of the second barrier layer 66 depends on its resistivity, a film thickness that satisfies the aforementioned contact resistance range is preferred. For example, the upper limit of the film thickness of the second barrier layer 66 can also be 50 nm.

[0131] Therefore, because the second barrier layer 66 in this example is provided on the entire surface of the sidewall 62 of the contact trench portion 60, it is easy to process. Furthermore, as mentioned earlier, the area of ​​the sidewall 62 of the contact trench portion 60 adjacent to the contact region 15 is much larger than the area adjacent to the emitter region 12. Additionally, the second barrier layer 66 in this example is at least conductive. Thus, the semiconductor device 100 in this example, by having a second barrier layer 66 on the sidewall 62 of the contact trench portion 60 that contacts both the emitter region 12 and the contact region 15, can function as a device and also improve its resistance to silicon defects.

[0132] Figure 6 It is shown Figure 3B A magnified view of another example of region T in [the image]. Here, [the image is] compared to... Figure 4B The explanation will focus on the differences.

[0133] The first barrier layer 64 has a silicide region 65 on the bottom surface 61 of the contact trench portion 60. As an example, the silicide region 65 includes Ti-series silicide or Ta-silicide. In contrast, the first barrier layer 64 does not have a silicide region on the sidewall 62 of the contact trench portion 60 because a second barrier layer 66 is provided at a position closer to the contact area 15 than the first barrier layer 64.

[0134] It should be noted that on the sidewall 62 of the contact groove portion 60 adjacent to the launch area 12, such as Figure 5 As shown, the second blocking layer 66 can be disposed in contact with the launch area 12, or as... Figure 4A As shown, a second barrier layer 66 is not provided. Figure 4A As shown, when the first barrier layer 64 is disposed in contact with the emitter region 12 on the sidewall 62 of the contact trench portion 60, the first barrier layer 64 can improve the device characteristics by having a silicide region 65 on the sidewall 62 of the contact trench portion 60.

[0135] Figure 7 This is a diagram illustrating an example of a method for manufacturing the first barrier layer 64 and the second barrier layer 66.

[0136] In step S102, a contact hole 54 is formed by etching through the emitter region 12 to the base region 14. Here, the interlayer insulating film 38 obtained by etching the region corresponding to the contact hole 54 is used as an oxide mask, and the contact hole 54 is formed by anisotropic etching of the semiconductor substrate 10.

[0137] Additionally, in step S102, using the interlayer insulating film 38 as a mask, ion implantation is performed to form the contact layer 19, and the contact layer 19 is formed by heat treatment. The contact layer 19 can be provided extending into the emitter region 12 by heat treatment.

[0138] It should be noted that in this example, after the contact hole 54 of the contact trench portion 60 is provided, ion implantation is performed to form the contact layer 19. That is, because the dopant ions of the contact layer 19 are implanted using the interlayer insulating film 38 as a mask, the positioning accuracy of the contact layer 19 relative to the contact trench portion 60 is improved.

[0139] In step S104, a second barrier layer 66 is formed by forming a film of oxides containing boron, phosphorus, etc., on the entire surface inside the contact hole 54.

[0140] In step S106, the second barrier layer 66 is removed from the bottom surface of the contact hole 54 by anisotropic etching or the like.

[0141] In step S108, a first barrier layer 64 is formed by forming a film of Ti or the like on the entire side of the contact hole 54.

[0142] It should be explained that, for example Figure 4A As shown, in the area where only the first barrier layer 64 is formed, in step S106, the second barrier layer 66 can also be removed from the inner wall of the contact hole 54 by pattern forming or the like.

[0143] Figure 8 It is shown Figure 1 An enlarged view of an example of region B in the image. It should be noted that... Figures 1 to 7 This illustrates a structure in which dummy trench portions 30 and gate trench portions 40 are arranged along a predetermined arrangement direction on the front side 21 of the semiconductor substrate 10. In contrast, Figure 8 The diagram shows a lattice-like structure in which the dummy trench portion 30 and the gate trench portion 40 are arranged on the front side 21 of the semiconductor substrate 10.

[0144] As an example, in the transistor section 70, a plurality of gate trench sections 40 extending along the Y-axis direction and arranged along the X-axis direction, and a plurality of gate trench sections 40 extending along the X-axis direction and arranged along the Y-axis direction are arranged in a grid pattern. Similarly, in the diode section 80 and the boundary section 90, a plurality of dummy trench sections 30 extending along the Y-axis direction and arranged along the X-axis direction, and a plurality of dummy trench sections 30 extending along the X-axis direction and arranged along the Y-axis direction are arranged in a grid pattern.

[0145] exist Figure 8 Although the transistor section 70 is shown as an all-gate structure without the dummy trench section 30, it is not limited thereto. The transistor section 70 may have both the dummy trench section 30 and the gate trench section 40. It should be noted that in... Figure 8 In this case, the interlayer insulating film 38 and the emitting electrode 52 can be omitted.

[0146] Contact holes 54 are provided on the table surface 71, table surface 81, and table surface 91. Contact groove portions 60 are provided on the contact holes 54. The contact groove portions 60 are provided extending in the extending direction. The contact groove portions 60 are arranged in a matrix between the groove portions arranged in a grid pattern.

[0147] Figure 9A An example top view of the semiconductor device 1100 of the embodiment is shown. Here, elements common to the semiconductor device 1100 are labeled with the same symbols, and the description focuses on the differences.

[0148] In addition to the gate metal layer 50, the semiconductor device 1100 also has an inner gate metal layer 51. The inner gate metal layer 51 extends along the Y-axis direction on the active region 160 and is connected to the gate metal layer 50. Figure 9A Although only a few inner gate metal layers 51 are shown for simplicity, the design is not limited thereto. As will be described later, the inner gate metal layers 51 extend over a plurality of gate trench portions 40.

[0149] Figure 9B It is shown Figure 9A An enlarged view of an example of region C in the image. The semiconductor device 1100 has trench portions arranged in a matrix on the front side 21 side of the semiconductor substrate 10. That is, in the semiconductor device 100, each trench portion extends along the Y-axis direction, while in the semiconductor device 1100, each trench portion is divided into multiple portions along the Y-axis direction, and the whole is arranged in a matrix.

[0150] exist Figure 9B In the transistor section 70, the Y-axis end of the gate trench section 40 and the Y-axis end of the dummy trench section 30 are adjacent to the contact region 15, but are not limited thereto. The Y-axis end of the gate trench section 40 and the Y-axis end of the dummy trench section 30 may also be adjacent to the emitter region 12.

[0151] Above each gate trench portion 40, an inner gate metal layer 51 extending in the Y-axis direction is provided along each gate trench portion 40, but... Figure 9B Explanation omitted. Thus, the gate trench portion 40 is connected to the gate pad via the inner gate metal layer 51 and the gate metal layer 50.

[0152] Contact holes 54 are provided in the table surface 71, table surface 81, and table surface 91. Contact groove portions 60 are provided in the contact holes 54. The contact groove portions 60 are provided extending in the extending direction. The contact groove portions 60 are arranged in a grid pattern between the groove portions arranged in a matrix.

[0153] While the present invention has been described above using embodiments, its technical scope is not limited to that described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiments. As can be seen from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

[0154] It should be noted that the execution order of actions, processes, steps, and stages in the apparatus, system, program, and method shown in the claims, specification, and drawings can be implemented in any order, unless specifically stated as "earlier than" or "before," and unless the results of previous processes are used in subsequent processes. Even if the workflow in the claims, specification, and drawings is described using terms such as "firstly" or "next" for convenience, it does not mean that it must be implemented in that order.

Claims

1. A semiconductor device, characterized in that, have: The drift region of the first conductivity type is disposed on the semiconductor substrate; A base region of a second conductivity type is disposed on the semiconductor substrate; The emitter region of the first conductivity type is disposed on the front side of the semiconductor substrate; A second conductivity type contact region is disposed on the front side of the base region and has a higher doping concentration than the base region; A contact trench is provided on the front side of the semiconductor substrate; A first barrier layer is disposed on the sidewall and bottom surface of the contact groove portion; as well as A second barrier layer is disposed in contact with the contact area on the sidewall of the contact groove portion. The second barrier layer is a silicon oxide film. The contact resistance between the second barrier layer and the emission region is below 100Ω.

2. The semiconductor device according to claim 1, characterized in that, The second barrier layer is disposed in contact with the emission area on the sidewall of the contact groove.

3. A semiconductor device, characterized in that, have: The drift region of the first conductivity type is disposed on the semiconductor substrate; A base region of a second conductivity type is disposed on the semiconductor substrate; The emitter region of the first conductivity type is disposed on the front side of the semiconductor substrate; A second conductivity type contact region is disposed on the front side of the base region and has a higher doping concentration than the base region; A contact trench is provided on the front side of the semiconductor substrate; A first barrier layer is disposed on the sidewall and bottom surface of the contact groove portion; as well as A second barrier layer is disposed in contact with the contact area on the sidewall of the contact groove portion. The first barrier layer is disposed in contact with the emission area on the sidewall of the contact groove.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The thickness of the second barrier layer is above 1 nm and below 50 nm.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, The conductivity of the second barrier layer is the same as that of the first barrier layer, or the conductivity of the second barrier layer is lower than that of the first barrier layer.

6. The semiconductor device according to claim 4, characterized in that, The conductivity of the second barrier layer is the same as that of the first barrier layer, or the conductivity of the second barrier layer is lower than that of the first barrier layer.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first barrier layer comprises at least one of Ti, TiN, Ta, and TaN.

8. The semiconductor device according to claim 4, characterized in that, The first barrier layer comprises at least one of Ti, TiN, Ta, and TaN.

9. The semiconductor device according to claim 5, characterized in that, The first barrier layer comprises at least one of Ti, TiN, Ta, and TaN.

10. The semiconductor device according to claim 6, characterized in that, The first barrier layer comprises at least one of Ti, TiN, Ta, and TaN.

11. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first barrier layer has a silicide region formed by siliconization on the bottom surface of the contact trench.

12. The semiconductor device according to any one of claims 1 to 3, characterized in that, The contact trenches are arranged in a stripe pattern between a plurality of trenches arranged in a predetermined direction on the front side of the semiconductor substrate.

13. The semiconductor device according to any one of claims 1 to 3, characterized in that, The contact trenches are arranged in a matrix among a plurality of trenches arranged in a grid pattern on the front side of the semiconductor substrate.

14. The semiconductor device according to any one of claims 1 to 3, characterized in that, The contact trenches are arranged in a matrix between multiple trenches on the front side of the semiconductor substrate, and are configured in a grid pattern along the multiple trenches.

Images