A superconducting digital circuit structure capable of suppressing quasiparticle poisoning and a manufacturing method thereof

Abstract

The present invention provides a superconducting digital circuit structure capable of suppressing quasiparticle poisoning and a manufacturing method thereof, wherein the circuit structure comprises a substrate, a superconducting structure and a normal metal layer; the superconducting structure is arranged on the substrate, the normal metal is electrically connected to the bottom electrode of the superconducting structure, and the normal metal layer is used to suppress quasiparticles generated in the manufacture of the superconducting digital circuit, wherein the quasiparticles are electrons after Cooper pairs are disassembled. The superconducting digital circuit of the present invention can effectively suppress quasiparticle poisoning in the superconducting digital circuit.

Description

Technical Field

[0001] The present invention relates to a superconducting quantum technology, in particular to a superconducting digital circuit structure capable of suppressing quasiparticle poisoning and a manufacturing method thereof. Background Art

[0002] For superconducting quantum circuits, the generation and existence of quasiparticles (quasiparticles refer to electrons after Cooper pairs are separated) can bring harm and cause quasiparticle poisoning. For example, first of all, quasiparticles are a source of loss, which will cause superconducting quantum bits to relax and the quality factor of superconducting resonant cavities to decrease. Moreover, because quasiparticles themselves carry electric charge, they will disturb quantum systems that are sensitive to charge, such as changing the frequency of quantum bits and causing phase decoherence. Therefore, it is necessary to avoid quasiparticle poisoning as much as possible in superconducting quantum circuits. There are many sources for introducing additional non-equilibrium quasiparticles into superconducting quantum circuits, such as temperature fluctuations, electromagnetic radiation, cosmic rays, etc., and these quasiparticles will reduce the performance of superconducting quantum circuits. In addition, some superconducting devices or circuits themselves will also produce quasiparticles during operation, such as superconducting digital circuits. Taking the SFQ circuit as an example, when the Josephson junction is triggered, the Cooper pairs are separated to produce non-equilibrium quasiparticles. In superconductors, quasiparticles usually have a long lifetime and a propagation distance of millimeters. The quasiparticles generated by multiple SFQ pulses will gradually accumulate, and eventually the entire device will be filled with quasiparticles, thus restricting the on-chip integration of superconducting digital circuits and superconducting quantum bits. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a superconducting digital circuit and a manufacturing method thereof that can suppress quasiparticle poisoning, so as to solve the problem of quasiparticle poisoning in superconducting digital circuits in the prior art.

[0004] To achieve the above-mentioned purpose and other related purposes, the present invention provides a superconducting digital circuit structure capable of suppressing quasiparticle poisoning, comprising a substrate, a superconducting structure and a normal metal layer; the superconducting structure is arranged on the substrate, the normal metal layer is electrically connected to the bottom electrode of the superconducting structure, and the normal metal layer is used to suppress the quasiparticles generated by the superconducting digital circuit.

[0005] Preferably, the superconducting structure comprises a bottom electrode, a first insulating material layer, a top electrode, a second insulating material layer, a resistance layer, a third insulating material layer and a wiring layer;

[0006] The first insulating material layer is disposed between the bottom electrode and the top electrode, and the bottom electrode, the first insulating material layer and the top electrode form a Josephson junction;

[0007] The second insulating material layer is disposed on the Josephson junction;

[0008] The resistance layer is disposed on the second insulating material layer;

[0009] The third insulating material layer is disposed on the edge portions of the second insulating material layer, the resistance layer and the normal metal layer;

[0010] The wiring layer is disposed on the third insulating material layer, and a first portion of the wiring layer electrically connects the top electrode and the resistance layer, and a second portion of the wiring layer electrically connects the resistance layer and the bottom electrode.

[0011] Preferably, an edge portion of the normal metal layer is arranged on the second insulating material layer, and a middle portion of the normal metal layer is arranged on the bottom electrode.

[0012] Preferably, a first connection hole is provided on the second insulating material layer, the first connection hole exposes the top electrode, and the top electrode is electrically connected to the first part of the wiring layer through the first connection hole.

[0013] Preferably, a ring hole is provided on the third insulating material layer, the ring hole exposes the resistor layer, and the resistor layer is electrically connected to the first part of the wiring layer and the second part of the wiring layer through the ring hole.

[0014] Preferably, a second connection hole is opened on the third insulating material layer, the second connection hole exposes the resistance layer, and the second connection hole is used to separate the first part of the wiring layer and the second part of the wiring layer.

[0015] Preferably, the second connection hole is located in the ring hole to expose part of the resistance layer to the air.

[0016] Preferably, a third connection hole is provided on the second insulating material layer, the third connection hole exposes the bottom electrode, and the bottom electrode is connected to the second portion of the wiring layer through the third connection hole.

[0017] Preferably, a contact opening is provided on the second insulating material layer, the contact opening exposes the bottom electrode, and the bottom electrode is electrically connected to the middle portion of the normal metal layer through the contact opening.

[0018] To achieve the above-mentioned object and other related objects, the present invention also provides a method for manufacturing a superconducting digital circuit structure capable of suppressing quasiparticle poisoning, the manufacturing method comprising at least the following steps:

[0019] S1, providing a substrate,

[0020] S2, forming three layers of thin films in sequence on the surface of the substrate, and etching the three layers of thin films into a Josephson junction, wherein the Josephson junction includes a bottom electrode, a first insulating material layer and a top electrode; the first insulating material layer is arranged between the bottom electrode and the top electrode; and the bottom electrode is arranged on the substrate;

[0021] S3, forming a second insulating material layer on the surface of the Josephson junction structure, and opening a first connection hole, a third connection hole and a contact opening in the second insulating material layer; the first connection hole exposes the top electrode, the third connection hole exposes the bottom electrode, and the contact opening exposes the bottom electrode;

[0022] S4, forming a resistor layer on the second insulating material layer, and forming a normal metal layer on the second insulating material layer at the bottom of the contact opening and the edge of the contact opening, wherein the portion of the normal metal layer disposed on the second insulating material layer is the edge portion of the normal metal layer, and the portion of the normal metal layer disposed on the bottom electrode through the contact opening is the middle portion of the normal metal layer;

[0023] S5, forming a third insulating material layer, wherein the third insulating material layer is deposited on the edges of the second insulating material layer, the resistance layer and the normal metal layer; and a ring hole and a second connecting hole are opened in the third insulating material layer, both for exposing the resistance layer;

[0024] S6, forming a wiring layer, the wiring layer comprising a first part and a second part, the first part of the wiring layer and the second part of the wiring layer are separated by the resistance layer exposed by the second connecting hole, the first part of the wiring layer is electrically connected to the top electrode through the first connecting hole, the first part of the wiring layer and the second part of the wiring layer are both electrically connected to the resistance layer through the annular hole, and the second part of the wiring layer is connected to the bottom electrode through the third connecting hole.

[0025] Preferably, in step S4, an adhesive layer is firstly sputtered onto the second insulating material layer, and then the resistance layer is sputtered onto the second insulating material layer, the adhesive layer corresponding to the resistance layer.

[0026] Preferably, the material used for the adhesive layer is Ti.

[0027] As described above, the superconducting quantum circuit structure capable of suppressing quasiparticle poisoning and the manufacturing method thereof of the present invention have the following beneficial effects:

[0028] A superconducting digital circuit structure of the present invention comprises a substrate, a superconducting structure and a normal metal layer. The superconducting digital circuit structure manufactures a normal metal trap containing a normal metal trap capable of suppressing quasiparticle poisoning through the normal metal layer, thereby reducing and minimizing the generated quasiparticles, and can reduce the loss caused by quasiparticles in the superconducting digital circuit, which is conducive to the on-chip integration of superconducting digital circuits and superconducting quantum bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Shown is a schematic diagram of the principle of the normal metal trap capturing quasi-particle mechanism of the present invention.

[0030] Figure 2 It is a schematic diagram showing the energy loss caused by inelastic scattering of some electrons in the normal metal trap of the present invention.

[0031] Figure 3 Shown is a schematic diagram of the structure of a superconducting quantum circuit in an embodiment of the present invention.

[0032] Figure 4 Shown is an optical microscope image of a DC / SFQ converter and CPWR according to an embodiment of the present invention.

[0033] Figure 5 Shown is the CPWR-1 quality factor measurement result of an embodiment of the present invention.

[0034] Figure 6 Shown is the CPWR-2 quality factor measurement result of an embodiment of the present invention.

[0035] Component number description

[0036] 00 Normal metal layer

[0037] 011 Edge of normal metal layer

[0038] 012 The middle part of the normal metal layer

[0039] 10 Substrate

[0040] 11 Josephson knot

[0041] 111 Bottom electrode

[0042] 112 first insulating material layer

[0043] 113 Top electrode

[0044] 12. Second insulating material layer

[0045] 13. Third insulating material layer

[0046] 14. Resistor layer

[0047] 15 Power Distribution Layer

[0048] 151 The first part of the power distribution layer

[0049] 152 The second part of the distribution layer DETAILED DESCRIPTION

[0050] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] See also Figure 1-6 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0052] The present invention aims to solve the harm caused by quasiparticle poisoning in superconducting digital circuits and provide a superconducting digital circuit that can suppress quasiparticle poisoning. The invention mainly uses the energy level difference formed by the superconducting band gap between the superconductor and the normal metal (normal metal, non-superconducting metal) to capture the quasiparticles with the normal metal, thereby reducing the life of the quasiparticles and the cumulative number of quasiparticles in the superconductor, so as to achieve the purpose of suppressing the quasiparticles. The principle is as follows Figure 1 and Figure 2 As shown, the superconducting band gap of normal metal is zero. After entering the normal state, the quasiparticles lose energy due to inelastic scattering with electrons, which is insufficient to cross the energy gap between the normal state and the superconducting state and return to the superconductor. As a result, they are trapped in the normal metal layer 00 and cannot return to the superconductor. This can reduce and decrease the quasiparticles, thereby achieving the purpose of suppressing quasiparticles.

[0053] Embodiment 1:

[0054] The superconducting digital circuit structure capable of suppressing quasiparticle poisoning of the present invention comprises a substrate, a superconducting structure and a normal metal layer; the superconducting structure is arranged on the substrate 10, the normal metal layer is electrically connected to the bottom electrode 111 of the superconducting structure, and the normal metal layer 00 is used to suppress the quasiparticles generated by the superconducting digital circuit.

[0055] Based on the above principle, the present invention proposes a superconducting digital circuit structure that can suppress quasiparticle poisoning. The superconducting digital circuit structure uses a normal metal layer to create normal metal traps that can suppress quasiparticle poisoning, thereby reducing and minimizing the quasiparticles generated, thereby achieving the effect of suppressing quasiparticle poisoning.

[0056] The superconducting structure of the present invention comprises a bottom electrode 111, a first insulating material layer 112, a top electrode 113, a second insulating material layer 12, a resistance layer 14, a third insulating material layer 13 and a wiring layer 15;

[0057] The first insulating material layer 112 is disposed between the bottom electrode 111 and the top electrode 113, and the bottom electrode 111, the first insulating material layer 112 and the top electrode 113 form a Josephson junction 11;

[0058] The second insulating material layer 12 is disposed on the Josephson junction 11;

[0059] The resistance layer 14 is disposed on the second insulating material layer 12;

[0060] The third insulating material layer 13 is disposed on the second insulating material layer 12, the resistance layer 14 and the edge portion 011 of the normal metal layer;

[0061] The wiring layer 15 is disposed on the third insulating material layer 13 , and a first portion 151 of the wiring layer electrically connects the top electrode 113 and the resistance layer 14 , and a second portion 152 of the wiring layer electrically connects the resistance layer 14 and the bottom electrode 15 .

[0062] In the embodiment of the present invention, a superconducting structure is formed by a bottom electrode 111, a first insulating material layer 112, a top electrode 113, a second insulating material layer 12, a resistor layer 14, a third insulating material layer 13 and a wiring layer 15. The superconducting structure is described as an example and is not intended to be a specific limitation of the present invention. In the embodiment of the present invention, an edge portion 011 of the normal metal layer is disposed on the second insulating material layer, and a middle portion 012 of the normal metal layer is disposed on the bottom electrode, that is, the normal metal layer 00 includes an edge portion 011 of the normal metal layer and a middle portion 012 of the normal metal layer. The normal metal layer 00 not only includes the middle portion 012 of the normal metal layer disposed on the bottom electrode 111, but also includes an edge portion 011 of the normal metal layer, in order to ensure that the manufactured normal metal trap can be completely covered.

[0063] In the embodiment of the present invention, a first connection hole is provided on the second insulating material layer 12, the first connection hole exposes the top electrode 113, and the top electrode 113 is electrically connected to the first part of the wiring layer 15 through the first connection hole. The present invention realizes penetrating the second insulating material layer 12 and the third insulating material layer through the first connection hole, and realizes the electrical connection between the wiring layer 15 and the top electrode 113, and the specific electrical connection is to arrange the wiring layer in the first connection hole.

[0064] In the embodiment of the present invention, an annular ring is provided on the third insulating material layer 13, and the annular ring exposes the resistor layer 14, and the resistor layer 14 is electrically connected to the first part of the wiring layer 15 and the second part of the wiring layer through the annular ring. The present invention exposes a local area of ​​the resistor layer 14 through the annular ring, and then a part of the wiring layer 15 is arranged in the annular ring, so as to realize the electrical connection between the wiring layer 15 and the resistor layer 14.

[0065] In an embodiment of the present invention, a second connection hole is provided on the third insulating material layer 13, the second connection hole exposes the resistor layer, and the second connection hole is used to separate the first part 151 of the wiring layer and the second part 152 of the wiring layer; and the second connection hole is located in the annular ring to expose the middle part of the resistor layer 14 to the air. In the present invention, the annular ring and the second connection hole are concentric, and the outer diameter of the second connection hole is smaller than the inner diameter of the annular ring to ensure that the middle part of the resistor layer 14 is exposed and in contact with the air. The present invention does not impose strict restrictions on the shape and position requirements of the second connection hole and the annular ring. As other embodiments, the annular ring and the second connection hole may also be non-concentric, as long as it can ensure that the wiring layer 15 and the resistor layer 14 can be electrically connected while exposing a partial area of ​​the resistor layer to the air.

[0066] In the embodiment of the present invention, a third connection hole is provided on the second insulating material layer 12, and the third connection hole exposes the bottom electrode 111, and the bottom electrode 111 is connected to the second portion 152 of the wiring layer through the third connection hole. The present invention exposes a local area of ​​the bottom electrode 111 through the third connection hole, and then a portion of the wiring layer 15 is disposed in the third connection hole, thereby achieving electrical connection between the wiring layer 15 and the bottom electrode 111.

[0067] In the embodiment of the present invention, a contact opening is provided on the second insulating material layer 12, and the contact opening exposes the bottom electrode 111, and the bottom electrode 111 is electrically connected to the middle portion of the normal metal layer 00 through the contact opening. The present invention forms a normal metal trap by providing a contact opening on the second insulating material layer 12 and placing the normal metal layer 00 in the contact opening to capture the quasi-particles.

[0068] In the embodiment of the present invention, the process requirements of each layer in the superconducting digital circuit structure are shown in Table 1, including the materials used, thickness, film forming method and patterning; specifically:

[0069] The material used for the substrate is Si, which serves as the basis for the entire superconducting digital circuit structure;

[0070] The material used for the bottom electrode 111 (L1 layer) is Nb, and its thickness is 150nm. The bottom electrode 111 needs to be grown into a film by magnetron sputtering first, and then i-line stepper patterning is performed, specifically using RIE (Reactive Ion Etching) etching, that is, reactive ion etching.

[0071] The material of the first insulating material layer 112 (L2 layer) is Al, and its thickness is 10nm. The first insulating material layer is first formed by in-situ oxidation / magnetron sputtering, and then i-line stepper patterning is performed, specifically by wet etching with AZ300 developer. Specifically, due to the electrical connection between the wiring layer 15 and the top electrode 113, the Al connected to the wiring layer 15 is oxidized to form aluminum oxide AlO x , so that the first insulating material layer 112 insulates the top electrode 113 and the bottom electrode 111. In fact, the material of the first insulating material layer is Al / AlO x .

[0072] The material used for the top electrode 113 (L3 layer) is Nb, and its thickness is 150 nm. The top electrode 113 needs to be first grown into a film by magnetron sputtering, and then patterned by i-line stepper, specifically by RIE etching.

[0073] Among them, the superconducting structure in this embodiment takes the Josephson junction as the basic structure, therefore, the bottom electrode 111 (L1 layer), the first insulating material layer 112 (L2 layer) and the top electrode 113 (L3 layer) are formed by three in-situ magnetron sputtering and in-situ oxidation after sputtering Al, and then they are etched to complete the manufacture of the Josephson junction, that is, the Josephson junction is realized as a Nb / Al-AlOx / Nb junction.

[0074] The second insulating material layer (L4 layer) is made of SiO2 with a thickness of 200 nm. The second insulating material layer is first grown into a film by PECVD (chemical vapor deposition) and then patterned by i-line stepper, specifically by RIE etching.

[0075] The material used for the resistance layer (L5 layer) is Pd, and its thickness is 45nm. It is first grown into a film by magnetron sputtering, and then i-line stepper patterning is performed, specifically using IBE, that is, ion beam etching.

[0076] The third insulating material layer (L6 layer) is made of SiO2 with a thickness of 100 nm. The third insulating material layer is first grown into a film by PECVD (chemical vapor deposition) and then patterned by i-line stepper, specifically by RIE etching.

[0077] The wiring layer (L7 layer) is made of Nb with a thickness of 350 nm. It is grown into a film by magnetron sputtering and then patterned by i-line stepper, specifically by RIE etching.

[0078] It should be noted that the process requirements in Table 1 of this embodiment are not intended to be specific limitations on the technical concept of the present invention. For example, the thickness may also be other values, which are set according to actual applications.

[0079] Table 1

[0080] Layer Name Material Thickness(nm) Film forming method Graphical L1 Nb 150 Magnetron sputtering RIE L2 <![CDATA[Al / AlO x ]]> 10 In-situ oxidation / magnetron sputtering Developer Etching L3 Nb 150 Magnetron sputtering RIE L4 <![CDATA[SiO2]]> 200 PECVD RIE L5 Pd 45 Magnetron sputtering IBE L6 <![CDATA[SiO2]]> 100 PECVD RIE L7 Nb 350 Magnetron sputtering RIE

[0081] Embodiment 2:

[0082] In order to solve the above technical problems, the present invention also provides a method for manufacturing a superconducting digital circuit structure capable of suppressing quasiparticle poisoning, the manufacturing method at least comprising the following steps:

[0083] S1, providing a substrate,

[0084] The substrate in this embodiment serves as the structural basis of the entire superconducting digital circuit structure;

[0085] S2, forming three layers of thin films in sequence on the surface of the substrate, and etching the three layers of thin films into a Josephson junction, wherein the Josephson junction includes a bottom electrode, a first insulating material layer and a top electrode; the first insulating material layer is arranged between the bottom electrode and the top electrode; and the bottom electrode is arranged on the substrate;

[0086] The three-layer film in this step is the bottom electrode (L1 layer), the first insulating material layer (L2 layer) and the top electrode (L3 layer), wherein the bottom electrode (L1 layer) and the top electrode (L3 layer) are made of Nb, and the first insulating material layer (L2 layer) is made of Al. The three-layer film is formed by three in-situ magnetron sputtering, and then the first insulating material layer with insulating function is formed by in-situ oxidation after sputtering Al. In other words, the first insulating material layer includes Al and AlO x ; Finally, the three-layer film with insulating function is etched to obtain the Josephson junction, that is, the basic unit of the superconducting structure is manufactured.

[0087] S3, forming a second insulating material layer on the surface of the Josephson junction structure, and opening a first connection hole, a third connection hole and a contact opening in the second insulating material layer; the first connection hole exposes the top electrode, the third connection hole exposes the bottom electrode, and the contact opening exposes the bottom electrode;

[0088] In this step, the material used for the second insulating material layer is SiO2, and the Joseph connection hole (i.e., the first connection hole), as well as the contact opening and the normal metal trap of the bottom electrode (L1 layer) are opened by etching. The contact opening here is smaller than the known normal metal trap area to ensure that the contact opening can be completely covered by the normal metal trap; that is, the middle part of the normal metal layer is in the contact opening, and the edge part of the normal metal layer is arranged on the second insulating material layer, so that the normal metal layer can safely cover the contact opening.

[0089] S4, forming a resistor layer on the second insulating material layer, and forming a normal metal layer on the second insulating material layer at the bottom of the contact opening and at the edge of the contact opening, wherein the portion of the normal metal layer disposed on the second insulating material layer is the edge portion of the normal metal layer, and the portion of the middle portion of the normal metal layer disposed on the bottom electrode through the contact opening is the middle portion of the normal metal layer;

[0090] In the step, an adhesive layer is firstly sputtered onto the second insulating material layer, and then the resistance layer is sputtered onto the second insulating material layer, the adhesive layer corresponds to the resistance layer.

[0091] When sputtering the normal metal layer and the resistance layer, in the actual manufacturing process, a sticky layer with a thickness of about 10 nm can be sputtered before the resistance layer and the normal metal layer are sputtered to increase the adhesion between the resistance layer and the second insulating material layer. The material used for the sticky layer is Ti. At the same time, the parallel resistor used to eliminate the Josephson junction hysteresis and the normal metal layer are completed in the photolithography of this layer to form a normal metal trap;

[0092] S5, forming a third insulating material layer, wherein the third insulating material layer is deposited on the edges of the second insulating material layer, the resistance layer and the normal metal layer; and a ring hole and a second connecting hole are opened in the third insulating material layer, both for exposing the resistance layer;

[0093] In this step, a third insulating material film is first sputtered to form, and then a third insulating material layer is obtained by etching. A ring hole is opened on the third insulating material layer to expose a local area of ​​the resistor layer, and a second connecting hole is opened on the third insulating material layer. The second connecting hole also exposes another local area of ​​the resistor layer to be exposed to the air.

[0094] S6, forming a wiring layer, the wiring layer comprising a first part and a second part, the first part of the wiring layer and the second part of the wiring layer are separated by the resistance layer exposed by the second connecting hole, the first part of the wiring layer is electrically connected to the top electrode through the first connecting hole, the first part of the wiring layer and the second part of the wiring layer are both electrically connected to the resistance layer through the annular hole, and the second part of the wiring layer is connected to the bottom electrode through the third connecting hole.

[0095] The superconducting digital circuit structure of the present invention can manufacture a superconducting circuit device containing a normal metal trap for suppressing quasiparticle poisoning without adding superconducting structure technology during the manufacturing process.

[0096] Based on this process, we designed and manufactured Figure 4 The sample shown in Figure 1. In the middle of the sample is a DC / SFQ converter, a common part in an SFQ circuit. When it is working, it becomes a device based on a superconducting digital circuit. On the left and right sides of the sample, there is a superconducting coplanar waveguide resonator (CPWR) with an almost identical design and symmetrical position, where a normal metal trap is made around the left resonant cavity. The quality factors of the two resonant cavities of the DC / SFQ converter are measured at different bias currents and driving microwave amplitudes. The measurement results are shown in Figure 1. Figure 5 and Figure 6 As shown. For the case where there is no normal metal trap resonant cavity around (CPWR-1), the quality factor drops significantly when the DC / SFQ converter starts to work, that is, the quasiparticles cause significant additional losses to it; for the case where a normal metal trap resonant cavity is made around (CPWR-2), regardless of whether the DC / SFQ converter starts to work or not, its quality factor has no significant rise or fall associated with it, that is, the quasiparticles are captured by the normal metal traps near CPWR-2, and they are suppressed to a certain extent on the left. This experimental result is a proof of the effectiveness of suppressing quasiparticle poisoning by normal metal trap suppression in the present invention.

[0097] In summary, the superconducting digital circuit structure and the manufacturing method thereof of the present invention can also be understood as a quasiparticle poisoning suppression method that can be integrated into the design and manufacture of superconducting digital circuits, which can reduce the loss caused by quasiparticles in superconducting quantum circuits and facilitate the on-chip integration of superconducting digital circuits and superconducting quantum bits. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0098] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a superconducting digital circuit structure capable of suppressing quasiparticle poisoning, characterized in that: The manufacturing method comprises at least the following steps: S1, providing a substrate; S2, forming three layers of thin films in sequence on the surface of the substrate, and etching the three layers of thin films into a Josephson junction, wherein the Josephson junction includes a bottom electrode, a first insulating material layer and a top electrode; the first insulating material layer is arranged between the bottom electrode and the top electrode; and the bottom electrode is arranged on the substrate; S3, forming a second insulating material layer on the surface of the Josephson junction structure, and opening a first connection hole, a third connection hole and a contact opening in the second insulating material layer; the first connection hole exposes the top electrode, the third connection hole exposes the bottom electrode, and the contact opening exposes the bottom electrode; S4, forming a resistor layer on the second insulating material layer, and forming a normal metal layer on the second insulating material layer at the bottom of the contact opening and at the edge of the contact opening, wherein the portion of the normal metal layer disposed on the second insulating material layer is the edge portion of the normal metal layer, and the portion of the normal metal layer disposed on the bottom electrode through the contact opening is the middle portion of the normal metal layer; S5, forming a third insulating material layer, wherein the third insulating material layer is deposited on the edges of the second insulating material layer, the resistance layer and the normal metal layer; and a ring hole and a second connecting hole are opened in the third insulating material layer, both for exposing the resistance layer; S6, forming a wiring layer, the wiring layer comprising a first part and a second part, the first part of the wiring layer and the second part of the wiring layer are separated by the resistance layer exposed by the second connecting hole, the first part of the wiring layer is electrically connected to the top electrode through the first connecting hole, the first part of the wiring layer and the second part of the wiring layer are both electrically connected to the resistance layer through the annular hole, and the second part of the wiring layer is connected to the bottom electrode through the third connecting hole.

2. The method for manufacturing a superconducting digital circuit structure capable of suppressing quasiparticle poisoning according to claim 1, characterized in that: In step S4, an adhesive layer is firstly sputtered onto the second insulating material layer, and then the resistance layer is sputtered onto the second insulating material layer, wherein the adhesive layer corresponds to the resistance layer.

3. The method for manufacturing a superconducting digital circuit structure capable of suppressing quasiparticle poisoning according to claim 2, characterized in that: The material used for the adhesive layer is Ti.

4. A superconducting digital circuit structure capable of suppressing quasiparticle poisoning, which is realized based on the manufacturing method of the superconducting digital circuit structure capable of suppressing quasiparticle poisoning according to any one of claims 1 to 3, characterized in that: It comprises a substrate, a superconducting structure and a normal metal layer; the superconducting structure is arranged on the substrate, the normal metal layer is electrically connected to the bottom electrode of the Josephson junction in the superconducting structure, and the normal metal layer is used to suppress quasi-particles generated by the superconducting digital circuit; the superconducting structure comprises a bottom electrode, a first insulating material layer, a top electrode, a second insulating material layer, a resistance layer, a third insulating material layer and a wiring layer; the first insulating material layer is arranged between the bottom electrode and the top electrode, and the bottom electrode, the first insulating material layer and the top electrode form a Josephson junction; the second insulating material layer is arranged on the Josephson junction; the resistance layer is arranged on the second insulating material layer; the third insulating material layer is arranged on the edge of the second insulating material layer, the resistance layer and the normal metal layer; The wiring layer is disposed on the third insulating material layer, and a first portion of the wiring layer electrically connects the top electrode and the resistance layer, and a second portion of the wiring layer electrically connects the resistance layer and the bottom electrode.

5. The superconducting digital circuit structure capable of suppressing quasiparticle poisoning according to claim 4, characterized in that: The edge portion of the normal metal layer is disposed on the second insulating material layer, and the middle portion of the normal metal layer is disposed on the bottom electrode.

6. The superconducting digital circuit structure capable of suppressing quasiparticle poisoning according to claim 4, characterized in that: A first connection hole is provided in the second insulating material layer, wherein the first connection hole exposes the top electrode, and the top electrode is electrically connected to the first part of the wiring layer through the first connection hole.

7. The superconducting digital circuit structure capable of suppressing quasiparticle poisoning according to claim 6, characterized in that: The third insulating material layer is provided with an annular ring, the annular ring exposing the resistor layer, and the resistor layer is electrically connected to the first part of the wiring layer and the second part of the wiring layer through the annular ring.

8. The superconducting digital circuit structure capable of suppressing quasiparticle poisoning according to claim 7, characterized in that: A second connection hole is provided on the third insulating material layer, the second connection hole exposes the resistance layer, and the second connection hole is used to separate the first part of the wiring layer and the second part of the wiring layer.

9. The superconducting digital circuit structure capable of suppressing quasiparticle poisoning according to claim 8, characterized in that: The second connection hole is located in the ring hole to expose a part of the resistance layer to the air.

10. The superconducting digital circuit structure capable of suppressing quasiparticle poisoning according to claim 5, characterized in that: A third connection hole is provided on the second insulating material layer, the third connection hole exposes the bottom electrode, and the bottom electrode is connected to the second part of the wiring layer through the third connection hole.

11. The superconducting digital circuit structure capable of suppressing quasiparticle poisoning according to claim 5, characterized in that: A contact opening is provided on the second insulating material layer, wherein the contact opening exposes the bottom electrode, and the bottom electrode is electrically connected to the middle portion of the normal metal layer through the contact opening.

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