Method and apparatus for self-referenced clockless delay adaptive for random data

Abstract

A method and apparatus for self-referenced clockless delay adaptation of random data. A clockless delay adaptation loop (200) configured to adapt to random data includes first and second delay lines (210, 220), an autocorrelator (230), and a controller. The autocorrelator receives an input signal (205) for the delay adaptation loop and an output (215) from the first delay line, and includes a first logic circuit (235) configured to output a first autocorrelation (240) and a second logic circuit (245) configured to output a second autocorrelation (250). The controller is configured to generate a control signal (280) for one of the first and second delay lines based on the first and second autocorrelations. In some examples, the first logic circuit is an XNOR gate and the second logic circuit is an OR gate. In some examples, the OR gate can have a gain that is twice the gain of the XNOR gate. In some examples, an amplifier having twice the gain of the XNOR gate is coupled to the OR gate.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 045,439, filed June 29, 2020, entitled "Self-Referenced Clockless Delay Adaptation for Random Data," the entire contents of which are hereby incorporated by reference. Technical Field

[0003] This invention relates to the technical field of circuits, and more particularly to a method and apparatus for self-referenced, clock-delay-free adaptive random data. Background Technology

[0004] Equalization is the process of adjusting electrical signals at the transmitter or receiver to compensate for channel-induced inter-symbol interference (ISI) and improve signal integrity. One nonlinear equalization technique is called decision feedback equalization (DFE). In DFE, a delay element is introduced into the receiver circuitry, and the equalization value is combined with the input data stream. In many applications (e.g., adapter drivers), a clock is unavailable, thus requiring a clockless delay line (to delay random data). For a range of permissible data rates, the delay needs to automatically adapt to a unit interval (UI) or a multiple of UI.

[0005] Some clock-delay-free adaptive loops configured to adapt to random data include an autocorrelation control circuit that compares the autocorrelation of an input signal with a reference voltage and outputs a control signal for a delay line based on the comparison. However, the autocorrelation of the input signal can change in response to voltage and temperature variations, which in turn causes variations in the adaptive delay. Furthermore, supplying a reference voltage to the autocorrelation control circuit increases the area and complexity of the clock-delay-free adaptive loop. Summary of the Invention

[0006] A clock-delay-free adaptive loop configured to adapt to random data includes two delay lines, an autocorrelation circuit, and a controller. A first delay line receives an input signal and outputs a first delayed signal. A second delay line receives the first delayed signal and outputs a second delayed signal. The autocorrelation circuit receives the input signal and the first delayed signal and includes an XNOR gate and an OR gate. The XNOR gate outputs a first autocorrelation, and the OR gate outputs a second autocorrelation. The controller generates a control signal for at least one of the delay lines based on the first and second autocorrelation.

[0007] In some instances, the control signal causes at least one of the delay lines to have a delay value of half the unit interval. The OR gate may have a gain twice that of an XNOR gate or be coupled to an amplifier having a gain twice that of an XNOR gate. In some instances, the controller includes a transconductance stage and a capacitor. The transconductance stage receives a first autocorrelation at the positive input and a second autocorrelation at the negative input and outputs a control signal. The capacitor is coupled to the output of the transconductance stage and to ground.

[0008] In some instances, the control signal may be an analog control signal, and the controller may include a first counter that receives a first autocorrelation and a second counter that receives a second autocorrelation. In some instances, the second counter doubles the count of the second autocorrelation. An accumulator and comparator in the controller output a digital control signal based on the outputs from the first and second counters. In some instances, a digital-to-analog converter converts the digital control signal into an analog control signal. In some instances, the first and second delay lines include digital control delay lines and receive the digital control signal.

[0009] In some instances, the delay adaptive loop generates a first control signal for a first delay line and also includes a second autocorrelator and a second controller to generate a second control signal for a second delay line. In some instances, the delay adaptive loop includes a second autocorrelator that receives the first and second delayed signals. The second autocorrelator includes a second XNOR gate that outputs a third autocorrelation and a second OR gate that outputs a fourth autocorrelation. A first summer receives the first and third autocorrelations, and a second summer receives the second and fourth autocorrelations. The controller generates the control signal based on the outputs of the first and second summers.

[0010] In some instances, at least one of the first and second delay lines includes a voltage-to-current converter and a differential amplifier. The voltage-to-current converter receives a control signal and generates a control current. The differential amplifier delays the signal input to the delay line based on the control signal and the control current. In some instances, the voltage-to-current converter includes an operational amplifier (op-amp), three transistors, two resistors, and a current source. The negative input of the operational amplifier receives the control signal, and the control terminals of the first and second transistors receive the output of the operational amplifier.

[0011] The current terminal of the first transistor is coupled to the positive input of the operational amplifier and to ground. The first resistor is coupled to the power supply voltage rail and to the positive input of the operational amplifier and one of the current terminals of the first transistor. The current terminal of the second transistor is coupled to a current source and to ground. One of the current terminals of the third transistor is coupled to a current source, one of the current terminals of the second transistor, and a control terminal of the third transistor. The other current terminal of the third transistor is coupled to a second resistor, which is further coupled to ground. Attached Figure Description

[0012] For a detailed description of various examples, please refer to the accompanying drawings, in which:

[0013] Figure 1 Describe an example communication system that includes a repeater or transfer driver.

[0014] Figure 2 This example illustrates a delay-adaptive loop.

[0015] Figure 3 Show the autocorrelation curves using XNOR gates and the autocorrelation curves using OR gates.

[0016] Figure 4 This section describes an example delay-adaptive loop with independent autocorrelators for each delay line.

[0017] Figure 5 This illustrates an example delay adaptive loop with a single transconductance stage and a single integrated capacitor for two delay lines.

[0018] Figure 6 This section describes an example delay-adaptive loop with a digital autocorrelation controller.

[0019] Figure 7 Example of a voltage-controlled delay line. Detailed Implementation

[0020] This paper discloses a delay-adaptive loop topology employing an autocorrelation function. In the presence of inter-symbol interference (ISI), the autocorrelation function can have a non-zero tail with a time shift exceeding one UI. A more robust option involves locking the autocorrelation function to 0.5UI by forcing it to 0.5 (instead of 0). Instead of comparing the autocorrelation with a reference voltage, the delay-adaptive loop described in this paper uses two different methods that intersect at 0.5UI to calculate the autocorrelation and compares the two autocorrelation values.

[0021] As described herein, the example delay element comprises a voltage-controlled delay line (VCDL) controlled by an autocorrelator and a controller. The autocorrelator comprises an XNOR gate and an OR gate, both receiving input data provided to the VCDL and delayed data output from the VCDL. In some embodiments, the OR gate has a gain twice that of the XNOR gate. In some embodiments, the OR gate has a gain substantially the same as that of the XNOR gate and is coupled to an amplifier having a gain twice that of the XNOR gate. The controller compares the output from the XNOR gate with the output from the OR gate and generates control signals for one or more of the VCDLs in the delay loop.

[0022] Figure 1This describes an example communication system 100 that includes a repeater or adapter driver 130. In addition to the adapter driver 130, the communication system 100 also includes a transmitter 110, a first channel 120, a repeater or adapter driver 130, a second channel 175, and a receiver 180. A transmission signal 105 is output from the transmitter 110 and represented by a transmission signal eye diagram 115. After transmission via the first channel 120, the transmission signal 105 is no longer distinguishable, as represented by a reception signal eye diagram 125. The repeater or adapter driver 130 is used to recover the transmission signal 105 from the transmitter 120, and a driver 165 is used to forward the signal. The signal forwarded by the driver 165 is represented by a recovered signal eye diagram 170. The recovered signal is transmitted by the driver 165 to the receiver 180 via the second channel 175. Channels 120 and 175 represent the physical transmission medium (e.g., cable, board trace, optical fiber, etc.) used to transmit signals between transmitter 110 and repeater or transfer driver 130 and between transfer driver 130 and receiver 180.

[0023] exist Figure 1 In one example, the repeater or transfer driver 130 includes a continuous-time linear equalizer (CTLE) 135 and a clockless DFE loop 140. The equalization operation of the CTLE 135 and the clockless DFE loop 140 facilitates the recovery of the transmitted signal 105. Figure 1 In one example, the DFE loop 140 includes a summer 145 and a delay adaptive loop 150 with a cascaded delay line 155 and an autocorrelation control circuit 160. In some examples, the cascaded delay line 155 includes at least one VCDL and DFE tap circuit. In the clockless DFE loop 140, the summer 145 subtracts the output of the delay adaptive loop 150 from the output of CTLE 135 and provides the difference to the driver 165 and the delay adaptive loop 150. In the delay adaptive loop 150, the autocorrelation control circuit 160 receives input / output data from the cascaded delay line 155 and correlates the input / output data. The correlation is used to generate a control signal Vctrl for the cascaded delay line 155.

[0024] Figure 2 Explanation can be replaced Figure 1 The example delay adaptive loop 200 used in the delay adaptive loop 150 shown is an example delay adaptive loop 200. The delay adaptive loop 200 includes a first VCDL 210, a second VCDL 220, an autocorrelator 230, a transconductance stage 260, and a capacitor 270. The transconductance stage 260 and capacitor 270 can be considered as controllers. Although delay lines 210 and 220 are VCDLs in this example, any suitable delay line, such as a current-controlled delay line or a digitally controlled delay line, can be used in place of or in combination with VCDLs 210 and 220. Input Vin 205 (e.g., Figure 1 The output of the summer 145 shown is provided to the autocorrelator 230 and to the VCDL 210, which outputs a delayed signal 215. The delayed signal 215 is provided to the autocorrelator 230 and to the VCDL 220, which outputs an output signal Vout 290. The outputs 240 and 250 from the autocorrelator 230 are provided to the transconductance stage 260. The output Vctrl 280 of the transconductance stage 260 is integrated using a capacitor 270, which is further coupled to ground 275. Vctrl 280 is provided to the VCDLs 210 and 220 to adjust the delay implemented by the VCDLs 210 and 220.

[0025] Autocorrelator 230 includes an XNOR gate 235 and an OR gate 245, both of which receive Vin 205 and a delay signal 215. The OR gate 245 can be configured to implement a gain twice that of the XNOR gate 235. The output 240 from the XNOR gate 235 is provided to the positive input of the transconductance stage 260, and the output 250 from the OR gate 245 is provided to the negative input of the transconductance stage 260. Instead of comparing to a reference voltage, the autocorrelation output 240 from the XNOR gate 235 is compared to the autocorrelation output 250 from the OR gate 245. The XNOR gate 235 and the OR gate 245 can be implemented such that they are matched in terms of process, voltage, and temperature (PVT) variations, reducing the variation of the adaptive delay in terms of PVT variations compared to a delay adaptive loop with a reference voltage.

[0026] Figure 3 Graph 300 shows the autocorrelation 240 using XNOR gate 235 and the autocorrelation 250 using OR gate 245 with twice the gain of XNOR gate 235. For the random data stream Vin 205, the average XNOR 235 of data Vin 205 and delayed data 215 decreases with increasing delay and flattens out when the delay exceeds one UI. Similarly, the average OR 245 of data Vin 205 and delayed data 215 increases with increasing delay and flattens out when the delay exceeds one UI. The autocorrelation 240A to C using XNOR gate 235 represents different channel losses and diverges as the delay approaches and exceeds one UI. Similarly, the autocorrelation 250A to C using OR gate 245 represents different channel losses and diverges as the delay approaches and exceeds one UI. Although the variation is due to different channel losses, the average value of XNOR and twice the average value of OR intersect at approximately 0.5 UI, thus allowing Vctrl 280 to control VCDL 210 and 220 to each implement a 0.5 UI delay, so that the total delay of cascaded VCDL 210 and 220 is one UI.

[0027] Figure 4 This describes an example delay adaptive loop 400 with independent autocorrelators for each VCDL. The individual autocorrelators and control loops for each VCDL allow the delay implemented by each VCDL to be adjusted to 0.5UI independently of the other delays. The delay adaptive loop 400 is essentially the same as... Figure 2 The delay adaptive loop 200 shown is the same, but also includes a second autocorrelator 430, a second transconductance stage 460, and a second capacitor 470. The transconductance stage 260 outputs the control signal Vctrl,1280 to VCDL 210 instead of VCDL 220.

[0028] The second autocorrelator 430 includes a second XNOR gate 435 and a second OR gate 445, the second OR gate 445 being configured to implement a gain twice that of the XNOR gate 435. The XNOR gate 435 and the OR gate 445 each receive a delayed signal 215 and an output Vout 290. The output 440 from the XNOR gate 435 is provided to the positive input of the second transconductance stage 460, and the output 450 from the OR gate 445 is provided to the negative input of the second transconductance stage 460. A capacitor 470 is used to integrate the output Vctrl,2 480 from the second transconductance stage, the capacitor 470 being further coupled to ground 275. The output Vctrl,2 480 is provided to the second VCDL 220.

[0029] Figure 5 This describes an example delay adaptive loop 500 with a single transconductance stage and a single integrated capacitor for two VCDLs. Using the same transconductance stage and integrated capacitor for both VCDLs reduces power consumption and area. Depending on the mismatch between the VCDLs, the VCDLs can be locked to slightly above or below 0.5 UI, while the total delay across the two VCDLs is locked to one UI. The delay adaptive loop 500 is essentially the same as... Figure 2 The delay adaptive loop 200 shown is the same, but also includes a second autocorrelator 530 and summers 560 and 570.

[0030] The second autocorrelator 530 includes a second XNOR gate 535, a second OR gate 545A, and an amplifier 545B. The OR gate 545A implements a gain approximately equal to that of the XNOR gate 535 and is coupled to the amplifier 545B, which has a gain twice that of the XNOR gate 535. The outputs 240 and 540 from the XNOR 235 and XNOR 535 are added together by a summer 560. The output 565 of the summer 560 is provided to the positive input of the transconductance stage 260. The outputs 250 and 550 from the OR 245 and amplifier 545B are added together by a summer 570. The output 575 of the summer 570 is provided to the negative input of the transconductance stage 260.

[0031] Figure 6 This illustrates an example delay-adaptive loop 600 with a digital feedback loop 610. The delay-adaptive loop 600 is essentially the same as... Figure 2 The delay adaptive loop 200 shown is identical, but includes a digital feedback loop 610 and a digital-to-analog converter (DAC) 660 as the controller, instead of transconductance stage 260 and capacitor 270. The digital feedback loop 610 includes a first counter 620, a second counter 630, and an accumulator and comparator 640. The first counter 620 receives output 240 from an XNOR gate 235, and the second counter 630 receives output 250 from an OR gate 240. In this example, the OR gate 245 has substantially the same gain as the XNOR gate 235. The second counter 630 is configured to double the count from output 250. The outputs of counters 620 and 630 are provided to the accumulator and comparator 640. Output 650 is provided to the DAC 660, which outputs Vctrl 280 to VCDL 210 and 220.

[0032] Figure 7 Example voltage-controlled delay line 700 includes a voltage-to-current (VI) converter 730 and a differential amplifier 750. The VI converter 730 includes n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) M1 and M2 and a bipolar junction transistor (BJT) Q1. The differential amplifier 750 includes BJTs Q2 through Q9. In this example, M1 and M2 are n-type MOSFETs (NMOS). In other examples, one or more of M1 and M2 are p-type MOSFETs (PMOS) or BJTs. In this example, Q1 through Q9 are BJTs. In other examples, Q1 through Q9 are MOSFETs. Each BJT includes a base corresponding to a gate terminal, and collector and emitter corresponding to drain and source terminals. The base of the BJT and the gate terminal of the MOSFET are also referred to as control inputs. The collector and emitter of the BJT and the drain and source terminals of the MOSFET are also referred to as current terminals.

[0033] In addition to M1 to M2 and Q1, the VI converter 730 also includes an operational amplifier (op-amp) 735, resistors R1 and R2, and a current source 740. Resistor R1 is coupled between the voltage power rail Vdd 705 and the drain terminal of M1. The source terminal of M1 is coupled to ground 710. Current source 740 is coupled between the voltage power rail Vdd 705 and the drain terminal of M2. The source terminal of M2 is coupled to ground 710. The base and collector terminals of Q1 are also coupled to current source 740 and the drain terminal of M1. The emitter terminal of Q1 is coupled to R2, which is further coupled to ground 710.

[0034] The gate terminals of M1 and M2 are coupled to the output of operational amplifier 735. The positive input of operational amplifier 735 is coupled to the drain terminals of R1 and M1. The negative input of operational amplifier 735 is configured, for example, from... Figure 6 The DAC 660 or shown in the video Figure 2 The transconductance stage 260 shown receives the control signal Vctrl 715. The current source 740 is configured to generate a current It. The current I1 through M1 and M2 is expressed as:

[0035]

[0036] The current Ictrl through Q1 is expressed as:

[0037]

[0038] The current It from current source 740 and (Vdd 705 / R1) are constant.

[0039] Q1 in the VI converter 730 is a portion of the current mirror of BJTs Q2 through Q5 in the differential amplifier 750. Q2 and Q3 produce copies of Ictrl, and Q4 and Q5 produce twice the current of Ictrl. R10 is coupled to the node to which Vctrl 715 is applied and to voltage-dependent capacitors (varactor diodes) C1 and C2. C1 is further coupled to the source terminal of Q8, and C2 is further coupled to the source terminal of Q9. The delay of the differential amplifier 750 can be tuned by adjusting the capacitance of varactor diodes C1 and C2 based on Vctrl 715. For a higher tuning range, Ictrl is generated using the VI converter 730 as a function of Vctrl 715.

[0040] The term "coupled" is used throughout this specification. This term may encompass a connection, communication, or signal path that achieves a functional relationship consistent with the description of this invention. For example, if device A generates a signal to control device B to perform an action, then in a first instance, device A is coupled to device B, or in a second instance, device A is coupled to device B via an intermediary component C, provided that the intermediary component C does not substantially alter the functional relationship between device A and device B such that device A controls device B via a control signal generated by device A.

[0041] Within the scope of the claims, modifications are possible in the described embodiments, and other embodiments are also possible.

Claims

1. A clock-delay-free adaptive loop configured to adapt to random data, the loop comprising: A first delay line is configured to receive an input signal and output a first delay signal; A second delay line is configured to receive the first delay signal and output a second delay signal; An autocorrelation device configured to receive the input signal and the first delayed signal, wherein the autocorrelation device includes: A first logic circuit, configured to output a first autocorrelation; and A second logic circuit, configured to output a second autocorrelation; and A controller configured to generate a control signal for at least one of the first and second delay lines based on the first and second autocorrelation.

2. The clock-delay-free adaptive loop according to claim 1, wherein the first logic circuit includes an XNOR gate, and wherein the second logic circuit includes an OR gate.

3. The clock-delay-free adaptive loop of claim 2, wherein the OR gate is further configured to implement a gain that is twice the gain of the XNOR gate.

4. The clock-delay-free adaptive loop of claim 2, further comprising an amplifier having a gain that is twice the gain of the XNOR gate, wherein the OR gate has a gain approximately equal to the gain of the XNOR gate.

5. The clock-delay-free adaptive loop according to claim 1, wherein the controller comprises: The transconductance stage is configured as follows: The first autocorrelation is received at the positive input and the second autocorrelation is received at the negative input; and Output the control signal for at least one of the first and second delay lines; and A capacitor that is coupled to the output of the transconductance stage and to ground.

6. The clock-delay-free adaptive loop according to claim 1, wherein the control signal includes an analog control signal, and wherein the controller includes: A first counter, configured to receive the first autocorrelation; A second counter, configured to receive the second autocorrelation; The accumulator and comparator are configured to: Receive output from the first and second counters; and Output digital control signals; and A digital-to-analog converter configured to convert the digital control signal for at least one of the first and second delay lines into the analog control signal.

7. The clock-delay-free adaptive loop of claim 6, wherein the second counter is configured to double the count of the second autocorrelation.

8. The clock-delay-free adaptive loop of claim 1, wherein the autocorrelator is a first autocorrelator, wherein the controller is a first controller configured to generate a first control signal for the first delay line, and wherein the clock-delay-free adaptive loop further comprises: A second autocorrelation unit configured to receive the first delayed signal and the second delayed signal, wherein the second autocorrelation unit includes: The third logic circuit is configured to output the third autocorrelation; and A fourth logic circuit, configured to output a fourth autocorrelation; and A second controller is configured to generate a second control signal for the second delay line based on the third and fourth autocorrelation.

9. The clock-delay-free adaptive loop according to claim 1, wherein the autocorrelator is a first autocorrelator, and wherein the clock-delay-free adaptive loop further comprises: A second autocorrelation unit configured to receive the first delayed signal and the second delayed signal, wherein the second autocorrelation unit includes: The third logic circuit is configured to output the third autocorrelation; and The fourth logic circuit is configured to output the fourth autocorrelation; A first summer, configured to receive the first autocorrelation and the third autocorrelation; and A second summer is configured to receive the second autocorrelation and the fourth autocorrelation, wherein the controller is further configured to generate the control signal based on the output of the first summer and the output of the second summer.

10. The clock-delay-free adaptive loop of claim 1, wherein at least one of the first and second delay lines comprises: A voltage-to-current (VI) converter configured to receive the control signal and generate a control current; and Differential amplifier, configured to: Receives one of the control signal, the control current, the input signal, and the first delay signal; and Output one of the first delayed signal and the second delayed signal.

11. An apparatus comprising: The first delay line is coupled to the input; A second delay line, which is coupled to the output of the first delay line; An XNOR gate, which is coupled to the input and the output of the first delay line; and An OR gate, which is coupled to the input and the output of the first delay line; and A controller coupled to the output of the XNOR gate and the output of the OR gate, wherein the controller is further coupled to at least one of the first and second delay lines.

12. The device of claim 11, wherein the controller comprises: A transconductance stage, which is coupled to the output of the XNOR gate and the output of the OR gate; and A capacitor coupled to the output of the transconductance stage and coupled to a ground node, wherein the output of the transconductance stage is further coupled to at least one of the first and second delay lines.

13. The device of claim 11, wherein the controller comprises: A first counter, which is coupled to the output of the XNOR gate; A second counter, which is coupled to the output of the OR gate; and An accumulator and a comparator are coupled to the outputs of the first counter and the second counter.

14. The device of claim 13, wherein the controller further includes a digital-to-analog converter coupled to the outputs of the accumulator and the comparator, wherein the output of the digital-to-analog converter is further coupled to at least one of the first and second delay lines.

15. The device of claim 13, wherein at least one of the first and second delay lines comprises a digitally controlled delay line coupled to the output of the accumulator and the comparator.

16. The device of claim 11, wherein the XNOR gate is a first XNOR gate, the OR gate is a first OR gate, wherein the controller is a first controller coupled to the first delay line, and wherein the device further comprises: A second XNOR gate is coupled to the output of the first delay line and the output of the second delay line; A second OR gate is coupled to the output of the first delay line and the output of the second delay line; and A second controller is coupled to the output of the second XNOR gate and the output of the second OR gate, wherein the second controller is further coupled to the second delay line.

17. The apparatus of claim 11, wherein the XNOR gate is a first XNOR gate, the OR gate is a first OR gate, and wherein the apparatus further comprises: A second XNOR gate is coupled to the output of the first delay line and the output of the second delay line; A second OR gate is coupled to the output of the first delay line and the output of the second delay line; A first summer, coupled to the output of the first XNOR gate and the output of the second XNOR gate; and A second summer is coupled to the output of the first OR gate and the output of the second OR gate, wherein the controller is coupled to the output of the first summer and the output of the second summer.

18. The device of claim 11, wherein at least one of the first and second delay lines comprises: A voltage-to-current (VI) converter coupled to the controller; and Differential amplifier, which is coupled to: The controller; The output of the VI converter; and One of the input and the output of the first delay line.

19. A delay-adaptive loop, comprising: First delay line; Second delay line; A first autocorrelation calculator is configured to apply a first autocorrelation function to the input and output data of at least one of the first and second delay lines to obtain a first autocorrelation. A second autocorrelation calculator is configured to apply a second autocorrelation function to the input data and the output data of at least one of the first and second delay lines to obtain a second autocorrelation. and A controller coupled to the first and second autocorrelation calculators and to at least one of the first and second delay lines, wherein the controller is configured to generate a control signal for the at least one of the first and second delay lines based on the first and second autocorrelation.

20. The delay adaptive loop of claim 19, wherein the first autocorrelation calculator comprises an XNOR gate, and wherein the second autocorrelation calculator comprises an OR gate.

21. The delay adaptive loop of claim 20, wherein the OR gate has a gain that is twice the gain of the XNOR gate.

22. The delay adaptive loop of claim 19, wherein the controller comprises: A transconductance stage having inputs coupled to the first and second autocorrelation calculators and further having an output coupled to at least one of the first and second delay lines; and A capacitor that is coupled to the output of the transconductance stage and to ground.

23. The delay adaptive loop of claim 19, wherein the controller comprises: A first counter, which is coupled to the first autocorrelation calculator; A second counter, which is coupled to the second autocorrelation calculator; An accumulator and a comparator, which are coupled to the first and second counters; and A digital-to-analog converter coupled to the outputs of the accumulator and comparator and further coupled to at least one of the first and second delay lines.

24. The delay adaptive loop of claim 19, wherein the control signal includes a control voltage signal, and wherein at least one of the first and second delay lines comprises: A voltage-to-current converter configured to convert the control voltage signal into a control current; and A differential amplifier configured to delay the input signal of at least one of the first and second delay lines based on the control signal and the control current.

25. An apparatus comprising: A voltage-to-current (VI) converter configured to receive a control voltage Vctrl and generate a control current Ictrl; and A differential amplifier configured to delay the input signal based on Vctrl and Ictrl; The VI converter includes: An operational amplifier (op-amp) includes a positive input, a negative input configured to receive Vctrl, and an output; The first transistor includes a first control terminal coupled to the output of the operational amplifier, a first current terminal coupled to the positive input of the operational amplifier, and a second current terminal coupled to ground. A first resistor is coupled to a power supply voltage rail and to the positive input of the operational amplifier and the first current terminal of the first transistor; The second transistor includes a second control terminal coupled to the output of the operational amplifier, a third current terminal, and a fourth current terminal coupled to ground; A current source coupled to the third current terminal; A third transistor includes a fifth current terminal, a sixth current terminal, and a third control terminal coupled to the current source and the third current terminal, wherein the fifth current terminal is coupled to the third control terminal, the current source, and the third current terminal; and The second resistor is coupled to the sixth current terminal and to ground.

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