Semiconductor structure, fabrication method, and three-dimensional memory
By simultaneously forming isolation trenches and recessed gate structures of different depths in a three-dimensional memory, the problems of cumbersome process and high cost are solved, and the storage density is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2021-08-31
- Publication Date
- 2026-07-21
AI Technical Summary
The existing 3D memory manufacturing process is cumbersome, leading to increased costs and making it difficult to increase storage density without increasing storage area.
By simultaneously forming a first isolation trench and a second isolation trench in the first device region and the second device region, with the depth of the second isolation trench being the sum of the depths of the first isolation trench and the first groove, the isolation requirements of different semiconductor devices can be met by combining the recessed gate structure and the dual STI process.
Without increasing the process flow, it achieves good isolation, reduces costs, and increases storage density.
Smart Images
Figure CN113939906B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor structure, fabrication method, and three-dimensional memory. Background Technology
[0002] 3D NAND Flash memory is widely used in computers, solid-state drives, and electronic devices due to its advantages such as high storage density and fast programming speed. Market demands are constantly increasing storage capacity without increasing storage area; to meet this demand, it is necessary to increase the storage density and reduce the size of 3D NAND Flash memory.
[0003] The peripheral circuitry of a 3D memory includes devices operating at various voltages, such as high-voltage (HV) devices and low-voltage (LV) devices. Both HV and LV devices employ PMOS, NMOS, and shallow trench isolation (STI) to isolate adjacent devices. However, because high-voltage devices operate at higher voltages than low-voltage devices, achieving good isolation requires complex processes when creating shallow trench isolation in different regions, leading to cumbersome procedures and increased costs.
[0004] Therefore, existing technologies have shortcomings and need to be improved and developed.
[0005] Technical issues
[0006] The purpose of this application is to provide a semiconductor structure, fabrication method, and three-dimensional memory that can reduce the number of processes and save costs while achieving good isolation.
[0007] Technical solutions
[0008] To address the aforementioned problems, this application provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including a first device region and a second device region; forming a plurality of first grooves on the first device region and forming a second groove on the second device region, the first grooves and the second grooves being formed simultaneously; forming a first isolation trench in the first device region, the first isolation trench separating adjacent first grooves; and forming a second isolation trench in the second device region corresponding to the position of the second groove.
[0009] The first isolation trench and the second isolation trench were formed simultaneously.
[0010] Before forming the first groove, the process also includes:
[0011] Ion doping is performed on the first device region and the second device region.
[0012] After forming the second isolation trench in the second device region corresponding to the second recess position, the method further includes:
[0013] A first dielectric layer and a second dielectric layer are formed on the first device region and the second device region, respectively. The first dielectric layer is at least partially located on the inner wall of the first groove, and the thickness of the first dielectric layer is less than the thickness of the second dielectric layer. A first gate and a second gate are formed on the first dielectric layer and the second dielectric layer, respectively, and a source and a drain are formed on both sides of the first gate and the second gate, respectively.
[0014] While forming the second groove, multiple third grooves are formed in the second device area, with the second groove located between adjacent third grooves.
[0015] In this configuration, a first dielectric layer and a second dielectric layer are formed on the first device region and the second device region, respectively. The first dielectric layer is at least partially located on the inner wall of the first groove, and the second dielectric layer is at least partially located on the inner wall of the third groove. The thickness of the first dielectric layer is less than the thickness of the second dielectric layer. A first gate and a second gate are formed on the first dielectric layer and the second dielectric layer, respectively, and a source and a drain are formed on both sides of the first gate and the second gate, respectively.
[0016] After forming the second isolation trench in the second device region corresponding to the second recess position, the method further includes:
[0017] Medium material is filled into the first isolation trench and the second isolation trench respectively to form the first isolation structure and the second isolation structure.
[0018] To address the aforementioned issues, this application also provides a semiconductor structure, comprising: a substrate, the substrate including a first device region and a second device region; the first device region having a plurality of first transistors and a first isolation structure located between adjacent first transistors, the gates of the first transistors being at least partially located within a first groove; the second device region having a plurality of second transistors and a second isolation structure located between adjacent second transistors, the depth of the second isolation structure being greater than the depth of the first isolation structure.
[0019] The depth of the second isolation structure is the sum of the depth of the first isolation structure and the depth of the first groove.
[0020] The first transistor includes a first dielectric layer located at least partially within a first groove, and the gate of the first transistor is located on the first dielectric layer. The second transistor includes a second dielectric layer located at least partially within a third groove, and the second gate of the second transistor is located at least partially within the third groove. The thickness of the first dielectric layer is less than the thickness of the second dielectric layer.
[0021] To address the aforementioned issues, this application also provides a three-dimensional memory, including an array storage structure and peripheral circuitry, wherein any of the aforementioned semiconductor structures is located within the peripheral circuitry.
[0022] Beneficial effects
[0023] This application provides a semiconductor structure, a fabrication method, and a three-dimensional memory. The semiconductor structure fabrication method includes: providing a substrate, the substrate including a first device region and a second device region; forming a plurality of first grooves on the first device region and forming a second groove on the second device region, the first grooves and the second grooves being formed simultaneously; forming a first isolation trench in the first device region, the first isolation trench separating adjacent first grooves; forming a second isolation trench in the second device region corresponding to the position of the second groove, by forming the second groove and the first groove simultaneously, and forming the second isolation trench based on the position of the second groove, such that the depth of the second isolation trench corresponds to the sum of the depth of the first groove and the depth of the first isolation trench, without adding additional processes, first isolation trenches and second isolation trenches of different depths are formed in the first device region and the second device region respectively, to meet the isolation requirements of different semiconductor devices. Attached Figure Description
[0024] Figure 1 This is a flowchart of a semiconductor structure fabrication method according to an embodiment of this application;
[0025] Figure 2 This is a schematic diagram of the substrate structure provided in one embodiment of the present application;
[0026] Figure 3 This is a schematic diagram of the structure forming the first active region and the second active region in one embodiment of this application;
[0027] Figure 4 This is a schematic diagram of the structure forming the first groove and the second groove in one embodiment of this application;
[0028] Figure 5 This is a schematic diagram of the structure forming the first isolation trench and the second isolation trench in one embodiment of this application;
[0029] Figure 6 This is a schematic diagram of the structure forming the first isolation structure and the second isolation structure in one embodiment of this application;
[0030] Figure 7 This is a schematic diagram of the structure forming the first dielectric layer in one embodiment of this application;
[0031] Figure 8 This is a schematic diagram of the structure forming the first gate in one embodiment of this application;
[0032] Figure 9This is a schematic diagram of the semiconductor structure formed in one embodiment of this application;
[0033] Figure 10 This is a flowchart of a semiconductor structure fabrication method according to another embodiment of this application;
[0034] Figure 11 This is a schematic diagram of the structure forming the first groove, the second groove, and the third groove in another embodiment of this application;
[0035] Figure 12 This is a schematic diagram of the structure forming the first isolation trench and the second isolation trench in another embodiment of this application;
[0036] Figure 13 This is a schematic diagram of the structure forming the first isolation structure and the second isolation structure in another embodiment of this application;
[0037] Figure 14 This is a schematic diagram of the structure forming the first dielectric layer and the second dielectric layer in another embodiment of this application;
[0038] Figure 15 This is a schematic diagram of the structure forming the first gate and the second gate in another embodiment of this application;
[0039] Figure 16 This is a schematic diagram of the semiconductor structure formed in another embodiment of this application;
[0040] Figure 17 This is a schematic diagram of a semiconductor structure comprising multiple transistors in another embodiment of this application;
[0041] Figure 18 This is a schematic block diagram of the storage system in some embodiments of this application.
[0042] Implementation methods of this application
[0043] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be particularly noted that the following embodiments are for illustrative purposes only and do not limit the scope of the application. Similarly, the following embodiments are only some, not all, embodiments of the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.
[0044] Furthermore, the directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], and [side], are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative and interpretative purposes only, and not for limiting the scope of this application. In the various figures, structurally similar units are represented by the same reference numerals. For clarity, the various parts in the figures are not drawn to scale. Additionally, some well-known parts may not be shown in the figures.
[0045] To make the purpose, technical solution and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings.
[0046] like Figure 1 As shown, this application provides a method for fabricating a semiconductor structure, with the specific process described below. Figures 2 to 9 The structural diagram may include the following:
[0047] Step S101: Provide a substrate 210, which includes a first device region and a second device region.
[0048] Specifically, in combination Figures 2 to 9 The method for fabricating the semiconductor structure according to the embodiments of this application will be described in detail.
[0049] Figure 2 The structure formed in step S101 is shown, including: substrate 210, respectively located in Figure 2 The first device region and the second device region are shown in regions A1 and A2. The substrate 210 serves as the basis for forming the semiconductor device. The substrate 210 is a semiconductor material, which can be silicon (Si), germanium (Ge) or silicon-germanium (GeSi), silicon carbide (SiC), or other materials.
[0050] The process following step S101 also includes:
[0051] Step S105: Ion doping is performed on the first device region and the second device region.
[0052] Figure 3 The structure formed in step S104 includes: substrate 210, first active region 221 and second active region 222.
[0053] Specifically, ion doping is performed on the first device region and the second device region, forming a first active region 221 and a second active region 222, respectively. A first groove 231 is located in the first active region 221 (i.e., the first device region), and a second groove 232 is located in the second active region 222 (i.e., the second device region). An active area (AA) refers to the region covered by the formation of the active electrode, drain electrode, and conductive trench. After performing step S101, a well region is formed by one or more ion implantations into the substrate 210. Subsequently, an etching process divides the substrate 210 into regions, which can be either the first active region 221 or the second active region 222; that is, the first active region 221 and the second active region 222 are formed on the substrate 210.
[0054] Unlike logic chips, 3D memories need to perform read, write, and erase operations, and different operations require different operating voltages. This necessitates multiple devices providing different maximum operating voltages in the peripheral circuitry of a 3D memory. Correspondingly, the peripheral circuitry of a 3D memory forms a high-voltage (HV) device region and a low-voltage (LV) device region. The first device region and the second device region can be the low-voltage device region and the high-voltage device region, respectively.
[0055] Step S102: A plurality of first grooves 231 are formed on the first device area, and a second groove 232 is formed on the second device area. The first grooves 231 and the second grooves 232 are formed simultaneously.
[0056] Figure 4 The structure formed in step S102 includes: a substrate 210, a first active region 221, a first groove 231 located in the first active region 221, a second active region 222, and a second groove 232 located in the second active region 222. The first groove 231 and the second groove 232 can be formed in the first active region 221 and the second active region 222 respectively in the longitudinal direction perpendicular to the substrate 210 by an etching process.
[0057] Step S103: A first isolation trench 241 is formed in the first device region, and the first isolation trench 241 separates the adjacent first groove 231.
[0058] Step S104: A second isolation trench 242 is formed in the second device region corresponding to the position of the second groove 232.
[0059] Figure 5The structure formed in steps S103 and S104 includes: a substrate 210, a first active region 221, a first groove 231 and a first isolation trench 241 located in the first active region 221, a second active region 222 and a second isolation trench 242 located in the second active region 222, wherein the depth of the first groove 231 is L1, the depth of the first isolation trench 241 is L2, the depth of the second isolation trench 242 is L3, and the depth L3 of the second isolation trench 242 is greater than the depth L2 of the first isolation trench 241.
[0060] Specifically, under normal circumstances, a first groove 231 and a second groove 232 can be simultaneously formed on the substrate 210 through an etching process. Therefore, the depths of the first groove 231 and the second groove 232 are the same, that is, the depths of the first groove 231 and the second groove 232 are both L1. After forming the first groove 231 and the second groove 232, a first isolation trench 241 is formed in the first active region 221 that does not correspond to the first groove 231 through an etching process. A second isolation trench 242 is formed in the second device region corresponding to the position of the second groove 232. Here, "corresponding" means continuing to etch downwards from the bottom of the second groove 232 to form the second isolation trench 242. By forming the second groove 232 and the first groove 231 simultaneously, and forming the second isolation trench 242 based on the position of the second groove 232, the depth L3 of the second isolation trench 242 is made greater than the depth L2 of the first isolation trench 241. Without adding additional processes, first isolation trenches 241 and second isolation trenches 242 with different depths are formed in the first device region and the second device region, respectively, to meet the isolation requirements of different semiconductor devices.
[0061] The first isolation trench 241 and the second isolation trench 242 are formed simultaneously.
[0062] Specifically, when steps S103 and S104 are executed simultaneously, i.e., the first isolation trench 241 and the second isolation trench 242 are formed simultaneously, the first isolation trench 241 is formed in the first active region 221, which is not corresponding to the first groove 231, by etching. At the same time, the second isolation trench 242 is formed in the second device region corresponding to the position of the second groove 232. That is, the second isolation trench 242 is formed by etching downward from the bottom of the second groove 232. The depth L2 of the first isolation trench 241 is consistent with the depth of the etching in the second groove 232. Therefore, the depth L3 of the second isolation trench 242 is the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241. By forming the first isolation trench and the second isolation trench with different depths at the same time, the isolation requirements of different semiconductor devices are met while reducing the process flow, saving costs, and providing possibilities for the further development of semiconductor technology.
[0063] Furthermore, it should be noted that, generally, the depth L3 of the second isolation trench 242 is the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241. However, in actual manufacturing processes, since the second isolation trench 242 is formed by further etching on the basis of the second groove 232, and the second isolation trench 242 is formed by etching on a basis not corresponding to the first groove 231, the initial etching depths of the first isolation trench 241 and the second isolation trench 242 are not the same. Based on the difference in the initial depths of the first isolation trench 241 and the second isolation trench 242, the etching depths of the second isolation trench 241 and the second isolation trench 242 are not the same. During the etching process, as the etching depth gradually increases, the depth of further etching will be affected by the existing etching depth. Therefore, in the actual process, there may be a slight deviation between the depth L3 of the second isolation trench 242 and the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241. However, the depth L3 of the second isolation trench 242 is positively correlated with the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241. That is, the depth L3 of the second isolation trench 242 always corresponds to the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241.
[0064] The process following step S104 also includes:
[0065] Medium material is filled into the first isolation trench 241 and the second isolation trench 242 respectively to form the first isolation structure 243 and the second isolation structure 244.
[0066] The dielectric material includes oxides.
[0067] Specifically, such as Figure 6As shown, multiple isolation structures exist within the first active region 221 and the second active region 222, as well as between the first active region 221 and the second active region 222. For example, there is a first isolation structure 243 located in the first active region 221 and a second isolation structure 244 located in the second active region 222. The first isolation structure 243 and the second isolation structure 244 can be shallow trench isolation (STI), providing lateral isolation for NMOS and PMOS devices. The first isolation structure 243 and the second isolation structure 244 can be formed by filling the first isolation trench 241 and the second isolation trench 242 with dielectric material through thermal oxidation. Since the depth L3 of the second isolation trench 242 always corresponds to the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241, the depth of the second isolation structure 244 is greater than the depth of the first isolation structure 243 to meet the isolation requirements of different semiconductor devices. Generally, the material for shallow trench isolation is an oxide, such as silicon dioxide (SiO2). In addition, it should be noted that the medium material filled in the first isolation trench 241 and the second isolation trench 242 only needs to provide lateral isolation, and there is no specific limitation.
[0068] The process following step S104 also includes:
[0069] Step S106: A first dielectric layer 251 is formed on the first device region, and the first dielectric layer 251 is at least partially located on the inner wall of the first groove 231.
[0070] Figure 7 The structure formed in step S106 includes: a substrate 210, a first active region 221 and a first isolation structure 243 located in the first active region 221, a first groove 231 and a first dielectric layer 251 located in the first groove 231, a second active region 222 and a second isolation structure 244 located in the second active region 222, wherein the first dielectric layer 251 is at least partially located on the inner wall of the first groove 231, and the height of the first dielectric layer 251 is lower than the top surface of the substrate 210. Furthermore, as shown... Figure 7 As shown, a second dielectric layer 252 may also be formed on the second device region.
[0071] Specifically, a first groove 231 is located in the substrate 210 to form a gate corresponding to the first groove 231, and a first dielectric layer 251 is located in the first groove 231 as a gate oxide layer to maintain insulation between the substrate 210 and the gate. Typically, the substrate 210 is made of silicon, and the natural oxide of silicon is silicon dioxide. When exposed to an environment containing an oxidant at a high temperature, a thin oxide layer gradually forms on all silicon surfaces in contact with the oxidant. A high-quality dielectric layer, such as the first dielectric layer 251 serving as the gate oxide layer, can be formed through a thermal oxidation reaction. Furthermore, during the process, the thermally grown oxide can be used as a mask for implantation, diffusion, and etching.
[0072] In addition, it should be noted that the method for forming the second dielectric 252 is basically the same as the method for forming the first dielectric layer 251. Adjustments can be made according to the position, thickness and width of the second dielectric layer 252. Since the method for forming the first dielectric layer 251 has been described in detail, it will not be repeated here.
[0073] Specifically, thermal oxidation refers to placing a silicon wafer in an atmosphere of gaseous oxidant, such as molecular oxygen (O2) and / or water vapor (H2O), at a high temperature (typically 900-1200℃). When the gaseous oxidant is molecular oxygen, the thermal oxidation reaction is a dry oxidation method, while when the gaseous oxidant is water vapor, the thermal oxidation reaction is a wet oxidation method. Through thermal oxidation, an initial oxide layer is formed at the gas / solid interface. The oxidant needs to diffuse through the initial oxide layer to reach the wafer surface and form an oxide layer. Once it reaches the wafer surface, the oxidant needs to diffuse through the newly formed oxide layer again, and this cycle continues until the first dielectric layer 251 is finally formed. By controlling the temperature, rate constant (such as the type of oxidant and the characteristics of the wafer surface) and reaction time of the thermal oxidation reaction, a first dielectric layer 251 with controllable thickness can be formed so that the thickness of the first dielectric layer 251 is less than the depth of the first groove 231, that is, the first dielectric layer 251 is at least partially located on the inner wall of the first groove 231, and the height of the first dielectric layer 251 is lower than the top surface of the substrate 210.
[0074] Step S107: A first gate 261 is formed on the first dielectric layer 251, and a source and a drain are formed on both sides of the first gate 261, respectively.
[0075] Figure 8The structure formed in step S107, "forming the first gate 261 on the first dielectric layer 251," includes: a substrate 210; a first active region 221 and a first isolation structure 243, a first recess 231, the first dielectric layer 251, and the first gate 261 located in the first active region 221; a second active region 222 and a second isolation structure 244 located in the second active region 222, wherein a portion of the first gate 261 is located in the first recess 231, and another portion is located above the top surface of the substrate 210. Furthermore, as shown... Figure 8 As shown, a second gate 262 may also be formed on the second dielectric layer 252 of the second device region.
[0076] Specifically, after forming the first dielectric layer 251, conductive material can be filled into the first recess 231 by physical vapor deposition (PVD) to form a first gate 261 corresponding to the first recess 231. Part of the first gate 261 is located in the first recess 231, and the other part is located above the top surface of the substrate 210, that is, the top of the first gate 261 is higher than the top of the substrate 210. By adopting a recess gate structure, the first recess 231 is formed on the substrate 210, and then the first dielectric layer 251 and the first gate 261 are formed sequentially in the first recess 231 to form a first gate 261 that is partly located in the substrate 210 and partly located above the substrate 210. The recess gate structure increases the effective contact area between the first gate 261 and the first active region 221, increases the channel length of the first gate 261, and improves the problem of slow read and write speed of semiconductor devices, thereby making the area of semiconductor devices smaller. Meanwhile, by employing a first isolation structure 243 and a second isolation structure 244 with different depths in different active regions (i.e., Dual STI process), the isolation requirements of different semiconductor devices can be met. The integration of recessed gate structure technology and Dual STI process effectively reduces the area of peripheral circuits and meets the isolation requirements of different semiconductor devices, providing possibilities for further development of semiconductor technology.
[0077] Furthermore, it should be noted that the method for forming the second gate 262 is basically the same as the method for forming the first gate 261. Adjustments can be made according to the position of the second dielectric layer 252 and the thickness and width of the second gate 262. Since the method for forming the first gate 261 has been described in detail, it will not be repeated here.
[0078] Specifically, since the first gate 261 is used to control whether the semiconductor device is turned on, the first gate 261 is mostly made of conductive materials, such as polysilicon, tungsten, or aluminum. As long as it is a conductive material, it is not limited.
[0079] Figure 9 The structure formed in step S107, which involves "forming source and drain electrodes on both sides of the first gate 261," includes: a substrate 210; a first active region 221 and a first isolation structure 243, a first groove 231, a first dielectric layer 251 in the first groove 231, and a first transistor corresponding to the first gate 261; a second active region 222 and a second isolation structure 244 in the second active region 222, wherein a portion of the first gate 261 is located in the substrate 210, and another portion is located above the substrate 210. Furthermore, as shown... Figure 9 As shown, an active electrode and a drain electrode can be formed on both sides of the second gate 262 in the second device region, respectively.
[0080] As can be seen from the above, thermally grown oxides can be used as masks for ion implantation, diffusion, and etching during the process. For example, after forming the first dielectric layer 251 as the gate oxide layer, a first gate 261 is formed on the first dielectric layer 251. Since the first gate 261 is very thick and its top is higher than the top of the substrate 210, the first gate 261 can be used as a mask layer for forming the source and drain to prevent ion implantation into the corresponding area below the first gate 261 (the thickness of the first gate 261 is thick enough that the ion-implanted atoms cannot reach the first dielectric layer 251). The source and drain are formed only on both sides of the first gate 261 (while the ion-implanted atoms can easily pass through the gate oxide layer above the source and drain to form the source and drain). That is, self-alignment is formed between the source, drain, and the first gate 261 according to the first gate 261.
[0081] Furthermore, it should be noted that the method for forming the source and drain of the second gate 262 is basically the same as the method for forming the source and drain of the first gate 261. Adjustments can be made according to the position, thickness and width of the second gate 262, as well as the position, width and depth of the source and drain of the second gate 262. Since the method for forming the source and drain of the first gate 261 has been described in detail, it will not be repeated here.
[0082] Specifically, transistors can be divided into PMOS transistors and NMOS transistors. PMOS transistors are also known as P-type metal-oxide-semiconductors, while NMOS transistors are also known as N-type metal-oxide-semiconductors. The first transistor includes a first gate 261 and source and drain electrodes located on both sides of the gate. By applying a driving voltage to the first gate 261, the conduction between the source and drain electrodes is controlled, thereby controlling whether the circuit in the semiconductor device is turned on.
[0083] The above steps are the first embodiment of this application, which can simultaneously form first isolation trenches and second isolation trenches of different depths. This reduces the process flow and saves costs while meeting the isolation requirements of different semiconductor devices. Figure 10 The diagram shown is a schematic flowchart of a semiconductor structure fabrication method according to another embodiment of this application. The specific process is compared below. Figures 2 to 3 and Figures 11 to 16 The structural diagram may include the following:
[0084] While forming the second groove 332, a plurality of third grooves 333 are formed in the second device area, with the second groove 332 located between adjacent third grooves 333.
[0085] Specifically, unlike Figure 4 The structure formed in step S102 includes: a substrate 210 and a first groove 231 and a second groove 232 formed on the substrate 210, as shown. Figure 11 The diagram shown is a structural schematic of forming a first groove 331, a second groove 332 and a third groove 333 in another embodiment of this application, including: a substrate 310, a first active region 321 and a first groove 331, a second active region 322 and a second groove 332 and a third groove 333 located in the first active region 321.
[0086] When the first groove 331, the second groove 332, and the third groove 333 are formed on the substrate 310, the subsequent steps S103 and S104 need to be adjusted accordingly based on the third groove 333. Subsequently, steps S103 and S104 described above are adjusted based on the third groove 333. Figure 12The structure formed by the adjusted steps S103 and S104 is shown, including: a substrate 310; a first active region 321 and a first groove 331 and a first isolation trench 341 located in the first active region 321; a second active region 322 and a second isolation trench 342 and a third groove 333 located in the second active region 322, wherein the depth of the first groove 331 is L4, the depth of the first isolation trench 341 is L5, the depth of the second isolation trench 342 is L6, and the depth L6 of the second isolation trench 342 is the sum of the depth L4 of the first groove 331 and the depth L5 of the first isolation trench 341.
[0087] The process following step S104 also includes:
[0088] Medium material is filled into the first isolation trench 341 and the second isolation trench 342 respectively to form the first isolation structure 343 and the second isolation structure 344.
[0089] Specifically, such as Figure 13 As shown, multiple isolation structures can exist within the first active region 321 and the second active region 322, as well as between the first active region 321 and the second active region 322. For example, a first isolation structure 343 and a second isolation structure 344. The first isolation structure 343 and the second isolation structure 344 can be shallow trench isolation (STI), providing lateral isolation for NMOS and PMOS devices. The first isolation structure 343 and the second isolation structure 344 can be formed in the first isolation trench 341 and the second isolation trench 342 respectively through thermal oxidation. Since the depth L6 of the second isolation trench 342 always corresponds to the sum of the depth L4 of the first groove 331 and the depth L5 of the first isolation trench 341, the depth of the second isolation structure 344 corresponds to the depth L4 of the first groove 331 and the depth of the first isolation structure 343, thus meeting the isolation requirements of different semiconductor devices. Generally, the material for shallow trench isolation is an oxide, such as silicon dioxide.
[0090] When the first groove 331, the second groove 332, and the third groove 333 are formed on the substrate 310, subsequent steps S106 to S107 need to be adjusted accordingly based on the third groove 333. For example, in steps S108 to S109, ... Figures 14 to 16 The structural diagrams corresponding to steps S108 to S109 are shown respectively.
[0091] The process following step S104 also includes:
[0092] Step S108: A first dielectric layer 351 and a second dielectric layer are formed on the first device region and the second device region, respectively. The first dielectric layer 351 is at least partially located on the inner wall of the first groove, and the second dielectric layer is at least partially located on the inner wall of the third groove. The thickness of the first dielectric layer is less than the thickness of the second dielectric layer.
[0093] Figure 14 The structure formed in step S108 includes: a substrate 310; a first active region 321 and a first isolation structure 343, a first groove 331 and a first dielectric layer 351 located in the first active region 321; a second active region 322 and a second isolation structure 344, a third groove 333 and a second dielectric layer 352 located in the second active region 322, wherein the first dielectric layer 351 is at least partially located on the inner wall of the first groove 331, the second dielectric layer 352 is at least partially located on the inner wall of the third groove 333, and the height of the first dielectric layer 351 and the second dielectric layer 352 is lower than the top surface of the substrate 310.
[0094] Step S109: A first gate 361 and a second gate are formed on the first dielectric layer 351 and the second dielectric layer 352, respectively, and a source and a drain are formed on both sides of the first gate 361 and the second gate 362, respectively.
[0095] Figure 15 The structure formed in step S109, which involves "forming a first gate 361 and a second gate 362 on the first dielectric layer 351 and the second dielectric layer 352 respectively", includes: a substrate 310; a first active region 321 and a first isolation structure 343, a first groove 331, a first dielectric layer 351 and a first gate 361 located in the first active region 321; a second active region 322 and a second isolation structure 344, a third groove 333 and a second dielectric layer 352 and a second gate 362 located in the second active region 322, wherein a portion of the first gate 361 and the second gate 362 are located in the substrate 310 and another portion is located above the substrate 310 respectively.
[0096] Specifically, the gate is used to control whether the semiconductor device is turned on. The first gate 361 and the second gate 362 are mostly made of conductive materials, such as polysilicon, tungsten, or aluminum. As long as it is a conductive material, there are no specific restrictions.
[0097] Specifically, after forming the first dielectric layer 351 and the second material layer 352, conductive materials can be filled in the first groove 331 and the third groove 333 by physical vapor deposition (PVD) to form a first gate 361 and a second gate 362 corresponding to the first groove 331 and the third groove 333, respectively. A portion of the first gate 361 and the second gate 362 are located in the first groove 331, and another portion is located above the substrate 310, that is, the top of the first gate 361 is higher than the top of the substrate 310. By employing a recessed gate structure, a first recess 331 and a third recess 333 are formed on the substrate 310. Subsequently, a first dielectric layer 351 and a first gate 361 are sequentially formed in the first recess 331 and the third recess 333. Simultaneously, a second dielectric layer 352 and a second gate 362 are sequentially formed in the third recess 333 and the third recess 333. This results in a first gate 361 and a second gate 362 partially located in the first recess 331 and the third recess 333, and partially located above the top surface of the substrate 310. The recessed gate structure increases the effective contact area between the gate and the active region, and increases the channel length of the first gate 361 and the second gate 362, improving the slow read / write speed of the semiconductor device and allowing for a further reduction in the area of the semiconductor device. Furthermore, by simultaneously forming a first isolation structure 343 and a second isolation structure 344 with different depths (i.e., Dual STI process), the isolation requirements of different semiconductor devices are met while reducing the process flow and saving costs. By combining recessed gate structure technology and Dual STI technology, the area of peripheral circuits can be effectively reduced and the isolation requirements of different semiconductor devices can be met, thus enabling further development of semiconductor technology.
[0098] Figure 16 The structure formed in step S109, which involves "forming source and drain electrodes on both sides of the first gate 361 and the second gate 362 respectively", includes: a substrate 310, a first active region 321 and a first isolation structure 343 located in the first active region 321, a first groove 331, a first dielectric layer 351 located in the first groove 331 and a first transistor corresponding to the first gate 361, a second active region 322 and a second isolation structure 344 located in the second active region 322, a third groove 333 and a second dielectric layer 352 located in the third groove 333 and a second transistor corresponding to the second gate 362, wherein a portion of the first gate 361 and the second gate 362 are located in the first groove 331 and the third groove 333 respectively, and another portion is located above the top surface of the substrate 310.
[0099] Specifically, a transistor includes a gate and source and drain located on both sides of the gate. By applying a driving voltage to the gate, the conduction from the source to the drain can be controlled, thereby controlling whether the circuit in the semiconductor device is turned on.
[0100] like Figure 17 The diagram shows a semiconductor device in which a plurality of first transistors and a plurality of second transistors are formed in the first device region and the second device region, respectively. Figure 17 As can be seen, a plurality of first transistors are formed in the first device region, and a first isolation structure 343 is formed between the plurality of first transistors to separate them; a plurality of second transistors are formed in the second device region, and a second isolation structure 344 is formed between the second transistors to separate them. Generally, the first device region and the second device region are respectively a low-voltage device region and a high-voltage device region. By forming shallow trench isolation structures of different depths in different device regions, i.e., the depth of the second isolation structure 344 is greater than the depth of the first isolation structure 343, the isolation requirements of different semiconductor devices are met.
[0101] Furthermore, it should be noted that the specific process flow of steps S106 to S107 has been described in detail above. At this point, the formation of... Figures 14 to 16 The specific process flow of steps S108 to S109 in the structural schematic diagram is basically the same as that of steps S106 to S107, except that it is adjusted according to the third groove 333. Since it has been described in detail above, it will not be repeated here.
[0102] With the development of semiconductor devices, there is a need for devices with more different maximum operating voltages. Correspondingly, a third device region is formed in the peripheral circuit of the three-dimensional memory. This third device region is formed on the side of the first device region away from the second device region. The third device region (not shown in the figure), the first device region, and the second device region can be an ultra-low voltage device region, a low voltage device region, and a high voltage device region, respectively.
[0103] In addition to the ultra-low voltage device region, low voltage device region, and high voltage device region, one or more device regions different from the ultra-low voltage device region, low voltage device region, and high voltage device region can be formed in the peripheral circuit, without specific limitations. When the semiconductor structure has a third device region or more device regions, similar to...
[0104] The process flow from steps S101 to S107 forms multiple recessed gate structures and shallow trench isolation structures of different depths in different device regions to meet the isolation requirements of different semiconductor devices. Since the principles are similar and have been described in detail above, they will not be repeated here.
[0105] Based on the semiconductor structure fabrication method described in the above embodiments, this application also provides a semiconductor structure, including:
[0106] Substrate 210, the substrate includes a first device region and a second device region;
[0107] The first device region is provided with a plurality of first transistors and a first isolation structure 243 located between adjacent first transistors, wherein the first gate 261 of the first transistor is at least partially located within the first recess 231;
[0108] The second device region is provided with a plurality of second transistors and a second isolation structure located between adjacent second transistors, wherein the depth of the second isolation structure 244 is greater than the depth of the first isolation structure 243.
[0109] The depth of the second isolation structure 244 is the sum of the depth of the first isolation structure 243 and the depth of the first groove 231.
[0110] like Figure 9 The diagram shown is a schematic diagram of a semiconductor structure formed in one embodiment of this application, including: a substrate 210, a first active region 221, a first isolation structure 243 located in the first active region 221, a first groove 231, a first dielectric layer 251 located in the first groove 231, a first transistor corresponding to a first gate 261, a first active region 222, and a second isolation structure 244 located in the first active region 222. The first gate 261 is partially located in the first groove 331 and partially located above the top surface of the substrate 210. The depth of the second isolation structure 244 corresponds to the sum of the depth of the first groove 231 and the depth of the first isolation structure 243.
[0111] The semiconductor structure further includes: a first transistor comprising a first dielectric layer 251 at least partially located within a first recess 231, and a first gate 261 of the first transistor located on the first dielectric layer 251.
[0112] Specifically, such as Figure 9The diagram shows a schematic of the semiconductor structure formed by performing steps S101 to S107. By employing a recessed gate structure, a first groove 231 is formed on the substrate 210. Subsequently, a first dielectric layer 251 and a first gate 261 are sequentially formed in the first groove 231, resulting in a first gate 261 partially located within the first groove 231 and partially located above the top surface of the substrate 210. The recessed gate structure increases the effective contact area between the gate and the active region, increases the channel length of the first gate 261, and improves the slow read / write speed of the semiconductor device, thereby allowing for a smaller semiconductor device area. Simultaneously, by forming first and second isolation trenches of different depths, the isolation requirements of different semiconductor devices are met while reducing the process flow and saving costs. The combination of the recessed gate structure process and the Dual STI process effectively reduces the area of the peripheral circuit and meets the isolation requirements of different semiconductor devices, providing possibilities for further development of semiconductor technology.
[0113] The semiconductor structure further includes: a first transistor including a first dielectric layer 351 at least partially located within a first groove 331, a first gate 361 of the first transistor located on the first dielectric layer 351, a second transistor including a second dielectric layer 352 at least partially located within a third groove 333, a second gate 362 of the second transistor at least partially located within the third groove 333, and the thickness of the first dielectric layer 351 being less than the thickness of the second dielectric layer 352.
[0114] Specifically, unlike Figure 9 The scheme shown is as follows: Figure 16 The diagram shown is a schematic diagram of a semiconductor structure formed in another embodiment of this application, including: a substrate 310, a first active region 321 and a first isolation structure 343 located in the first active region 321, a first groove 331, a first dielectric layer 351 located in the first groove 331 and a first transistor corresponding to the first gate 361, a second active region 322 and a second isolation structure 344 located in the second active region 322, a third groove 333, a second dielectric layer 352 located in the third groove 333 and a second transistor corresponding to the second gate 362, wherein a portion of the first gate 361 and the second gate 362 are located in the substrate 310 and another portion is located above the substrate 310, and the depth of the second isolation structure 344 corresponds to the sum of the depth of the first groove 331 and the depth of the first isolation structure 343.
[0115] Specifically, such as Figure 11 As shown, when the first groove 331, the second groove 332, and the third groove 333 are formed on the substrate 310, subsequent steps S103 to S106 need to be adjusted accordingly based on the third groove 333, ultimately forming the following... Figure 16The schematic diagram of the semiconductor structure shown has been described in detail above and will not be repeated here. By employing a recessed gate structure, a first recess 331, a second recess 332, and a third recess 333 are formed on the substrate 310. Subsequently, a first dielectric layer 351 and a first gate 361 are sequentially formed in the first recess 331, and a second dielectric layer 352 and a second gate 362 are sequentially formed in the third recess 333. This results in a first gate 361 and a second gate 362 partially located in the first and third recesses 331 and 333, respectively, and partially located above the top surface of the substrate 310. The recessed gate structure increases the effective contact area between the gate and the active region, and increases the channel length of the first gate 361 and the second gate 362, improving the slow read / write speed of the semiconductor device and allowing for a further reduction in the area of the semiconductor device. By simultaneously forming a first isolation structure 343 and a second isolation structure 344 with different depths, the isolation requirements of different semiconductor devices are met while reducing the process flow and saving costs. By combining recessed gate structure technology and Dual STI technology, the area of peripheral circuits can be effectively reduced and the isolation requirements of different semiconductor devices can be met, thus enabling further development of semiconductor technology.
[0116] The first device area and the first device region can be the low-voltage device area and the high-voltage device area, respectively, as described in detail above, and will not be repeated here.
[0117] With the development of semiconductor devices, there is a need for devices with more different maximum operating voltages. Correspondingly, a third device region is formed in the peripheral circuit of the three-dimensional memory. This third device region is formed on the side of the first device region away from the second device region. The third device region, the first device region, and the second device region can be an ultra-low voltage device region, a low voltage device region, and a high voltage device region, respectively.
[0118] In addition to the high-voltage device region, low-voltage device region, and ultra-low-voltage device region, one or more device regions different from the high-voltage device region, low-voltage device region, and ultra-low-voltage device region can be formed in the peripheral circuit, without any specific restrictions. When there is a third or more device regions in the semiconductor structure, multiple recessed gate structures and shallow trench isolation structures of different depths can be formed in the third or more device regions through a process flow similar to steps S101 to S107 to meet the isolation requirements of different semiconductor devices. Since the principle is similar and has been described in detail above, it will not be elaborated here.
[0119] Based on the semiconductor structure fabrication method described in the above embodiments, this application also provides a three-dimensional memory (not shown in the figure), the three-dimensional memory including an array storage structure and peripheral circuits, wherein any of the above semiconductor structures is located in the peripheral circuits.
[0120] Specifically, a 3D NAND Flash memory includes an array of memory structures and peripheral circuitry. Any of the aforementioned semiconductor structures is located within the peripheral circuitry. The array of memory structures stores information, while the peripheral circuitry can be located above, below, or around the array of memory structures. The peripheral circuitry controls the corresponding array of memory structures. Furthermore, this semiconductor structure can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), without any specific limitations.
[0121] Based on the semiconductor structure described in the above embodiments, this application also provides a storage system, wherein a controller is coupled to a three-dimensional memory and is used to control the three-dimensional memory to store data, and the three-dimensional memory includes the semiconductor structure described above.
[0122] Specifically, such as Figure 18 As shown, the storage system 400 includes a controller 410 and one or more three-dimensional memories 420, wherein each three-dimensional memory 420 includes one or more array storage structures 421 and peripheral circuitry 422. The storage system 400 can communicate with the host 500 via the controller 410, wherein the controller 410 can be connected to one or more three-dimensional memories 420 via channels in the three-dimensional memories 420. Each three-dimensional memory 420 can be managed by the controller 410 via channels in the three-dimensional memory 420.
[0123] Unlike existing technologies, the semiconductor structure, fabrication method, and three-dimensional memory in this embodiment include the following steps: providing a substrate, the substrate including a first device region and a second device region; forming a plurality of first grooves on the first device region and forming a second groove on the second device region, the first grooves and the second grooves being formed simultaneously; forming a first isolation trench in the first device region, the first isolation trench separating adjacent first grooves; forming a second isolation trench in the second device region corresponding to the position of the second groove, by forming the second groove and the first groove simultaneously, and forming the second isolation trench based on the position of the second groove, so that the depth of the second isolation trench corresponds to the sum of the depth of the first groove and the depth of the first isolation trench, without adding additional processes, first isolation trenches and second isolation trenches of different depths are formed in the first device region and the second device region respectively, to meet the isolation requirements of different semiconductor devices.
[0124] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method for fabricating a semiconductor structure, the method comprising: A substrate is provided, the substrate including a first device region and a second device region; Multiple first grooves are formed on the first device region, and second grooves are formed on the second device region, wherein the first grooves and the second grooves are formed simultaneously; A first isolation trench is formed in the first device region, the first isolation trench separating adjacent first grooves; A second isolation trench is formed in the second device area corresponding to the location of the second groove.
2. The method for fabricating a semiconductor structure as described in claim 1, wherein, The first isolation trench and the second isolation trench are formed simultaneously.
3. The method for fabricating a semiconductor structure as described in claim 2, wherein, Before forming the first groove, the method further includes: Ion doping is performed on the first device region and the second device region.
4. The method for fabricating a semiconductor structure as described in claim 3, wherein, After forming the second isolation trench in the second device region corresponding to the second recess position, the method further includes: A first dielectric layer is formed on the first device region, wherein the first dielectric layer is at least partially located on the inner wall of the first groove; A first gate is formed on the first dielectric layer, and a source and a drain are formed on both sides of the first gate, respectively.
5. The method for fabricating a semiconductor structure as described in claim 3, wherein, While forming the second groove, a plurality of third grooves are formed in the second device area, with the second groove located between adjacent third grooves.
6. The method for fabricating a semiconductor structure as described in claim 5, wherein, A first dielectric layer and a second dielectric layer are formed on the first device region and the second device region, respectively. The first dielectric layer is at least partially located on the inner wall of the first groove, and the second dielectric layer is at least partially located on the inner wall of the third groove. The thickness of the first dielectric layer is less than the thickness of the second dielectric layer. A first gate and a second gate are formed on the first dielectric layer and the second dielectric layer, respectively, and a source and a drain are formed on both sides of the first gate and the second gate, respectively.
7. The method for fabricating a semiconductor structure as described in claim 1, wherein, After forming the second isolation trench in the second device region corresponding to the second recess position, the method further includes: Medium material is filled into the first isolation trench and the second isolation trench respectively to form a first isolation structure and a second isolation structure.
8. A semiconductor structure, said semiconductor structure comprising: A substrate, the substrate comprising a first device region and a second device region; The first device region is provided with a plurality of first transistors and a first isolation structure located between adjacent first transistors, wherein the first gate of the first transistor is at least partially located within a first recess; The second device region is provided with a plurality of second transistors and a second isolation structure located between adjacent second transistors. The depth of the second isolation structure is greater than the depth of the first isolation structure. The depth of the second isolation structure is the sum of the depth of the first isolation structure and the depth of the first groove.
9. The semiconductor structure as claimed in claim 8, wherein, The first transistor includes a first dielectric layer at least partially located within the first recess, and the gate of the first transistor is located on the first dielectric layer. The second transistor includes a second dielectric layer at least partially located within a third recess, and the second gate of the second transistor is at least partially located within the third recess. The thickness of the first dielectric layer is less than the thickness of the second dielectric layer.
10. A three-dimensional memory, wherein, The three-dimensional memory includes a memory cell array and peripheral circuitry, wherein the peripheral circuitry includes the semiconductor structure as described in claim 8.