Apparatus having a driver circuit that overwrites data locked in a sense amplifier

Abstract

This application relates to devices with drive circuits that overwrite data locked in sense amplifiers. Disclosed herein is an apparatus including a first digit line and a second digit line, a sense amplifier configured to amplify a potential difference between the first digit line and the second digit line, a drive circuit configured to drive each of the first digit line and the second digit line to one of a first logic level and a second logic level different from each other, a first transistor coupled between the drive circuit and the first digit line, a second transistor coupled between the drive circuit and the second digit line, and a control circuit configured to supply a first potential to control electrodes of the first transistor and the second transistor in response to a write command, and to supply a second potential different from the first potential to the control electrodes of the first transistor and the second transistor in response to a read command.

Description

Technical Field

[0001] This application relates to an apparatus having a drive circuit for overwriting data latched in a sense amplifier. Background Technology

[0002] In typical dynamic random access memory (DRAM), action (ACT) commands and read commands are issued sequentially when a read operation is to be performed, and action commands and write commands are issued sequentially when a write operation is to be performed. Therefore, when an action command has been issued, it is not yet determined whether a read or write operation will be performed. On the other hand, US 2011 / 0007593 A1 discloses a memory device that can issue read or write commands in an idle state. In this type of memory device, whether to perform a read or write operation is determined based on the command issued in the idle state. Summary of the Invention

[0003] This application relates to an apparatus comprising: a first digital line and a second digital line; a sensing amplifier configured to operate on a first power supply potential and a second power supply potential and amplify the potential difference between the first digital line and the second digital line, the sensing amplifier having a first power node supplied with the first power supply potential and a second power node supplied with the second power supply potential; a first transistor coupled between the first power node and a first power line supplying the first power supply potential; a second transistor coupled between the second power node and a second power line supplying the second power supply potential; a driving circuit configured to drive each of the first digital line and the second digital line to one of a first logic level and a second logic level that are different from each other; a third transistor coupled between the driving circuit and the first digital line; a fourth transistor coupled between the driving circuit and the second digital line; and a control circuit configured to turn on the first transistor when the second transistor remains in an off state and before the third transistor and the fourth transistor enter an on state in response to a first command.

[0004] Another aspect of this application relates to an apparatus comprising: a first digital line and a second digital line; a sense amplifier configured to amplify a potential difference between the first digital line and the second digital line; a drive circuit configured to drive each of the first digital line and the second digital line to one of a first logic level and a second logic level different from each other; a first transistor coupled between the drive circuit and the first digital line; a second transistor coupled between the drive circuit and the second digital line; and a control circuit configured to supply a first potential to the control electrodes of the first transistor and the second transistor in response to a write command, and to supply a second potential different from the first potential to the control electrodes of the first transistor and the second transistor in response to a read command.

[0005] Another aspect of this application relates to an apparatus comprising: a sense amplifier including a pull-down portion configured to be activated in response to the supply of a first power supply potential and a pull-up portion configured to be activated in response to the supply of a second power supply potential; and control circuitry configured at the first moment of a write operation to control the sense amplifier to amplify data by activating the pull-down portion when the first power supply potential is supplied and not activating the pull-up portion when the second power supply potential is not supplied. Attached Figure Description

[0006] Figure 1 A block diagram illustrating the configuration of a semiconductor device according to this disclosure.

[0007] Figure 2 This is a diagram illustrating the state transitions of a semiconductor device according to the present disclosure.

[0008] Figure 3 This is a circuit diagram illustrating the configuration of the main parts of the semiconductor device according to the present disclosure.

[0009] Figure 4 This is a circuit diagram of the sensing amplifier and its surroundings.

[0010] Figure 5 It is a waveform diagram used to explain the operation of the semiconductor device according to this disclosure. Detailed Implementation

[0011] Various embodiments of the invention will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments of the invention that can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural, logical, and electrical changes may be made, without departing from the scope of the invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0012] Figure 1 The semiconductor device 10 shown is, for example, a DRAM, and includes a memory cell array 11, an access control circuit 12 that performs access to the memory cell array 11, and an I / O circuit 13 that performs input / output of data to / from the memory cell array 11. The access control circuit 12 performs access to the memory cell array 11 based on a command address signal CA input from an external controller via a command address terminal 14. During a read operation, data DQ read from the memory cell array 11 is output to a data terminal 15 via the I / O circuit 13. During a write operation, data DQ input from an external controller to the data terminal 15 is supplied to the memory cell array 11 via the I / O circuit 13.

[0013] The command address signal CA contains the command and address. The state of semiconductor device 10 is defined by the command. For example... Figure 2 As shown, when a read command is issued while the semiconductor device 10 is in an idle state, the semiconductor device 10 transitions to a read state. Upon completion of the read operation, the semiconductor device 10 returns to an idle state. Conversely, when a write command is issued while the semiconductor device 10 is in an idle state, the semiconductor device 10 transitions to a write state. Upon completion of the write operation, the semiconductor device 10 returns to an idle state. In this way, since the action commands used in general-purpose DRAM are not used in the semiconductor device 10 according to this embodiment of the invention, the determination of whether to perform a read or write operation is based on the command issued while in an idle state.

[0014] Memory cell array 11 includes Figure 3Multiple memory banks 20 are shown in the diagram. Multiple digital line pairs DL0, DL1, DL2, DL3… are provided in each of the memory banks 20. Digital line pair DL0 consists of complementary digital lines DL0T and DL0B, digital line pair DL1 consists of complementary digital lines DL1T and DL1B, digital line pair DL2 consists of complementary digital lines DL2T and DL2B, and digital line pair DL3 consists of complementary digital lines DL3T and DL3B. The digital line pairs DL are connected to corresponding sense amplifiers 30. Additionally, the digital line pairs DL are connected to local I / O line pairs LIO via corresponding column switches 40. Each column switch 40 includes N-channel MOS transistors 41 and 42. Transistor 41 is connected between one local I / O line LIO and digital lines DL0T, DL1T, DL2T, DL3T… respectively. Transistor 42 is connected between another local I / O line LIOB and other digital lines DL0B, DL1B, DL2B, DL3B… respectively. Each column switch 40 is supplied with a corresponding column selection signal CS. Specifically, column selection signals CS0, CS1, CS2, and CS3 are supplied to the column switches 40 corresponding to digital line pairs DL0, DL1, DL2, and DL3, respectively. The column selection signal CS assigned to the same local I / O line pair is specifically activated.

[0015] The local I / O line pair LIO is connected to the I / O circuit 13 via the main I / O line pair MIO. The main I / O line pair MIO consists of complementary main I / O lines MIOT and MIOB. During a read operation, read data read from memory bank 20 is transmitted to the I / O circuit 13 via the local I / O line pair LIO and the main I / O line pair MIO. During a write operation, write data supplied to the I / O circuit 13 from the outside is transmitted to the local I / O line pair LIO via the main I / O line pair MIO. A driver circuit 51 is placed between the main I / O line MIOT and the local I / O line LIOOT, and a driver circuit 52 is placed between the main I / O line MIOB and the local I / O line LIOOB. Driver circuits 51 and 52 are used to drive the local I / O line pair LIO during a write operation. During a write operation, there are cases where the data latched in the sense amplifier 30 is inverted and cases where the data is not inverted.

[0016] like Figure 4As shown, each of the sense amplifiers 30 includes cross-coupled P-channel MOS transistors P1 and P2, and cross-coupled N-channel MOS transistors N1 and N2. The drains of transistors P1 and N1 form a first data node 31 and are connected to the corresponding digital line DLT. The drains of transistors P2 and N2 form a second data node 32 and are connected to the corresponding digital line DLB. The sources of transistors P1 and P2 form a first power supply node 33 and are connected to the common source line SAP. The sources of transistors N1 and N2 form a second power supply node 34 and are connected to the common source line SAN. An N-channel MOS transistor 35 is connected between the power supply line V1 supplying the array potential VARY and the common source line SAP. A sense signal PSA is supplied to the gate electrode of transistor 35. An N-channel MOS transistor 36 is connected between the power supply line V2 supplying the ground potential VSS and the common source line SAN. A sense signal NSA is supplied to the gate electrode of transistor 36. Therefore, cross-coupled transistors P1 and P2 are activated when transistor 35 is turned on, and cross-coupled transistors N1 and N2 are activated when transistor 36 is turned on.

[0017] Memory cell MC is connected to each of digital lines DLT and DLB. Each memory cell MC has a configuration in which cell transistor T and cell capacitor C are connected in series. The gate electrode of cell transistor T is connected to the corresponding word line WL, and the source / drain of cell transistor T is connected to the corresponding digital line DLT or DLB. Word line WL is driven by word driver 50.

[0018] The operation of the semiconductor device 10 according to this embodiment will now be explained.

[0019] Figure 5 This is a waveform diagram used to explain the write operation of semiconductor device 10. The write operation is performed by issuing a write command to semiconductor device 10 in the idle state. When a write command is issued, a predetermined word line WL is driven at time t1 based on the address contained in the command address signal CA. Figure 5 This illustrates a scenario where a memory cell MC connected to the digital line DLB is selected by the chosen word line WL and the data in the selected memory cell MC is held low. Therefore, as the word line WL is driven at time t1, the potential of the digital line DLB gradually decreases. The potential of the digital line DLT remains largely unchanged.

[0020] Next, the sensing signal NSA is activated at time t2. At this time, the sensing signal PSA remains in an inactive state. When the sensing signal NSA is activated, the ground potential VSS is supplied to the common source line SAN, thus activating the cross-coupled transistors N1 and N2. Therefore, the potential of digital line DLB decreases more significantly. However, since the sensing signal PSA is in an inactive state at this time, the potentials of other digital lines DLT do not increase, and therefore the potential of digital line DLB decreases gradually.

[0021] Next, the column selection signal CS is activated at time t3. At this time, the sensing signal PSA remains in an inactive state. When the column selection signal CS is activated, transistors 41 and 42 that constitute the selected column switch 40 are turned on, and thus the data latched in the corresponding sensing amplifier 30 is rewritten using the local I / O line to the write data on the LIO. Figure 5 This demonstrates an example where the local I / O line LIOT is low and the local I / O line LIOB is high. Because the potential of the corresponding digital line DLT decreases accordingly and the potential of the corresponding digital line DLB increases, the data latched in the sense amplifier 30 is rapidly inverted. At this time, the sense signal PSA is in an inactive state, and therefore the potential of the digital line DLT decreases rapidly without being affected by the transistor P1 in the sense amplifier 30. The potential of the digital line DLB during this stage is limited by the level of the column select signal CS. That is, assuming the level of the column select signal CS is VYS3 and the threshold voltage of the transistors 41 and 42 constituting the column switch 40 is Vth, then the potential of the digital line DLB is limited to VYS3-Vth. The level VYS3 is lower than the array potential VARY. That is, the level VYS3 is between the ground potential VSS and the array potential VARY. The column select signal CS returns to the inactive state at time t4.

[0022] Next, the sensing signal PSA is activated at time t5. When the sensing signal PSA is activated, the array potential VARY is supplied to the common source line SAP, thus activating the cross-coupled transistors P1 and P2. Consequently, the potential of the digital line DLB increases to the array potential VARY. When the word line WL is subsequently reset, a series of write operations are completed. As described above, during the write operation, after activating the word line WL, the sensing signal NSA, the column select signal CS, and the sensing signal PSA are activated in sequence. Therefore, the data latched in the associated sensing amplifier 30 can be easily inverted. Associatedly, the level VYS3 of the column select signal CS is enabled to be set at a level lower than the array potential VARY, thereby reducing current consumption.

[0023] On the other hand, during the read operation, both the sensing signals NSA and PSA are activated at time t2, such as through Figure 5The dashed line indicates this. Therefore, all transistors P1, P2, N1, and N2 in the sense amplifier 30 are activated, and the sense amplifier 30 drives one of the digital lines DLT and DLB to the array potential VARY and the other to the ground potential VSS. When the column select signal CS is subsequently activated at time t3, the data on the relevant digital line pairs DLT and DLB is transmitted to the local I / O line pair LIO. To reduce transmission losses at this time, it is preferable to set the level VYS4 of the column select signal CS to a potential higher than VYS3, and more preferably, to set the level VYS4 to a potential higher than the array potential VARY.

[0024] While the invention has been disclosed in the context of certain preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the invention itself and its obvious modifications and equivalents. Furthermore, other modifications within the scope of the invention will be apparent to those skilled in the art based on this disclosure. Various combinations or sub-combinations of specific features and aspects of the embodiments are also contemplated and remain within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for each other to form variations of the disclosed invention. Therefore, it is intended that the scope of at least some of the invention disclosed herein should not be limited to the specific disclosed embodiments described above.

Claims

1. A method for use in a memory, comprising: A sensing amplifier operates a first power supply potential and a second power supply potential, and amplifies the potential difference between a first digital line and a second digital line. The sensing amplifier has a first power node supplied with the first power supply potential and a second power node supplied with the second power supply potential. The sensing amplifier includes one or more P-type MOS transistors and one or more N-type MOS transistors. The first source of at least one of the one or more P-type MOS transistors is coupled to the first power node, and the second source of at least one of the one or more N-type MOS transistors is coupled to the second power node. The first power potential is supplied through a first transistor, which is coupled to the sensing amplifier via the first power node; The second power potential is supplied through a second transistor, which is coupled to the sensing amplifier via the second power node; The driving circuit drives each of the first digital line and the second digital line to one of a first logic level and a second logic level that are different from each other. In response to a first command, the control circuit provides an active first sensing signal to the first transistor, an inactive second sensing signal to the second transistor, and inactive column selection signals to the third and fourth transistors to activate the first transistor to an on state, while the second transistor is in an off state. The inactive column selection signal is provided before the third and fourth transistors are activated to an on state. The third transistor is coupled between the driving circuit and the first digital line, and the fourth transistor is coupled between the driving circuit and the second digital line. The control circuit provides an active column selection signal to the third and fourth transistors, and then provides an active second sensing signal to the second transistor to activate the second transistor to an on state after the third and fourth transistors are activated to an on state.

2. The method according to claim 1, wherein the first command is a write command.

3. The method according to claim 1, wherein the control circuit causes the first transistor and the second transistor to enter the on state before the third transistor and the fourth transistor enter the on state in response to the second command.

4. The method of claim 3, wherein the first transistor and the second transistor enter the on state substantially simultaneously in response to the second command.

5. The method according to claim 3, wherein the second command is a read command.

6. A memory device comprising: First digit line and second digit line; A sensing amplifier configured to operate on a first power supply potential and a second power supply potential and amplify the potential difference between the first digital line and the second digital line, the sensing amplifier having a first power node supplied with the first power supply potential and a second power node supplied with the second power supply potential. A first transistor is coupled between the first power node and a first power line supplying the first power potential. The second transistor is coupled between the second power node and the second power line supplying the second power potential; A driving circuit configured to drive each of the first digital line and the second digital line to one of a first logic level and a second logic level that are different from each other. A third transistor is coupled between the driving circuit and the first digital line; A fourth transistor is coupled between the driving circuit and the second digital line; and A control circuit configured to turn on the first transistor while the second transistor remains in the off state and before the third and fourth transistors enter the on state in response to a first command. The control circuit is further configured to turn on the second transistor after the third transistor and the fourth transistor have turned on in response to the first command. The control circuitry is further configured to turn on the first transistor and the second transistor before the third transistor and the fourth transistor turn on in response to the second command. The first transistor and the second transistor generally enter the on state simultaneously in response to the second command; The control circuit is further configured to supply a third potential to the control electrodes of the third transistor and the fourth transistor in response to the first command, and to supply a fourth potential to the control electrodes of the third transistor and the fourth transistor in response to the second command; and The third potential is lower than the fourth potential.

7. The memory device according to claim 6, The second power supply potential is higher than the first power supply potential, and The third potential is lower than the second power supply potential.

8. The memory device of claim 7, wherein the fourth potential is higher than the second power supply potential.

9. A memory device comprising: First digit line and second digit line; A sensing amplifier configured to amplify the potential difference between the first digital line and the second digital line; A driving circuit configured to drive each of the first digital line and the second digital line to one of a first logic level and a second logic level that are different from each other. A first transistor is coupled between the driving circuit and the first digital line; The second transistor is coupled between the driving circuit and the second digital line; and A control circuit configured to supply a first potential to the control electrodes of the first and second transistors in response to a write command, and to supply a second potential, different from the first potential, to the control electrodes of the first and second transistors in response to a read command; and The first potential is lower than the second potential.

10. The memory device according to claim 9, The sensing amplifier is configured to drive each of the first and second digital lines to one of two different third and fourth potentials, and The first potential is between the third potential and the fourth potential.

11. The memory device of claim 10, wherein the second potential is higher than the third potential and the fourth potential.

12. The memory device according to claim 10, wherein, In response to the write command, the sense amplifier is configured to drive one of the first digital line and the second digital line to the third potential before the first transistor and the second transistor are turned on, and to drive the other of the first digital line and the second digital line to the fourth potential after the first transistor and the second transistor are turned on.

13. A method for a memory, comprising: In response to a first power supply potential being supplied via a first transistor coupled to the sense amplifier, the pull-down portion of the sense amplifier is activated, and in response to a second power supply potential being supplied via a second transistor coupled to the sense amplifier, the pull-up portion of the sense amplifier is activated. By means of control circuitry, at the first moment of the write operation, a first sensing signal is provided to the sensing amplifier to control the sensing amplifier to amplify the data by activating the pull-down portion when the first power supply potential with the first sensing signal is supplied and not activating the pull-up portion when the second power supply potential with the second sensing signal is not supplied. and Through the control circuit, at the second time of the write operation after the first time of the write operation, the data in the sensing amplifier is overwritten by activating the pull-down portion and deactivating the pull-up portion.

14. A memory device comprising: A sensing amplifier includes a pull-down portion configured to be activated in response to a first power supply potential and a pull-up portion configured to be activated in response to a second power supply potential. and A control circuit is configured at the first moment of a write operation to control the sense amplifier to amplify data by activating the pull-down portion when the first power supply potential is supplied and not activating the pull-up portion when the second power supply potential is not supplied. At a second time of the write operation following the first time of the write operation, the control circuit is configured to overwrite the data in the sense amplifier while activating the pull-down portion and deactivating the pull-up portion.

15. The memory device of claim 14, wherein at a third time of the write operation following the second time of the write operation, the control circuit is configured to activate the pull-up portion while the second power supply potential is supplied.

16. A memory device comprising: A sensing amplifier includes a pull-down portion configured to be activated in response to a first power supply potential and a pull-up portion configured to be activated in response to a second power supply potential. and A control circuit is configured at the first moment of a write operation to control the sense amplifier to amplify data by activating the pull-down portion when the first power supply potential is supplied and not activating the pull-up portion when the second power supply potential is not supplied. During the read operation, the control circuit is configured to control the sensing amplifier to amplify the data by substantially activating both the pull-up and pull-down portions simultaneously.

17. A memory device comprising: A sensing amplifier includes a pull-down portion configured to be activated in response to a first power supply potential and a pull-up portion configured to be activated in response to a second power supply potential. A control circuit is configured at the first moment of a write operation to control the sense amplifier to amplify data by activating the pull-down portion when the first power supply potential is supplied and not activating the pull-up portion when the second power supply potential is not supplied. and A first transistor is positioned between the pull-down portion of the sensing amplifier and a first voltage node supplied with the first power supply potential, and a second transistor is positioned between the pull-up portion of the sensing amplifier and a second voltage node supplied with the second power supply potential.

18. The memory device of claim 17, wherein during the first time of the write operation, the control circuit is configured to turn on the first transistor while the second transistor remains off.

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