Wafer and method for analyzing wafer shape

Abstract

Disclosed is a method of analyzing wafer shape. The method includes measuring the outer shape of a plurality of wafers, detecting a first point having the maximum curvature in the edge region of each wafer from the measurement values obtained in measuring the outer shape of the wafer, detecting a second point spaced apart from the first point in the direction toward the top of the corresponding one of the wafers, measuring a first angle formed between a first line configured to connect the first point and the second point and the front surface of the corresponding one of the wafers, forming a thin film layer on the surface of each wafer, measuring the thickness distribution of the thin film layer, and confirming the wafer in which the maximum value of the thickness distribution of the thin film layer is the smallest.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2020-0088216, filed on July 16, 2020, which is incorporated herein by reference as if fully set forth herein. Background of the Invention

[0002] Invention Field

[0003] The present invention relates to wafers and methods for analyzing wafer shape, and more particularly, to methods for confirming wafer shape, wherein the wafers are appropriately stacked with photoresist or the like during wafer manufacturing.

[0004] Discussions in related fields

[0005] Semiconductor devices are typically formed on wafers. To achieve high integration and high yield in semiconductor devices, the wafer edges require high purity and must also have a shape suitable for semiconductor device manufacturing processes. For this purpose, a practical and simple method for analyzing wafer edge shapes is needed.

[0006] For example, one of the most important mathematical parameters used to determine the shape of a wafer edge is curvature, and the overall curvature formed by the wafer front and edge must be as small as possible. The reason is that only when the wafer curvature is small can the wafer front and edge be smoothly formed without any boundary in between.

[0007] When the curvature formed by the wafer edge and front side is not small, fatal problems may occur during the manufacturing of semiconductor devices on the wafer, such as uneven coating of wafers with photoresist (PR).

[0008] One common method for analyzing wafer edge shape is to utilize optical phenomena (e.g., laser scattering) to analyze the wafer's shape. However, this common method requires expensive equipment that must be kept well aligned and presents technical requirements for reducing the laser spot size in order to perform very fine analysis corresponding to the calculation of edge curvature.

[0009] To address these issues, Korean Unexamined Patent Publication No. 10-2019-0049287 discloses a technique for dividing edge regions of a wafer, measuring cross-sectional images, and then measuring contours.

[0010] Figure 1 This is a schematic diagram illustrating a common method for analyzing wafer shape.

[0011] As shown in the attached figure, in this common method, the shape of the wafer W is analyzed using reference point P0 and first to third points P1 to P3.

[0012] The reference point P0 can be set to have a height approximately equal to or slightly lower than the height of the front face f in the bulk region B, and the reference point P0 can be regarded as the starting point of the edge region E.

[0013] The first point P1 can be a point on the oblique face WBf with the maximum curvature. The second point P2 can be a point on the oblique face WBf adjacent to the first point P1. Furthermore, the third point P3 can be a point on the oblique face WBf adjacent to the second point P1.

[0014] A first line is measured, connecting the point with the minimum radius of curvature (i.e., the first point P1 with the maximum curvature) and the second point P2 on the obliquely cut front face WBf in the edge region E of wafer W. Furthermore, an angle θ11 is measured, formed by the front face f in the volume region B of wafer W and the first line.

[0015] However, the aforementioned common methods used to analyze wafer shape have the following problems.

[0016] First, the wafer shape is analyzed using the front face f, reference point P0, and first and second points P1 and P2. Therefore, since four positions are used, errors are likely to occur.

[0017] Second, after dividing the wafer edge region, a cross-sectional image must be measured, followed by a contour measurement. Invention Overview

[0018] Accordingly, the present invention relates to wafers and methods for analyzing wafer shape, wherein the wafers and methods substantially eliminate one or more problems caused by limitations and defects in the relevant field.

[0019] One object of the present invention is to provide a method for analyzing wafer shape by measuring the profile of a beveled portion of a wafer edge region, thereby providing wafers of excellent quality by minimizing the amount of thin film layer left after the thin film removal process.

[0020] Another object of the present invention is to provide a method for analyzing wafer shape, wherein the variables that cause errors in wafer shape analysis are small.

[0021] Another object of the present invention is to provide a method for analyzing wafer shape, which can be applied to flat wafers with flat edges and circular wafers with rounded edges.

[0022] Another object of the present invention is to provide a method for analyzing wafer shape, wherein thickness distribution can be measured without dividing the edge region of the wafer.

[0023] Other advantages, objects, and features of the invention are set forth in part in the description which follows, and will become apparent to those skilled in the art upon reading the following, or may be learned from practice of the invention. The objects and other advantages of the invention can be realized and obtained by means of the structures specifically pointed out in the written description, its claims, and the accompanying drawings.

[0024] To achieve these objectives and other advantages, according to the objectives of the present invention, as specifically presented and broadly described herein, a method for analyzing wafer shape includes: measuring the external shape of a plurality of wafers; detecting, from measurements obtained in measuring the external shape of the wafers, a first point having maximum curvature in the edge region of each wafer; detecting, a second point spaced apart from the first point in a direction toward the top of a corresponding wafer in the wafer; measuring, between a first line constructed to connect the first and second points and the front face of the corresponding wafer in the wafer; forming a thin film layer on the surface of each wafer; measuring the thickness distribution of the thin film layer; and identifying the wafer with the minimum maximum value of the thin film layer thickness distribution in the wafer.

[0025] The first point can be a point configured to have the minimum (1 / R) value in each wafer edge region, and R can be the curvature of a wafer surface corresponding to that point in the wafer.

[0026] The first point can be a point constructed as the point on each wafer surface in the edge region with the smallest second-order differential value of its position coordinates.

[0027] The height difference between the first point and the second point can be proportional to the second derivative of the position coordinates of the first point on a corresponding wafer surface in the wafer.

[0028] The height difference between the first and second points satisfies the equation H = α × (1 / R). 2 Here, H can be the height difference, α can be any constant, and R can be the curvature at the first point of a corresponding wafer in the wafer.

[0029] The second point can be located at a position horizontally spaced within a distance of about 0.5 μm from the top of the edge region of a corresponding wafer in the direction towards the body region.

[0030] In another aspect of the invention, the wafer includes: a body region, a front side and a back side of the body region configured to be parallel to each other, and an edge region disposed at the edge of the body region, wherein the edge region includes a chamfered portion and a top disposed thereon, wherein: the chamfered portion includes a first point having a maximum curvature and a second point spaced apart from the first point at a distance in a direction toward the top, the first point and the second point being configured to be disposed sequentially at a distance along a direction from the front side to the top, and the height difference between the first point and the second point being proportional to the second derivative of the position coordinates of the first point on the wafer surface.

[0031] It should be understood that the general description above and the detailed description below are merely illustrative and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0032] The accompanying drawings, included in the specification and constituting a part of this application, are provided to further understand the invention, illustrating one or more embodiments of the invention, and together with the specification serve to explain the principles of the invention. In the drawings:

[0033] Figure 1 This is a view showing common methods used to analyze wafer shape;

[0034] Figure 2 This is a view showing a wafer according to an embodiment of the present invention, and the shape of the wafer to be analyzed;

[0035] Figure 3 yes Figure 2 An enlarged cross-sectional view of the wafer shown;

[0036] Figure 4 This is a view showing the reference point of the beveled portion of the wafer, as well as the first and second points;

[0037] Figure 5 This is a graph showing the correlation between photoresist thickness and angle 1-1 in common methods;

[0038] Figure 6 This is a graph showing the correlation between the photoresist thickness and angle 1-1 in a method according to an embodiment of the present invention;

[0039] Figure 7 It is a view showing the thin film deposition and etching processes performed on the wafer. Invention Details

[0040] Exemplary embodiments of the present invention will now be described in detail, examples of which are shown in the accompanying drawings.

[0041] However, embodiments of the present invention can be implemented in various different forms, and the scope of the invention is not limited to the embodiments disclosed below. Embodiments of the invention are provided to thoroughly describe the invention and to fully convey its scope to those skilled in the art.

[0042] Furthermore, it should be understood that while the terms “first” and “second”, “above” and “below” may not always be required to cover any physical or logical relationship or order between substances or elements, they are used only to distinguish any substance or element from other substances or elements.

[0043] First, a method for manufacturing a wafer according to one embodiment of the present invention will be described.

[0044] More specifically, silicon single-crystal substrates are manufactured through the following processes: single-crystal growth processes that produce ingots using the Czochralski method; slicing processes that obtain thin, circular wafers by slicing single-crystal ingots; grinding processes that process the outer periphery of the wafers obtained through the slicing process to prevent wafer breakage or deformation; polishing processes that remove residual damage from machining in the wafers; polishing processes that smooth the wafer surface; and cleaning processes that remove adhesives or foreign matter from polished wafers, etc.

[0045] Subsequently, the wafer shape is analyzed using a method for analyzing wafer properties according to an embodiment of the present invention.

[0046] In the following description, the wafer edge will be exemplarily described in the context of wafer shapes that can be obtained from images (e.g., wafer edge, wafer surface, wafer back side, etc.). However, this implementation can also be applied to other wafer shapes, namely wafer surface and wafer back side, in addition to the wafer edge.

[0047] Figure 2 This is a view showing a wafer according to an embodiment of the present invention, the shape of which is to be analyzed; and Figure 3 yes Figure 2 The image shows an enlarged cross-sectional view of the wafer.

[0048] See Figure 2 The wafer W is divided into a body region B, a front side f, a back side b, and an edge region E located at the edge of the body region B.

[0049] Figure 2 The lower part of the diagram shows a portion of the wafer W, namely, part "A", in more detail.

[0050] The body region W occupies most of the chip W. The upper surface of the body region W can be called the front side f, and the lower surface of the body region W can be called the back side b.

[0051] Additionally, the edge region E can be divided into the beveled portion WB and the top WA. The upper surface of the beveled portion WB can be called the beveled front face WBf, and the lower surface of the beveled portion Wb can be called the beveled back face WBb.

[0052] Figure 2 The wafer W shown is a planar wafer, whose edge region E is flat, while a circular wafer can have a rounded edge profile, rather than... Figure 2 The flat top of WA.

[0053] Figure 3 In the chip, the thickness of the bulk region B of the wafer W can be represented as "t", the height or thickness of the top WA can be represented as "B3", the height or thickness of the beveled front side WBf can be represented as "B1", and the height or thickness of the beveled back side WBb can be represented as "B2".

[0054] Additionally, the length or width of the beveled front face WBf in the horizontal direction can be denoted as "A1", and the length or width of the beveled back face WBb in the horizontal direction can be denoted as "A2". Here, although the dimensions of B1 and B2 can be the same as each other, and the dimensions of A1 and A2 can be the same as each other, they may be slightly different from each other considering the errors in the manufacturing process.

[0055] Furthermore, angle 1θ1 is formed by the front face f of wafer W and the beveled front face WBf, and angle 2θ2 is formed by the back face b of wafer W and the beveled back face WBb. Here, although angle 1θ1 and angle 2θ2 can be identical to each other, they may differ slightly from each other considering errors in the manufacturing process.

[0056] exist Figure 3 In the diagram, the dashed lines extending from the obliquely truncated front face WBb and obliquely truncated back face WBb of wafer W can be tangents on the obliquely truncated front face WBb and obliquely truncated back face WBb, respectively. Furthermore, the tangents can be tangents at designated points on the obliquely truncated front face WBb and obliquely truncated back face WBb of wafer W, or tangents connecting two points, as shown in the following reference. Figure 4 As stated above.

[0057] The cross-sectional shape of the wafer manufactured by the above process can be measured as follows, and here, the cross-sections of multiple wafers can be measured using the same method. More specifically, the wafer edge region is measured by using optical equipment to measure the wafer surface, and then the cross-sectional shape can be analyzed.

[0058] Figure 4 It is a view that shows the reference point, the first point, and the second point of the beveled section.

[0059] Figure 4The wafer is a planar wafer, with a flat shape in the edge region E, and shows a portion of the front face f in the wafer body region B, as well as a portion of the beveled front face WBf and top WA in the edge region.

[0060] The oblique face WBf in the edge region E forms a curved surface. The first point P1 and the second point P2' are located on the oblique face WBf starting from the volume region B.

[0061] The first point P1 can be a point on the beveled front surface WBf that has the maximum curvature. The point with the maximum curvature can be detected by measuring the curvature of the corresponding point on the beveled front surface WBf, or it can be defined as a point with a minimum second-order derivative value, which is obtained by calculating the second-order derivative of the position coordinate profile of the corresponding point on the beveled front surface WBf. Here, the point with the maximum curvature and the point with the minimum second-order derivative value refer to the point on the wafer surface with the maximum curvature on the beveled front surface WBf, and the point on the wafer surface with the minimum second-order derivative value of its position coordinates, respectively. Alternatively, the point on the wafer surface with the maximum curvature can be the point on the wafer surface with the minimum radius of curvature.

[0062] The second point P2' can be a point on the obliquely cut front face WBf, adjacent to the first point P1. The height difference between the first point P1 and the second point P2' is proportional to the second derivative of the position coordinates of the first point (1 / R). More specifically, the height difference H between the first point P1 and the second point P2' can be α×(1 / R). 2 And here, α can be any constant, and R can be the curvature of the first point P1.

[0063] Additionally, the horizontal distance D between the top WA and the second point P2' in the wafer edge region E can be within approximately 0.5 μm.

[0064] See Figure 4 Measurement line 1-1 connects the first point P1 and the second point P2'. The first point P1 is the point with the minimum radius of curvature (i.e., the point with the maximum curvature) on the oblique front surface WBf in the wafer edge region E. Furthermore, the measurement angle 1-1 (θ) 11 ), the angle 1-1(θ) 11 It is formed by the front side f and line 1-1 of the wafer body region B.

[0065] In order to avoid Figure 3 The angles 1θ1 and 2θ2 shown are confused, and angle 1-1(θ) 11 ) Displayed in Figure 4 middle. Figure 3 The angles θ1 and θ2 shown can be measured using various methods, but Figure 4 The angle 1-1(θ) shown11 Measurements can be taken using the first point P1 and the second point P2'.

[0066] Subsequently, a thin film layer can be formed on the surface of the corresponding wafer by methods such as deposition.

[0067] Subsequently, the thickness distribution of the wafer edge region on which the thin film layer is formed can be measured. Here, optical equipment can be used to determine the thickness distribution of the wafer edge region using a non-destructive method.

[0068] Subsequently, it can be confirmed that the wafer with the minimum maximum thickness distribution of the thin film layer in the wafer is the one with the smallest thickness distribution. The thin film layer deposited on the wafer surface can exhibit a maximum thickness distribution, especially on the aforementioned beveled portion or on the front side of the body region adjacent to the beveled portion. Furthermore, as the maximum thickness distribution decreases, the quality of the manufactured wafer can be improved, and the likelihood of semiconductor device defects can be reduced.

[0069] Here, considering that the shape of the first point P1 with the largest curvature in the aforementioned oblique section may have the greatest impact on the thickness distribution of the thin film layer, but it is difficult to accurately measure the slope of the tangent at the first point P1, it is possible to measure the tangent connecting the first point P1 and the second point P2' instead, and the angle formed by the measured tangent and the front side of the wafer body region can be measured.

[0070] Table 1 below shows the references Figure 1 The correlation between photoresist thickness and angle 1-1 is analyzed using the common methods described above, and the correlation between photoresist thickness and angle 1-1 is analyzed using the method described in the above embodiments of the present invention.

[0071] [Table 1]

[0072]

[0073] In Examples and Comparative Example 1, the shape of the wafer edge was analyzed using the method according to the above-described embodiments of the present invention and common methods, and here, device A can be a non-destructive measurement instrument using optical equipment. The analysis results of the edge region shape of the 17 wafers corresponding to the planar wafers of group 1, the 17 wafers of group 2 and the 17 wafers of group 3, and the 7 wafers corresponding to the circular wafers of group 4 showed that the correlation between the photoresist thickness and the angle 1-1 was generally about 90 and about 57.

[0074] In Comparative Example 2, the shape of the wafer edge was analyzed using common methods, and here, for example, device B could be a scanning electron microscope (SEM). The analysis results of the edge region shape of the 17 wafers in group 1, group 2, and group 3 corresponding to planar wafers, and the 7 wafers in group 4 corresponding to circular wafers, showed that the overall correlation between photoresist thickness and angle 1-1 was approximately 44.

[0075] Figure 5 This is a graph showing the correlation between photoresist thickness and angle 1-1 in common methods; and Figure 6 This is a graph illustrating the correlation between photoresist thickness and angle 1-1 in a method according to an embodiment of the present invention.

[0076] In the corresponding chart, the horizontal axis represents angle 1-1(θ) 11 ), and the vertical axis represents the thickness of the photoresist.

[0077] Figure 5 Comparative Example 2 in Table 1 is represented, and in the corresponding sample, the photoresist thickness PR and angle 1-1 (θ) are represented. 11 The coefficient of determination R of the correlation between ) 2 It is 0.4428, and Figure 6 The examples in Table 1 are shown, and in the corresponding samples, the thickness of the photoresist PR and the angle 1-1 (θ) are represented. 11 The coefficient of determination R of the correlation between ) 2 It is 0.9019.

[0078] In other words, with Figure 5 Compared to Comparative Example 2 shown, in the method according to the embodiment of the present invention, the photoresist thickness tends to increase rapidly with the increase of angle 1-1, and therefore, by adjusting the thickness of angle 1-1, it is possible to prevent the photoresist from being deposited to a very large thickness on the wafer, especially at the first point P1 in the edge region E.

[0079] In other words, in wafer manufacturing processes, the angle θ can be controlled through edge grinding, edge polishing, or double-sided polishing processes. 11 ).

[0080] By analyzing the wafer shape using the above method, when depositing the thin film layer on the wafer in post-processing, the wafer with the smallest thin film layer thickness, and in particular the wafer with the smallest maximum thin film layer thickness, can be defined as follows.

[0081] The wafer has a body region and an edge region disposed at the edge of the body region. The body region includes a front side and a back side formed parallel to each other on its upper and lower surfaces. The edge region may include a chamfered portion and a top disposed at its edge. The chamfered portion may include a first point having maximum curvature and a second point spaced apart from the first point in a direction toward the top, and the first and second points may be arranged sequentially from the front side to the top. This definition can be applied to circular wafers having edge regions with rounded edge profiles, in addition to flat wafers having edge regions with flat tops.

[0082] Figure 7 It is a view showing the thin film deposition and etching processes on the wafer.

[0083] After depositing a thin film layer on a wafer and coating it with a photoresist, the thin film layer can be removed by methods such as etching. Following the etching process, it can be confirmed that the thin film layer remains in the region adjacent to the wafer edge or beveled portion. When the wafer has the aforementioned beveled profile, the amount of thin film layer remaining in the region adjacent to the wafer edge or beveled portion can be minimized.

[0084] As is evident from the above description, in the method for analyzing wafer shape according to an embodiment of the present invention, only two points are defined in the wafer edge region, namely, a first point with maximum curvature and a second point spaced a specified distance from the first point, a tangent line constructed to connect the first point and the second point is measured, and the angle formed between the tangent line and the front surface of the wafer body region is measured. Therefore, a thin film layer with a smaller thickness can be formed on the wafer by adjusting the angle formed between the tangent line and the front surface of the wafer body region.

[0085] It will be apparent to those skilled in the art that various modifications and variations can be made to this invention without departing from its spirit or scope. Therefore, this invention should cover such modifications and variations, provided they fall within the scope of the appended claims and their equivalents.

[0086] Therefore, the scope of this invention is not defined by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents should be interpreted as included in this disclosure.

Claims

1. A method for analyzing wafer shape, the method comprising: Measure the external shape of multiple wafers; The first point with the maximum curvature in the edge region of each wafer is detected by measurements obtained from the external shape of the wafer. A second point, spaced a certain distance from the first point, is detected in the direction of the top of the corresponding wafer in the wafer; The first angle formed between the first line and the front face of a corresponding wafer in the wafer is measured, and the first line is configured to connect the first point and the second point; A thin film layer is formed on the surface of each wafer; Measure the thickness distribution of the thin film layer; as well as Identify the wafer with the smallest maximum value for the thin film layer thickness distribution within the wafer. The first point is a point constructed to have the least second-order differential value of the position coordinates on the surface of each wafer in the edge region.

2. The method as described in claim 1, wherein, The first point is to construct the point with the minimum (1 / R) value in the edge region of each wafer. Where R is the surface curvature of the corresponding wafer at that point.

3. The method as described in claim 1, wherein, The height difference between the first point and the second point is proportional to the second derivative of the position coordinates of the first point on the corresponding wafer surface in the wafer.

4. The method of claim 3, wherein, The height difference between the first point and the second point satisfies the equation H = α × (1 / R). 2 , Where H is the height difference, α is an arbitrary constant, and R is the curvature of the corresponding wafer at the first point.

5. The method of claim 1, wherein, The second point is located at a horizontal distance of less than 0.5 μm from the top of the edge region of a corresponding wafer in the direction toward the body region.

6. A chip comprising: Body region; The front and back sides of the volume regions are constructed to be parallel and opposite to each other; as well as The edge region is set at the edge of the body region. The edge region includes a beveled portion and a top portion disposed at its edge, wherein: The beveled portion includes a first point with maximum curvature and a second point spaced apart from the first point in the direction toward the top, the first and second points being configured to be sequentially arranged at a certain distance along the direction from the front to the top; and The height difference between the first point and the second point is proportional to the second derivative of the position coordinates of the first point on the wafer surface.

7. The wafer as claimed in claim 6, wherein, The first point is a point on the wafer surface in the edge region that has the least second-order differential value of its position coordinates.

8. The wafer as claimed in claim 6, wherein, The first point is the point configured to have the minimum (1 / R) value in the wafer edge region. Where R is the curvature of the wafer surface at that point.

9. The wafer as claimed in claim 6, wherein, The height difference between the first point and the second point satisfies the equation H = α × (1 / R). 2 , Where H is the height difference, α is an arbitrary constant, and R is the curvature of the first point.

10. The wafer as claimed in claim 6, wherein, The second point is located at a position horizontally spaced from the top of the wafer edge region at a distance of approximately 0.5 μm in the direction toward the body region.

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