A substrate in which an electronic component is embedded

Abstract

The present disclosure provides a substrate in which an electronic component is embedded, the substrate in which an electronic component is embedded including a core structure having a cavity, a metal layer disposed on a bottom surface of the cavity of the core structure, and an electronic component disposed on the metal layer in the cavity of the core structure. The substrate in which an electronic component is embedded has an excellent heat dissipation effect.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0088970, filed on July 17, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a substrate in which electronic components are embedded. Background Technology

[0003] As electronic devices (including mobile phones) in the information technology (IT) field have become thinner and lighter, in response to the technological demands for this, there is a need for technologies to insert electronic components such as integrated circuits (ICs) into printed circuit boards, and various methods have been developed in recent years to embed electronic components into printed circuit boards.

[0004] Furthermore, with the improvement of electronic component performance and the increase in signal transmission between components, the heat generated in electronic components increases. Therefore, much research and development has been carried out on the heat dissipation design of printed circuit boards in which such electronic components are embedded. Summary of the Invention

[0005] One aspect of this disclosure is to provide a substrate in which electronic components are embedded, which has excellent heat dissipation performance.

[0006] Another aspect of this disclosure is to provide a substrate in which electronic components are embedded, which has excellent wiring design efficiency.

[0007] According to one of the various solutions proposed in this disclosure, a first metal layer is disposed on the bottom surface of the cavity in which the electronic components are disposed, and a second metal layer is disposed on the side surface of the electronic components, so as to diversify the heat dissipation path and increase the heat dissipation area.

[0008] According to one aspect of this disclosure, a substrate in which an electronic component is embedded may include: a core structure including a first insulating body, a plurality of first wiring layers and one or more first via layers, the plurality of first wiring layers being disposed on and / or in the first insulating body, the one or more first via layers being disposed in the first insulating body, the core structure having a cavity penetrating at least a portion of the first insulating body; a first metal layer disposed on a bottom surface of the cavity; an electronic component disposed on the first metal layer in the cavity; and a second metal layer disposed on a side surface of the electronic component.

[0009] According to another embodiment of the various schemes proposed in this disclosure, a metal layer is disposed on the bottom surface of a cavity in which electronic components are disposed, and patterned holes are formed in the metal layer to use a portion of the metal layer as a barrier metal for forming the cavity and as a heat dissipation path, while the remaining portion of the metal layer is used as a signal path.

[0010] According to one aspect of this disclosure, a substrate in which an electronic component is embedded may include: a core structure including an insulating body, a plurality of wiring layers and one or more via layers, the plurality of wiring layers being disposed on and / or in the insulating body, the one or more via layers being disposed in the insulating body, the core structure having a cavity penetrating at least a portion of the insulating body; a metal layer disposed on the bottom surface of the cavity and having patterned holes; and an electronic component disposed on the metal layer in the cavity.

[0011] According to one aspect of this disclosure, a substrate may include: a core structure having a cavity and including an insulating body, one or more first wiring layers and one or more via layers, the one or more first wiring layers being disposed on and / or in the insulating body, the one or more via layers being disposed in the insulating body and connected to the one or more first wiring layers; a first metal layer being disposed on or in the insulating body; an electronic component being disposed on the first metal layer in the cavity; and a second metal layer extending from the first metal layer to contact a side surface of the electronic component. Attached Figure Description

[0012] The above and other aspects, features and advantages of this disclosure will be more clearly understood by taking into account the accompanying drawings and the following detailed description, in which:

[0013] Figure 1 This is a block diagram illustrating an example of an electronic device system;

[0014] Figure 2 This is a perspective view showing an example of an electronic device;

[0015] Figure 3 This is a cross-sectional view showing an example of a substrate in which electronic components are embedded;

[0016] Figure 4 It shows along Figure 3 The line I-I' in the middle is intercepted Figure 3 A schematic cross-sectional view of a substrate in which electronic components are embedded, shown;

[0017] Figure 5 It shows along Figure 3 The line II-II' in the middle is intercepted Figure 3A schematic cross-sectional view of a substrate in which electronic components are embedded, shown;

[0018] Figures 6 to 17 It is a schematic representation of manufacturing. Figure 3 A cross-sectional view of an example of a substrate in which electronic components are embedded;

[0019] Figure 18 This is a cross-sectional view schematically illustrating another example of a substrate in which electronic components are embedded;

[0020] Figure 19 This is a schematic cross-sectional view illustrating another example of a substrate in which electronic components are embedded; and

[0021] Figure 20 This is a cross-sectional view schematically illustrating another example of a substrate in which electronic components are embedded. Detailed Implementation

[0022] In the following description, exemplary embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. In the drawings, for clarity of description, the shape, size, etc., of the elements may be exaggerated or simplified.

[0023] Figure 1 This is a block diagram illustrating an example of an electronic device system.

[0024] Reference Figure 1 The electronic device 1000 can house the motherboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 can be physically and / or electrically connected to the motherboard 1010. These components can be connected to other components (described below) via various signal lines 1090.

[0025] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, etc.; application processor chips, such as central processing units (e.g., central processing units (CPU)), graphics processing units (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other.

[0026] Network-related components 1030 may include components that are compatible with or operate using protocols such as: Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM+, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, and 5G protocols, as well as any other wireless and wired protocols specified after the protocols listed above. However, network-related component 1030 is not limited to this, and may also include components that are compatible with or operate using various other wireless or wired standards or protocols. Furthermore, network-related component 1030 may be combined with the aforementioned chip-related component 1020.

[0027] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these and may also include passive components for various other purposes. Furthermore, other components 1040 may be combined with the aforementioned chip-related components 1020 and / or the aforementioned network-related components 1030.

[0028] Depending on the type of electronic device 1000, it may include other components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage device (e.g., a hard disk drive) (not shown), an optical disc (CD) drive (not shown), a digital versatile disc (DVD) drive (not shown), etc. However, these other components are not limited to these, and depending on the type of electronic device 1000, it may also include other components for various purposes.

[0029] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital video camera, digital camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these and can be any other electronic device capable of processing data.

[0030] Figure 2 This is a perspective view showing an example of an electronic device.

[0031] Reference Figure 2 In the various electronic devices 1000 described above, semiconductor packages can be used for various purposes. For example, a motherboard 1110 may be housed within the body of a smartphone 1100, and various electronic components 1120 may be physically and / or electrically connected to the motherboard 1110. Additionally, other components (such as a camera module 1130) that may or may not be physically and / or electrically connected to the motherboard 1110 may be housed within the body. Some of the electronic components 1120 may be chip-related components (e.g., semiconductor package 1121), but are not limited thereto. The electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

[0032] Figure 3 This is a cross-sectional view showing a substrate in which electronic components are embedded.

[0033] Figure 4 It shows along Figure 3 The line I-I' in the middle is intercepted Figure 3 The diagram shows a cross-sectional view of a substrate in which electronic components are embedded.

[0034] Figure 5 It shows along Figure 3 The line II-II' in the middle is intercepted Figure 3 The diagram shows a cross-sectional view of a substrate in which electronic components are embedded.

[0035] Referring to the accompanying drawings, the substrate 100A in which electronic components are embedded may include a core structure 110. The core structure 110 includes a first insulating layer 111, a plurality of first wiring layers 112a and 112b, and one or more first via layers 113. The core structure 110 has a cavity 110H penetrating the first insulating layer 111, a first metal layer M disposed on the bottom surface of the cavity 110H, an electronic component 120 disposed on the first metal layer M in the cavity 110H, and a second metal layer N disposed on the side surface of the electronic component 120.

[0036] As described above, in the substrate 100A according to the example in which an electronic component is embedded, a first metal layer M is disposed on the bottom surface of the cavity 110H in which the electronic component 120 is disposed, and a second metal layer N is disposed on the side surface of the electronic component 120. Therefore, heat dissipation paths for dissipating heat generated from the electronic component 120 can be provided in multiple ways, and the heat dissipation area can be increased. Therefore, the substrate 100A in which the electronic component is embedded can have excellent heat dissipation performance.

[0037] Furthermore, the second metal layer N can physically contact the side surfaces of the electronic component 120. In this case, heat generated from the electronic component 120 can be released more effectively. The second metal layer N can surround the side surfaces of the electronic component 120. For example, in the case where the electronic component 120 is generally cuboid, the second metal layer N can surround all four side surfaces of the electronic component 120. For example, the second metal layer N can continuously surround all four side surfaces of the electronic component 120, but this disclosure is not limited thereto, and local discontinuities h3 may exist in certain regions.

[0038] Furthermore, the second metal layer N can be in physical contact with the first metal layer M. In this case, heat can be efficiently transferred to the first metal layer M, and as a result, heat generated from the electronic component 120 can be efficiently released. The first metal layer M may have a groove h1, and the second metal layer N may fill the groove h1. For example, a portion of the second metal layer N may be disposed in the groove h1. In this case, for example, in... Figure 4 On the plane shown in Figure 5, the groove h1 may be formed along the four side surfaces of the electronic component 120. For example, the groove h1 may be formed continuously along the four side surfaces of the electronic component 120, but is not limited thereto, and local discontinuities h3 may exist in certain regions.

[0039] Furthermore, in the substrate 100A in which electronic components are embedded according to the example, the first metal layer M has a patterned hole h2. As a result, the first metal layer M may include a first metal pattern M1 and a plurality of second metal patterns M2, the first metal pattern M1 having a groove h1, and the plurality of second metal patterns M2 spaced apart from each other and surrounded by the first metal pattern M1. A portion of the plurality of second metal patterns M2 can be used as a direct heat dissipation path, and the remaining portion of the plurality of second metal patterns M2 can be used as a signal path. Therefore, heat generated from the bottom surface of the electronic component 120 can be effectively released to the outside through the first metal layer M via the shortest path, while a portion of the first metal layer M can be used as a signal path to improve the efficiency of the wiring design. The patterned hole h2 can be a single patterned hole h2, or it can be a plurality of patterned holes h2 that are distinct from each other, and the number and shape of the plurality of second metal patterns M2 can vary in various ways depending on the formation of the patterned hole h2.

[0040] Furthermore, at least a portion of the plurality of second metal patterns M2 may be electrically connected to at least one ground pattern among the plurality of first wiring layers 112a and 112b, and at least one of the remaining second metal patterns M2 may be connected (e.g., electrically connected) to at least one signal pattern among the plurality of first wiring layers 112a and 112b. The first metal pattern M1 may also be electrically connected to at least one ground pattern among the plurality of first wiring layers 112a and 112b; therefore, at least a portion of the plurality of second metal patterns M2 may be connected to the first metal pattern M1, and thereby electrically connected to at least one ground pattern among the plurality of first wiring layers 112a and 112b.

[0041] Alternatively, only the second metal layer N may be provided without forming the patterned hole h2 in the first metal layer M, or conversely, only the patterned hole h2 may be formed in the first metal layer M without providing the second metal layer N. However, satisfying both of these conditions (i.e., forming the patterned hole h2 and the second metal layer N simultaneously) is more preferable for excellent heat dissipation and excellent wiring design.

[0042] Referring to the accompanying drawings, the substrate 100A in which electronic components are embedded, according to the example, may further include: an encapsulant 130 disposed on the core structure 110 to fill at least a portion of the cavity 110H and embed at least a portion of the electronic component 120 within the encapsulant 130; a second wiring layer 132 disposed on the encapsulant 130; a second via layer 133 penetrating the encapsulant 130; a first passivation layer 150 disposed below the core structure 110; and / or a second passivation layer 160 disposed on the encapsulant 130. In this case, the first passivation layer 150 may have a plurality of first openings 151, the plurality of first openings 151 exposing at least a portion of the first wiring layer 112a disposed on the lowermost side and at least a portion of the first metal layer M. In this case, since the first metal layer M can be used as a direct heat dissipation path, the heat dissipation effect can be enhanced by minimizing the length of the heat dissipation path.

[0043] Referring to the accompanying drawings, the substrate 100A, in which electronic components are embedded, according to the example, may further include: a plurality of first electrical connection metals 155, respectively disposed in a plurality of first openings 151 of a first passivation layer 150; a plurality of second electrical connection metals 165, respectively disposed in a plurality of second openings 161 of a second passivation layer 160; and a plurality of surface mount components 170, which are surface mounted on the second passivation layer 160 via the plurality of second electrical connection metals 165. As described above, the substrate 100A, in which electronic components are embedded, according to the example, can be used as a packaging substrate and can have a package module form by providing the surface mount components 170.

[0044] In the following description, the assembly of a substrate 100A in which electronic components are embedded, according to an example, will be described in more detail with reference to the accompanying drawings.

[0045] The core structure 110 includes: an insulating body including a first insulating layer (or a first core insulating layer) 111; a plurality of first wiring layers 112a and 112b respectively disposed on or within the insulating body; and one or more first via layers (or first core via layers) 113 disposed within the insulating body. Additionally, the core structure 110 may have a cavity 110H penetrating the first insulating layer 111. For example, the core structure 110 may include: a first insulating layer 111; a 1-1 wiring layer (or a first core wiring layer) 112a embedded in the lower portion of the first insulating layer 111; a 1-2 wiring layer (or a second core wiring layer) 112b disposed on the upper surface of the first insulating layer 111; and a first via layer 113 penetrating the first insulating layer 111 and electrically connecting the 1-1 wiring layer 112a and the 1-2 wiring layer 112b, and the core structure 110 may have a cavity 110H penetrating the first insulating layer 111.

[0046] An insulating material may be used as the material for the first insulating layer 111. Thermosetting resins (such as epoxy resins) or thermoplastic resins (such as polyimide resins) may be used as the insulating material. Alternatively, insulating materials containing reinforcing materials (such as inorganic fillers (such as silica) and / or core materials (such as glass fibers)) may be used. For example, a prepreg may be used as the material for the first insulating layer 111, but it is not limited to this.

[0047] The first wiring layers 112a and 112b may include metallic materials. Copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof may be used as the metallic materials. The first wiring layers 112a and 112b may perform various functions depending on the design of the respective layers. For example, the first wiring layers 112a and 112b may include ground patterns, power patterns, signal patterns, etc. Each of the patterns may have a line shape, a surface shape, and / or a pad shape. The first wiring layers 112a and 112b may be formed using additive processing (AP), semi-AP (SAP), modified SAP (MSAP), via sealing (TT), etc., resulting in the first wiring layers 112a and 112b including a seed layer (electroplated layer) and an electroplated layer formed based on the seed layer.

[0048] A first step d1 may be present between the lower surface of the 1-1 wiring layer 112a and the lower surface of the first insulating layer 111. For example, the 1-1 wiring layer 112a may be formed by an embedded trace substrate (ETS) method, whereby, as described later, the metal foil used as a seed layer may be removed to form the first step d1. The 1-1 wiring layer 112a may not have a seed layer (a separate electroless layer) and may consist of only a single electroplated layer.

[0049] On the other hand, the 1-2 wiring layer 112b may include a seed layer (unplated layer) and an electroplated layer formed based on the seed layer. When resin-coated copper foil (RCC) is used as the first insulating layer 111, a metal foil (such as copper foil) may also be included on the bottommost side. If desired, a primer resin formed on the surface of the copper foil may further be included.

[0050] The first via layer 113 may include a metallic material. Copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof may be used as the metallic material. Depending on the design, the first via layer 113 may include connection vias for signal connections, connection vias for grounding connections, and connection vias for power connections, etc. Each connection via in the first via layer 113 may be a via in which the through hole is filled with a metallic material, or a via in which a metallic material is formed along the wall surface of the through hole. For example, see reference... Figure 3 As shown in the cross-sectional view, each wiring via (or connection via) may have a tapered shape in which the width of the upper surface is greater than the width of the lower surface. The first via layer 113 may be formed by a plating process (such as AP, SAP, MSAP, TT, etc.), and as a result, similar to wiring layer 112b 1-2, the first via layer 113 may include a seed layer (unplated layer) and an electroplated layer formed based on the seed layer.

[0051] The first metal layer M may comprise a metallic material. Copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof may be used as the metallic material. The central region of the first metal layer M may be exposed through the cavity 110H, and the edge regions of the first metal layer M may be embedded in the first insulating layer 111. In this case, a second step d2 may be formed between the upper surface of the first metal layer M in the central region and the upper surface of the first metal layer M in the edge region. For example, in a process that uses sandblasting to form the cavity 110H, a portion of the central region of the first metal layer M, which serves as a barrier, may be removed by erosion with fine particles to form the second step d2.

[0052] A first step d1 may be present between the lower surface of the first metal layer M and the lower surface of the first insulating layer 111. For example, when forming the 1-1 wiring layer 112a, the first metal layer M may also be formed by the ETS method, thereby removing the metal foil used as a seed layer to form the first step d1. The first metal layer M may not have a seed layer (a separate electroless layer) and may consist of only a single electroplated layer. According to an exemplary embodiment of the present invention, the first metal layer M may be disposed in the insulating body or on the insulating body.

[0053] The first metal layer M may have a groove h1, and the groove h1 may be filled with a second metal layer N. For example, in such a case... Figure 4 On the plane shown in Figure 5, the groove h1 may be formed along the four side surfaces of the electronic component 120. For example, the groove h1 may be formed continuously along the four side surfaces of the electronic component 120, but is not limited thereto, and local discontinuities h3 may exist in specific regions. Additionally, the first metal layer M may have a patterned hole h2, and the first metal layer M may include a first metal pattern M1 and a plurality of second metal patterns M2. The first metal pattern M1 is disposed along the edge of the cavity 110H through the patterned hole h2 and has the groove h1. The plurality of second metal patterns M2 are spaced apart from each other and surrounded by the first metal pattern M1. The shape of each of the plurality of second metal patterns M2 is not particularly limited and may have a line shape, a surface shape, and / or a pad shape. The patterned hole h2 may be filled with a first passivation layer 150.

[0054] The second metal layer N may comprise a metallic material, and may use copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof as the metallic material. The second metal layer N may be in physical contact with the side surface of the electronic component 120. For example, in... Figure 4 On the plane shown in Figure 5, the second metal layer N may surround the four side surfaces of the electronic component 120.

[0055] For example, the second metal layer N may continuously surround the four side surfaces of the electronic component 120, but this disclosure is not limited thereto, and local discontinuities h3 may exist in certain areas. The second metal layer N may physically contact the first metal layer M. For example, the second metal layer N may fill the trench h1 of the first metal layer M. The second metal layer N may be formed by, for example, a plating process, such as AP, SAP, MSAP, or TT processes. Thus, the second metal layer N may include a seed layer (an electroless plating layer formed on the bottom and wall surfaces of the deep via, which will be described later) and an electrolytic plating layer formed based on the seed layer to fill the deep via.

[0056] Electronic component 120 may be an integrated circuit (IC), in which hundreds to millions of components are integrated on a single chip. For example, electronic component 120 may be a processor chip (such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a field-programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc.), specifically, electronic component 120 may be an application processor (AP), but is not limited thereto, and electronic component 120 may be memory (such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.), an analog-to-digital converter, or a logic chip (such as an application-specific integrated circuit (ASIC), etc.).

[0057] Electronic component 120 can be arranged with its surface facing upwards, such that the surface on which the connection pad 120P is disposed faces upwards, and the opposing surfaces of these surfaces are attached to the first metal layer M via an adhesive film 125 (such as a die attach film (DAF)). An adhesive with excellent heat dissipation properties (e.g., DAF with excellent heat dissipation properties) can be used as the adhesive film 125. Electronic component 120 can be a surface-mount passive component, such as a surface-mount inductor or a surface-mount capacitor. Electronic component 120 can be a combination of an IC and a surface-mount passive component, in which case multiple cavities 110H can be formed.

[0058] Encapsulant 130 may be disposed on core structure 110 and may fill at least a portion of cavity 110H, and may embed at least a portion of electronic component 120 within encapsulant 130. Insulating materials may be used as the material for encapsulant 130. Thermosetting resins (such as epoxy resins) or thermoplastic resins (such as polyimide resins) may also be used as insulating materials. Furthermore, insulating materials in which inorganic fillers (such as silica) are contained may also be used. For example, Ajinomoto film (ABF) may be used as the material for encapsulant 130, but it is not limited thereto, and photosensitive encapsulant (PIE) may also be used as the material for encapsulant 130. Optionally, prepreg may also be used as the material for encapsulant 130.

[0059] The second wiring layer 132 may be disposed on the upper surface of the encapsulant 130. The second wiring layer 132 may include a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The second wiring layer 132 may perform various functions depending on the design. For example, the second wiring layer 132 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. Each of the patterns may have a line shape, a surface shape, or a pad shape.

[0060] The second wiring layer 132 can be formed by processes such as AP, SAP, MSAP, TT, etc. Therefore, the second wiring layer 132 may include a seed layer (electroplated layer) and an electroplated layer formed based on the seed layer. When RCC is used as the encapsulant 130, a metal foil (such as copper foil) may also be included at the bottom, and a primer resin formed on the surface of the copper foil may also be included.

[0061] The second via layer 133 can penetrate the encapsulant 130 and electrically connect the second wiring layer 132 to each of the 1-2 wiring layers 112b and the connection pad 120P. The second via layer 133 may include a metallic material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Depending on the design, the second via layer 133 may include connection vias for signal connections, connection vias for ground connections, connection vias for power connections, etc. The wiring vias of the second via layer 133 may be vias in which the via is filled with a metallic material, or vias in which a metallic material is formed along the wall surface of the via. For example, see reference... Figure 3 As shown in the cross-sectional view, each wiring via may have a tapered shape in which the width of the upper surface is greater than the width of the lower surface. The second via layer 133 may also be formed by a plating process (such as AP, SAP, MSAP, TT, etc.), and thus, similar to the second wiring layer 132, the second via layer 133 may include a seed layer (electroplated layer) and an electroplated layer formed based on the seed layer.

[0062] The first passivation layer 150 and the second passivation layer 160 protect the internal structure from external physical and chemical damage. The first passivation layer 150 may have a plurality of first openings 151, and the second passivation layer 160 may have a plurality of second openings 161. The plurality of first openings 151 expose at least a portion of each of the 1-1 wiring layer 112a and the first metal layer M. The plurality of second openings 161 expose at least a portion of the second wiring layer 132. The materials of the first passivation layer 150 and the second passivation layer 160 may include insulating materials. In this case, thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide resins), and materials in which thermosetting resins and / or thermoplastic resins are mixed with inorganic fillers can be used as insulating materials, for example, ABF can be used, but not limited thereto.

[0063] A first electrical connection metal 155 is disposed on a plurality of first openings 151 of the first passivation layer 150, and a second electrical connection metal 165 is disposed on a plurality of second openings 161 of the second passivation layer 160. The first electrical connection metal 155 is connected to the portion of the 1-1 wiring layer 112a exposed through the first openings 151 and the portion of the first metal layer M exposed through the first openings 151. The second electrical connection metal 165 is connected to the portion of the second wiring layer 132 exposed through the second openings 161. The first electrical connection metal 155 can physically connect and / or electrically connect the substrate 100A in which electronic components are embedded to an external entity. For example, the substrate 100A in which electronic components are embedded can be mounted on the motherboard of an electronic device, a ball grid array (BGA) substrate, etc., via the first electrical connection metal 155. The second electrical connection metal 165 can physically connect and / or electrically connect the substrate 100A in which electronic components are embedded to a surface mount assembly 170. The first electrical connection metal 155 and the second electrical connection metal 165 may be formed using tin (Sn) or an alloy containing tin (Sn) (e.g., solder), but this is merely an example, and the materials are not particularly limited thereto. The first electrical connection metal 155 and the second electrical connection metal 165 may be configured as pads, solder balls, leads, etc., respectively.

[0064] Each of the surface mount components 170 can be an active component and / or a passive component. Examples of active components may include the IC described above for electronic component 120. Examples of passive components may include surface mount capacitors (such as multilayer ceramic capacitors (MLCCs)) and surface mount inductors (such as power inductors (PIs)). If desired, a molding material covering the surface mount component 170 may also be disposed on the second passivation layer 160, and the molding material may be, but is not limited to, known epoxy molding compounds (EMCs). When the surface mount component 170 is further configured, the substrate 100A in which the electronic components are embedded can be used as a package module, such as a system-in-package (SiP).

[0065] Figures 6 to 17 It shows the manufacturing process. Figure 3 The diagram shows an example of a process for a substrate in which electronic components are embedded.

[0066] Reference Figure 6 A carrier 210 is prepared. A metal foil (such as a copper foil) m1 may be disposed on two surfaces (e.g., the upper surface and the lower surface) of the carrier 210.

[0067] Reference Figure 7 Metal foil m1 is used as a base seed layer, and a 1-1 wiring layer 112a and a first metal layer M are formed on the carrier 210 by ETS plating process.

[0068] Reference Figure 8A first insulating layer 111 is formed using RCC material, wherein a metal foil (such as copper foil) m2 is disposed on the upper surface of the prepreg. Subsequently, through holes 113h are formed in the first insulating layer 111 by means of laser processing or the like.

[0069] Reference Figure 9 A wiring layer 112b and a first via layer 113 are formed through a plating process. This forms a core structure 110. Subsequently, a patterned dry film 220 is stacked on the core structure 110 to form a cavity 110H in subsequent processes.

[0070] Reference Figure 10 The cavity 110H is formed by sandblasting or the like. In this process, the first metal layer M can be used as a barrier, and a portion of the first metal layer M can be removed from the area of ​​the first metal layer M exposed through the cavity 110H.

[0071] Reference Figure 11 Remove the dry film 220 and use the adhesive film 125 to attach the electronic component 120 to the first metal layer M in the cavity 110H with the surface facing upward (i.e., the surface on which the connection pad 120P is provided facing upward).

[0072] Reference Figure 12 Encapsulant 130 is formed by laminating ABF onto core structure 110, and through-holes 133h are formed by laser processing or the like.

[0073] Reference Figure 13 The second wiring layer 132 and the second via layer 133 are formed by a plating process. A laminate is then manufactured on both sides of the carrier 210 through a series of processes.

[0074] Reference Figure 14 Separate the laminate from the carrier 210.

[0075] Reference Figure 15 Dry films 230 and 240 are respectively attached to both sides of the separated laminate, and deep through-holes V penetrating the first metal layer M and the encapsulant 130 are formed by laser processing or the like, and patterned holes h2 penetrating the first metal layer M are formed. The area of ​​the deep through-hole V penetrating the first metal layer M is called the aforementioned groove h1.

[0076] Reference Figure 16 A second metal layer N is formed by filling the deep via V using a plating process. Additionally, dry films 230 and 240 are removed.

[0077] Reference Figure 17A first passivation layer 150 and a second passivation layer 160 are formed by ABF lamination or the like, and a plurality of first openings 151 and a plurality of second openings 161 are formed by laser processing or the like. Thereafter, a first electrical connection metal 155 and a second electrical connection metal 165 are formed as needed.

[0078] The substrate 100A with embedded electronic components according to the above example can be manufactured by a series of processes, and other repetitive descriptions of the substrate 100A with embedded electronic components are omitted.

[0079] Figure 18 This is a schematic cross-sectional view showing another example of a substrate in which electronic components are embedded.

[0080] Referring to the accompanying drawings, compared with the core structure 110 formed in the substrate 100A in which electronic components are embedded according to the above example, the core structure 110 in the substrate 100B in which electronic components are embedded according to another example is formed as more layers. For example, the core structure 110 may include: a 1-1 insulating layer 111a; a 1-1 wiring layer 112a embedded in the lower part of the 1-1 insulating layer 111a; a 1-2 wiring layer 112b disposed on the upper surface of the 1-1 insulating layer 111a; a 1-1 via layer 113a penetrating the 1-1 insulating layer 111a and electrically connecting the 1-1 wiring layer 112a and the 1-2 wiring layer 112b; a 1-2 insulating layer (or second core insulating layer) 111b disposed on the upper surface of the 1-1 insulating layer 111a and covering the 1-2 wiring layer 112b; a 1-3 wiring layer (or third core wiring layer) 112c disposed on the upper surface of the 1-2 insulating layer 111b; and a 1-2 via layer (or second core via layer) 113b penetrating the 1-2 insulating layer 111b and electrically connecting the 1-2 wiring layer 112b and the 1-3 wiring layer 112c. Furthermore, cavity 110H can penetrate insulation layer 111a and insulation layer 111b.

[0081] Therefore, the number of layers in the core structure 110 is not particularly limited and can be formed into more layers depending on the design. If desired, the core structure 110 can be formed into more layers than shown in the figures. Further description of the substrate 100B, in which electronic components are embedded, according to another example, will be omitted.

[0082] Figure 19 This is a schematic cross-sectional view showing another example of a substrate in which electronic components are embedded.

[0083] Referring to the accompanying drawings, compared to the substrate 100A according to the above example in which electronic components are embedded, in the substrate 100C according to another example in which electronic components are embedded, a stacked structure 140 is further provided on the encapsulant 130. The stacked structure 140 includes: a second insulating body including a second insulating layer 141; one or more third wiring layers 142 disposed on or within the second insulating body; and one or more third via layers 143 disposed within the second insulating body. A second passivation layer 160 may be disposed on the stacked structure 140. The second passivation layer 160 may have a plurality of second openings 161 exposing at least a portion of the third wiring layers 142.

[0084] An insulating material can be used as the material for the second insulating layer 141. Thermosetting resins (such as epoxy resins) or thermoplastic resins (such as polyimide resins) can be used as the insulating material. Alternatively, insulating materials containing reinforcing materials (such as inorganic fillers (such as silica) and / or core materials (such as glass fibers)) can be used. For example, a prepreg can be used as the material for the second insulating layer 141, but it is not limited to this, and materials that do not contain reinforcing materials (such as glass fibers), such as ABF, can be used. Optionally, a photosensitive insulating material (such as a photosensitive dielectric (PID)) can be used.

[0085] A third wiring layer 142 may be disposed on the upper surface of the second insulating layer 141. The third wiring layer 142 may include a metallic material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. In an exemplary embodiment, the third wiring layer 142 may perform various functions. For example, the third wiring layer 142 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. Each pattern may have a line shape, a surface shape, or a pad shape. The third wiring layer 142 may be formed by processes such as addition process (AP), semi-AP (SAP), modified SAP (MSAP), and via sealing (TT), thus the third wiring layer 142 may include a seed layer (electroplated layer) and an electroplated layer formed based on the seed layer. When RCC is used as the material of the second insulating layer 141, a metal foil (such as copper foil) may also be included at the bottommost side, and a primer resin formed on the surface of the copper foil may also be included.

[0086] The third via layer 143 can penetrate the second insulating layer 141 and electrically connect the third wiring layer 142 to the second wiring layer 132. The third via layer 143 may include a metallic material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Depending on the design, the third via layer 143 may include connection vias for signal connections, connection vias for ground connections, connection vias for power connections, etc. Each wiring via in the third via layer 143 may be a via in which the via is filled with a metallic material, or a via in which a metallic material is formed along the wall surface of the via. For example, see reference... Figure 19 As shown in the cross-sectional view, each wiring via may have a tapered shape in which the width of the upper surface is greater than the width of the lower surface. The third via layer 143 may also be formed by a plating process (such as AP, SAP, MSAP, TT, etc.), and therefore, the third via layer 143 may include a seed layer (electroplated layer) and an electroplated layer formed based on the seed layer.

[0087] Therefore, the stacked structure 140 can be further disposed on the encapsulant 130, and the number of layers of the stacked structure 140 is not particularly limited, and can be formed into more layers according to the design. If desired, the stacked structure 140 can be formed into more layers than those shown in the figure. Further description of the substrate 100C according to another example in which electronic components are embedded will be omitted.

[0088] Figure 20 This is a schematic cross-sectional view showing another example of a substrate in which electronic components are embedded.

[0089] Referring to the accompanying drawings, compared with the substrate 100A in which electronic components are embedded according to the above example, in the substrate 100D in which electronic components are embedded according to another example, the core structure 110 is formed as more layers. For example, the core structure 110 may include: a 1-1 insulating layer 111a; a 1-1 wiring layer 112a embedded in the lower part of the 1-1 insulating layer 111a; a 1-2 wiring layer 112b disposed on the upper surface of the 1-1 insulating layer 111a; a 1-1 via layer 113a penetrating the 1-1 insulating layer 111a and electrically connecting the 1-1 wiring layer 112a and the 1-2 wiring layer 112b; a 1-2 insulating layer 111b disposed on the upper surface of the 1-1 insulating layer 111a and covering the 1-2 wiring layer 112b; a 1-3 wiring layer 112c disposed on the upper surface of the 1-2 insulating layer 111b; and a 1-2 via layer 113b penetrating the 1-2 insulating layer 111b and electrically connecting the 1-2 wiring layer 112b and the 1-3 wiring layer 112c. Furthermore, cavity 110H can penetrate insulation layer 111a and insulation layer 111b.

[0090] Furthermore, compared to the substrate 100A in which electronic components are embedded according to the above example, in the substrate 100D in which electronic components are embedded according to another example, a stacked structure 140 is further provided on the encapsulant 130. The stacked structure 140 includes: a second insulating body including a second insulating layer 141; one or more third wiring layers 142 disposed on or in the second insulating body; and one or more third via layers 143 disposed in the second insulating body. A second passivation layer 160 may be disposed on the stacked structure 140. The second passivation layer 160 may have a plurality of second openings 161 that expose at least a portion of the third wiring layers 142.

[0091] As described above, as one of the various effects of this disclosure, an electronic component embedded substrate (i.e., a substrate in which electronic components are embedded) with excellent heat dissipation effect can be provided.

[0092] As another effect of this disclosure, a substrate in which electronic components are embedded can be provided, which has excellent wiring design efficiency.

[0093] In exemplary embodiments, for ease of description, terms such as "side region," "side surface," etc., may be used to indicate a surface formed along a left / right direction; terms such as "lower side," "lower portion," "lower surface," etc., may be used to indicate a downward direction relative to the cross-section in the drawings; and terms such as "upper side," "upper portion," "upper surface," etc., may be used to indicate a direction opposite to the aforementioned directions (i.e., an upward direction relative to the cross-section in the drawings). The concept of an element disposed on a side region, upper side, upper portion, or lower portion may include configurations in which the element is in direct contact with a reference element in various directions, and configurations in which the element is not in direct contact with a reference element. For ease of description, these terms may be defined as above, and the scope of exemplary embodiments is not particularly limited by the above terms.

[0094] In exemplary embodiments, the term "connection" may refer not only to "direct connection" but also to "indirect connection" via adhesive layers or the like. Furthermore, the term "electrical connection" can include both cases where elements are "physically connected" and cases where elements are "not physically connected." Additionally, the terms "first," "second," etc., can be used to distinguish one element from another and do not limit the order and / or importance associated with the elements. In some cases, without departing from the scope of exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0095] In exemplary embodiments, the term "exemplary embodiment" may not refer to the same exemplary embodiment, but may be provided to describe and emphasize the distinct features of each exemplary embodiment. The exemplary embodiments presented above may be implemented without excluding the possibility of combining features with other exemplary embodiments. For example, unless otherwise stated, even if a feature described in one exemplary embodiment is not described in another exemplary embodiment, the description may be understood to be relevant to that other exemplary embodiment.

[0096] The terminology used in the exemplary embodiments is for descriptive purposes only and is not intended to limit this disclosure. Unless otherwise stated, singular terms also include plural forms.

[0097] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A substrate in which electronic components are embedded, comprising: A core structure includes a first insulating body, a plurality of first wiring layers, and one or more first via layers, the plurality of first wiring layers being disposed on and / or in the first insulating body, the one or more first via layers being disposed in the first insulating body, and the core structure having a cavity penetrating at least a portion of the first insulating body; A first metal layer is disposed on the bottom surface of the cavity; Electronic components are disposed on the first metal layer in the cavity; The second metal layer is spaced apart from the inner wall of the cavity and in physical contact with the side surface of the electronic component; as well as An insulating material is disposed between the inner wall of the cavity and the second metal layer.

2. The substrate with embedded electronic components according to claim 1, wherein, The first metal layer has patterned holes and includes a first metal pattern and a plurality of second metal patterns, the plurality of second metal patterns being spaced apart from each other through the patterned holes and surrounded by the first metal pattern.

3. The substrate in which electronic components are embedded according to claim 1, wherein, The second metal layer surrounds the side surface of the electronic component.

4. The substrate in which electronic components are embedded according to any one of claims 1-3, wherein, The second metal layer is in physical contact with the first metal layer.

5. The substrate in which electronic components are embedded according to claim 4, wherein, The first metal layer has a groove, and A portion of the second metal layer is disposed in the groove.

6. The substrate in which electronic components are embedded according to claim 5, wherein, The groove extends along the side surface of the electronic component.

7. The substrate in which an electronic component is embedded according to any one of claims 1-3, the substrate further comprising a first passivation layer disposed below the core structure, the first passivation layer having a plurality of first openings, the plurality of first openings exposing at least a portion of the lowermost first wiring layer and at least a portion of the first metal layer.

8. The substrate in which electronic components are embedded according to any one of claims 1-3, the substrate further comprising: An encapsulating agent is disposed on the core structure, disposed in at least a portion of the cavity, and at least a portion of the electronic component is embedded in the encapsulating agent; A second wiring layer is disposed on the encapsulant; as well as The second via layer penetrates the encapsulant and connects the second wiring layer to each of the plurality of first wiring layers and the electronic component. The encapsulating agent contains the insulating material.

9. The substrate of claim 8 in which electronic components are embedded, the substrate further comprising a second passivation layer disposed on the encapsulant and having a plurality of second openings that expose at least a portion of the second wiring layer.

10. The substrate in which electronic components are embedded according to claim 8, wherein the substrate further comprises: The stacked structure includes a second insulating body, one or more third wiring layers, and one or more third via layers, wherein the second insulating body is disposed on the encapsulant, the one or more third wiring layers are disposed on or in the second insulating body, and the one or more third via layers are disposed in the second insulating body; as well as A second passivation layer is disposed on the stacked structure and has a plurality of second openings that expose at least a portion of the uppermost third wiring layer among the one or more third wiring layers.

11. The substrate in which electronic components are embedded according to any one of claims 1-3, wherein, The electronic component has a first surface and a second surface, a connecting pad is disposed on the first surface, the second surface is opposite to the first surface, and the second surface is attached to the first metal layer by an adhesive film.

12. The substrate in which electronic components are embedded according to any one of claims 1-3, wherein, The first insulating body includes a first core insulating layer, the plurality of first wiring layers include a first core wiring layer and a second core wiring layer, the first via layer includes a first core via layer, the first core wiring layer is embedded in the lower part of the first core insulating layer, the second core wiring layer is disposed on the upper surface of the first core insulating layer, and the first core via layer penetrates the first core insulating layer and connects the first core wiring layer and the second core wiring layer. The cavity penetrates the first core insulating layer. The first metal layer is located at the same height as the first core wiring layer, and At least a portion of the first metal layer is embedded in the first core insulating layer.

13. The substrate in which electronic components are embedded according to claim 12, wherein, The first insulating body further includes a second core insulating layer, the plurality of first wiring layers further include a third core wiring layer, the first via layer further includes a second core via layer, the second core insulating layer is disposed on the upper surface of the first core insulating layer to cover the second core wiring layer, the third core wiring layer is disposed on the upper surface of the second core insulating layer, and the second core via layer penetrates the second core insulating layer and connects the second core wiring layer and the third core wiring layer. The cavity also penetrates the second core insulation layer.

14. The substrate in which electronic components are embedded according to claim 12, wherein, There is a first step between the lower surface of the first core insulating layer and the lower surface of the first core wiring layer, and The first metal layer has a second step between its upper surface in the region exposed through the cavity and its upper surface in the region embedded in the first core insulating layer.

15. A substrate in which electronic components are embedded, comprising: The core structure includes a core insulating layer, a first core wiring layer, a second core wiring layer, and a core via layer. The first core wiring layer is embedded in the lower part of the core insulating layer, the second core wiring layer is disposed on the upper surface of the core insulating layer, and the core via layer penetrates the core insulating layer and connects the first core wiring layer and the second core wiring layer. The core structure has a cavity that penetrates the core insulating layer. A metal layer is disposed on the bottom surface of the cavity and has patterned holes; as well as Electronic components are disposed on the metal layer within the cavity. The metal layer is located at the same height as the first core wiring layer, and at least a portion of the metal layer is embedded in the core insulation layer.

16. The substrate in which electronic components are embedded according to claim 15, wherein, The metal layer comprises a plurality of metal patterns spaced apart from each other through the patterned holes. At least a portion of the plurality of metal patterns are connected to at least one ground pattern in the first core wiring layer and the second core wiring layer, and At least one of the remaining metal patterns in the plurality of metal patterns is connected to at least one signal pattern in the first core wiring layer and the second core wiring layer.

17. A substrate, comprising: The core structure has a cavity and includes an insulating body, one or more first wiring layers and one or more via layers, wherein the one or more first wiring layers are disposed on and / or in the insulating body, and the one or more via layers are disposed in the insulating body and connected to the one or more first wiring layers; A first metal layer is disposed on or within the insulating body; Electronic components are disposed on the first metal layer in the cavity; as well as A second metal layer extends from the first metal layer to contact the side surface of the electronic component. The first metal layer has a groove, and a portion of the second metal layer is disposed in the groove.

18. The substrate according to claim 17, wherein, The second metal layer covers the side surface of the electronic component.

19. The substrate of claim 17, further comprising an encapsulating agent comprising an insulating material, the encapsulating agent being disposed on the core structure and having a portion disposed in the cavity such that at least a portion of the electronic component is embedded in the encapsulating agent. in, The portion of the encapsulant disposed in the cavity is located between the second metal layer and the core structure.

20. The substrate according to any one of claims 17-19, wherein, The first metal layer comprises a plurality of metal patterns spaced apart from each other.

21. The substrate according to claim 17 or 18, wherein, The electronic component has a first surface on which a connection pad is disposed and a second surface opposite to the first surface. The second surface faces the first metal layer, and The substrate further includes: An encapsulating agent is disposed on the core structure; A second wiring layer is disposed on the encapsulating agent; and A second via layer is disposed in the encapsulant and connects the second wiring layer to at least one of the one or more first wiring layers and / or the connection pad.

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