Semiconductor device and method of manufacturing the same

Abstract

This invention relates to the field of storage technology and proposes a semiconductor device and its fabrication method. The semiconductor device includes a substrate and a plurality of conductors. The plurality of conductors are used to form a first electrode of a capacitor structure, and the plurality of conductors are distributed in rows and columns on one side of the substrate. Each conductor includes a cylindrical body and a plurality of annular protrusions. The axial direction of the cylindrical body intersects the substrate; the annular protrusions are arranged circumferentially around the cylindrical body, and the protrusion direction of the annular protrusions is parallel to the substrate. The plurality of annular protrusions are spaced apart along the axial direction of the cylindrical body; wherein, the annular protrusions of adjacent conductors in the row and column direction are staggered in the direction perpendicular to the substrate. This semiconductor device can integrate a large number of capacitor structures in a small space, or integrate capacitor structures with large capacitance values ​​with the same size and number of capacitor structures.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Memory typically consists of multiple memory cells, each containing a capacitor structure capable of storing logic "1" or "0". However, due to limitations such as photolithography processes, memory can only form a limited number of capacitor structures within a finite size, or only capacitor structures with small capacitance values.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which can form only a few capacitor structures or only capacitor structures with small capacitance values ​​within a limited size.

[0005] Other features and advantages of the invention will become apparent from the following detailed description, or may be learned distinctly by practice of the invention.

[0006] According to one aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising a plurality of capacitor structures, the semiconductor device further comprising: a substrate and a plurality of conductors. The plurality of conductors are used to form first electrodes of the capacitor structures, and the plurality of conductors are arranged in rows and columns on one side of the substrate. Each conductor comprises: a cylindrical body and a plurality of annular protrusions. The axial direction of the cylindrical body intersects the substrate; the annular protrusions are circumferentially disposed around the cylindrical body, and the plurality of annular protrusions are spaced apart along the axial direction of the cylindrical body; wherein the annular protrusions of adjacent conductors in the row and column direction are staggered in a direction perpendicular to the substrate.

[0007] In one exemplary embodiment of this disclosure, the annular protrusions of adjacent conductors at least partially overlap in their orthographic projections onto the substrate.

[0008] In one exemplary embodiment of this disclosure, each of the conductors is used to form a first electrode of one of the capacitor structures.

[0009] In one exemplary embodiment of this disclosure, a plurality of the conductors are used to form a first electrode of the capacitor structure.

[0010] In one exemplary embodiment of this disclosure, the semiconductor device further includes an electrical connection layer located between the substrate and the conductors, for electrically connecting a plurality of the conductors in one or more of the capacitor structures.

[0011] In one exemplary embodiment of this disclosure, the semiconductor device further includes: a first dielectric layer and a first conductive layer. The first dielectric layer covers the conductor; the first conductive layer is located on the side of the first dielectric layer opposite to the substrate and covers the first dielectric layer, serving to form the second electrode of the capacitor structure.

[0012] In one exemplary embodiment of this disclosure, the semiconductor device further includes an electrode connection layer disposed on the side of the first conductive layer away from the substrate and covering the first conductive layer.

[0013] In one exemplary embodiment of this disclosure, in the conductor, each of the annular protrusions has the same or different protrusion dimensions along a direction perpendicular to the side surface of the cylindrical body.

[0014] In one exemplary embodiment of this disclosure, the material of the conductor includes one or more of the following: tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polycrystalline silicon, and P-type polycrystalline silicon.

[0015] According to one aspect of the present invention, a method for fabricating a semiconductor device is provided, the semiconductor device comprising a plurality of capacitor structures, the method comprising:

[0016] Provide a substrate;

[0017] A composite layer is formed on the substrate, the composite layer comprising a first material layer and a second material layer that are alternately stacked in sequence;

[0018] Multiple through holes distributed in rows and columns are formed on the composite layer. The multiple through holes include multiple first through holes and multiple second through holes. Each first through hole is adjacent to only a second through hole in the row and column direction, and each second through hole is adjacent to only a first through hole in the row and column direction.

[0019] A first etching solution is injected into the first through hole. The etching rate of the first etching solution on the first material layer is greater than that on the second material layer, thereby forming an annular groove on the sidewall of the first through hole located in the first material layer.

[0020] A second etching solution is injected into the second through hole. The etching rate of the second etching solution on the second material layer is greater than that of the second etching solution on the first material layer, thereby forming an annular groove on the side wall of the second through hole located in the second material layer.

[0021] The through-holes are filled with conductive material to form a conductor within each through-hole, the conductor serving to form the first electrode of the capacitor structure.

[0022] In one exemplary embodiment of this disclosure, the annular grooves in adjacent through-holes in the row and column directions at least partially overlap in their orthographic projection onto the substrate.

[0023] In one exemplary embodiment of this disclosure, the material of the first material layer is silicon dioxide, the material of the second material layer is silicon nitride, the first etching solution is hydrofluoric acid, and the second etching solution is phosphoric acid.

[0024] In one exemplary embodiment of this disclosure, the through-hole is filled with a conductive material, and then the process further includes:

[0025] Remove the first material layer and the second material layer;

[0026] A first dielectric layer is formed on the surface of each of the conductors;

[0027] A first conductive layer is formed on the side of the first dielectric layer away from the substrate, the first conductive layer covering the first dielectric layer, and the first conductive layer is used to form the second electrode of the capacitor structure.

[0028] In one exemplary embodiment of this disclosure, the semiconductor device fabrication method further includes:

[0029] A third conductive layer is formed between the substrate and the composite layer;

[0030] The third conductive layer is patterned to form multiple independent connection structures, which are used to electrically connect multiple conductors in one or more of the capacitor structures.

[0031] In one exemplary embodiment of this disclosure, before forming a plurality of through-holes distributed through the composite layer, the method further includes:

[0032] Each of the first material layer and each of the second material layers is doped with ions of a preset concentration to adjust the etching rate of the first material layer or the second material layer.

[0033] In one exemplary embodiment of this disclosure, a first through hole is first formed on the composite layer, and an annular groove is formed on the side wall of the first through hole located on the first material layer, and then a second through hole penetrating the composite layer is formed on the composite layer.

[0034] Furthermore, after the first through-hole forms an annular groove on the sidewall of the first material layer, and before the second through-hole penetrating the composite layer is formed on the composite layer, the method further includes:

[0035] Sacrificial material is injected into the first through hole.

[0036] In one exemplary embodiment of this disclosure, the second through hole is first filled with conductive material, and then the first through hole is filled with conductive material.

[0037] After filling the second through-hole with conductive material, the process further includes:

[0038] Remove the sacrificial material.

[0039] This disclosure provides a semiconductor device and a method for fabricating the same. The semiconductor device includes multiple capacitor structures and further includes a substrate and multiple conductors. The multiple conductors form first electrodes of the capacitor structures, and the multiple conductors are arranged in rows and columns on one side of the substrate. Each conductor includes a cylindrical body and multiple annular protrusions. The axial direction of the cylindrical body extends along a first direction, which intersects the substrate. The annular protrusions are circumferentially arranged around the cylindrical body and protrude in a direction perpendicular to the side surface of the cylindrical body. The multiple annular protrusions are spaced apart along the axial direction of the cylindrical body. In the row and column direction, the annular protrusions of adjacent conductors are staggered in the first direction, and the annular protrusions of adjacent conductors at least partially overlap in their orthogonal projection onto the substrate. This semiconductor device can integrate a large number of capacitor structures in a small space, or integrate capacitor structures with larger capacitance values ​​while having the same size and number of capacitor structures.

[0040] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0041] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0042] Figure 1-5 This is a schematic diagram of the structure of each stage in the semiconductor device manufacturing process in related technologies;

[0043] Figure 6 This is a top view of a semiconductor device in the relevant technology;

[0044] Figure 7 This is a cross-sectional view of a semiconductor device semi-finished product along the row / column direction in an exemplary embodiment of this disclosure;

[0045] Figure 8 This is a top view of a semiconductor device semi-finished product in an exemplary embodiment of this disclosure;

[0046] Figure 9 This is a cross-sectional view of a semiconductor device semi-finished product along the row / column direction in an exemplary embodiment of this disclosure;

[0047] Figure 10 This is a cross-sectional view of a semiconductor device semi-finished product along the row / column direction in an exemplary embodiment of this disclosure;

[0048] Figure 11 This is a top view of a semiconductor device semi-finished product in an exemplary embodiment of this disclosure;

[0049] Figure 12a This is a cross-sectional view of a semiconductor device semi-finished product along the row / column direction in an exemplary embodiment of this disclosure;

[0050] Figure 12b This is a cross-sectional view of a semiconductor device semi-finished product along the row / column direction in another exemplary embodiment of this disclosure;

[0051] Figure 13 This is a cross-sectional view of a semiconductor device semi-finished product along the row / column direction in another exemplary embodiment of this disclosure;

[0052] Figure 14 This is a top view of a semiconductor device semi-finished product in another exemplary embodiment of this disclosure;

[0053] Figure 15 This is a cross-sectional view of a semiconductor device semi-finished product along the row / column direction in another exemplary embodiment of this disclosure;

[0054] Figure 16 This is a cross-sectional view of a semiconductor device semi-finished product along the row / column direction in another exemplary embodiment of this disclosure;

[0055] Figure 17 This is a cross-sectional view of a semiconductor device semi-finished product along the row / column direction in another exemplary embodiment of this disclosure;

[0056] Figure 18 This is a cross-sectional view of a semiconductor device semi-finished product along the row / column direction in another exemplary embodiment of this disclosure;

[0057] Figure 19 This is a cross-sectional view along the row / column direction in an exemplary embodiment of the semiconductor device disclosed herein;

[0058] Figure 20 This is a top view of an exemplary embodiment of the semiconductor device disclosed herein;

[0059] Figure 21This is a cross-sectional view along the row / column direction in an exemplary embodiment of the semiconductor device disclosed herein;

[0060] Figure 22 This is a cross-sectional view along the row / column direction in an exemplary embodiment of the semiconductor device disclosed herein. Detailed Implementation

[0061] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the invention will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0062] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the icon's arrangement is flipped so that it is upside down, the component described as "up" will become the component described as "down." Other relative terms such as "high," "low," "top," "bottom," "left," and "right" also have similar meanings. When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0063] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0064] In related technologies, semiconductor devices typically consist of multiple memory cells, each including a capacitor structure, and each capacitor structure is capable of storing logic "1" or "0". Related technologies propose a semiconductor device manufacturing method, such as... Figure 1-5 The diagram shown illustrates the structural details of each stage in the semiconductor device manufacturing process in related technologies. Figure 1 As shown, the semiconductor device fabrication method provided by the related technology includes: forming multiple alternating layers of first material layer 2 and second material layer 3 on a substrate 1, and forming multiple arrays of through holes 4 on the first material layer 2 and second material layer 3 through an etching process. Figure 2 As shown, etching solution is injected into the through-hole 4. The etching rate of this etching solution on the second material layer 3 is greater than that on the first material layer 2, thereby forming an annular groove 5 on the inner wall of the through-hole 4 at the location of the second material layer. Figure 3 As shown, conductive material is filled into the through hole 4 and the groove 5 to form a conductive body 6. The conductive body 6 includes a cylindrical body 61 filled in the through hole 4 and an annular protrusion 62 filled in the groove 5. Figure 4 As shown, multiple layers of first material layer 2 and second material layer 3 are removed. The conductor 6 can serve as the first electrode of the capacitor structure. Furthermore, as... Figure 5 As shown, the fabrication method may further include forming a dielectric layer 7 on the surface of the conductor 6, and forming a conductive layer 8 on the side of the dielectric layer 7 facing away from the substrate 1. The conductive layer 8 can form the second electrode of the capacitor structure. Each conductor 6 can form a capacitor structure with the conductive layer 8. It should be understood that multiple conductors 6 can also be electrically connected to each other, thereby forming a capacitor structure with the conductive layer 8. Figure 6 As shown, this is a top view of a semiconductor device in the related art. When etching the annular groove 5, to prevent adjacent annular grooves 5 from connecting along the row and column direction, a large distance needs to be reserved between adjacent vias 4 along the row and column direction, thus ensuring a certain distance S between adjacent grooves 5 along the row and column direction. In the related art, because adjacent grooves 5 have a certain distance S, the integration density of the capacitor structure in the semiconductor device is low; that is, the semiconductor device can only form a limited number of capacitor structures within a finite size.

[0065] Based on this, this exemplary embodiment provides a method for fabricating a semiconductor device, the semiconductor device including a plurality of capacitor structures, the method comprising:

[0066] Step S1: Provide a substrate;

[0067] Step S2: A composite layer is formed on the substrate, the composite layer comprising a first material layer and a second material layer that are alternately stacked in sequence;

[0068] Step S3: Form a plurality of through holes distributed in rows and columns through the composite layer. The plurality of through holes includes a plurality of first through holes and a plurality of second through holes. Each first through hole is adjacent to a second through hole in the row and column direction, and each second through hole is adjacent to a first through hole in the row and column direction.

[0069] Step S4: Inject the first etching solution into the first through hole. The etching rate of the first etching solution on the first material layer is greater than the etching rate of the first etching solution on the second material layer, thereby forming an annular groove on the side wall of the first through hole located on the first material layer.

[0070] Step S5: Inject a second etching solution into the second through hole. The etching rate of the second etching solution on the second material layer is greater than the etching rate of the second etching solution on the first material layer, thereby forming an annular groove on the sidewall of the second through hole located in the second material layer.

[0071] Step S6: Fill the through holes with conductive material to form a conductor in each through hole, the conductor being used to form the first electrode of the capacitor structure.

[0072] The following is a detailed explanation of the above steps:

[0073] like Figure 7 The image shows a cross-sectional view of a semiconductor device semi-finished product along a row / column direction in an exemplary embodiment of this disclosure. Step S1 includes providing a substrate 1. Step S2 includes applying a composite layer 2 to the substrate 1. The composite layer 2 may include a first material layer 21 and a second material layer 22 alternately stacked in sequence. The first material layer 21 and the second material layer 22 may each be multiple layers, and the number of layers in the first material layer 21 and the second material layer 22 may be the same or different. The bottom layer of the composite layer 2 facing the substrate may be either the first material layer 21 or the second material layer 22. Figure 7 , 8 As shown, Figure 8 This is a top view of a semiconductor device semi-finished product according to an exemplary embodiment of the present disclosure. Step S3 includes forming a plurality of through-holes distributed through the composite layer 2. The plurality of through-holes may include a plurality of first through-holes 31 and a plurality of second through-holes 32. Each first through-hole 31 is adjacent to a second through-hole 32 in the row and column direction, and each second through-hole 32 is adjacent to a first through-hole 31 in the row and column direction. The row direction can be X, and the column direction can be Y. The first through-holes 31 and the second through-holes 32 can be cylindrical through-holes, and their opening sizes can be the same. The through-holes can be formed by dry etching, plasma etching, or wet etching. To make the opening sizes of the through-holes similar in the stacking direction of the composite layer 2, the etching process of the through-holes can preferably be dry etching or plasma etching.

[0074] like Figure 9The diagram shows a cross-sectional view of a semiconductor device semi-finished product along a row / column direction in an exemplary embodiment of this disclosure. Step S4 includes injecting a first etching solution into a first through-hole 31, wherein the etching rate of the first etching solution on the first material layer is greater than the etching rate of the first etching solution on the second material layer, thereby forming an annular groove 41 on the sidewall of the first through-hole located on the first material layer. Step S5 includes injecting a second etching solution into a second through-hole 32, wherein the etching rate of the second etching solution on the second material layer is greater than the etching rate of the second etching solution on the first material layer, thereby forming an annular groove 42 on the sidewall of the second through-hole located on the second material layer. In this exemplary embodiment, the material of the first material layer may be silicon dioxide, and the material of the second material layer may be silicon nitride; the first etching solution may be hydrofluoric acid, and the second etching solution may be phosphoric acid. It should be understood that in other exemplary embodiments, the first material layer and the second material layer may also be composed of other materials, and correspondingly, the first etching solution and the second etching solution may also be other etching solutions.

[0075] like Figure 10 The image shown is a cross-sectional view along the row / column direction of a semiconductor device semi-finished product in an exemplary embodiment of this disclosure. Step S6 includes filling the through-hole with a conductive material. The conductive material can fill the entire through-hole and the groove to form a conductor 5 in each through-hole. Each conductor 5 can be used to form the first electrode of the capacitor structure. The conductor 5 may include a cylindrical body 51 filled in the through-hole and an annular protrusion 52 filled in the annular groove. The material of the conductor may include one or more of the following: tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polycrystalline silicon, and P-type polycrystalline silicon.

[0076] like Figure 11 The image shown is a top view of a semiconductor device semi-finished product according to an exemplary embodiment of this disclosure. (Comparison) Figure 6 , Figure 11 It can be seen that even Figure 11 In the middle, the distance between the orthographic projections of adjacent annular protrusions 52 along the row and column directions (row direction X, column direction Y) on the substrate is small, but according to Figure 10 It can be seen that there is a large reserved space between adjacent annular protrusions 52 along the row and column direction. That is, in this exemplary embodiment, when etching the annular grooves 41 and 42, a safe distance is reserved between the annular grooves 41 and 42 to prevent etching through. Obviously, according to Figure 11 As can be seen, the semiconductor device provided in this exemplary embodiment, by staggering the annular protrusions of adjacent conductors in the row and column directions in the direction perpendicular to the substrate, allows for the integration of more capacitor structures within a limited space. Furthermore, the annular protrusions can increase the surface area of ​​the first electrode, thereby increasing the capacitance value of the capacitor structure.

[0077] like Figure 12a The image shown is a cross-sectional view along the row / column direction of a semiconductor device semi-finished product according to an exemplary embodiment of this disclosure. The fabrication method may further include removing a first material layer 21 and a second material layer 22. This removal can be achieved by alternating etching with a first etching solution and a second etching solution. The fabrication method may also include forming a first dielectric layer 61 on the surface of a conductor 5, the first dielectric layer 61 covering the conductor 5; and forming a first conductive layer 71 on the side of the first dielectric layer 61 facing away from the substrate 1, the first conductive layer 71 covering the first dielectric layer 61. The first conductive layer 71 can be used to form the second electrode of the capacitor structure. The first conductive layer 71 can be formed by a coating process, thereby forming a horizontal film layer on its upper surface. Multiple capacitor structures in this semiconductor device can share the first conductive layer 71 as a common electrode.

[0078] like Figure 12b The diagram shows a cross-sectional view of a semiconductor device semi-finished product along a row / column direction in another exemplary embodiment of this disclosure. The fabrication method may include forming a first dielectric layer 61 on the surface of a conductor 5, the first dielectric layer 61 covering the conductor 5; and forming a first conductive layer 71 on the side of the first dielectric layer 61 facing away from the substrate 1, the first conductive layer 71 covering the first dielectric layer 61. The first conductive layer 71 can be formed by a vapor deposition process, thereby forming a film layer with the same shape as the outer surface of the first dielectric layer 61. The semiconductor device may further include an electrode connection layer 10, the electrode connection layer 10 being disposed on the side of the first conductive layer facing away from the substrate and covering the first conductive layer.

[0079] In one exemplary embodiment of this disclosure, such as Figure 13 , 14 As shown, Figure 13 This is a cross-sectional view of a semiconductor device semi-finished product along the row / column direction in another exemplary embodiment of this disclosure. Figure 14 This is a top view of a semiconductor device semi-finished product in another exemplary embodiment of this disclosure. In step S4: forming an annular groove 41 on the sidewall of the first through-hole 31, and in step S5: forming an annular groove 42 on the sidewall of the second through-hole 32, the orthographic projections of the annular grooves 41 and 42 within adjacent through-holes 31 and 32 in the row and column directions (row direction X, column direction Y) onto the substrate 1 can at least partially overlap. This arrangement can further increase the number of capacitor structures integrated within a limited space.

[0080] In one exemplary embodiment of this disclosure, a plurality of the conductors can be used to form a first electrode of one of the capacitor structures. Accordingly, as Figure 15The image shown is a cross-sectional view along the row / column direction of a semiconductor device semi-finished product in another exemplary embodiment of this disclosure. The semiconductor device fabrication method may further include: forming a third conductive layer between the substrate 1 and the composite layer 2, and performing a patterning process on the third conductive layer to form a plurality of independent connection structures 81, the connection structures 81 being used to electrically connect a plurality of conductors 5 in a capacitor structure. Figure 15 As shown, two conductors 5 are connected by a connection structure 81 to form the first electrode of a capacitor structure. It should be understood that in other exemplary embodiments, a connection structure 81 may also be connected to a number of other conductors 5, thereby allowing multiple conductors to form the first electrode of a capacitor structure. It should be noted that the connection structure 81 may also be connected to only one conductor 5 for connecting the conductor 5 to other layer structures (e.g., the source and drain layers of a transistor).

[0081] In this exemplary embodiment, before forming a plurality of through-holes distributed through the composite layer, the process may further include: performing ion doping on each of the first material layer and each of the second material layer at a preset concentration to adjust the etching rate of the first material layer or the second material layer. The doping ions may be boron or phosphorus.

[0082] In this exemplary embodiment, as Figure 7 As shown, after forming through-holes in composite layer 2, the rigidity of the semiconductor device semi-finished product decreases, making it susceptible to damage from external forces during subsequent processing. In an exemplary embodiment of this disclosure, as... Figure 16 The image shown is a cross-sectional view along the row / column direction of a semiconductor device semi-finished product in another exemplary embodiment of this disclosure. The semiconductor device fabrication method may first form a first through-hole 31 on the composite layer, and simultaneously form an annular groove 41 on the sidewall of the first through-hole located in the first material layer. As shown... Figure 17 The image shown is a cross-sectional view along the row / column direction of a semiconductor device semi-finished product in another exemplary embodiment of this disclosure. Then, sacrificial material 9 can be injected into the first through-hole 31 to fill the first through-hole 31 and the annular groove 41. This sacrificial material can increase the rigidity of the semiconductor device semi-finished product. The sacrificial material can be BPSG, silicon oxide, etc. Then, as... Figure 18The diagram shows a cross-sectional view of a semiconductor device semi-finished product along a row / column direction in another exemplary embodiment of this disclosure. A second through-hole 32 penetrating the composite layer can be formed on the composite layer, and an annular groove 42 can be formed on the sidewall of the second through-hole located in the second material layer using an etching process. Then, conductive material can be injected into the second through-hole 32 to fill the second through-hole 32 and the annular groove 42, thereby forming a conductor. Then, sacrificial material is removed to inject conductive material into the first through-hole 31 to fill the first through-hole 31 and the annular groove 41, thereby forming a conductor.

[0083] This disclosure also provides a semiconductor device that can be formed by the above-described semiconductor device fabrication method, such as... Figure 19 , 20 As shown, Figure 19 This is a cross-sectional view along the row / column direction in an exemplary embodiment of the semiconductor device disclosed herein. Figure 20 This is a top view of an exemplary embodiment of the semiconductor device disclosed herein. The semiconductor device includes multiple capacitor structures and further includes a substrate 1 and multiple conductors 5. The multiple conductors 5 are used to form the first electrodes of the capacitor structures, and the multiple conductors 5 are distributed in rows and columns on one side of the substrate 1. Each conductor 5 includes a cylindrical body 51 and multiple annular protrusions 52. The axial direction Z of the cylindrical body 51 may be perpendicular to the substrate 1; the annular protrusions 52 may be arranged circumferentially around the cylindrical body 51, and the protrusion direction of the annular protrusions 51 may be parallel to the substrate. The multiple annular protrusions 52 may be spaced apart along the axial direction of the cylindrical body 51; wherein, in the row and column directions (row direction X, column direction Y), the annular protrusions of adjacent conductors may be staggered in the direction perpendicular to the substrate. The axial direction of the cylindrical body 51 may also intersect the substrate at other angles. The cylindrical body may be cylindrical.

[0084] The semiconductor device provided in this exemplary embodiment allows for the integration of more capacitor structures within a limited space by staggering the annular protrusions of adjacent conductors in the row and column directions in a direction perpendicular to the substrate. Furthermore, the annular protrusions can increase the surface area of ​​the first electrode, thereby increasing the capacitance value of the capacitor structure.

[0085] In this exemplary embodiment, as Figure 19 , 20 As shown, the annular protrusions 52 of adjacent conductors can at least partially overlap in their orthogonal projection onto the substrate. This arrangement can further increase the number of capacitor structures integrated within a limited space.

[0086] In this exemplary embodiment, as Figure 21The diagram shows a cross-sectional view along a row / column direction in an exemplary embodiment of the semiconductor device disclosed herein. Each of the conductors can be used to form a first electrode of the capacitor structure. The semiconductor device may further include a first dielectric layer 61 and a first conductive layer 71. The first dielectric layer 61 covers the conductors 5; the first conductive layer 71 is located on the side of the first dielectric layer 61 facing away from the substrate 1 and covers the first dielectric layer 71, serving to form a second electrode of the capacitor structure.

[0087] In one exemplary embodiment of this disclosure, such as Figure 22 The diagram shows a cross-sectional view along a row / column direction in an exemplary embodiment of the semiconductor device disclosed herein. Multiple conductors 5 can be used to form a first electrode of the capacitor structure. The semiconductor device may further include an electrical connection layer 81 located between the substrate 1 and the conductors 5, for electrically connecting the multiple conductors in the capacitor structure. Similarly, the semiconductor device may further include a second dielectric layer 62 and a second conductive layer 72. The second dielectric layer 62 covers the conductors 5 and the electrical connection layer 81; the second conductive layer 72 is located on the side of the dielectric layer 62 facing away from the substrate and covers the second dielectric layer 62, for forming a second electrode of the capacitor structure. It should be noted that the electrical connection layer 81 may also be connected to only one conductor 5, for connecting the conductor 5 to other layer structures (e.g., the source / drain layer of a transistor).

[0088] In this exemplary embodiment, in the conductor, the size of each of the annular protrusions along the direction perpendicular to the side of the cylindrical body may be the same or different.

[0089] In this exemplary embodiment, the material of the conductor may include one or more of the following: tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polycrystalline silicon, and P-type polycrystalline silicon.

[0090] It should be understood that, in other exemplary embodiments, the semiconductor device may also include other components integrated between the substrate and the conductor 5, such as transistors.

[0091] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the generality of this disclosure and include, but are not disclosed herein, common knowledge or customary techniques in the art. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0092] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A semiconductor device comprising a plurality of capacitor structures, characterized in that, include: Substrate; A plurality of conductors are provided for forming the first electrode of the capacitor structure. The plurality of conductors are arranged in rows and columns on one side of the substrate, and each conductor comprises: A cylindrical body, the axial direction of which intersects with the substrate; Multiple annular protrusions are arranged around the circumference of the cylindrical body, and the multiple annular protrusions are spaced apart along the axial direction of the cylindrical body. In this configuration, the annular protrusions of adjacent conductors in the row and column direction are staggered in the direction perpendicular to the substrate; and the plurality of conductors are formed by the following steps: A composite layer is formed on the substrate, the composite layer comprising a first material layer and a second material layer that are alternately stacked in sequence; Multiple through-holes distributed in rows and columns are formed on the composite layer, the multiple through-holes including multiple first through-holes and multiple second through-holes, each first through-hole being adjacent to a second through-hole in the row and column direction, and each second through-hole being adjacent to a first through-hole in the row and column direction; A first etching solution is injected into the first through hole. The etching rate of the first etching solution on the first material layer is greater than that on the second material layer, thereby forming an annular groove on the sidewall of the first through hole located in the first material layer. A second etching solution is injected into the second through hole. The etching rate of the second etching solution on the second material layer is greater than that of the second etching solution on the first material layer, thereby forming an annular groove on the side wall of the second through hole located in the second material layer. The through-holes are filled with conductive material to form the conductor within each through-hole.

2. The semiconductor device according to claim 1, characterized in that, The annular protrusions of adjacent conductors in the row and column directions at least partially overlap in their orthogonal projection onto the substrate.

3. The semiconductor device according to claim 1 or 2, characterized in that, The semiconductor device further includes: A first dielectric layer covers the conductor; A first conductive layer covers the first dielectric layer and is used to form the second electrode of the capacitor structure.

4. The semiconductor device according to claim 1 or 2, characterized in that, The semiconductor device further includes: An electrical connection layer, located between the substrate and the conductor, is used to electrically connect one or more of the conductors.

5. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes: An electrode connection layer is disposed on the side of the first conductive layer opposite to the substrate and covers the first conductive layer.

6. A method for fabricating a semiconductor device, the semiconductor device comprising a plurality of capacitor structures, characterized in that, include: Provide substrate; A composite layer is formed on the substrate, the composite layer comprising a first material layer and a second material layer that are alternately stacked in sequence; Multiple through-holes distributed in rows and columns are formed on the composite layer, the multiple through-holes including multiple first through-holes and multiple second through-holes, each first through-hole being adjacent to a second through-hole in the row and column direction, and each second through-hole being adjacent to a first through-hole in the row and column direction; A first etching solution is injected into the first through hole. The etching rate of the first etching solution on the first material layer is greater than that on the second material layer, thereby forming an annular groove on the sidewall of the first through hole located in the first material layer. A second etching solution is injected into the second through hole. The etching rate of the second etching solution on the second material layer is greater than that of the second etching solution on the first material layer, thereby forming an annular groove on the side wall of the second through hole located in the second material layer. The through-holes are filled with conductive material to form a conductor within each through-hole, the conductor serving to form the first electrode of the capacitor structure.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, The first material layer is made of silicon dioxide, and the second material layer is made of silicon nitride. The first etching solution is hydrofluoric acid, and the second etching solution is phosphoric acid.

8. The method for fabricating a semiconductor device according to claim 6 or 7, characterized in that, The process further includes filling the through-hole with conductive material, and then: Remove the first material layer and the second material layer; A first dielectric layer is formed on the surface of each of the conductors; A first conductive layer is formed on the side of the first dielectric layer away from the substrate, the first conductive layer covering the first dielectric layer, and the first conductive layer is used to form the second electrode of the capacitor structure.

9. The method for fabricating a semiconductor device according to claim 6 or 7, characterized in that, The semiconductor device fabrication method further includes: A third conductive layer is formed between the substrate and the composite layer; The third conductive layer is patterned to form multiple separate connection structures, which are used to electrically connect one or more of the conductors in the capacitor structure.

10. The method for fabricating a semiconductor device according to claim 6 or 7, characterized in that, The composite layer is formed with a plurality of through-holes distributed in rows and columns, and the process further includes: Each of the first material layer and each of the second material layers is doped with ions of a preset concentration to adjust the etching rate of the first material layer or the second material layer.

11. The method for fabricating a semiconductor device according to claim 6 or 7, characterized in that, First, a first through hole is formed on the composite layer, and an annular groove is formed on the side wall of the first through hole located on the first material layer. Then, a second through hole is formed on the composite layer that penetrates the composite layer. Furthermore, after the first through-hole forms an annular groove on the sidewall of the first material layer, and before the second through-hole penetrating the composite layer is formed on the composite layer, the method further includes: Sacrificial material is injected into the first through hole.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, First, fill the second through hole with conductive material, and then fill the first through hole with conductive material. After filling the second through-hole with conductive material, the process further includes: Remove the sacrificial material.

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