NAND type flash memory and manufacturing method thereof

Abstract

The present invention provides a NAND type flash memory and a manufacturing method thereof that can reduce the planar size of a memory cell. The three-dimensional NAND type flash memory of the present invention comprises: a substrate, an insulating layer, a lower conductive layer (source), a three-dimensional memory cell structure, and a bit line. The memory cell structure comprises: a plurality of strip-shaped gate stacks, including a stack of insulators and conductors stacked in a vertical direction from the substrate; and a plurality of channel stacks, which are separately arranged along one of the side surfaces of the gate stack. The upper end of the channel stack is electrically connected to the orthogonal bit line, and the lower end of the channel stack is electrically connected to the lower conductive layer.

Description

Technical Field

[0001] The present invention relates to a NAND type flash memory, and in particular to a three-dimensional NAND type flash memory and a manufacturing method thereof. Background Art

[0002] In recent years, in order to improve the integration of memory cells, NAND flash memories with a three-dimensional structure in which memory cells are stacked vertically have been put into practical use. For example, memory cells are formed using semiconductor pillars extending vertically from a substrate (Patent Document 1).

[0003] In addition, in non-patent document 1, Figure 1 As shown, a plurality of rectangular gates are stacked on a substrate, and an insulator including a charge storage layer (e.g., a silicon nitride layer) and a thin film channel are formed vertically along the ends of the gates in a vertical direction. The thin film channel includes polysilicon and has a U-shaped shape. A NAND string includes a U-shaped thin film channel, an insulator including a charge storage layer, and a gate. One upper end of the thin film channel is connected to a local source line via a plug, and the other upper end is connected to a bit line via a plug. Figure 2A Cut along the horizontal direction Figure 1 A cross-sectional view of a thin film channel of a flash memory. Figure 2B This is a cross-sectional view when the thin film channel is cut vertically. Figure 2A The black oval portion shown is a hole formed by etching, and the hole is an insulating region for insulating the thin film channel formed along the multi-gate. The spacing is 100 nm. In addition, the spacing between adjacent multi-gates is 220 nm.

[0004] [Prior art literature]

[0005] [Patent Document]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2015-176870

[0007] [Non-patent document 1] A Novel Double-density, Single-Gate Vertical Channel (SGVC) 3D NAND Flash That Is Tolerant to Deep Vertical Etching CD Variation and Process Robust Read-disturb Immunity, Hang-Ting Lue et al, IEEEInternational Electron Devices Meeting (IEDM) 15-44, P321-324 Summary of the invention

[0008] [Problems to be solved by the invention]

[0009] An object of the present invention is to provide a NAND type flash memory and a method for manufacturing the same which can reduce the planar size of a memory cell compared with the related art.

[0010] [Technical means to solve the problem]

[0011] The three-dimensional structure of the NAND flash memory of the present invention includes: a substrate; a lower conductive layer formed in or on the substrate; a plurality of stacks extending along a first direction on the lower conductive layer, and the plurality of stacks respectively include stacks of insulators and conductors stacked in a vertical direction from the substrate; a plurality of channel stacks separately arranged along one of the side surfaces of the plurality of stacks, and the plurality of channel stacks respectively include an insulating layer including a charge storage layer and a channel film, the insulating layer and the channel film extending in a vertical direction from the substrate, and the lower end of the channel film being electrically connected to the lower conductive layer; and a plurality of upper conductive layers extending in a second direction orthogonal to the first direction and being in the shape of a band, and the plurality of upper conductive layers are respectively arranged on the plurality of channel stacks and electrically connected to the upper ends of the crossed channel films.

[0012] The manufacturing method of the three-dimensional structure NAND type flash memory of the present invention comprises: the step of forming a lower conductive layer in or on a substrate; the step of forming a stack formed by alternately stacking insulators and conductors on the lower conductive layer; the step of etching the stack to a depth reaching the lower conductive layer to form a plurality of stacks extending along a first direction; the step of forming a channel stack on the entire surface of the substrate including the plurality of stacks; the step of etching the channel stack in a manner of separately arranging the channel stack along one of the side surfaces of each of the plurality of stacks; the step of forming a plurality of upper conductive layers in the form of strips extending in a second direction orthogonal to the first direction on the channel stack; and the step of electrically connecting the plurality of upper conductive layers to the upper ends of the crossed channel stacks, respectively.

[0013] [Effects of the Invention]

[0014] According to the present invention, a separate channel stack is arranged along one side of the stack, and the upper conductive layer is electrically connected to the intersecting channel stack, so that the plane size of a memory cell can be reduced compared with the past. Thus, a highly integrated NAND flash memory can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic three-dimensional diagram of a conventional three-dimensional structure of a NAND type flash memory;

[0016] Figure 2A yes Figure 1 A top view of the flash memory is shown;

[0017] Figure 2B yes Figure 1 A cross-sectional view of a flash memory is shown;

[0018] Figure 3 (A) is a top view of a NAND flash memory according to an embodiment of the present invention, Figure 3 (B) is a top view showing the positional relationship between the channel stack and the gate stack;

[0019] Figure 4 is a schematic cross-sectional view taken along line AA of a NAND flash memory according to an embodiment of the present invention;

[0020] Figure 5 is a schematic cross-sectional view taken along line BB of a NAND flash memory device according to an embodiment of the present invention;

[0021] Figure 6 is a schematic cross-sectional view taken along line CC of a NAND flash memory device according to an embodiment of the present invention;

[0022] Figure 7 It is a schematic three-dimensional diagram for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention;

[0023] Figure 8 It is a schematic three-dimensional diagram for explaining the manufacturing steps of the NAND flash memory according to the embodiment of the present invention;

[0024] Fig. 9 is a schematic cross-sectional view taken along line AA for illustrating the manufacturing steps of the NAND flash memory according to the embodiment of the present invention;

[0025] Fig.10 is a schematic cross-sectional view taken along line AA for illustrating the manufacturing steps of the NAND flash memory according to the embodiment of the present invention;

[0026] Fig. 10A It is used to illustrate Fig.10 A schematic cross-sectional view of the manufacturing steps of the trench stack is shown;

[0027] Fig. 10B It is used to illustrate Fig.10 A schematic cross-sectional view of the manufacturing steps of the trench stack is shown;

[0028] Fig. 10C It is used to illustrate Fig.10 A schematic cross-sectional view of the manufacturing steps of the trench stack is shown;

[0029] Fig. 10D It is used to illustrate Fig.10 A schematic cross-sectional view of the manufacturing steps of the trench stack is shown;

[0030] Fig.11 is a schematic cross-sectional view taken along line CC for illustrating the manufacturing steps of the NAND flash memory according to the embodiment of the present invention;

[0031] Fig.12 is a schematic cross-sectional view taken along line CC for illustrating the manufacturing steps of the NAND flash memory according to the embodiment of the present invention;

[0032] Fig.13 is a schematic cross-sectional view taken along line CC for illustrating the manufacturing steps of the NAND flash memory according to the embodiment of the present invention;

[0033] Fig.14 is a schematic cross-sectional view taken along line AA for illustrating the manufacturing steps of the NAND flash memory according to the embodiment of the present invention;

[0034] Fig.15 is a schematic cross-sectional view taken along line AA for illustrating the manufacturing steps of the NAND flash memory according to the embodiment of the present invention;

[0035] Fig.16 is a schematic cross-sectional view taken along line AA for illustrating the manufacturing steps of the NAND flash memory according to the embodiment of the present invention;

[0036] Fig.17 is a schematic cross-sectional view taken along line AA for illustrating the manufacturing steps of the NAND flash memory according to the embodiment of the present invention;

[0037] Fig.18 is a schematic cross-sectional view taken along line AA for illustrating the manufacturing steps of the NAND flash memory according to the embodiment of the present invention;

[0038] Fig.19 (A) is a top view of a NAND flash memory according to an embodiment of the present invention, and schematically shows a state without a bit line and a contact. Fig.19 (B) schematically shows a top view of a state where a bit line and a contact are provided;

[0039] Fig. 20 (A) is a top view of a conventional NAND flash memory, and schematically shows a state without a bit line and a plug. Fig. 20 (B) is a top view schematically showing a state of a bit line and a plug.

[0040] [Explanation of Symbols]

[0041] 1: Substrate

[0042] 2: Insulation layer

[0043] 3: Lower conductive layer (source)

[0044] 4: Insulator

[0045] 5: Conductor (gate)

[0046] 5A, 5B: Conductors

[0047] 6: Insulator

[0048] 7: Insulator (intermediate insulator)

[0049] 8: Bit line

[0050] 9: Channel stack

[0051] 9A: Upper end

[0052] 9B: Lower end

[0053] 10, 12: Insulation layer (insulator)

[0054] 11: Electricity storage layer (insulator)

[0055] 13, 14: Polysilicon layer (polysilicon)

[0056] 15: Etching mask

[0057] 16: Contact (BL contact)

[0058] 17: Plug

[0059] 18: Gate insulation film

[0060] 19: Channel film

[0061] 100: Flash memory (NAND type flash memory)

[0062] 110: Gate stack (gate insulator)

[0063] 110A: Stack

[0064] MC: Memory cell stack (memory cell structure)

[0065] MC1, MC2: storage unit

[0066] P: Spacing

[0067] Q1, Q2: Region

[0068] R, R1: rectangular area (plane size)

[0069] WL: Word Line DETAILED DESCRIPTION

[0070] The three-dimensional NAND flash memory of the present invention is used as a storage medium in various semiconductor devices (for example, a microcontroller, a microprocessor, a logic, etc. in which such a flash memory is embedded).

[0071] [Example]

[0072] Next, embodiments of the present invention will be described with reference to the drawings. It should be noted that the scales of the drawings are exaggerated to facilitate understanding of the invention and do not necessarily represent the scales of actual products.

[0073] The NAND flash memory 100 of the present embodiment includes: a substrate 1, an insulating layer 2 formed on the substrate 1, a lower conductive layer 3 formed on the insulating layer 2, a memory cell structure MC stacked on the lower conductive layer 3 in a vertical direction, and a bit line 8 formed on the memory cell structure MC.

[0074] The substrate 1 is not particularly limited, and includes, for example, a silicon substrate. The silicon substrate may be any one of true, n-type, and p-type. In addition, when a peripheral circuit (for example, a row selection drive circuit, or an integrated circuit such as a page buffer / readout circuit) is formed on the surface of the silicon substrate, the silicon substrate may include an n-type or a p-type. In the following description, a case where a silicon substrate is used as the substrate 1 is exemplified.

[0075] The insulating layer 2 formed on the silicon substrate 1 includes, for example, a silicon oxide film or a silicon nitride film, etc. The lower conductive layer 3 includes, for example, n-type polysilicon or a stack of a metal material and n-type polysilicon. The lower conductive layer 3 functions as a common source SL of the NAND string.

[0076] The memory cell structure MC includes a plurality of NAND strings formed in a vertical direction or longitudinal direction on the lower conductive layer 3. As in the prior art, one NAND string includes a plurality of memory cells connected in series, a bit line side selection transistor connected to one end of the plurality of memory cells, and a source line side selection transistor connected to the other end. Furthermore, the NAND string may also include a dummy memory cell between the bit line side selection transistor and the memory cell or between the source line side selection transistor and the memory cell.

[0077] A gate stack 110 is formed on the lower conductive layer 3 by alternately stacking insulators 4 and conductors 5. Figure 3 (A) Figure 3As shown in (B), the gate stack 110 is processed in a strip-like (rectangular shape) manner when viewed in a planar direction, and they extend in a stripe-like manner along the column direction. The uppermost layer of the gate stack 110 is an insulator 6 connected to the bit line 8 via an insulator 7, and the lowermost layer is an insulator 4 connected to the lower conductive layer 3. Insulators 4 and 6 include, for example, a silicon oxide film or a silicon nitride film. The conductor 5A directly below the insulator 6 constitutes the gate of the bit line side selection transistor, and the conductor 5B directly above the lowermost insulator 4 constitutes the gate of the source line side selection transistor. The multiple conductors 5 between the conductor 5A and the conductor 5B respectively constitute the gates of the storage cells. The conductors 5, the conductors 5A, and the conductors 5B include, for example, n-type polysilicon. The conductor 5A constituting the gate of the bit line side selection transistor is connected to one or more selection gate lines SGD generated by a row selection drive circuit not shown. The conductor 5B constituting the gate of the source line side selection transistor is connected to one or more selection gate lines SGS generated by the same row selection drive circuit or the like, and the plurality of conductors 5 are connected to corresponding word lines WL.

[0078] The memory cell structure MC further includes a channel stack 9. Figure 3 (B) Figure 4 , Figure 6 As shown, the channel stack 9 is formed separately in the column direction along one of the side surfaces of the gate stack 110. One channel stack 9 extends from the lower conductive layer 3 to the bit line 8 in the vertical direction, and the upper end 9A of the channel stack 9 is connected to the intersecting bit line 8, and the lower end 9B is connected to the lower conductive layer 3. In this example, the upper end 9A of the channel stack 9 is formed in a manner covering a portion of the insulator 6 of the gate stack 110. This is to increase the contact area between the channel stack 9 and the bit line 8. However, this configuration is an example and is not limited thereto.

[0079] A NAND string includes a channel stack 9 extending in a vertical direction. The channel stack 9 includes a channel film constituting a channel and a gate insulator formed between the channel film and the gate 5. The channel film, for example, includes polysilicon. The gate insulator includes a charge accumulation layer for accumulating charges and a plurality of insulating layers sandwiching the charge accumulation layer. The gate insulator can be, for example, an ONO structure of silicon oxide film (O) / silicon nitride film (N) / silicon oxide film (O). Other semiconductor materials with high dielectric constants can also be used instead of silicon oxide film. Furthermore, the details of the channel stack 9 will be described later.

[0080] As described above, a plurality of channel stacks 9 are separately formed on one side surface of the gate stack 110, and an insulator 7 is formed between these channel stacks 9. Furthermore, an insulator 7 is also formed on the other side surface of the gate stack 110. In other words, the space between two adjacent gate stacks is filled with the insulator 7.

[0081] like Figure 3 As shown in (A), above the memory cell structure MC, a plurality of bit lines 8 processed in a stripe-like (rectangular shape) shape when viewed in a planar direction extend in a stripe-like shape along the row direction. The plurality of bit lines 8 are electrically connected to the upper end 9A of the channel stack 9 corresponding to the position intersecting the gate stack 110. The bit line 8 includes, for example, a metal material such as polysilicon or Al (aluminum).

[0082] Next, refer to Figure 7 to Figure 18 The manufacturing method of the NAND flash memory of this embodiment is described. Figure 7 As shown, an insulating layer 2 is formed on a substrate 1, and a lower conductive layer 3 is formed on the insulating layer 2. Next, a stack 110A including a stack of an insulator 4, an insulator 6, and a conductor 5 is formed on the lower conductive layer 3. The stack 110A is a precursor of the gate stack 110. The number of conductors 5 stacked in the stack 110A is determined according to the number of memory cells of the NAND string (e.g., 32 or 64).

[0083] Next, a patterned etching mask (not shown) is formed on the insulator 6 by a photolithography step, and the insulator 4, the insulator 6, and the conductor 5 of the stack 110A are anisotropically etched simultaneously by using the etching mask. The etching is performed until the lower conductive layer 3 is reached. The etching is performed, for example, by anisotropic etching or a combination of anisotropic etching and isotropic etching. A tiny step or concave portion that can be removed by etching may be formed on the surface of the lower conductive layer 3, and the lower conductive layer 3 is preferably thick enough for such a step or concave portion. In this way, as Figure 8 As shown, strip-shaped gate stacks 110 extending in the column direction are formed on the lower conductive layer 3. The pitch P between the gate stacks 110 is, for example, 180 nm. Fig. 9 It is the AA line section (AA line is Figure 3 The same position as the AA line of (A).

[0084] Then, if Fig.10 As shown in FIG. 1 , the channel stack 9 is formed on the entire surface of the substrate so as to cover the gate stack 110. FIG. 10A to FIG. 10D The structure of the channel stack 9 will be described. FIG. 10B to FIG. 10D The enlarged cross-sectional diagrams are respectively Fig. 10A The areas Q1 and Q2 shown correspond to each other.

[0085] like Fig. 10B As shown in FIG. 1 , an insulating layer 10, a charge storage layer 11, an insulating layer 12, and a polysilicon layer 13 are sequentially stacked on the entire surface of the substrate in a manner covering the gate stack 110. The method for forming these films is not particularly limited, and for example, chemical vapor deposition (CVD) or sputtering can be used. The insulating layer 12 includes silicon dioxide (SiO 2 ), or silicon dioxide (SiO 2 ) and silicon nitride (SiN) stack. The charge storage layer 11 includes a plurality of insulators, such as silicon nitride (SiN) or silicon dioxide (SiO 2 The insulating layer 10 includes a plurality of insulators such as a high dielectric constant (HighK, HiK) material having a high dielectric constant. The polysilicon layer 13 is not doped and therefore includes intrinsic silicon.

[0086] Then, if Fig. 10C As shown, the bottom of the insulating layer 10, the charge storage layer 11, the insulating layer 12, and the polysilicon layer 13 are etched using an etching mask (not shown). The etching is performed, for example, by anisotropic etching or a combination of anisotropic etching and isotropic etching until the surface of the lower conductive layer 3 is exposed. A small step or concave portion that can be removed by etching may be formed on the surface of the lower conductive layer 3, and the lower conductive layer 3 is preferably thick enough for such a step or concave portion. Next, as shown in FIG. Fig. 10D As shown, a polysilicon layer 14 is deposited on the entire surface of the substrate. The polysilicon layer 14 is also not doped, so it is intrinsic silicon. The two polysilicon layers 13 and 14 are electrically connected to each other, and the lower end of the polysilicon layer 14 is electrically connected to the lower conductive layer 3. In this way, the channel stack 9 is formed in a manner that covers both side surfaces of the gate stack 110. Fig.11 is with Figure 3 Cross-sectional view at the same position of line CC in (A).

[0087] Then, if Fig.12 As shown in FIG. 1 , the channel stack 9 is processed into a plurality of stripes by etching to form a plurality of channel stacks 9 insulated from each other. Fig.13 As shown, one channel stack 9 extends in a direction perpendicular to the direction in which the gate insulator 110 extends, and a plurality of channel stacks 9 are arranged at regular intervals along the direction in which the gate insulator 110 extends.

[0088] Next, the channel stack 9 is further processed along one of the side surfaces of the gate insulator 110. The processing flow is shown in FIG. Figure 14 to Figure 16 In. Furthermore, Figure 14 to Figure 16 It is along Fig.13 The cross-sectional view of the AA line. Fig.14 As shown, a patterned etching mask 15 is formed by using a photolithography step so as to cover the side surfaces and a part of the upper surface of the channel stack 9 .

[0089] Then, if Fig.15 As shown, etching is performed through the etching mask 15 to partially remove the channel stack 9. The etching is performed, for example, by anisotropic etching or a combination of anisotropic etching and isotropic etching, until the surface of the lower conductive layer 3 is exposed. A small step or recess that is removed by etching may be formed on the surface of the lower conductive layer 3, and the lower conductive layer 3 is preferably thick enough for such a step or recess. Through the etching, the channel stack 9 remains on one side of the gate insulator 110 and covers a portion of the insulator 6 of the gate stack 110. The reason for forming the channel stack 9 in a manner covering the insulator 6 is to increase the contact area with the bit line 8 or to increase the area for forming a contact hole for connecting to the bit line. In addition, the bottom of the channel stack 9 is separated from the bottom of the channel stack 9 of the adjacent gate stack 110, and the lower conductive layer 3 is exposed here.

[0090] Then, if Fig.16 As shown, the etching mask 15 is removed. After the etching mask 15 is removed, the intermediate insulator 7 is deposited on the entire surface of the substrate so as to cover the channel stack 9 and the gate stack 110. Thus, the space between the adjacent gate stacks 110 is filled with the intermediate insulator 7.

[0091] Then, if Fig.17 As shown, the intermediate insulator 7 is planarized by chemical mechanical planarization (CMP) or the like. The top of the channel stack 9 is exposed by the planarization process.

[0092] Then, if Fig.18 As shown, the material of the bit line is deposited on the entire surface of the substrate, and then the bit line 8 is patterned into a strip shape. The bit line 8 is electrically connected to the polysilicon layer 13 and the polysilicon layer 14 of the channel stack 9 that crosses it directly below. Here, an example in which the bit line 8 is directly in contact with the upper end 9A of the channel stack 9 is shown, but an interlayer insulating film may be formed after the planarization process, and a contact hole may be formed in the interlayer insulating film to expose the upper end 9A of the channel stack 9, and the bit line 8 may be electrically connected to the channel stack 9 through the contact hole.

[0093] In this way, a NAND string connected between the bit line 8 and the lower conductive layer (source) 3 is formed, and a three-dimensional memory cell array is obtained.

[0094] Next, the cell size of the three-dimensional NAND flash memory of this embodiment is compared with the cell size of a conventional product. Fig.19 (B) schematically shows a top view of the flash memory of this embodiment, Fig.19 (A) schematically shows a top view without the bit line 8 and the bit line (BL) contact 16 between the bit line 8 and the channel film 19. In these figures, 18 is a gate insulating film ( Fig. 10B The insulator 10, insulator 11, insulator 12 shown in the figure, 19 is a channel film ( Fig. 10D In addition, the dotted rectangular area R represents the planar size of a memory cell. When the pitch of the gate 5 is 180nm and the pitch of the channel film 19 is 50nm, the planar size R is 50×180nm. 2 .

[0095] on the other hand, Fig. 20 (B) schematically shows a top view of a conventional memory cell structure shown in Non-Patent Document 1. Fig. 20 (A) schematically shows a top view without the bit line 8 and the plug 17 for contact between the bit line 8 and the channel film 19. The rectangular area R1 represents the plane size of a memory cell, which is in the same Fig. 20 The same scale as (A) is shown.

[0096] In the existing memory cell structure, two memory cells are formed on both sides of the gate 5, and the bit line 8 is connected to the two opposing memory cells in a shared manner. For example, two memory cells MC1 and MC2 are connected to the bit line 8 via a plug 17. In order for the two memory cells to operate separately, the bit lines 8 connected to the two memory cells must be separated from each other. In contrast, in the memory cell structure of the present embodiment, the memory cell is only arranged on one side of the gate 5. Therefore, the bit line 8 connected to the two memory cells can be shared. According to this difference, the pitch of the bit lines 8 of the present embodiment is approximately half of the pitch of the existing bit lines 8, so that the planar size R of the memory cell of the present embodiment can be smaller than the planar size R1 of the existing memory cell. Specifically, it can be seen that the planar size R1 of the existing memory cell is approximately 160×100nm. 2 , the plane size R of the storage unit of this embodiment is smaller than that of the prior art.

[0097] In the embodiment, an example is shown in which a lower conductive layer (source) 3 comprising n-type polysilicon is formed on a substrate 1 via an insulating layer 2, but the present invention is not limited thereto. The lower conductive layer (source) may, for example, be a highly doped n-type well region formed in a P-type silicon substrate.

[0098] The NAND flash memory includes a plurality of blocks, each of which includes a NAND string of a three-dimensional structure as described above. The storage cell can be a single-level cell (SLC) type that stores 1 bit (binary data) or a type that stores multiple bits. In the NAND flash memory, reading or programming is performed in units of pages, and erasing is performed in units of blocks. Since these operations are already known, the description here is omitted.

[0099] Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the invention described in the claims.

Claims

1. A three-dimensional NAND flash memory, comprising: substrate; a lower conductive layer formed in or on the substrate; A plurality of stacked bodies extending along a first direction on the lower conductive layer, wherein the plurality of stacked bodies respectively include stacks of insulators and conductors stacked along a vertical direction from the substrate; A plurality of channel stacks are separately arranged along one of the side surfaces of the plurality of stacks, and the plurality of channel stacks respectively include an insulating layer including a charge storage layer and a channel thin film, the insulating layer and the channel thin film extend from the substrate in a vertical direction, the lower end of the channel thin film is electrically connected to the lower conductive layer, wherein the topmost surface of each of the stacks includes a first portion covered by the corresponding upper end of the channel stack and a second portion exposed by the corresponding upper end of the channel stack; as well as A plurality of upper conductive layers extend along a second direction orthogonal to the first direction, and the plurality of upper conductive layers are respectively disposed on the plurality of channel stacks and electrically connected to upper ends of the intersecting channel thin films.

2. The flash memory according to claim 1, wherein The plurality of channel stacks are arranged at a first pitch along the first direction, and one NAND string includes one channel stack.

3. The flash memory according to claim 2, wherein The plurality of stacked bodies are arranged at a second pitch along the second direction, and a planar dimension of one memory cell is defined by the first pitch and the second pitch.

4. The flash memory according to claim 1, wherein One stack includes the one side surface and another side surface facing the one side surface, and the channel stack and the insulator are arranged between the one side surface of the first stack and the other side surface of the second stack adjacent to each other in the second direction.

5. The flash memory according to any one of claims 1 to 4, wherein The upper conductive layer is a bit line, the lower conductive layer is a source line, the conductor formed on the uppermost layer of the stack is a gate of a bit line side selection transistor, and the conductor formed on the lowermost layer is a gate of a source line side selection transistor.

6. The flash memory according to claim 5, wherein The conductor between the conductor in the uppermost layer and the conductor in the lowermost layer of the stacked body is a gate of a transistor of a memory cell and is connected to a corresponding word line.

7. A method for manufacturing a flash memory, which is a method for manufacturing a three-dimensional structured NAND type flash memory, comprising: forming a lower conductive layer in or on a substrate; forming a stack of alternately stacked insulators and conductors on the lower conductive layer; The step of etching the stack to a depth reaching the lower conductive layer to form a plurality of stacked bodies extending along a first direction; A step of forming a channel stack on the entire surface of the substrate including the plurality of stacks; A step of etching the channel stacks in a manner of being separately arranged along one of the side surfaces of each of the plurality of stacks, wherein the topmost surface of each of the stacks includes a first portion covered by a corresponding upper end of the channel stack and a second portion exposed by the corresponding upper end of the channel stack; forming a plurality of upper conductive layers extending in a second direction orthogonal to the first direction on the channel stack; as well as A step of electrically connecting the plurality of upper conductive layers to upper ends of the intersecting channel stacks, respectively.

8. The method for manufacturing a flash memory according to claim 7, wherein The steps of forming the channel stack include: forming a first insulating layer; forming a charge storage layer on the first insulating layer; forming a second insulating layer on the charge storage layer; And a step of forming a channel film on the second insulating layer.

9. The method for manufacturing a flash memory according to claim 7, wherein The connecting step includes forming a contact hole in an insulating film formed on the channel stack, and the upper conductive layer is electrically connected to an upper end portion of the channel stack via the contact hole.

10. The method for manufacturing a flash memory according to claim 7, wherein The manufacturing method further comprises: After the step of etching the channel stack, a step of forming an insulating film so as to cover the plurality of channel stacks and the plurality of stacks; and a step of planarizing the insulating film to expose the channel stack.

11. The method for manufacturing a flash memory according to claim 7, wherein The film thickness of the lower conductive layer is sufficiently larger than a step or a recess formed on the surface of the lower conductive layer when the stack is etched.

12. The method for manufacturing a flash memory according to claim 7, wherein The film thickness of the lower conductive layer is sufficiently larger than a step or a recess formed on the surface of the lower conductive layer when the channel stack is etched.

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