Display device

Abstract

A display device includes a display panel including a display area configured to display an image and a non-display area located around the display area, wherein the display panel further includes a base and on the base: a plurality of driving voltage lines located in the display area; a plurality of initializing voltage lines located in the display area; a plurality of driving voltage transmission lines located in the non-display area and configured to transmit a driving voltage to the driving voltage lines, and the plurality of driving voltage transmission lines includes a first driving voltage transmission line and a second driving voltage transmission line adjacent to each other; an initializing voltage transmission line located in the non-display area and configured to transmit an initializing voltage to the initializing voltage lines; and a bridge connecting the first driving voltage transmission line and the second driving voltage transmission line and overlapping the initializing voltage transmission line.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0088741, filed on July 17, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of some exemplary embodiments of this disclosure relate to display devices. Background Technology

[0004] The display device includes a display panel in which pixels are formed on a substrate. Pixels are arranged in the display area of ​​the display panel, thus forming a screen for displaying images. The display panel can receive various signals to drive the pixels. These signals can include not only data signals for controlling the brightness of the pixels, but also electrical signals such as drive voltage and common voltage.

[0005] Pixels can be implemented by light-emitting elements, and the display panel can include circuit elements for driving the light-emitting elements in the display area. Such circuit elements can include transistors, and some transistors can be driven by a driving voltage applied through a driving voltage line. Wiring for transmitting the driving voltage to the driving voltage line (e.g., a driving voltage transmission line) can be located in the peripheral area around the display area, and as the length of such wiring increases or the width decreases, the resistance, current density, and voltage drop increase, which may lead to a deterioration in the brightness uniformity of the image displayed in the display area.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background, and therefore, the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0007] When the resistance of the drive voltage transmission line decreases, the drive voltage can be supplied relatively evenly to the entire display area of ​​the display panel. When the width of the drive voltage transmission line increases, its resistance can decrease. However, increasing the width of the drive voltage transmission line may lead to an increase in the non-display area of ​​the display panel. When the non-display area of ​​the display panel increases, the bezel or dead space of the display device increases, and therefore the screen-to-body ratio of the display device increases.

[0008] Some example embodiments include a display device that can improve the brightness uniformity of a display area without increasing the non-display area of ​​the display panel.

[0009] A display device according to some example embodiments of the present disclosure includes: a display panel, the display panel including a display area for displaying an image and a non-display area surrounding the display area, wherein the display panel further includes a substrate and the following on the substrate: a plurality of driving voltage lines located in the display area; a plurality of initialization voltage lines located in the display area; a plurality of driving voltage transmission lines located in the non-display area for transmitting driving voltage to the plurality of driving voltage lines, and the plurality of driving voltage transmission lines including a first driving voltage transmission line and a second driving voltage transmission line adjacent to each other; an initialization voltage transmission line located in the non-display area for transmitting initialization voltage to the plurality of initialization voltage lines; and a bridge connecting the first driving voltage transmission line and the second driving voltage transmission line and overlapping the initialization voltage transmission line.

[0010] According to some example embodiments, the display panel may further include: a driving voltage bus extending in a first direction between the display area and the plurality of driving voltage transmission lines, and connected to the plurality of driving voltage transmission lines. The bridge may connect the first driving voltage transmission line and the second driving voltage transmission line in the first direction.

[0011] According to some example embodiments, the initialization voltage transmission line may be located between the first driving voltage transmission line and the second driving voltage transmission line in the first direction.

[0012] According to some example embodiments, the display panel may further include: a transistor located in the display area; an insulating layer located on the transistor; and a pixel electrode located in the display area on the insulating layer and connected to the transistor. The bridge may be located in the same layer as the pixel electrode.

[0013] According to some example embodiments, the bridge can be connected to the first drive voltage transmission line and the second drive voltage transmission line through contact holes located in the insulating layer.

[0014] According to some example embodiments, the display panel may further include: a pixel defining layer located on the insulating layer and having an opening overlapping the pixel electrode; a common electrode located on the pixel defining layer in the display area; and a common voltage transmission line located in the non-display area and transmitting a common voltage to the common electrode. The bridge may overlap with the common voltage transmission line.

[0015] According to some example embodiments, the common voltage transmission line may be located between the first driving voltage transmission line and the second driving voltage transmission line.

[0016] According to some example embodiments, the multiple drive voltage transmission lines, the initialization voltage transmission line, and the common voltage transmission line may be located in the same layer.

[0017] According to some example embodiments, the display panel may further include a plurality of IC chips. The first driving voltage transmission line and the second driving voltage transmission line may be connected to different IC chips among the plurality of IC chips.

[0018] According to some example embodiments, the plurality of IC chips may be located in the non-display area and may be arranged in a first direction. The bridge may connect the first drive voltage transmission line and the second drive voltage transmission line in the first direction.

[0019] According to some example embodiments, the display panel may further include: an encapsulation substrate overlapping the substrate; and a sealant bonding the substrate to the encapsulation substrate. Each of the first drive voltage transmission line, the second drive voltage transmission line, and the initialization voltage transmission line may include a portion overlapping the sealant and a portion not overlapping the sealant.

[0020] A display device according to some example embodiments of the present disclosure includes: a display panel, the display panel including a display area for displaying an image and a non-display area surrounding the display area, wherein the display panel further includes a substrate and: a pixel located on the substrate, the pixel being located in the display area; a driving voltage line located in the display area and applying a driving voltage to the pixel; a plurality of driving voltage transmission lines located in the non-display area, transmitting a driving voltage to the driving voltage line, and the plurality of driving voltage transmission lines including a first driving voltage transmission line and a second driving voltage transmission line adjacent to each other; a common voltage transmission line located in the non-display area and transmitting a common voltage to the pixel; and a bridge connecting the first driving voltage transmission line and the second driving voltage line and overlapping the common voltage transmission line.

[0021] According to some example embodiments, the display panel may further include: a driving voltage bus extending in a first direction between the display area and the plurality of driving voltage transmission lines, and connected to the plurality of driving voltage transmission lines. The bridge may connect the first driving voltage transmission line and the second driving voltage transmission line in the first direction.

[0022] According to some example embodiments, the common voltage transmission line may be located between the first driving voltage transmission line and the second driving voltage transmission line in the first direction.

[0023] According to some example embodiments, the display panel may further include: a transistor located in the display area; an insulating layer located on the transistor; and a pixel electrode located on the insulating layer and connected to the transistor. The bridge may be located in the same layer as the pixel electrode and connected to the first driving voltage transmission line and the second driving voltage transmission line through a contact hole located in the insulating layer.

[0024] According to some example embodiments, the display panel may further include: a pixel defining layer located on the insulating layer and including an opening overlapping the pixel electrode; and a common electrode for the pixel located on the pixel defining layer. The common voltage transmission line can transmit a common voltage to the common electrode.

[0025] A display device according to some example embodiments of the present disclosure includes: a display panel, the display panel including a display area for displaying an image and a non-display area surrounding the display area, wherein the display panel further includes a substrate and: a plurality of driving voltage lines located in the display area; a plurality of initialization voltage lines located in the display area; a first driving voltage transmission line and a second driving voltage transmission line located in the non-display area, and transmitting driving voltage to the plurality of driving voltage lines, wherein the first driving voltage transmission line and the second driving voltage transmission line are located in the non-display area and transmit driving voltage to the plurality of driving voltage lines. Each of the driving voltage transmission lines includes a first portion and a second portion extending in different directions, and the first driving voltage transmission line and the second driving voltage transmission line are connected in the first direction through the second portion; an initialization voltage transmission line is located in the non-display area between the first portion of the first driving voltage transmission line and the first portion of the second driving voltage transmission line, transmitting an initialization voltage to the plurality of initialization voltage lines, and includes a first portion and a second portion separated from each other; and a first bridge connects the first portion and the second portion of the initialization voltage transmission line in a second direction intersecting the first direction.

[0026] According to some example embodiments, the display panel may further include: a common voltage transmission line located in the non-display area between a first portion of the first driving voltage transmission line and a first portion of the second driving voltage transmission line, transmitting a common voltage to the display area, and including a first portion and a second portion separated from each other; and a second bridge connecting the first portion and the second portion of the common voltage transmission line in the second direction.

[0027] According to some example embodiments, the display panel may further include: a transistor located in the display area; an insulating layer located on the transistor; and a pixel electrode located on the insulating layer and connected to the transistor. The first bridge may be located in the same layer as the pixel electrode.

[0028] According to some example embodiments, the display panel may further include: a plurality of IC chips, wherein the first portion of the first driving voltage transmission line and the first portion of the second driving voltage transmission line may be connected to different IC chips among the plurality of IC chips.

[0029] According to an embodiment, a display device can be provided that can improve brightness uniformity in a display area. This display device can be implemented without increasing the non-display area of ​​the display panel. Attached Figure Description

[0030] Figure 1 This is a schematic top plan view of a display device according to some example embodiments.

[0031] Figure 2 Based on some example embodiments Figure 1 A schematic top view of the signal lines in the lower part of the display device.

[0032] Figure 3 Based on some example embodiments Figure 2 A magnified view of region R in the image.

[0033] Figure 4 It is along Figure 3 A cross-sectional view of a display device according to some example embodiments, taken by line A-A'.

[0034] Figure 5 It is along Figure 3 A cross-sectional view of a display device according to some example embodiments, taken by line A-A'.

[0035] Figure 6 It is along Figure 3 A cross-sectional view of a display device according to some example embodiments, taken by line A-A'.

[0036] Figure 7 and Figure 8 The brightness of each position in the lower portion of the display area of ​​the display device according to the comparative example is shown.

[0037] Figure 9 The brightness of each position in the lower portion of the display area of ​​a display device according to some example embodiments is shown.

[0038] Figure 10 This is a schematic top view of the signal line connection relationship at the lower part of a display device according to some example embodiments.

[0039] Figure 11 It is along Figure 10 A cross-sectional view of a display device according to some example embodiments, taken by line B-B'.

[0040] Figure 12 It is along Figure 10 A cross-sectional view of a display device according to some example embodiments, taken by line C-C'.

[0041] Figure 13It is along Figure 1 A cross-sectional view of a display device according to some example embodiments, taken by line D-D'.

[0042] Figure 14 It is along Figure 1 A cross-sectional view of a display device according to some example embodiments, taken by line E-E'.

[0043] Figure 15 This is an equivalent circuit diagram of the pixels of a display device according to some example embodiments.

[0044] Figure 16 This is a top plan view of a pixel region in a display device according to some example embodiments.

[0045] Figure 17 This is a schematic top plan view of a display device according to some example embodiments. Detailed Implementation

[0046] In the following description, aspects of some exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings, in which aspects of some exemplary embodiments of the inventive concept are illustrated.

[0047] In the accompanying drawings, the thickness of layers, films, panels, areas, etc., is exaggerated for clarity.

[0048] It will be understood that when an element, such as a layer, film, region, or substrate, is referred to as being "on" another element, the element may be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present.

[0049] In addition, unless explicitly stated otherwise, the words “including” and variations such as “contains” or “comprising” will be understood to implicitly include the elements of the statement, but do not exclude any other elements.

[0050] Throughout this specification, “connection” means not only when two or more constituent elements are directly connected, but also when two or more constituent elements are indirectly connected through another constituent element, or when physically or electrically connected, and “connection” may include situations where substantially integral parts are connected to each other, although they are referred to by different names depending on their location or function.

[0051] In the accompanying drawings, the symbol "x" used to indicate direction is a first direction, "y" is a second direction perpendicular to the first direction, and "z" is a third direction perpendicular to both the first and second directions. The first direction x, the second direction y, and the third direction z can correspond to the horizontal direction, vertical direction, and thickness direction of the display device, respectively.

[0052] Unless otherwise stated in the specification, “overlap” means overlap in a planar view and overlap in a third direction z.

[0053] Figure 1 This is a schematic top plan view of a display device according to some example embodiments.

[0054] Reference Figure 1 The display device may include a display panel 10, a flexible printed circuit film 20, an integrated circuit (IC) chip 30, and a printed circuit board 40.

[0055] The display panel 10 includes a display area DA and a non-display area NA. The display area DA corresponds to the screen displaying the image, and circuitry and / or signal lines for generating and / or transmitting various signals applied to the display area DA are formed in the non-display area NA. The non-display area NA may surround the display area DA. Figure 1 In the diagram, the boundary between the display area DA and the non-display area NA is shown as a dashed quadrilateral.

[0056] Pixels PX can be arranged in a matrix format in the display area DA of the display panel 10. Signal lines such as scan lines 121, initialization voltage lines 127, data lines 171, and drive voltage lines 172 can be positioned in the display area DA. Scan lines 121 and initialization voltage lines 127 can extend generally in a first direction x, and data lines 171 and drive voltage lines 172 can extend generally in a second direction y. In an example embodiment, the initialization voltage lines 127 may include voltage lines extending generally in the first direction x and voltage lines extending generally in the second direction y, and can therefore be arranged in a grid shape. Each pixel PX is connected to the scan lines 121, initialization voltage lines 127, data lines 171, and drive voltage lines 172, and therefore each pixel PX can receive scan signals, initialization voltages, data voltages, and drive voltages from the signal lines. Each pixel PX can also receive a common voltage. Pixels PX can be implemented as light-emitting elements such as light-emitting diodes.

[0057] Touch sensors used to detect user contact and / or non-contact touch can be located in the display area DA of the display panel 10.

[0058] A pad portion PP, which has pads for receiving signals from the outside of the display panel 10, can be positioned in the non-display area NA of the display panel 10, and a flexible printed circuit film 20 can be bonded to the pad portion PP. The pads of the flexible printed circuit film 20 can be electrically connected to the pads of the pad portion PP. The display panel 10 may include two or more pad portions PP, and the pad portions PP can be positioned along one edge of the display panel 10 at a distance spaced apart from each other. Each pad portion PP can be bonded to a corresponding flexible printed circuit film 20. The display panel 10 may include one pad portion PP depending on its size, and a flexible printed circuit film 20 can be bonded to the pad portion PP. Additionally, the non-display area NA of the display panel 10 may also include pad portions for receiving signals used to drive touch sensors.

[0059] A driving unit that generates and / or processes various signals for driving the display panel 10 may be located in the non-display area NA of the display panel 10. The driving unit may include a data driver that applies data signals to data lines 171, a gate driver that applies gate signals to scan lines 121, and a signal controller that controls the data driver and the gate driver. Pixel PX may receive data voltages according to a certain timing sequence (e.g., a set or predetermined timing sequence) based on the scan signals generated from the gate driver. The gate driver may be integrated with the display panel 10 and may be located on at least one side of the display area DA.

[0060] A data driver can be provided as an IC chip 30, and the IC chip 30 can be mounted in the non-display area NA of the display panel 10. The IC chip 30 can be positioned between the display area DA and the pad portion PP. Multiple IC chips 30 can be provided in the display panel 10, and the multiple IC chips 30 can be arranged along a first direction x. As the size of the display panel 10 increases, the number of IC chips 30 can increase. A signal controller can be provided as an IC chip and can be mounted on a printed circuit board 40. In other embodiments, the data driver and the signal controller can be provided as integrated chips. A flexible printed circuit film 20 is bonded to and electrically connected to the printed circuit board 40, thereby transmitting signals between the display panel 10 and the printed circuit board 40.

[0061] IC chip 30 can output signals provided to display area DA. For example, IC chip 30 can output data voltage, drive voltage, common voltage, and initialization voltage. IC chip 30 can be connected to data voltage transmission line DVL that transmits data voltage to data line 171, initialization voltage transmission line ITL that transmits initialization voltage to initialization voltage line 127, and common voltage transmission line CTL that transmits common voltage to one electrode of the light-emitting element forming pixel PX. IC chip 30 can output signals for controlling the gate driver, and wiring for transmitting signals can be connected to IC chip 30.

[0062] The drive voltage transmission line (DTL), common voltage transmission line (CTL), and initialization voltage transmission line (ITL) can be formed as conductors located in the same layer within the display panel 10. The drive voltage transmission line (DTL), common voltage transmission line (CTL), and initialization voltage transmission line (ITL) can be arranged in the first direction x.

[0063] The data voltage transmission line DVL can be formed from a conductive layer in the display panel 10 that is located on a different layer than the drive voltage transmission line DTL, the common voltage transmission line CTL, and the initialization voltage transmission line ITL. At least one insulating layer can be positioned between the data voltage transmission line DVL, the drive voltage transmission line DTL, the common voltage transmission line CTL, and / or the initialization voltage transmission line ITL.

[0064] Data voltage transmission lines (DVLs) can be provided corresponding to the number of data lines 171 so that different data voltages can be transmitted to each pixel PX via the data lines 171.

[0065] The driving voltage, common voltage, and initialization voltage can be applied equally to the entire pixel PX. Therefore, driving voltage transmission lines DTL, common voltage transmission lines CTL, and initialization voltage transmission lines ITL can be formed and arranged to minimize the voltage drop from the IC chip 30 to the display area DA and to supply a constant voltage throughout the display area DA. One or more driving voltage transmission lines DTL, one or more common voltage transmission lines CTL, and one or more initialization voltage transmission lines ITL can be connected to each IC chip 30. The driving voltage transmission lines DTL, common voltage transmission lines CTL, and initialization voltage transmission lines ITL can be located on one side of the display panel 10 (e.g., [missing information]). Figure 1 The lower long side of the middle side is arranged symmetrically along the perpendicular bisector extending approximately in the second direction y.

[0066] Drive voltage transmission lines (DTLs) requiring a more constant voltage supply can have a relatively wide width. Furthermore, each drive voltage transmission line (DTL) can include a portion extending in the second direction y (vertical portion) and a portion extending in the first direction x (horizontal portion), and a combination of the horizontal portions of the drive voltage transmission lines (DTLs) can be provided along the entire edge of the display area DA. However, because the common voltage transmission line (CTL) and the initialization voltage transmission line (ITL) are formed in the same layer as the drive voltage transmission lines (DTLs), interference with the common voltage transmission line (CTL) and the initialization voltage transmission line (ITL) cannot be avoided when the horizontal portions of the drive voltage transmission lines (DTLs) are formed to extend continuously in the first direction x; that is, short circuits. Therefore, the horizontal portions of the drive voltage transmission lines (DTLs) are not connected, and the common voltage transmission line (CTL) and / or the initialization voltage transmission line (ITL) can be positioned between the drive voltage transmission lines (DTLs). The common voltage transmission line (CTL) and the initialization voltage transmission line (ITL) can extend substantially in the second direction y. The common voltage transmission line (CTL) and / or the initialization voltage transmission line (ITL) can include portions extending substantially in the second direction y.

[0067] Because resistance increases with wiring length, the drive voltage may not be uniformly distributed across the entire display area DA. For example, a drive voltage with a smaller voltage drop may be distributed to areas closer to the IC chip 30 compared to areas farther away in the display area DA. Therefore, brightness is uneven in the display area DA, and certain areas (e.g., areas closer to the IC chip 30) may have relatively higher brightness than areas farther away from the IC chip 30. Image quality degradation caused by uneven brightness or deviations in the display area DA can be improved by electrically connecting adjacent drive voltage transmission lines DTL, as will be discussed below. Figures 2 to 4 To provide a more detailed description of some of the aspects of this.

[0068] Figure 2 Based on some example embodiments Figure 1 A schematic top view of the signal lines in the lower part of the display device. Figure 3 Based on some example embodiments Figure 2 A magnified view of region R in the image, and Figure 4 It is along Figure 3 A cross-sectional view of a display device according to some example embodiments, taken by line A-A'.

[0069] Reference Figure 2 and Figure 3The diagram shows the drive voltage transmission line DTL, common voltage transmission line CTL, initialization voltage transmission line ITL, and IC chip 30 and buses DBL, CBL and IBL connected to these signal lines in the non-display area NA located below the display area DA.

[0070] The drive voltage transmission line DTL applies the drive voltage to the drive voltage line 172 in the display area DA via the drive voltage bus DBL. The common voltage transmission line CTL applies the common voltage to the electrodes of the light-emitting element in the display area DA via the common voltage bus CBL. The initialization voltage transmission line ITL applies the initialization voltage to the initialization voltage line 127 in the display area DA via the initialization voltage bus IBL (see [link to initialization voltage line]). Figure 1 ).

[0071] The driving voltage bus DBL, the common voltage bus CBL, and the initialization voltage bus IBL can extend in a first direction x between the driving voltage transmission line DTL, the common voltage transmission line CTL, and the initialization voltage transmission line ITL. Of the three buses DBL, CBL, and IBL, the common voltage bus CBL is positioned closest to the display area DA, and the driving voltage bus DBL can be positioned between the common voltage bus CBL and the initialization voltage bus IBL. The common voltage bus CBL can be positioned below the display area DA; however, this disclosure is not limited thereto, and in embodiments, the common voltage bus CBL can be positioned around the display area DA.

[0072] The driving voltage transmission line DTL can be connected to the driving voltage bus DBL via bridge BD1. The common voltage transmission line CTL can be connected to the common voltage bus CBL via bridge BD2. The initialization voltage transmission line ITL can be connected to the initialization voltage bus IBL via bridge BD3. Bridges BD1, BD2, and BD3 can be formed in the same layer as a conductive layer (e.g., pixel electrodes, described later), which is located in a different layer than the driving voltage transmission lines DTL in the display panel 10. To illustrate aspects of some exemplary embodiments according to this disclosure more clearly, in Figure 2 Only bridge BD1 out of bridges BD1, BD2, and BD3 is shown, but as... Figure 3 As shown, bridges BD2 and BD3 can be located between bridges BD1.

[0073] The driving voltage bus DBL, common voltage bus CBL, and initialization voltage bus IBL can be formed as a conductive layer, which is located in the same layer in the display panel 10. The driving voltage bus DBL, common voltage bus CBL, and initialization voltage bus IBL can be formed in the same layer as the driving voltage transmission line DTL. The driving voltage bus DBL, common voltage bus CBL, and initialization voltage bus IBL are directly connected to the driving voltage line 172, the electrodes of the light-emitting element, and the initialization voltage line 127, respectively (see...). Figure 1 Alternatively, it can be connected via other conductors to the driving voltage line 172, the electrodes of the light-emitting element, and the initialization voltage line 127 (see [link]). Figure 1 For example, drive voltage line 172 can be connected to drive voltage bus DBL via a conductor located in a different layer than the common voltage bus CBL, while overlapping with the common voltage bus CBL.

[0074] The drive voltage bus DBL can be supplied with drive voltage from drive voltage transmission lines DTL via bridge BD1. Because the voltage drop level can vary depending on the drive voltage transmission line DTL, drive voltages with different voltage drop levels can be supplied depending on the region of the drive voltage bus DBL (i.e., the region to which the drive voltage transmission lines DTL are connected). Therefore, the drive voltage supplied to drive voltage line 172 may deviate depending on the portion of the drive voltage bus DBL connected to drive voltage line 172. To prevent or reduce this drive voltage deviation, adjacent drive voltage transmission lines DTL are connected via bridge BR1. Thus, drive voltage transmission lines DTL with relatively high and relatively low resistances are electrically connected, and therefore the resistance of each drive voltage transmission line DTL can be compensated by the average resistance of the drive voltage transmission lines DTL. Through such resistance averaging compensation, the drive voltage bus DBL can receive a uniform drive voltage overall, regardless of which drive voltage transmission line DTL it is connected to, and can improve brightness uniformity or deviation in the display area DA. Bridge BR1 can be formed as long in approximately the first direction x. Bridge BR1 can connect drive voltage transmission lines (DTL) in approximately the first direction x. Bridge BR1 can connect drive voltage transmission lines (DTL) connected to the same IC chip 30, and can also connect drive voltage transmission lines (DTL) connected to different IC chips 30.

[0075] Simultaneously, the width of the drive voltage bus DBL can be widened to reduce its resistance, thereby making the drive voltage uniform across the entire drive voltage bus DBL. However, there are limitations in widening the drive voltage bus DBL due to design constraints regarding the area where it can be arranged. According to some example embodiments, the drive voltage can be supplied uniformly across the entire drive voltage bus DBL without widening its width.

[0076] Reference Figure 4 The cross-sectional structure of the display panel 10 will be described, with a focus on the area where the drive voltage transmission line DTL is connected via bridge BR1.

[0077] Display panel 10 (reference) Figure 1 The device may have a structure in which an insulating layer and a conductive layer are stacked on a substrate 110. A buffer layer 120 may be positioned on the substrate 110, and a first gate insulating layer 141 may be positioned on the buffer layer 120.

[0078] The first data voltage transmission line DVLa, the second gate insulating layer 142, and the second data voltage transmission line DVLb can be sequentially positioned on the first gate insulating layer 141. The data voltage transmission line DVL includes the first data voltage transmission line DVLa and the second data voltage transmission line DVLb and is formed as two layers, while the second gate insulating layer 142 is disposed between the two layers, so that multiple data voltage transmission lines DVL, each having a width (e.g., a set or predetermined width), can be positioned in a limited area.

[0079] Interlayer insulation layer 160 can be positioned on the second data voltage transmission line DVLb, and drive voltage transmission line DTL, common voltage transmission line CTL, and initialization voltage transmission line ITL can be positioned on interlayer insulation layer 160. Planarization layer 180 can be positioned on drive voltage transmission line DTL, common voltage transmission line CTL, and initialization voltage transmission line ITL.

[0080] The driving voltage transmission line (DTL), common voltage transmission line (CTL), and initialization voltage transmission line (ITL) are located in the same layer, with the CTL and ITL positioned between adjacent driving voltage transmission lines (DTLs). Therefore, adjacent driving voltage transmission lines (DTLs) between the interlayer insulating layer 160 and the planarization layer 180 cannot be directly connected. Adjacent driving voltage transmission lines (DTLs) can be electrically connected to each other via a bridge (BR1) positioned on the planarization layer 180. The bridge (BR1) can be connected to adjacent driving voltage transmission lines (DTLs) via contact holes H1 and H2 in the planarization layer 180. The bridge (BR1) includes portions overlapping with the common voltage transmission line (CTL) and the initialization voltage transmission line (ITL), but can be insulated from them via the planarization layer 180. The bridge (BR1) can be formed on the same layer as the pixel electrode, made of the same material as the pixel electrode, which will be described in more detail later. A pixel defining layer 360 covering the bridge (BR1) can be positioned on the planarization layer 180.

[0081] Figure 4 The bridge BR1 shown is formed using a conductive layer positioned between the planarization layer 180 and the pixel defining layer 360, but the bridge BR1 can also be formed using a conductive layer positioned between other insulating layers. As an example, reference will be made to... Figure 5 and Figure 6 To describe it in more detail.

[0082] Figure 5 and Figure 6 Each of them is along Figure 3 A cross-sectional view of a display device according to some example embodiments, taken by line A-A'.

[0083] Reference Figure 5 The planarization layer is formed by a double layer of first planarization layer 181 and second planarization layer 182. A bridge BR1 connecting adjacent drive voltage transmission lines DTL is positioned between the first planarization layer 181 and the second planarization layer 182, and can be connected to the drive voltage transmission lines DTL through contact holes H1 and H2 in the first planarization layer 181. Bridge BR1 includes portions overlapping with the common voltage transmission line CTL and the initialization voltage transmission line ITL, but bridge BR1 can be insulated from the common voltage transmission line CTL and the initialization voltage transmission line ITL through the first planarization layer 181. A pixel defining layer 360 covering bridge BR1 can be positioned on the second planarization layer 182.

[0084] Reference Figure 6The gate insulating layer is formed of three layers: a first gate insulating layer 141, a second gate insulating layer 142, and a third gate insulating layer 143. The second data voltage transmission line DVLb can be positioned between the second gate insulating layer 142 and the third gate insulating layer 143. A bridge BR1 connecting adjacent drive voltage transmission lines DTL is positioned between the third gate insulating layer 143 and the interlayer insulating layer 160, and the drive voltage transmission lines DTL can be connected to the bridge BR1 through contact holes H1 and H2 of the interlayer insulating layer 160. The common voltage transmission line CTL and the initialization voltage transmission line ITL include portions overlapping with the bridge BR1, but can be insulated from each other via the interlayer insulating layer 160. As described, the bridge BR1 can be formed using a conductive layer positioned between the second data voltage transmission line DVLb and the drive voltage transmission line DTL.

[0085] Figure 7 and Figure 8 The brightness of each position in the lower portion of the display area of ​​the display device according to the comparative example is shown, and Figure 9 The brightness of each position in the lower portion of the display area of ​​a display device according to some example embodiments is shown.

[0086] Reference Figure 7 and Figure 8 The image shows the brightness in the lower portion of the display area DA in a display device according to a comparative example, where adjacent drive voltage transmission lines DTL are not connected via bridge BR1. Figure 8 The diagram shows the brightness of each position in which the numbers displayed in the display area DA are placed. Positions 2, 5, and 8 are positions close to IC chip 30, while positions 1, 3, 4, 6, 7, and 9 are positions far from IC chip 30.

[0087] like Figure 8 As shown in the graph, positions 2, 5, and 8 have the highest brightness, and IC chip 30 (see...) Figure 7 The brightness of positions 3, 4, 6, and 7 between these points is approximately 3.3%, 5.1%, 5.3%, and 3.8% lower than the maximum brightness, respectively. Such brightness differences may be visually perceptible, and the display quality of the display device may be degraded as a result. (See reference...) Figure 9 The graphs in the diagram show that, similar to the display device according to the comparative example, the display device according to some example embodiments, where the drive voltage transmission line DTL is connected via bridge BR1, can have maximum brightness at positions 2, 5, and 8. However, the brightness at positions 3, 4, 6, and 7 is approximately 2.1%, approximately 1.9%, approximately 2.8%, and approximately 1.9% lower than the maximum brightness, respectively. In other words, compared to the display device of the comparative example, the brightness difference of the display device by position can be reduced by approximately half.

[0088] According to some example embodiments, brightness deviations or uneven brightness that may occur in the display device of the comparative example can be improved, and display quality can be improved.

[0089] Figure 10 This is a schematic top view of the signal line connections at the lower portion of a display device according to some example embodiments. Figure 11 It is along Figure 10 A cross-sectional view of a display device according to some example embodiments, taken by line B-B', and Figure 12 It is along Figure 10 A cross-sectional view of a display device according to some example embodiments, taken by line C-C'.

[0090] In such Figures 10 to 12 In the display device shown according to some example embodiments, one or more drive voltage transmission lines (DTLs), one or more common voltage transmission lines (CTLs), and one or more initialization voltage transmission lines (ITLs) are respectively connected to the IC chip 30. The drive voltage transmission lines (DTLs), common voltage transmission lines (CTLs), and initialization voltage transmission lines (ITLs) can be formed by conductive layers formed in the same layer in the display panel 10. Each drive voltage transmission line (DTL) includes a portion (horizontal portion) extending in a first direction x, and the horizontal portions of the drive voltage transmission lines (DTLs) are combined and span the entire edge of the display area DA.

[0091] However, unlike the embodiments described above, the horizontal portion of the drive voltage transmission line DTL extends continuously in the first direction x. The horizontal portion of the drive voltage transmission line DTL can be integrally formed. Therefore, as in the embodiment where the drive voltage transmission lines DTL spaced apart from each other are connected by a bridge BR1, the resistance of each drive voltage transmission line DTL is compensated by the average resistance of the drive voltage transmission line DTL, thereby improving brightness uniformity in the display area DA.

[0092] A common voltage transmission line (CTL) and an initialization voltage transmission line (ITL) are formed between the drive voltage transmission lines (DTL) so as not to interfere with the horizontal portion of the drive voltage transmission lines (DTL).

[0093] Reference Figure 10 and Figure 11While arranging the horizontal portion of the driving voltage transmission line DTL, the common voltage transmission line CTL is divided into two parts in the second direction y. The two parts divided from the common voltage transmission line CTL can be electrically connected via a bridge BR2. The bridge BR2 can extend approximately in the second direction y. The bridge BR2 can connect the two parts of the common voltage transmission line CTL in approximately the second direction y. The bridge BR2 can be positioned between the planarization layer 180 and the pixel defining layer 360, and can be connected to the two parts of the common voltage transmission line CTL through contact holes in the planarization layer 180. Unlike this, as in regarding... Figure 5 As described in the above embodiments, when the display panel 10 includes a first planarization layer 181 and a second planarization layer 182, the bridge BR2 is positioned between the first planarization layer 181 and the second planarization layer 182, and therefore can be connected to the two portions of the common voltage transmission line CTL through the contact holes of the first planarization layer 181. (See also: Regarding...) Figure 6 As described in the embodiment, when the display panel 10 includes a third gate insulating layer 143, the bridge BR2 can be positioned between the third gate insulating layer 143 and the interlayer insulating layer 160, and the two portions of the common voltage transmission line CTL can be connected to the bridge BR2 through the contact holes of the third gate insulating layer 143.

[0094] Reference Figure 10 and Figure 12 While arranging the horizontal portion of the drive voltage transmission line DTL, the initialization voltage transmission line ITL is divided into two parts in the second direction y. The two parts of the initialization voltage transmission line ITL can be electrically connected via bridge BR3 in the same manner as the two parts of the common voltage transmission line CTL are electrically connected via bridge BR2. Bridge BR3 can extend approximately in the second direction y. Bridge BR3 can connect the two parts of the initialization voltage transmission line ITL approximately in the second direction y.

[0095] Alternatively, the common voltage transmission line CTL extends only in the second direction y to the horizontal portion of the drive voltage transmission line DTL, and can be connected to the common voltage bus CBL via the bridge BR2 described above. The initialization voltage transmission line ITL extends only in the second direction y to the horizontal portion of the drive voltage transmission line DTL, and can be connected to the initialization voltage bus IBL via the bridge BR3 described above.

[0096] Reference Figure 13 and Figure 14 The cross-sectional structure of the display device according to some example embodiments will be described in more detail. Figure 13 It is along Figure 1 A cross-sectional view of a display device according to some example embodiments, taken by line D-D', and Figure 14 It is along Figure 1 The diagram shows a cross-sectional view of a display device according to some example embodiments, taken along line E-E'. When illustrating the connection relationships between the drive voltage transmission line DTL, the common voltage transmission line CTL, and the initialization voltage transmission line ITL, reference will also be made to… Figures 1 to 4 and Figures 10 to 12 .

[0097] The display panel 10 includes a substrate 110. The substrate 110 may be an insulating substrate formed of glass, quartz, ceramic, etc.

[0098] Buffer layer 120 may be positioned on substrate 110, and semiconductor layer 131 of transistor TR may be positioned on buffer layer 120. Semiconductor layer 131 may include a channel region and source and drain regions positioned on opposite sides of the channel region. Semiconductor layer 131 may include polysilicon, amorphous silicon, or oxide semiconductor. Buffer layer 120 may prevent or reduce the diffusion or penetration of moisture, contaminants, or impurities that degrade the characteristics of semiconductor layer 131.

[0099] A first gate insulating layer 141 may be positioned on the semiconductor layer 131. A first gate conductor, which may include a scan line 121, a gate electrode 124 of a transistor TR, a first data voltage transmission line DVLa, and electrodes of a storage capacitor, may be positioned on the first gate insulating layer 141. The gate electrode 124 may overlap with the channel region of the semiconductor layer 131. The first gate conductor may be fabricated from the same material using the same process.

[0100] A second gate insulating layer 142 may be positioned on the first gate conductor. The second gate conductor, which may include an initialization voltage line 127, a second data voltage transmission line DVLb, and electrodes of a storage capacitor, may be positioned on the second gate insulating layer 142. The second gate conductor may be made of the same material using the same process. An interlayer insulating layer 160 may be positioned on the second gate conductor.

[0101] The buffer layer 120, the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 160 may include materials such as silicon oxide (SiO2). x ) and silicon nitride (SiN) x Inorganic insulating materials such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), and titanium (Ti). The first gate conductor and the second gate conductor may include metals such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), and titanium (Ti).

[0102] Data conductors, including data lines 171, drive voltage lines 172, source electrodes 173 and drain electrodes 175 of transistor TR, drive voltage transmission lines DTL, common voltage transmission lines CTL, initialization voltage transmission lines ITL, drive voltage buses DBL, common voltage buses CBL, and initialization voltage buses IBL, can be positioned on interlayer insulating layer 160. The data conductors can be made from the same materials using the same process. The data conductors can include metals such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), and tantalum (Ta).

[0103] The source electrode 173 and drain electrode 175 can be connected to the source region and drain region of the semiconductor layer 131, respectively, through contact holes in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 160. The gate electrode 124, source electrode 173, and drain electrode 175, together with the semiconductor layer 131, form a transistor TR. The transistor TR can be a driving transistor in a pixel PX of a light-emitting display device, or it can be a transistor electrically connected to the driving transistor.

[0104] A planarization layer 180 may be positioned on the interlayer insulating layer 160 and the data conductor. The planarization layer 180 may include organic insulating materials such as acrylic polymers, siloxane polymers, and imide polymers. The planarization layer 180 may be used to planarize by removing steps, thereby improving the luminous efficiency of the light-emitting element to be formed on the planarization layer 180. A passivation layer, which may include an inorganic insulating material, may be positioned between the data conductor and the planarization layer 180.

[0105] According to some example embodiments, in the driving region GDA adjacent to the display region DA, elements forming drivers such as gate drivers (e.g., transistors and capacitors) and wiring can be positioned between the substrate 110 and the planarization layer 180.

[0106] Pixel conductors, including pixel electrode 191, connector 195, bridges BD1, BD2, and BD3, and bridges BR1 or BR2 and BR3, can be positioned on planarization layer 180. The pixel conductors can be fabricated from the same material using the same process. Pixel electrode 191 can be connected to the source electrode 173 or drain electrode 175 of transistor TR through contact holes in planarization layer 180. Connector 195 can be connected to common voltage bus CBL. Through contact holes in planarization layer 180, bridge BD1 can connect drive voltage transmission line DTL and drive voltage bus DBL, bridge BD2 can connect common voltage transmission line CTL and common voltage bus CBL, and bridge BD3 can connect initialization voltage transmission line ITL and initialization voltage bus IBL. Bridge BR1 can connect adjacent drive voltage transmission line DTL through contact holes in planarization layer 180. Bridge BR3 can connect two divided portions of common voltage transmission line CTL, and bridge BR3 can connect two divided portions of initialization voltage transmission line ITL through contact holes in planarization layer 180.

[0107] Pixel conductors can be formed of reflective conductive materials or semi-transparent conductive materials, or they can be formed of transparent conductive materials. Pixel conductors can include transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). Pixel conductors can also include metals such as lithium (Li), calcium (Ca), aluminum (Al), silver (Ag), magnesium (Mg), and gold (Au).

[0108] The pixel defining layer 360 can be positioned on the pixel conductor. The pixel defining layer 360 can also be referred to as a spacer. The pixel defining layer 360 may include an opening 610 overlapping with the pixel electrode 191. The opening 610 may define a region corresponding to the light-emitting region of the pixel PX. The pixel defining layer 360 may include an organic insulating material such as an acrylic polymer, an imide polymer, or an amide polymer.

[0109] The light-emitting component 260 can be positioned on the pixel electrode 191. The light-emitting component 260 includes an emitting layer and may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0110] A common electrode 270 can be positioned on the light-emitting component 260. The common electrode 270 may comprise a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO). The common electrode 270 may comprise a metal such as calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), and silver (Ag). The common electrode 270 can be connected to the connector 195 through the contact hole 620 of the pixel defining layer 360. Because the connector 195 is connected to the common voltage bus CBL, and the common voltage bus CBL is connected to the common voltage transmission line CTL, the common electrode 270 can receive a common voltage. At least one protective layer or functional layer may be positioned on the common electrode 270.

[0111] Each pixel PX has a pixel electrode 191, a light-emitting element 260, and a common electrode 270 forming a light-emitting diode (LED), which can be an organic light-emitting diode (OLED). The pixel electrode 191 can be an anode that can serve as a hole injection electrode, and the common electrode 270 can be a cathode that can serve as an electron injection electrode; however, the situation can be reversed. Holes and electrons are injected into the light-emitting element 260 from the pixel electrode 191 and the common electrode 270, respectively, and when an exciton generated by the recombination of the injected holes and electrons transitions from an excited state to a ground state, the exciton emits light with brightness (e.g., a set or predetermined brightness).

[0112] The encapsulation substrate 210 facing the substrate 110 can be an insulating substrate formed of glass, quartz, ceramic, etc. The encapsulation substrate 210 can be bonded to the substrate 110 by a sealant 50.

[0113] A touch sensor layer, including touch signal line 410 and touch electrode 420, can be positioned on the encapsulation substrate 210. The touch sensor layer can be used to detect user contact and / or non-contact touch. Touch signal line 410 can be positioned in a non-display area NA, and touch electrode 420 can be positioned in a display area DA. Touch signal line 410 can be formed of metal or metal alloy, and touch electrode 420 can be formed of transparent conductive material, metal mesh, and / or conductive polymer. A protective layer 430, acting as an insulating layer, can be positioned on touch signal line 410 and touch electrode 420. Touch electrode 420 can be positioned on touch signal line 410, and vice versa, and touch signal line 410 and touch electrode 420 can be positioned on the same layer. Touch signal line 410 and touch electrode 420 can be positioned inside the encapsulation substrate 210 (i.e., the side facing substrate 110), or touch signal line 410 and touch electrode 420 can be formed in a separate substrate and then attached to the encapsulation substrate 210.

[0114] The sealant 50 can be positioned between the substrate 110 and the encapsulation substrate 210, and the sealant 50 hermetically seals the display panel 10 while bonding the substrate 110 and the encapsulation substrate 210. The drive voltage transmission line DTL, the common voltage transmission line CTL, and the initialization voltage transmission line ITL can each include portions that overlap with the sealant 50 and portions that do not overlap with the sealant 50, and the bridges BD1, BD2, BD3, BR1, BR2, and BR3 can be positioned inside the sealant 50 without overlapping with the sealant 50.

[0115] Figure 15 This is an equivalent circuit diagram of the pixels of a display device according to some example embodiments.

[0116] Reference Figure 15 The pixel PX may include transistors T1 to T7 connected to signal lines 121, 127, 152, 153, 158, 171 and 172, a storage capacitor CS and a light-emitting diode LED.

[0117] Transistors T1 to T7 may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, an initialization transistor T4, an operation control transistor T5, a light-emitting control transistor T6, and a bypass transistor T7.

[0118] Signal lines 121, 127, 152, 153, 158, 171, and 172 may include scan line 121, initialization voltage line 127, pre-stage scan line 152, light emission control line 153, bypass control line 158, data line 171, and drive voltage line 172.

[0119] Scan line 121 transmits the scan signal GW to switching transistor T2 and compensation transistor T3. Pre-amplifier scan line 152 transmits the pre-amplifier scan signal GI to initialization transistor T4. Illumination control line 153 transmits the illumination control signal EM to operation control transistor T5 and illumination control transistor T6. Bypass control line 158 transmits the bypass signal GB to bypass transistor T7. Bypass control line 158 may be the same as or different from pre-amplifier scan line 152.

[0120] Data line 171 can receive the data voltage Vdat, and drive voltage line 172 and initialization voltage line 127 can receive the drive voltage ELVDD and initialization voltage Vint, respectively. Drive voltage line 172 is referenced above. Figure 14 The stated drive voltage transmission line (DTL) is connected. The initialization voltage Vint initializes the drive transistor T1.

[0121] Transistors T1 to T7 each include gate electrodes G1 to G7, source electrodes S1 to S7, and drain electrodes D1 to D7, and the storage capacitor CS includes a first electrode C1 and a second electrode C2. The electrodes of transistors T1 to T7 and the storage capacitor CS can be configured as follows: Figure 15 The ground shown is connected. The anode of the light-emitting diode (LED), which can be used as an organic light-emitting diode, can be connected to the drain electrode D1 of the driving transistor T1 via the light-emitting control transistor T6. The cathode of the LED can receive the common voltage ELVSS via connector 195.

[0122] In the circuit structure of a pixel PX, various modifications can be made to the number of transistors, the number of capacitors, and the connections between transistors and capacitors.

[0123] Figure 16 This is a top plan view of a pixel region in a display device according to some example embodiments. In the following, reference will be made to... Figure 15 and Figure 16 Describe it.

[0124] Scan line 121, pre-amplifier scan line 152, light emission control line 153, and initialization voltage line 127 can extend substantially in the first direction x. A bypass signal GB can be transmitted via pre-amplifier scan line 152. Scan line 121, pre-amplifier scan line 152, and light emission control line 153 can be first gate conductors. Initialization voltage line 127 can be a second gate conductor.

[0125] Data line 171 and drive voltage line 172 may extend substantially in the second direction y. Data line 171 and drive voltage line 172 may be gate conductors.

[0126] In transistors T1 to T7, compensation transistor T3 and initialization transistor T4 have a dual-gate structure, that is, a structure in which the first compensation transistor T3-1 and the second compensation transistor T3-2 are connected and the first initialization transistor T4-1 and the second initialization transistor T4-2 are connected to prevent or reduce leakage current.

[0127] Each channel, source region, and drain region of each of transistors T1 to T7 can be located on a single semiconductor layer 130, which can be bent in various shapes.

[0128] The channels of transistors T1 to T7 may overlap with the gate electrodes of transistors T1 to T7, and may be positioned between the source and drain electrodes of transistors T1 to T7, respectively. For example, the driving transistor T1 includes a channel 130a, a gate electrode 155, a source region 136, and a drain region 137. The channel 130a overlaps with the gate electrode 155 between the source region 136 and the drain region 137. The connector 71 can be connected to the gate electrode 155 through a contact hole 61. For such a connection, the second electrode C2 of the storage capacitor CS may have an opening 56 through which the connector 71 can pass.

[0129] The gate electrode of the switching transistor T2 can be part of the scan line 121. The data line 171 can be connected to the source electrode of the switching transistor T2 through the contact hole 62.

[0130] The compensation transistor T3 may include a first compensation transistor T3-1 and a second compensation transistor T3-2. The gate electrode of the first compensation transistor T3-1 may be part of the scan line 121. The source electrode of the first compensation transistor T3-1 may be connected to the source electrode of the light-emitting control transistor T6 and the drain electrode of the driving transistor T1. The source electrode of the second compensation transistor T3-2 may be connected to the drain electrode of the first compensation transistor T3-1. The gate electrode of the second compensation transistor T3-2 may be a protruding portion of the scan line 121. The connector 71 may be connected to the drain electrode of the second compensation transistor T3-2 through the contact hole 63.

[0131] The initialization transistor T4 may include a first initialization transistor T4-1 and a second initialization transistor T4-2. The gate electrode of the first initialization transistor T4-1 and the gate electrode of the second initialization transistor T4-2 may be part of the front-end scan line 152. Connector 72 may be connected to the source electrode of the first initialization transistor T4-1 through contact hole 65. Connector 71 may be connected to the drain electrode of the second initialization transistor T4-2 through contact hole 63. The drain electrode of the first initialization transistor T4-1 may be connected to the source electrode of the second initialization transistor T4-2.

[0132] As described, when the first compensation transistor T3-1 and the second compensation transistor T3-2 are formed as compensation transistor T3 and the first initialization transistor T4-1 and the second initialization transistor T4-2 are formed as initialization transistor T4, leakage current can be effectively prevented or reduced by blocking the electron movement path of the channel in the off state.

[0133] The gate electrode of the operation control transistor T5 can be part of the light-emitting control line 153. The drive voltage line 172 is connected to the source electrode of the operation control transistor T5 through the contact hole 67.

[0134] The gate electrode of the light-emitting control transistor T6 can be part of the light-emitting control line 153. Connector 73 can be connected to the drain electrode of the light-emitting control transistor T6 via contact hole 69. Connectors 71, 72, and 73 can be data conductors.

[0135] The gate electrode of the bypass transistor T7 can be part of the front-end scan line 152. The connector 73 can be connected to the source electrode of the bypass transistor T7 through the contact hole 81. The drain electrode of the bypass transistor T7 can be connected to the source electrode of the first initialization transistor T4-1.

[0136] The storage capacitor CS may include a first electrode C1 and a second electrode C2 that overlap each other, with a second gate insulating layer 142 disposed between the first electrode C1 and the second electrode C2. The first electrode C1 may correspond to the gate electrode 155 of the driving transistor T1, and the second electrode C2 may be an extension of the storage voltage line 126. The first electrode C1 may be a first gate conductor, and the second electrode C2 may be a second gate conductor.

[0137] The first end of connector 71 can be connected to the first electrode C1 of gate electrode 155 through contact hole 61 and opening 56. The second end of connector 71 can be connected to the drain electrode of the second compensation transistor T3-2 and the drain electrode of the second initialization transistor T4-2 through contact hole 63. Connector 71 can connect the gate electrode 155 of driving transistor T1 to the drain electrode of the second compensation transistor T3-2 and the drain electrode of the second initialization transistor T4-2.

[0138] The drive voltage line 172 can be connected to the second electrode C2 through the contact hole 68. Therefore, the storage capacitor CS can store a charge corresponding to the difference between the drive voltage ELVDD transmitted to the second electrode C2 through the drive voltage line 172 and the gate voltage of the gate electrode 155.

[0139] Connector 72 can be connected to initialization voltage line 127 via contact hole 64. Connector 73 can be connected to pixel electrode 191 via contact hole 81.

[0140] A parasitic capacitance control pattern 125 can be positioned on the opposite side of the gate electrode of the second compensation transistor T3-2. Parasitic capacitors exist within pixels, and image quality characteristics may change when the voltage applied to them changes. A drive voltage line 172 can be connected to the parasitic capacitance control pattern 125 via a contact hole 66. Therefore, changes in image quality characteristics can be prevented or reduced by applying a drive voltage ELVDD, which is a constant DC voltage, to the parasitic capacitor.

[0141] Contact holes 61 to 69 can penetrate the interlayer insulation layer 160 (see...) Figure 13 or Figure 14 The contact holes 61 to 69 are formed therethrough, and depending on the location of the constituent element to be connected, the contact holes may further penetrate the second gate insulating layer 142 (see [reference]). Figure 13 or Figure 14 ) or the second gate insulating layer 142 (see Figure 13 or Figure 14 ) and the first gate insulating layer 141 (see Figure 13 or Figure 14 Contact hole 81 can penetrate planarization layer 180 (see...). Figure 13 or Figure 14 It is formed by ).

[0142] Figure 17 This is a schematic top plan view of a display device according to some example embodiments.

[0143] Regarding Figure 1 The embodiment described differs from the one in which the IC chip 30 is installed in the display panel 10. Regarding... Figure 17 In the described embodiment, the IC chip 30 is mounted in the flexible printed circuit film 20. Therefore, the signal output from the IC chip 30 can be transmitted to the display panel 10 through the pads of the flexible printed circuit film 20 and the pad portion PP of the display panel 10.

[0144] Although aspects of some exemplary embodiments of the inventive concept have been described in conjunction with embodiments which are now considered practical examples, it will be understood that embodiments of the inventive concept are not limited to the exemplary embodiments. Rather, the inventive concept is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims and their equivalents.

Claims

1. A display device, wherein, The display device includes: The display panel includes a display area configured to display an image and a non-display area surrounding the display area. The display panel further includes a substrate and a surface located on the substrate: Multiple driving voltage lines are located in the display area; Multiple initialization voltage lines are located in the display area; Multiple drive voltage transmission lines are located in the non-display area and configured to transmit drive voltage to the multiple drive voltage lines, and the multiple drive voltage transmission lines include a first drive voltage transmission line and a second drive voltage transmission line that are adjacent to each other. An initialization voltage transmission line, located in the non-display area, and configured to transmit an initialization voltage to the plurality of initialization voltage lines; and A bridge connects the first driving voltage transmission line and the second driving voltage transmission line, and overlaps with the initialization voltage transmission line.

2. The display device according to claim 1, wherein, The display panel also includes: A driving voltage bus extends in a first direction between the display area and the plurality of driving voltage transmission lines, and is connected to the plurality of driving voltage transmission lines. The bridge connects the first driving voltage transmission line and the second driving voltage transmission line in the first direction.

3. The display device according to claim 2, wherein, The initialization voltage transmission line is located between the first driving voltage transmission line and the second driving voltage transmission line in the first direction.

4. The display device according to claim 1, wherein, The display panel also includes: A transistor, the transistor being located in the display area; An insulating layer, the insulating layer being located on the transistor; and Pixel electrodes, located on the insulating layer in the display area and connected to the transistor, The bridge and the pixel electrode are located in the same layer, and the bridge is connected to the first driving voltage transmission line and the second driving voltage transmission line through a contact hole located in the insulating layer.

5. The display device according to claim 4, wherein, The display panel also includes: A pixel defining layer, the pixel defining layer being located on the insulating layer and having an opening overlapping the pixel electrode; A common electrode, wherein the common electrode is located on the pixel defining layer in the display area; and A common voltage transmission line, located in the non-display area, is configured to transmit a common voltage to the common electrode. The bridge overlaps with the common voltage transmission line.

6. The display device according to claim 5, wherein, The common voltage transmission line is located between the first driving voltage transmission line and the second driving voltage transmission line.

7. The display device according to claim 1, wherein, The display panel also includes: Multiple integrated circuit chips, The first driving voltage transmission line and the second driving voltage transmission line are connected to different integrated circuit chips among the plurality of integrated circuit chips.

8. The display device according to claim 1, wherein, The display panel also includes: Encapsulation substrate, the encapsulation substrate overlapping the substrate; and A sealant that bonds the substrate to the encapsulation substrate. Each of the first driving voltage transmission line, the second driving voltage transmission line, and the initialization voltage transmission line includes a portion that overlaps with the sealant and a portion that does not overlap with the sealant.

9. A display device, wherein, The display device includes: The display panel includes a display area configured to display an image and a non-display area surrounding the display area. The display panel further includes a substrate and a surface located on the substrate: Pixels, the pixels being located in the display area; A driving voltage line located in the display area and configured to apply a driving voltage to the pixel; Multiple drive voltage transmission lines are located in the non-display area and configured to transmit drive voltage to the drive voltage lines, and the multiple drive voltage transmission lines include a first drive voltage transmission line and a second drive voltage transmission line that are adjacent to each other. A common voltage transmission line, located in the non-display area, transmits a common voltage to the pixel; and A bridge that connects the first driving voltage transmission line and the second driving voltage transmission line and overlaps with the common voltage transmission line.

10. The display device according to claim 9, wherein, The display panel also includes: A driving voltage bus extends in a first direction between the display area and the plurality of driving voltage transmission lines, and is connected to the plurality of driving voltage transmission lines. The bridge connects the first driving voltage transmission line and the second driving voltage transmission line in the first direction, and the common voltage transmission line is located between the first driving voltage transmission line and the second driving voltage transmission line in the first direction.

11. The display device according to claim 9, wherein, The display panel also includes: A transistor, the transistor being located in the display area; An insulating layer, the insulating layer being located on the transistor; and A pixel electrode, which is located on the insulating layer and connected to the transistor. The bridge and the pixel electrode are located in the same layer and are connected to the first driving voltage transmission line and the second driving voltage transmission line through contact holes located in the insulating layer.

12. A display device, wherein, The display device includes: The display panel includes a display area configured to display an image and a non-display area surrounding the display area. The display panel further includes a substrate and a surface located on the substrate: Multiple driving voltage lines are located in the display area; Multiple initialization voltage lines are located in the display area; A first driving voltage transmission line and a second driving voltage transmission line are located in the non-display area and configured to transmit driving voltage to the plurality of driving voltage lines. Each of the first driving voltage transmission line and the second driving voltage transmission line includes a first portion and a second portion extending in different directions, and the first driving voltage transmission line and the second driving voltage transmission line are connected in the first direction through the second portion. An initialization voltage transmission line is provided, located in the non-display area between a first portion of a first driving voltage transmission line and a first portion of a second driving voltage transmission line, wherein the initialization voltage transmission line is configured to transmit an initialization voltage to the plurality of initialization voltage lines and includes a first portion and a second portion that are separated from each other; and A first bridge connects the first portion and the second portion of the initialization voltage transmission line in a second direction that intersects the first direction.

13. The display device according to claim 12, wherein, The display panel also includes: A common voltage transmission line, located in the non-display area between a first portion of a first driving voltage transmission line and a first portion of a second driving voltage transmission line, wherein the common voltage transmission line is configured to transmit a common voltage to the display area and includes a first portion and a second portion separated from each other; and The second bridge connects the first portion and the second portion of the common voltage transmission line in the second direction.

14. The display device according to claim 12, wherein, The display panel also includes: A transistor, the transistor being located in the display area; An insulating layer, the insulating layer being located on the transistor; and A pixel electrode, which is located on the insulating layer and connected to the transistor, wherein the first bridge is located in the same layer as the pixel electrode.

15. The display device according to claim 12, wherein, The display panel also includes: Multiple integrated circuit chips, The first portion of the first driving voltage transmission line and the first portion of the second driving voltage transmission line are connected to different integrated circuit chips among the plurality of integrated circuit chips.

16. A display device, wherein, The display device includes: The substrate includes a display area configured to display an image and a non-display area surrounding the display area; A first voltage transmission line is located in the non-display area and configured to transmit a first voltage, and the first voltage transmission line includes a first first voltage transmission line and a second first voltage transmission line; A second voltage transmission line is located in the non-display area and configured to transmit a second voltage; The first pad portion is located in the non-display area; and The second pad portion is located in the non-display area and is spaced apart from the first pad portion. Wherein, the second voltage transmission line is located in a first direction between the first voltage transmission line and the second first voltage transmission line, and The second voltage transmission line includes a first portion extending from the first pad portion in a second direction intersecting the first direction, a second portion extending from the first portion in the first direction, and a third portion extending from the second portion in the second direction.

17. The display device according to claim 16, wherein, The first part, the second part, and the third part are integrally formed.

18. The display device according to claim 16, wherein, The second voltage transmission line and the first voltage transmission line are connected to the first pad portion, and the second voltage transmission line is connected to the second pad portion.

19. The display device according to claim 16, wherein, The intersection area of ​​the second part and the third part is located between the first part and the second pad part in the first direction.

20. The display device according to claim 16, wherein, The third portion is located between the first pad portion and the second pad portion in the first direction, and does not overlap with either the first first voltage transmission line or the second first voltage transmission line in the second direction.

21. The display device according to claim 16, wherein, The display device further includes: A third voltage transmission line is located in the non-display area and configured to transmit a third voltage. The third voltage transmission line is connected to the first pad portion and does not overlap with the second voltage transmission line in the second direction.

22. The display device according to claim 16, wherein, The display device further includes: Encapsulation substrate, overlapping the substrate; and A sealant is used to bond the substrate and the encapsulation substrate. The second voltage transmission line includes a portion that overlaps with the sealant and a portion that does not overlap with the sealant.

23. A display device, wherein, The display device includes: The substrate includes a display area configured to display an image and a non-display area surrounding the display area; A first voltage transmission line is located in the non-display area and configured to transmit a first voltage, and the first voltage transmission line includes a first first voltage transmission line and a second first voltage transmission line; A second voltage transmission line is located in the non-display area and configured to transmit a second voltage; A first integrated circuit chip is located in the non-display area; and The second integrated circuit chip is located in the non-display area. Wherein, the second voltage transmission line is located in a first direction between the first voltage transmission line and the second first voltage transmission line, and The second voltage transmission line includes a first portion extending from the first integrated circuit chip in a second direction intersecting the first direction, a second portion extending from the first portion in the first direction, and a third portion extending from the second portion in the second direction.

24. The display device according to claim 23, wherein, The second voltage transmission line and the first voltage transmission line are connected to the first integrated circuit chip, and the second first voltage transmission line is connected to the second integrated circuit chip.

25. The display device according to claim 23, wherein, The intersection area of ​​the second part and the third part is located between the first integrated circuit chip and the second integrated circuit chip in the first direction.

26. The display device according to claim 23, wherein, The third portion is located between the first integrated circuit chip and the second integrated circuit chip in the first direction, and does not overlap with either the first first voltage transmission line or the second first voltage transmission line in the second direction.

27. The display device according to claim 23, wherein, The display device further includes: A third voltage transmission line is located in the non-display area and configured to transmit a third voltage. The third voltage transmission line is connected to the first integrated circuit chip and does not overlap with the second voltage transmission line in the second direction.

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