Phase rotator calibration equipment and related methods

Abstract

A phase rotator calibration system is provided. The phase rotator calibration system includes a phase rotator section having an input for receiving an input signal and an output for providing an output signal. A calibration section is coupled to the phase rotator section. The calibration section is configured to determine a phase error based on a phase estimate. The phase estimate is generated using an inverse cosine function.

Description

Technical Field

[0001] This disclosure generally relates to electronic circuits, and more specifically, to phase rotator calibration apparatus and methods. Background Technology

[0002] Today, many integrated circuit (IC) and system-on-a-chip (SoC) devices used in advanced automotive radar systems require high-speed and high-precision operation. IC and SoC devices typically include complex circuitry for controlling these radar systems. As radar systems improve, the demands on control circuitry also increase to meet performance targets. However, balancing product cost while meeting these performance targets remains a challenge. Summary of the Invention

[0003] In general, a circuit is provided, comprising: a phase rotator portion having an input for receiving an input signal and an output for providing an output signal; and a calibration portion coupled to the phase rotator portion, the calibration portion being configured to determine a phase error based on a phase estimate generated by means of an inverse cosine function. The calibration portion may include an inverse cosine circuit block configured to generate the phase estimate based on a digital signal corresponding to the output signal. The calibration portion may be further configured to determine the phase error as the difference between the generated phase estimate and the input signal. The circuit may also include a storage unit coupled to the phase rotator portion, the storage unit being configured to store a phase error value representing the phase error. The phase rotator portion may be configured to predistort the input signal based on the stored phase error value and to generate an adjusted output signal at the output based on the predistorted input signal. The phase rotator section may further include a mixer having a first input coupled to an input of the phase rotator section and a second input coupled to a storage unit and a calibration section. The mixer is configured to receive the input signal at the first input, receive the phase error at the second input, and provide a summed signal at an output signal. The calibration section may further include: a saturation circuit coupled to receive the output signal and configured to generate a saturation signal corresponding to the output signal; and a mixer configured to down-convert the saturation signal to form a down-converted signal. The calibration section may further include an analog-to-digital converter (ADC) configured to receive the down-converted signal and generate a digital signal, the inverse cosine function utilizing a normalized version of the digital signal to generate the phase estimate. The circuitry may further include a switch coupled between the outputs of the phase rotator section and the calibration section, the switch being configured to close during calibration operations.

[0004] In another embodiment, a method is provided, the method comprising: generating an output signal at an output of a phase rotator based on a phase signal received at an input of the phase rotator; coupling a calibration circuit to the phase rotator; receiving the output signal of the phase rotator at an input of the calibration circuit; generating a phase estimate by means of an inverse cosine function of the calibration circuit, the inverse cosine function being configured to generate the phase estimate based on a digital signal corresponding to the output signal; and determining a phase error based on the phase estimate. Determining the phase error may include determining the difference between the generated phase estimate and the phase signal. The method may further comprise storing a phase error value in a storage unit coupled to an input of the phase rotator, the phase error value representing the phase error. The method may further comprise: retrieving the phase error value from the storage unit to predistort the phase signal based on the phase error value; and generating an adjusted output signal at the output of the phase rotator based on the predistorted phase signal. The method may further comprise: saturating the received output signal by means of a saturation circuit to form a saturated signal corresponding to the output signal; and downconverting the saturated signal by means of a mixer to form a downconverted signal. The method may also include generating a digital signal by means of an analog-to-digital converter (ADC), the ADC being configured to receive the down-converted signal.

[0005] In another embodiment, a circuit is provided, comprising: a phase rotator section having an input for receiving a phase signal and an output for providing an output signal; and a calibration section coupled to the phase rotator section, the calibration section being configured to determine a phase error as the difference between a phase estimate and the input signal, the calibration section including an anticosine circuit block configured to generate the phase estimate based on a digital signal corresponding to the output signal. The circuit may further include a storage unit coupled to the phase rotator section, the storage unit being configured to store a phase error value representing the phase error. The phase rotator section may be configured to predistort the phase signal based on the stored phase error value and generate a calibrated output signal at the output based on the predistorted phase signal. The circuit may further include a switch coupled between the outputs of the phase rotator section and the calibration section, the switch being configured to be open during normal operation of the phase rotator section. The calibration section may further include: a saturation circuit coupled to receive the output signal and configured to generate a saturation signal corresponding to the output signal; a mixer configured to down-convert the saturation signal to form a down-converted signal; and an analog-to-digital converter (ADC) configured to receive the down-converted signal and generate a digital signal. Attached Figure Description

[0006] The invention is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. The elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0007] Figure 1 An example phase rotator calibration system according to an embodiment is shown in simplified block diagram form.

[0008] Figure 2 An example phase rotator core according to an embodiment is shown in simplified block diagram form.

[0009] Figure 3 An example calibration method according to an embodiment is shown in the form of a simplified flowchart.

[0010] Figure 4 Example simulation results based on the embodiments are shown in simplified graph form. Detailed Implementation

[0011] In summary, a phase rotator calibration system is provided, comprising calibration circuitry configured to determine a phase error based on a phase estimate during calibration mode. The phase estimate is generated digitally using an inverse cosine function. A phase error value is determined for an input signal swept across a range of phases in predetermined increments. A storage unit is used to store the phase error value during calibration mode. The storage unit also acts as a lookup table to pre-distort the input signal during normal operation mode, thereby providing a calibrated phase rotator output signal.

[0012] Figure 1 An example phase rotator calibration system 100 according to an embodiment is shown in simplified block diagram form. The phase rotator calibration system 100 includes a phase rotator circuit section 120, a calibration circuit section 140, a storage unit 136, and a switching circuit 138. The phase rotator circuit 120 has: a first input labeled PHIN for receiving a phase input signal; a second input labeled CIN for receiving a calibration signal; a third input labeled LO for receiving a local oscillator signal; and an output labeled PHOUT for providing an output signal PHOUT. In this embodiment, the calibration signal is described as a phase error signal. The phase rotator calibration system 100 may be part of a transmitter system, including a power amplifier 114 coupled to receive the PHOUT signal and an antenna 116 coupled to receive the output signal from the power amplifier 114. The calibration circuit 140 has: a first input coupled to the PHOUT output for receiving the PHOUT signal; a second input labeled LO for receiving the local oscillator signal; a third input labeled PHIN for receiving the PHIN signal; and an output coupled to the CIN input and the storage unit 136 by means of a switch 138.

[0013] In this embodiment, the phase rotator circuit 120 has a first (I) signal component path and a second (Q) signal component path configured to generate complex analog signals (e.g., AI and AQ), which are coupled as input signals to the phase rotator core circuit 112. The I signal component path includes a digital circuit block 102 labeled DIG_I and a digital-to-analog converter (DAC) circuit block 104 labeled DAC_I. The digital circuit block 102 includes an input for receiving the PHIN signal and is configured to generate the I signal component of the PHIN signal at the output based on a CORDIC algorithm. For example, the digital circuit block 102 is coupled to receive the PHIN signal and configured to generate a digital I signal component substantially in phase with the PHIN signal. The DAC circuit block 104 includes an input coupled to the output of the digital circuit block 102 to receive the I signal component and is configured to generate an analog signal labeled AI.

[0014] The Q-signal component path includes a mixer 106, a digital circuit block 108 labeled DIG_Q, and a DAC circuit block 110 labeled DAC_Q. The mixer 106 includes a first input for receiving the PHIN signal and a second input for receiving the CIN signal, and is configured to generate a summed signal (e.g., PHIN + phase error). The digital circuit block 108 includes an input for receiving the summed signal and is configured to generate the Q-signal component of the PHIN signal at its output based on a CORDIC algorithm. For example, the digital circuit block 108 is coupled to receive the summed signal from the mixer 106 and is configured to generate a digital Q-signal component that is substantially 90 degrees out of phase with the PHIN signal (+ / - phase error contribution). The DAC circuit block 110 includes an input coupled to the output of the digital circuit block 108 to receive the Q-signal component and is configured to generate an analog signal labeled AQ.

[0015] The phase rotator core 112 is configured and arranged to receive complex analog signals (e.g., AI and AQ) at a first set of inputs, receive an LO signal at another input, and then generate a PHOUT signal at an output labeled PHOUT. In this embodiment, the LO signal is modulated by the corresponding AI and AQ signals and then combined to generate the PHOUT signal.

[0016] The calibration circuit 140 is configured and arranged to receive PHOUT, LO, and PHIN signals at its inputs, and then generate a phase error signal (e.g., PHERR) at its output, which is coupled to the CIN input and the memory cell. In this embodiment, the calibration circuit 140 includes a saturation circuit block 122 labeled SAT, an analog-to-digital converter (ADC) circuit block 126 labeled ADC, a normalization circuit block 128 labeled NORM, an inverse cosine function circuit block 130 labeled ACOS, a filter circuit block 134 labeled FIR, and mixer circuits 124 and 132.

[0017] Saturation circuit 122 is configured to receive the PHOUT signal and then generate a saturation signal 123 corresponding to the PHOUT signal. The saturated version of the PHOUT signal is provided to mixer 124. Mixer 124 is configured to receive the saturation signal 123 at a first input, receive the LO signal at a second input, and then generate a down-converted signal 125 at the output. The down-converted signal 125 is then provided to ADC 126. The ADC is configured to receive the down-converted saturated version of the PHOUT signal at its input and then generate a digital signal 127 representing the down-converted signal at its output. The digital signal 127 is then provided to normalization circuit 128. Normalization circuit 128 is configured to receive the digital signal 127 at its input and then generate a normalized digital signal 129 at its output based on the digital signal. The normalized signal 129 is then provided to anticosine circuit 130. In this embodiment, the anticosine circuit 130 is configured to receive the normalized signal 129 at its input and then generate a phase estimate signal labeled PHEST at its output. The received normalized signal is digitally converted into a phase estimate signal by means of an anticosine function performed by the anticosine circuit 130. The PHEST signal is then provided to the mixer 132.

[0018] Mixer circuit 132 is configured and arranged to generate a phase error signal labeled PHERR based on the difference between the generated phase estimate signal PHEST and the phase input signal PHIN. A first input of mixer 132 is coupled to receive the PHEST signal, and a second input of mixer 132 is coupled to receive the PHIN signal, thereby generating the PHERR signal as the difference between the PHEST and PHIN signals. Filter circuit 134 includes an input coupled to the output of mixer 132 and is configured to provide a filtered phase error signal labeled PHERF at the output. In this embodiment, filter circuit 134 is described as an FIR filter. In this embodiment, the output of filter circuit 134 is coupled to a first terminal of switch 138 to provide the PHERF signal to phase rotator section 120 and storage unit 136 when switch 138 is closed. In other embodiments, the output of mixer circuit 132 may be coupled to a first terminal of switch 138 to provide an unfiltered PHERR signal to phase rotator section 120 and storage unit 136 when switch 138 is closed.

[0019] Switching circuit 138 includes a second end coupled to storage cell 136 and at the CIN input to phase rotator section 120. In this embodiment, switch 138 is configured to close during calibration mode and open during normal operation mode of phase rotator section 120. Storage cell 136 acts as, for example, a lookup table and is configured to store phase error values ​​calculated for corresponding PHIN signal values. During normal operation and during calibration mode, phase error values ​​can be retrieved from storage cell 136 and applied at the CIN input of mixer circuit 106 to pre-distort the PHIN signal. For example, during calibration mode, the phase of the PHIN signal can be swept from 0 to 360 degrees in predetermined increments (e.g., 3-degree increments), and a corresponding phase error value for each increment subsequently written to storage cell 136 is determined. In subsequent iterations, as the PHIN signal is swept from 0 to 360 degrees, the corresponding stored phase error value is read from storage cell 136 and applied at the CIN input to pre-distort the PHIN signal and, for example, compensate for analog defects. The corresponding phase error value for each increment of the optimized phase error value is determined based on the predistorted PHIN signal. A control circuit system (not shown) may be coupled to the memory cell 136 to control operations such as reading and writing to storage locations within the memory cell 136. The memory cell 136 may be formed of any suitable volatile or non-volatile memory element or a combination thereof.

[0020] Figure 2 The embodiments are illustrated in simplified block diagram form. Figure 1Example phase rotator core implementation 200 of circuit block 112. Phase rotator core 112 is configured and arranged to receive AI and AQ signals, LO signal, and then generate PHOUT signal. In this embodiment, phase rotator core 200 includes IQ quadrature separator circuit block 208 labeled IQ, multiplier mixer circuits 202 and 204, and summing circuit 206.

[0021] The IQ circuit block 208 is configured and arranged to receive the LO RF signal and subsequently generate a corresponding complex (IQ) RF signal consisting of a first (I) signal component labeled LOI and a second (Q) signal component labeled LOQ. In this embodiment, the LOI signal component is described as an in-phase signal substantially in phase with the received LO signal, and the LOQ signal component is described as an orthogonal signal substantially 90 degrees out of phase with the received LO signal.

[0022] Mixer 202 has a first input configured to receive an LOI signal, a second input configured to receive an AI signal, and an output configured to provide a first product signal labeled PI. Mixer 204 has a first input configured to receive an LOQ signal, a second input configured to receive an AQ signal, and an output configured to provide a second product signal labeled PQ. Mixer 206 has a first input configured to receive a PI signal, a second input configured to receive a PQ signal, and an output configured to provide a summed output signal labeled PHOUT.

[0023] Figure 3 An example calibration method 300 according to an embodiment is illustrated in simplified flowchart form. In this embodiment, the steps of calibration method 300 correspond to the operation of phase rotator calibration system 100 during calibration mode.

[0024] At step 302, the phase of the input signal PHIN is swept using a predetermined increment. In this embodiment, the control circuitry is configured to sweep the PHIN signal over a range of phases in predetermined increments during the calibration mode of the phase rotator calibration system 100. For example, the phase of the PHIN signal can be swept in 3-degree increments from 0 to 360 degrees for a total of 120 increments. In this embodiment, any suitable phase range can be swept. The predetermined increment value can be selected or determined, for example, based on the minimum step size required to guarantee the specifications or performance targets of the phase rotator 120.

[0025] At step 304, the output signal PHOUT is saturated, the saturated PHOUT signal is down-converted, and the down-converted signal is digitized into a digital signal. In this embodiment, for each phase increment, the corresponding PHOUT signal is saturated by means of saturation circuit 122 to form a saturated version of the PHOUT signal. The saturated PHOUT signal 123 is then down-converted by means of mixer circuit 124 to form a down-converted signal 125. The down-converted signal 125 is then converted into a digital signal 127 by means of ADC 126. At this step, the digital signal 127 corresponds to the down-converted saturated version of the PHOUT signal.

[0026] At step 306, the digitized signal is normalized. In this embodiment, the digital signal 127 corresponding to the down-conversion saturated version of the PHOUT signal is normalized by means of a normalization circuit 128 to form a normalized digital signal 129. For example, when the PHIN signal sweeps across a certain range of phases, the resulting digital signal 127 is converted into a normalized digital signal 129 within a range of minimum value -1.0 and maximum value 1.0.

[0027] At step 308, the normalized signal is converted into a phase estimate and compared with the phase of the input signal. In this embodiment, the normalized digital signal 129 is digitally converted into a phase estimate PHEST by means of an inverse cosine function executed by the inverse cosine circuit 130.

[0028] At step 310, a phase error is generated based on a comparison of the phase estimate PHEST with the phase of the input signal PHIN. In this embodiment, the PHEST signal is compared with the PHIN signal using a mixer 132 to generate a phase error signal PHERR. For example, the PHEST signal and the PHIN signal are received at the input of the mixer 132, and then a PHERR signal is generated at the output of the mixer 132 as the difference between the PHEST signal and the PHIN signal. At this step, the generated PHERR signal can be filtered using a filter circuit 134 to form a filtered phase error signal PHERF.

[0029] At step 312, the generated phase error PHERR for each increment is stored. In this embodiment, for each phase increment, the corresponding PHERR value is stored by means of storage unit 136. For example, when sweeping the phase of the PHIN signal over a range of 0 to 360 degrees, PHERR is generated for every 3-degree phase increment of the PHIN signal, thus forming a lookup table with 120 PHERR values ​​stored (e.g., written) in storage unit 136. Alternatively, the filtered phase error signal PHERF value can be stored for each phase increment instead of the original PHERR signal value. In this embodiment, storage unit 136 can be formed of any suitable volatile or non-volatile memory element or a combination thereof.

[0030] At step 314, the stored phase error is injected into the phase rotator circuit 120. In this embodiment, phase error (e.g., PHERR, PHERF) values ​​are retrieved (e.g., read) from storage unit 136 and injected into the phase rotator circuit 120 by means of mixer 106 to predistort the PHIN signal (e.g., the Q signal component path). The control circuitry of step 302, configured to sweep the PHIN signal in predetermined increments over the phase range, can be further configured to retrieve the corresponding phase error values ​​from storage unit 136 during calibration mode or normal operation mode and apply those phase error values ​​at the CIN input of mixer 106. For example, for each phase of the PHIN signal, the corresponding phase error value can be retrieved and applied at the CIN input to predistort the PHIN signal, thus providing an adjusted or calibrated PHOUT signal associated with each phase. In this embodiment, during normal operation mode, storage unit 136 will act as a lookup table such that for each PHIN phase, the corresponding phase error value is retrieved and used to predistort the PHIN signal to provide a calibrated PHOUT signal. During calibration mode, several iterations can be performed to further optimize the phase error value stored in storage unit 136, thereby improving the overall calibration of the PHOUT signal.

[0031] Figure 4 The embodiments are illustrated in simplified graph form. Figure 1 Example simulation results of the example phase rotator calibration system 100 depicted in the figure. Graph 400 includes the phase error signal PHERF waveform corresponding to three consecutive iterations of calibration method 300. The PHERF waveform is shown, where the phase error value is on the Y-axis and the time value is on the X-axis.

[0032] For example, the simulation results of the phase rotator calibration system 100 during calibration mode are further described below. In this example, it may be necessary to sweep the phase of the PHIN signal in 3-degree increments over a range of 0 to 360 degrees. The phase of the PHIN signal is incremented in 1-microsecond steps to produce each increment phase (e.g., 3, 6, 9, ... 360 degrees). During the first iteration (e.g., iteration 1), a first phase error value is determined for each increment phase by means of calibration circuitry 140 and stored in storage unit 136. Figure 4 The plot shows the relationship between the first phase error value and time for each incrementing phase. Iteration 1 of the simulated Phef waveform shows phase error values ​​exceeding + / - 2 degrees.

[0033] During the second iteration (e.g., iteration 2), the phase error value stored in storage unit 136 during the first iteration is retrieved and applied at the CIN input of mixer 106 to pre-distort the PHIN signal for each incrementing phase. A second phase error value is determined for each incrementing phase by means of calibration circuit 140 and stored in storage unit 136. The second phase error value for each incrementing phase is plotted in the iteration 2 section showing the simulated Phref waveform with improved phase error values.

[0034] During the third iteration (e.g., iteration 3), the improved phase error value stored in storage unit 136 during the second iteration is retrieved and applied at the CIN input of mixer 106 to pre-distort the PHIN signal for each incrementing phase. A third phase error value is determined for each incrementing phase by means of calibration circuit 140 and stored in storage unit 136. The third phase error value for each incrementing phase is plotted in the iteration 3 section of the simulated Phref waveform, which shows a further improved phase error value substantially close to 0 degrees. In some embodiments, for the first and second iterations, it may be necessary to sweep the phase of the PHIN signal sequentially within a range of 0 to 360 degrees, and then for the third iteration, sweep the phase of the PHIN signal in a non-sequential (e.g., random) order within that range to further optimize the calibration process.

[0035] In this example, the calibration process is considered complete once the target phase error result of essentially 0 degrees is achieved at the end of the third iteration. After the calibration process is complete, switch 138 is turned off, and the phase rotator circuit 120 resumes operation in its normal operating mode.

[0036] It should now be understood that a phase rotator calibration system is provided, comprising calibration circuitry configured to determine a phase error based on a phase estimate during calibration mode. The phase estimate is generated digitally using an inverse cosine function. A phase error value is determined for an input signal swept across a range of phases in predetermined increments. A storage unit is used to store the phase error value during calibration mode. The storage unit also acts as a lookup table to pre-distort the input signal during normal operation mode, thereby providing a calibrated phase rotator output signal.

[0037] In general, a phase rotator calibration system is provided. The phase rotator calibration system includes a phase rotator section having an input for receiving an input signal and an output for providing an output signal. A calibration section is coupled to the phase rotator section. The calibration section is configured to determine a phase error based on a phase estimate. The phase estimate is generated by means of an inverse cosine function.

[0038] Since the devices implementing this invention are mostly composed of electronic components and circuits known to those skilled in the art, the circuit details will not be explained to any greater extent than that deemed necessary above in order to understand and comprehend the basic concepts of this invention and to avoid obscuring or departing from its teachings.

[0039] While the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, this specification and figures should be viewed in an illustrative rather than restrictive sense, and all such modifications are intended to be included within the scope of the invention. It is not intended that any benefit, advantage, or solution to a problem described herein with respect to specific embodiments be construed as a key, necessary, or essential feature or element of any or all claims.

[0040] As used in this article, the term “coupling” is not intended to be limited to direct coupling or mechanical coupling.

[0041] Furthermore, as used herein, the term "a" is defined as one or more. Additionally, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed as implying that another claim element introduced by the indefinite article "a" limits any particular claim containing such an introductory claim element to an invention containing only one such element, even when the same claim includes the introductory phrase "one or more" or "at least one" and an indefinite article such as "a". The same applies to the use of definite articles.

[0042] Unless otherwise stated, terms such as “first” and “second” are used to distinguish, arbitrarily, the elements described by such terms. Therefore, these terms are not necessarily intended to indicate a temporal or other priority order of such elements.

Claims

1. A circuit, characterized in that, include: The phase rotator section has an input for receiving an input signal and an output for providing an output signal; as well as A calibration section, coupled to the phase rotator section, is configured to determine the phase error based on a phase estimate generated by means of an inverse cosine function; The calibration section further includes: A saturation circuit, coupled to receive the output signal and configured to generate a saturation signal corresponding to the output signal; as well as A mixer configured to downconvert the saturated signal to form a downconverted signal.

2. The circuit according to claim 1, characterized in that, The calibration section includes: An anticosine circuit block is configured to generate the phase estimate based on a digital signal corresponding to the output signal.

3. The circuit according to claim 1, characterized in that, The calibration section is further configured to determine the phase error as the difference between the generated phase estimate and the input signal.

4. The circuit according to claim 1, characterized in that, In addition, including: A storage unit coupled to the phase rotator portion, the storage unit being configured to store a phase error value representing the phase error.

5. The circuit according to claim 4, characterized in that, The phase rotator section is configured to predistort the input signal based on the stored phase error value and to generate an adjusted output signal at the output based on the predistorted input signal.

6. A phase rotator calibration method, characterized in that, include: An output signal is generated at the output of the phase rotator based on the phase signal received at the input of the phase rotator. Couple the calibration circuit to the phase rotator; The output signal of the phase rotator is received at the input of the calibration circuit; A phase estimate is generated using an inverse cosine function of the calibration circuit, the inverse cosine function being configured to generate the phase estimate based on a digital signal corresponding to the output signal; The phase error is determined based on the phase estimate; The received output signal is saturated by means of a saturation circuit to form a saturation signal corresponding to the output signal; as well as The saturated signal is down-converted using a mixer to form a down-converted signal.

7. The method according to claim 6, characterized in that, Determining the phase error includes determining the difference between the generated phase estimate and the phase signal.

8. The method according to claim 6 or 7, characterized in that, In addition, including: The phase error value is stored in a storage unit coupled to the input of the phase rotator, the phase error value representing the phase error.

9. The method according to claim 8, characterized in that, In addition, including: The phase error value is retrieved from the storage unit to predistort the phase signal based on the phase error value; as well as An adjusted output signal is generated at the output of the phase rotator based on the pre-distorted phase signal.

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