High isolation radio frequency switch

Abstract

The present disclosure relates to high isolation radio frequency switches. Embodiments provide a radio frequency (RF) switch circuit. The switch includes a branch configured and arranged to pass an RF signal coupled at an input node to an output node when a control signal is at a first logic value. A first transistor in the branch includes a first current electrode coupled at the input node and a second current electrode coupled to an intermediate node. The first transistor is formed in a first isolation well coupled to a bias voltage supply terminal. A second transistor in the branch includes a first current electrode coupled to the second current electrode of the first transistor at the intermediate node and a second current electrode coupled at the output node. The second transistor is formed in a second isolation well coupled to the bias voltage supply terminal. A third transistor includes a first current electrode coupled at a first intermediate node and a second current electrode coupled at a first supply terminal.

Description

Technical Field

[0001] This disclosure generally relates to electronic circuits, and more specifically to a high-isolation radio frequency switch circuit. Background Technology

[0002] Today, many high-performance RF and microwave communication devices, such as automotive radar systems, incorporate circuitry configured and arranged to process and manipulate RF and microwave signals. However, such circuit systems may encounter signal leakage current and excessive impedance, resulting in high insertion loss and poor isolation. Therefore, there is a need for circuit systems that can accommodate RF and microwave signals while minimizing leakage current and impedance. Summary of the Invention

[0003] Typically, a circuit is provided, comprising: a first branch coupled between a first input node and a first output node, the first branch being configured and arranged to transmit a radio frequency (RF) signal coupled at the first input node to the first output node when a first control signal is at a first logic value; a first transistor in the first branch, the first transistor having a first current electrode coupled at the first input node and a second current electrode coupled to a first intermediate node, the first transistor being formed in a first isolation well coupled to a bias voltage power supply terminal; a second transistor in the first branch, the second transistor having a first current electrode coupled to the second current electrode of the first transistor at the first intermediate node and a second current electrode coupled to the first output node, the second transistor being formed in a second isolation well coupled to the bias voltage power supply terminal; and a third transistor having a first current electrode coupled at the first intermediate node and a second current electrode coupled to a first power supply terminal. The circuit may further include: a first resistor having a first terminal coupled to receive the first control signal and a second terminal coupled to a control electrode of the first transistor; and a second resistor having a first terminal coupled to receive the first control signal and a second terminal coupled to a control electrode of the second transistor. The circuit may further include: a first resistor having a first end coupled to the bias voltage power supply and a second end coupled to the first isolation well of the first transistor; and a second resistor having a first end coupled to the bias voltage power supply and a second end coupled to the second isolation well of the second transistor. The third transistor may further include a control electrode coupled to receive a second control signal, which is a complementary signal to the first control signal. The third transistor may be formed in a third isolation well directly connected to the bias voltage power supply. The RF signal may be coupled at the first input node by means of a capacitor.The circuit may further include: a second branch coupled between a second input node and a second output node, the second branch being configured and arranged to transmit a second RF signal coupled at the second input node to the second output node when the first control signal is at the first logic value; a fourth transistor in the second branch, the fourth transistor having a first current electrode coupled at the second input node and a second current electrode coupled to a second intermediate node; a fifth transistor in the second branch, the fifth transistor having a first current electrode coupled to the second current electrode of the fourth transistor at the second intermediate node and a second current electrode coupled to the second output node; and a seventh transistor having a first current electrode coupled to the first intermediate node and a second current electrode coupled to the second intermediate node, the seventh transistor being configured to be in a non-conducting state when the first control signal is at the first logic value. The first RF signal and the second RF signal together may be characterized as differential signals. The circuit may further include impedance matching circuitry connected at the first input node and the second input node.

[0004] In another embodiment, a circuit is provided, comprising: a first branch coupled between a first input node and a first output node, the first branch being configured and arranged to transmit an input signal coupled at the first input node to the first output node when a first control signal is at a first logic value; a first transistor in the first branch, the first transistor having a first current electrode coupled at the first input node and a second current electrode coupled to a first intermediate node, the first transistor being formed in a first isolation well coupled to a bias voltage power supply terminal; a second transistor in the first branch, the second transistor having a first current electrode coupled to the second current electrode of the first transistor at the first intermediate node and a second current electrode coupled to the first output node, the second transistor being formed in a second isolation well coupled to the bias voltage power supply terminal; and a third transistor having a first current electrode coupled at the first intermediate node and a second current electrode coupled to a first power supply terminal, the third transistor being formed in a third isolation well directly connected to the bias voltage power supply terminal. The circuit may further include: a first resistor having a first end coupled to receive the first control signal and a second end coupled to a control electrode of the first transistor; and a second resistor having a first end coupled to receive the first control signal and a second end coupled to a control electrode of the second transistor. The third transistor may further include a control electrode coupled to receive a second control signal, the second control signal being a complementary signal to the first control signal. The circuit may further include: a first resistor having a first end coupled to the bias voltage power supply and a second end coupled to the first isolation well of the first transistor; and a second resistor having a first end coupled to the bias voltage power supply and a second end coupled to the second isolation well of the second transistor. The circuit may further include: a second branch coupled between a second input node and a second output node, the second branch being configured and arranged to transmit a second input signal coupled at the second input node to the second output node when the first control signal is at the first logic value; a fourth transistor in the second branch, the fourth transistor having a first current electrode coupled at the second input node and a second current electrode coupled to a second intermediate node; and a fifth transistor in the second branch, the fifth transistor having a first current electrode coupled to the second current electrode of the fourth transistor at the second intermediate node and a second current electrode coupled to the second output node. The first input signal and the second input signal together can be characterized as a differential signal.The circuit may further include an eighth transistor having a first current electrode coupled to the second intermediate node and a second current electrode coupled to the first intermediate node, the eighth transistor being configured to be in an on state when the first control signal is at a second logic value.

[0005] In yet another embodiment, a circuit is provided, comprising: a first branch coupled between a first input node and a first output node, the first branch being configured and arranged to transmit an input signal coupled at the first input node to the first output node when a first control signal is at a first logic value, the first branch comprising: a first transistor having a first current electrode coupled at the first input node, a second current electrode coupled to a first intermediate node, and a control electrode coupled to receive the first control signal; a second transistor having a first current electrode coupled to the second current electrode of the first transistor at the first intermediate node, a second current electrode coupled to the first output node, and a control electrode coupled to receive the first control signal; and a third transistor having a first current electrode coupled to the first intermediate node, a second current electrode coupled to a first power supply terminal, and a control electrode coupled to receive a second control signal, the second control signal being... The first control signal is a complementary signal; the second branch is coupled between the second input node and the second output node, and is configured and arranged to transmit a second input signal coupled at the second input node to the second output node when the first control signal is at the first logic value, the second branch comprising: a fourth transistor having a first current electrode coupled at the second input node, a second current electrode coupled to the second intermediate node, and a control electrode coupled to receive the first control signal; a fifth transistor having a first current electrode coupled to the second current electrode of the fourth transistor at the second intermediate node, a second current electrode coupled to the second output node, and a control electrode coupled to receive the first control signal; and a seventh transistor having a first current electrode coupled to the first intermediate node, a second current electrode coupled to the second intermediate node, and a control electrode coupled to receive the second control signal. The circuit may further include: a first resistor having a first end coupled to receive the first control signal and a second end connected to the control electrode of the first transistor; a second resistor having a first end coupled to receive the first control signal and a second end connected to the control electrode of the second transistor; and a third resistor having a first end coupled to receive the second control signal and a second end connected to the control electrode of the third transistor. Each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor may be formed in a corresponding isolation well.Each isolation well of the first transistor, the second transistor, the fourth transistor, and the fifth transistor can be coupled to a bias voltage power supply by means of a resistor, and each isolation well of the third transistor and the sixth transistor can be directly connected to the bias voltage power supply. Attached Figure Description

[0006] This invention is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. The elements in the drawings are shown for simplicity and clarity, and these elements are not necessarily drawn to scale.

[0007] Figure 1 An example radio frequency switch circuit according to an embodiment is shown in simplified schematic form.

[0008] Figure 2A An example N-channel transistor having a double-well body formed using a triple-well process is shown in simplified cross-sectional view form according to an embodiment.

[0009] Figure 2B The embodiments are illustrated in simplified schematic form. Figure 2A An example of an N-channel transistor with a body connection circuit.

[0010] Figure 3A An example N-channel transistor with a P-well body formed using a triple-well process is shown in simplified cross-sectional view form according to an embodiment.

[0011] Figure 3B The embodiments are illustrated in simplified schematic form. Figure 3A An example of an N-channel transistor with a body connection circuit. Detailed Implementation

[0012] Typically, a radio frequency (RF) switching circuit with high isolation and low impedance is provided. The RF switch is characterized as closed when a control signal is in a first logic state, and as open when the control signal is in a second logic state. The RF switching circuit includes a first branch of a transistor connected in series and a second branch of a transistor connected in series, the first branch and the second branch being coupled to transmit a differential RF signal received at the input to the output. A network of shunt transistors is coupled between the first branch and the second branch to short-circuit leakage signals to ground and improve isolation.

[0013] Figure 1An example radio frequency (RF) switching circuit 100 according to an embodiment is shown in simplified schematic form. The switching circuit 100 is implemented as an integrated circuit and has input terminals labeled INP and INN for receiving differential input signals, output terminals labeled OUTP and OUTN for providing differential output signals, and enable input terminals labeled EN and ENB for receiving corresponding enable control signals EN and ENB. In this embodiment, an example implementation of the switching circuit 100 includes a first switching branch, a second switching branch, a shunt circuit system, and an impedance matching circuit. For illustrative purposes, Figure 1 The transistors depicted are shown as three-terminal devices (e.g., gate, drain, source). Figure 2A and 2B The corresponding block connections and volume connections are shown in 3A and 3B.

[0014] Switching circuit 100 is configured and arranged to close (e.g., conduct) when the control signal EN is in a first state (e.g., logic high) and open (e.g., not conduct) when the control signal EN is in a second state (e.g., logic low). For example, switching circuit 100 is configured and arranged to transmit an RF signal coupled at the input (e.g., INP and INN) to the output (e.g., OUTP and OUTN) when the control signal EN is in a first logic value (e.g., logic high). In this embodiment, the frequency of the RF signal can be in the range of 3 kHz to 300 GHz. For example, the RF signal can be characterized as a microwave signal (e.g., 1 GHz to 100 GHz), a radar signal (e.g., 30 MHz to 130 GHz), a millimeter-wave signal (e.g., 30 GHz to 300 GHz), etc. In this embodiment, the ENB control signal is a complementary signal (e.g., an inverted signal) to the EN control signal.

[0015] The first switching branch includes N-channel MOS transistors 102-104 series coupled between nodes labeled N1 and N3. In this embodiment, transistors 102-104 are formed using a triple-well fabrication process and are configured to have a resistor-connected bulk bias supply (e.g., Figure 2A , 2BThe transistor 102 is a floating double-well structure. The first current electrode of transistor 102 is coupled at node N1, and the second current electrode of transistor 102 is coupled at an intermediate node labeled N2. The first current electrode of transistor 104 is coupled to the second current electrode of transistor 102 at node N2, and the second current electrode of transistor 104 is coupled to node N3. An EN control signal line is coupled to the control electrodes of transistors 102 and 104 by means of resistors 122 and 124. The first end of resistor 122 is connected to the EN control signal line to receive the EN control signal, and the second end of resistor 122 is connected to the control electrode of transistor 102. The first end of resistor 124 is connected to the EN control signal line to receive the EN control signal, and the second end of resistor 124 is connected to the control electrode of transistor 104. In some embodiments, transistors 102-104 may be formed as bipolar junction transistors (BJTs).

[0016] The second switching branch includes N-channel MOS transistors 112-114 series coupled between nodes labeled N4 and N6. In this embodiment, transistors 112-114 are formed using a triple-well fabrication process and configured to have a floating double-well structure with a block bias power supply having resistor connections. A first current electrode of transistor 112 is coupled at node N4, and a second current electrode of transistor 112 is coupled at an intermediate node labeled N5. A first current electrode of transistor 114 is coupled to the second current electrode of transistor 112 at node N5, and a second current electrode of transistor 114 is coupled to node N6. An EN control signal line is coupled to the control electrodes of transistors 112 and 114 by means of resistors 132 and 134. A first end of resistor 132 is connected to the EN control signal line to receive an EN control signal, and a second end of resistor 132 is connected to the control electrode of transistor 112. A first end of resistor 134 is connected to the EN control signal line to receive an EN control signal, and a second end of resistor 134 is connected to the control electrode of transistor 114. In some embodiments, transistors 112-114 may be configured as BJTs.

[0017] The shunt circuit system includes N-channel MOS transistors 106-110 and 116-120 and is configured to shunt a leakage signal between a first switching branch and a second switching branch when the switching circuit 100 is turned off. In this embodiment, transistors 106-110 and 116-120 are formed using a triple-well fabrication process and are configured to have a floating single-well structure (e.g., Figure 3A , 3B ).

[0018] A first current electrode of transistor 106 is coupled at node N2, and a second current electrode of transistor 106 is coupled to a power supply voltage terminal marked GND. In this embodiment, a ground voltage (e.g., 0 volts) is supplied at the GND power supply terminal. A first current electrode of transistor 108 is coupled at node N2, and a second current electrode of transistor 108 is coupled at node N5. A first current electrode of transistor 110 is coupled at node N2, and a second current electrode of transistor 110 is coupled at node N5. The ENB control signal line is coupled to the control electrodes of transistors 106-110 by means of resistors 126-130. A first end of resistor 126 is connected to the ENB control signal line to receive the ENB control signal, and a second end of resistor 126 is connected to the control electrode of transistor 106. A first end of resistor 128 is connected to the ENB control signal line to receive the ENB control signal, and a second end of resistor 128 is connected to the control electrode of transistor 108. The first end of resistor 130 is connected to the ENB control signal line to receive the ENB control signal, and the second end of resistor 130 is connected to the control electrode of transistor 110.

[0019] Transistor 116 has its first current electrode coupled at node N5, and its second current electrode coupled to the GND power supply terminal. Transistor 118 has its first current electrode coupled at node N2, and its second current electrode coupled to node N5. Transistor 120 has its first current electrode coupled at node N2, and its second current electrode coupled to node N5. The ENB control signal line is coupled to the control electrodes of transistors 116-120 via resistors 136-140. The first end of resistor 136 is connected to the ENB control signal line to receive the ENB control signal, and the second end of resistor 136 is connected to the control electrode of transistor 116. The first end of resistor 138 is connected to the ENB control signal line to receive the ENB control signal, and the second end of resistor 138 is connected to the control electrode of transistor 118. The first end of resistor 140 is connected to the ENB control signal line to receive the ENB control signal, and the second end of resistor 140 is connected to the control electrode of transistor 120. In this embodiment, resistors 122-140 are configured to have substantially the same resistance value, wherein the resistance value is in the range of 1 kΩ to 10 kΩ. For example, each of resistors 122-140 may be configured to have a resistance value of 5 kΩ.

[0020] The first impedance matching circuit is coupled at input nodes N1 and N4 and includes capacitors 142-144 and inductor 150. The first terminal of capacitor 142 is coupled to the INP terminal, and the second terminal of capacitor 142 is coupled to node N1. The first terminal of capacitor 144 is coupled to the INN terminal, and the second terminal of capacitor 144 is coupled to node N4. The first terminal of inductor 150 is coupled to node N1, and the second terminal of inductor 150 is coupled to node N5.

[0021] The second impedance matching circuit is coupled at output nodes N3 and N6 and includes capacitors 146-148 and inductor 152. The first terminal of capacitor 146 is coupled to the OUTP terminal, and the second terminal of capacitor 146 is coupled to node N3. The first terminal of capacitor 148 is coupled to the OUTN terminal, and the second terminal of capacitor 148 is coupled to node N6. The first terminal of inductor 152 is coupled to node N3, and the second terminal of inductor 152 is coupled to node N6.

[0022] Figure 2A An example five-terminal N-channel transistor 200 having a double-well body formed using a triple-well process is shown in simplified cross-sectional view according to an embodiment. In this embodiment, transistor 200 corresponds to Figure 1 Transistors 102-104 and 112-114 are depicted in the diagram. Transistor 200 is formed in an isolated P-well 212 and includes a gate electrode 202, labeled G, formed on a gate dielectric 204. The gate electrode 202 typically comprises a polysilicon material, but may comprise any suitable conductive material. The gate dielectric 204 may be formed of any suitable dielectric material, such as a grown or deposited oxide material. Transistor 200 includes an N+ region 206, labeled S, of a first current electrode 206, and an N+ region 208, labeled D, of a second current electrode 208, formed on the opposite side of the gate electrode 202, thereby forming a channel beneath the gate dielectric 204. Transistor 200 may include... Figure 2A Other aspects not shown include, for example, gate electrode contacts, source / drain extension implants, and / or sidewall spacers.

[0023] A P+ well tie 210 provides a connection between the P-well body electrode contact, labeled B, and the P-well body 212. A first body connection resistor 222 is configured to couple the body electrode B of transistor 200 to a GND power supply terminal. The P-well 212 of transistor 200 is formed within a surrounding body isolation N-well 216. The surrounding isolation N-well 216 is formed as a deep N-well or a buried N-well implant, wherein the formed N-type doped or implanted wall portion surrounds the P-well 212. An N+ well tie 214 provides a connection between the isolation N-well electrode contact, labeled IW, and the isolation N-well 216. A second body connection resistor 224 is configured to couple the body isolation electrode IW of transistor 200 to a bias voltage power supply terminal, labeled VB. In this embodiment, for example, a positive voltage, such as the operating voltage of the circuit system (e.g., VDD), can be provided at the VB power supply terminal. The isolation N-well 216 isolates the body P-well 212 from the P-type substrate 220. The P+ substrate tie 218 provides a connection between the substrate electrode contact, labeled SUB, and the P-substrate 220. The gate electrode G, the first current electrode S, and the second current electrode D (e.g., source and drain), the isolated P-well body electrode B, and the body-isolated N-well electrode IW can be characterized as the five terminals of the transistor 200. In this embodiment, when referring to the transistor 200, the term "electrode" may be used interchangeably with the term "terminal".

[0024] Figure 2B An example five-terminal N-channel transistor 230 with a body connection circuit according to an embodiment is shown in simplified schematic form. In this embodiment, transistor 230 corresponds to Figure 2A A cross-sectional example of a five-terminal transistor 200 is shown. Transistor 230 includes a first current electrode (e.g., source) labeled S, a second current electrode (e.g., drain) labeled D, and a control electrode (e.g., gate) labeled G. Transistor 230 further includes a body electrode labeled B and a body isolation electrode (e.g., isolation well) labeled IW. Each of the electrodes S, D, G, B, and IW of transistor 230 corresponds to the corresponding electrode S, D, G, B, and IW in the cross-sectional view of transistor 200. In this embodiment, when referring to transistor 230, the term "electrode" may be used interchangeably with the term "terminal".

[0025] The body connection circuit of transistor 230 includes resistors 222 and 224 coupled to provide corresponding voltages to the body well 212 and the isolation well 216. A first terminal of resistor 222 is connected to the body electrode B, and a second terminal of resistor 222 is connected to the GND power supply terminal. A first terminal of resistor 224 is connected to the body isolation electrode IW, and a second terminal of resistor 222 is connected to the VB power supply terminal. For the sake of clarity regarding the specific body connection, transistor 230 with body connection circuitry can be used instead. Figure 1Each of transistors 102-104 and 112-114 shown.

[0026] In this embodiment, transistor 230 can be characterized as a double-well (e.g., P-well 212 and isolated N-well 216) body floating transistor. For example, during operation (e.g., when switch circuit 100 is closed), resistors 222 and 224 provide an open circuit during the transmission of RF signals through switch 100, thereby reducing insertion loss without affecting the impedance when switch 100 is closed. In this way, intrinsic diodes formed between source region 206 and body region 212, drain region 208 and body region 212, body region 212 and body isolation region 216, and body isolation region and substrate 220 are prevented from being turned on by large signals, thereby improving linearity.

[0027] Figure 3A An example five-terminal N-channel transistor 300 having a double-well body formed using triple-well process technology is shown in simplified cross-sectional view according to an embodiment. In this embodiment, transistor 300 corresponds to Figure 1 Transistors 106-110 and 116-120 are depicted in the diagram. Transistor 300 is formed in an isolated P-well 312 and includes a gate electrode 302, labeled G, formed on a gate dielectric 304. The gate electrode 302 typically comprises a polysilicon material, but may comprise any suitable conductive material. The gate dielectric 304 may be formed of any suitable dielectric material, such as a grown or deposited oxide material. Transistor 300 includes an N+ region 306, labeled S, of a first current electrode 306, and an N+ region 308, labeled D, of a second current electrode 308, formed on the opposite side of the gate electrode 302, thereby forming a channel beneath the gate dielectric 304. Transistor 300 may include... Figure 3A Other aspects not shown include, for example, gate electrode contacts, source / drain extension implants, and / or sidewall spacers.

[0028] P+ interconnect 310 provides a connection between the P-well body electrode contact, labeled B, and the P-well body 312. A body connection resistor 322 is configured to couple the body electrode B of transistor 300 to the GND power supply terminal. The P-well 312 of transistor 300 is formed within a surrounding body isolation N-well 316. The surrounding isolation N-well 316 is formed as a deep N-well or a buried N-well implant, wherein the formed N-type doped or implanted wall portion surrounds the P-well 312. N+ interconnect 314 provides a connection between the isolation N-well electrode contact, labeled IW, and the isolation N-well 316. In this embodiment, the body isolation electrode IW of transistor 300 is directly connected to the bias voltage power supply terminal, labeled VB. The isolation N-well 316 isolates the body P-well 312 from the P-type substrate 320. A P+ substrate connection 318 provides a connection between the substrate electrode contact, labeled SUB, and the P-substrate 320. The gate electrode G, the first current electrode S, and the second current electrode D (e.g., source and drain), the isolated P-well body electrode B, and the body-isolated N-well electrode IW can be characterized as the five terminals of transistor 300. In this embodiment, when referring to transistor 300, the term "electrode" can be used interchangeably with the term "terminal".

[0029] Figure 3B An example five-terminal N-channel transistor 330 with a body connection circuit according to an embodiment is shown in simplified schematic form. In this embodiment, transistor 330 corresponds to Figure 3A A cross-sectional example of a five-terminal transistor 300 is shown. Transistor 330 includes a first current electrode (e.g., source) labeled S, a second current electrode (e.g., drain) labeled D, and a control electrode (e.g., gate) labeled G. Transistor 330 further includes a body electrode labeled B and a body isolation electrode (e.g., isolation well) labeled IW. Each of the electrodes S, D, G, B, and IW of transistor 330 corresponds to the corresponding electrode S, D, G, B, and IW in the cross-sectional view of transistor 300. In this embodiment, when referring to transistor 330, the term "electrode" may be used interchangeably with the term "terminal".

[0030] The body connection circuit of transistor 330 includes a resistor 322 coupled to provide a ground voltage to body well 312 and a direct connection to provide a VB voltage to isolation well 316. A first terminal of resistor 322 is connected to body electrode B, and a second terminal of resistor 322 is connected to the GND power supply terminal. In this embodiment, the body isolation electrode IW is connected to the VB power supply terminal. For the sake of describing the specific body connection, transistor 330 with body connection circuitry can be used instead. Figure 1 Each of transistors 106-110 and 116-120 shown.

[0031] In this embodiment, transistor 330 can be characterized as a single-well (e.g., P-well 312) bulk floating transistor. For example, when switch circuit 100 is off, shunt transistors 106-110 and 116-120 are enabled, causing resistor 322 to provide an open circuit for RF leakage signals, thereby minimizing the Coff impedance of switch 100. In this way, insertion loss and linearity are improved.

[0032] It should now be understood that a radio frequency (RF) switching circuit with high isolation and low impedance has been provided. The RF switch is characterized as closed when the control signal is in a first logic state, and as open when the control signal is in a second logic state. The RF switching circuit includes a first branch of a transistor connected in series and a second branch of a transistor connected in series, the first branch and the second branch being coupled to transmit a differential RF signal received at the input to the output. A network of shunt transistors is coupled between the first branch and the second branch to short-circuit leakage signals to ground and improve isolation.

[0033] Since the devices implementing this invention are mostly composed of electronic components and circuits known to those skilled in the art, the circuit details will not be explained to any greater extent than that deemed necessary above, in order to understand and comprehend the basic concepts of this invention and to avoid obscuring or deviating from its teachings.

[0034] While the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, the specification and figures should be considered illustrative rather than restrictive, and all such modifications are contemplated to be included within the scope of the invention. It is not intended that any advantage, benefit, or solution to the problem described herein with reference to specific embodiments be construed as a key, necessary, or essential feature or element of any or all claims.

[0035] Furthermore, as used herein, the term “a” or “an” is defined as one or more. Similarly, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed as implying that any particular claim containing such an introduced claim element is limited to an invention containing only one such element, even when the same claim includes the introductory phrase “one or more” or “at least one” and an indefinite article such as “a” or “an.” The same applies to the use of definite articles.

[0036] Unless otherwise stated, terms such as “first” and “second” are used to distinguish, arbitrarily, the elements described by such terms. Therefore, these terms are not necessarily intended to indicate temporal or other priorities of such elements.

Claims

1. A high-isolation radio frequency switch circuit, characterized in that, include: A first branch, coupled between a first input node and a first output node, is configured and arranged to transmit a first RF signal coupled at the first input node to the first output node when a first control signal is at a first logic value. The first transistor in the first branch has a first current electrode coupled to the first input node and a second current electrode coupled to the first intermediate node, and the first transistor is formed in a first isolation well coupled to a bias voltage power supply terminal. The second transistor in the first branch has a first current electrode coupled to the second current electrode of the first transistor at the first intermediate node and a second current electrode coupled to the first output node. The second transistor is formed in a second isolation well coupled to the bias voltage power supply terminal. as well as A third transistor, the third transistor having a first current electrode coupled to the first intermediate node and a second current electrode coupled to the first power supply terminal; The second branch is coupled between the second input node and the second output node, and the second branch is configured and arranged to transmit a second RF signal coupled at the second input node to the second output node when the first control signal is at the first logic value. The fourth transistor in the second branch has a first current electrode coupled to the second input node and a second current electrode coupled to the second intermediate node; The fifth transistor in the second branch has a first current electrode coupled to the second current electrode of the fourth transistor at the second intermediate node and a second current electrode coupled to the second output node; as well as The sixth transistor (116) has a first current electrode coupled to the second intermediate node (N5) and a second current electrode coupled to the first power supply terminal; as well as A seventh transistor (108) having a first current electrode coupled to the first intermediate node (N2) and a second current electrode coupled to the second intermediate node (N5), the seventh transistor being configured to be in a non-conducting state when the first control signal is at the first logic value; as well as The eighth transistor (118) has a first current electrode coupled to the second intermediate node (N5) and a second current electrode coupled to the first intermediate node (N2), and is configured to be in an on state when the first control signal is at a second logic value. The first RF signal and the second RF signal together are characterized as differential signals; The third transistor (106), the sixth transistor (116), the seventh transistor (108), and the eighth transistor (118) further include control electrodes coupled to receive a second control signal, which is a complementary signal to the first control signal.

2. The circuit according to claim 1, characterized in that, In addition, including: A first resistor has a first end coupled to receive the first control signal and a second end coupled to the control electrode of the first transistor. as well as The second resistor has a first end coupled to receive the first control signal and a second end coupled to the control electrode of the second transistor.

3. The circuit according to claim 1, characterized in that, In addition, including: A first resistor having a first end coupled to the bias voltage power supply terminal and a second end coupled to the first isolation well of the first transistor; as well as The second resistor has a first end coupled to the bias voltage power supply terminal and a second end coupled to the second isolation well of the second transistor.

4. The circuit according to claim 1, characterized in that: The third transistor is formed in a third isolation well that is directly connected to the bias voltage power supply terminal.

5. The circuit according to claim 1, characterized in that, In addition, including: A third resistor has a first end coupled to receive the second control signal and a second end connected to the control electrode of the third transistor.

6. The circuit according to claim 1, characterized in that, Each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor is formed in a corresponding isolation trap.

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