Semiconductor structure and method of forming the same

Abstract

Embodiments of the present application provide a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises: providing a wafer, the wafer having a front surface and a back surface, the wafer having a conductive plug therein, the conductive plug extending from the front surface to the back surface, and a bottom surface of the conductive plug being located in the wafer; performing an etching process on the back surface of the wafer to form a groove exposing at least the bottom surface of the conductive plug; and forming a functional layer covering the bottom surface of the conductive plug. The present application is beneficial to improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the research and development of 3D chip structures, in order to enhance the thermal conductivity of the chip package, components with good thermal conductivity are usually embedded in the wafer to conduct and dissipate heat at a certain location on the wafer, such as pseudo-conductive plugs.

[0003] During the formation of conductive plugs, when the depth-to-width ratio of the groove used to fill the conductive material and form the protective film is large, the film covering the bottom and sidewalls of the groove formed by the deposition process suffers from poor deposition, leading to performance defects. To address this performance defect, existing technologies typically adjust the poorly deposited areas; however, these technologies have several limitations. Summary of the Invention

[0004] This invention provides a semiconductor structure and a method for forming the same, which is beneficial for improving the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a wafer having a front side and a back side, having a conductive plug within the wafer, the conductive plug extending from the front side to the back side, and having the bottom surface of the conductive plug located within the wafer; performing an etching process on the back side of the wafer to form a groove that at least exposes the bottom surface of the conductive plug; and forming a functional layer covering the bottom surface of the conductive plug.

[0006] In addition, prior to the etching process, a planarization process is performed on the back side of the wafer.

[0007] In addition, the wafer has a plurality of conductive plugs, and the bottom surface heights of the plurality of conductive plugs are different in a direction perpendicular to the back surface of the wafer; the groove exposes the bottom surface of any of the conductive plugs.

[0008] In addition, the groove also exposes a portion of the sidewall of the conductive plug; during the process step of forming the functional layer, the functional layer is also formed on a portion of the sidewall of the conductive plug.

[0009] In addition, the bottom surface of the conductive plug is covered with a protective layer; during the process step of forming the groove, the etching process is also used to remove the protective layer.

[0010] In addition, the functional layer includes a barrier layer covering the bottom surface of the conductive plug and a dielectric layer filling the groove. The barrier layer is used to prevent metal ions in the conductive plug from migrating into the dielectric layer.

[0011] In addition, the material of the dielectric layer includes at least one of silicon dioxide, silicon nitride, or silicon oxynitride, and the material of the barrier layer includes silicon carbonitride.

[0012] In addition, the functional layer includes a bonding layer for performing a melt bonding process.

[0013] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a wafer having a front side and a back side, a conductive plug having a conductive plug extending from the front side to the back side, and the bottom surface of the conductive plug being located within the wafer; a groove having a top opening located on the plane of the back side of the wafer, the groove at least exposing the bottom surface of the conductive plug; and a functional layer covering the bottom surface of the conductive plug.

[0014] Additionally, the groove exposes the bottom surface and part of the sidewall of the conductive plug, and the functional layer covers the bottom surface and part of the sidewall of the conductive plug.

[0015] In addition, in the direction perpendicular to the back side of the wafer, the height difference between the bottom surface of the groove and the bottom surface of the conductive plug is 2nm to 10nm.

[0016] In addition, the functional layer is a stacked structure, which includes a barrier layer covering the bottom surface of the conductive plug and a dielectric layer filling the groove. The barrier layer is used to prevent metal ions in the conductive plug from migrating into the dielectric layer.

[0017] Additionally, the barrier layer may be made of silicon carbonitride, or the barrier layer may consist of a tantalum layer and a tantalum nitride layer stacked sequentially, wherein the tantalum layer covers the bottom surface of the conductive plug and the tantalum nitride layer covers the tantalum layer.

[0018] In addition, the conductive plug and the groove are arranged in a marking pattern.

[0019] Compared with the prior art, the technical solution provided by the embodiments of the present invention has the following advantages:

[0020] In the above technical solution, the etching process is used to expose the bottom surface of the conductive plug, which helps to avoid stress damage to the conductive plug and its adjacent structures during the exposure process, and to prevent structural changes to the conductive plug and its adjacent structures due to stress problems during the exposure process, thereby ensuring that the semiconductor structure has good performance.

[0021] In addition, the groove exposes the bottom surface of any conductive plug, so that the bottom surface of any conductive plug can be covered by the functional layer. This helps to avoid performance defects in the semiconductor structure caused by some conductive plugs not being covered by the functional layer. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments, and unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0023] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step of a method for forming a semiconductor structure.

[0024] Figures 5 to 12 This is a schematic diagram of the structure corresponding to each step of a method for forming a semiconductor structure provided in an embodiment of the present invention;

[0025] Figure 13 This is a schematic diagram of a semiconductor structure provided in another embodiment of the present invention. Detailed Implementation

[0026] refer to Figure 1 The semiconductor structure includes: a wafer 10 having a front side 101 and a back side 102 opposite to the front side 101; a conductive plug 11 having a conductive plug 11 extending from the front side 101 to the back side 102, with the bottom surface of the conductive plug 11 located within the wafer 10; a protective layer 12 covering the bottom surface and sidewalls of the conductive plug 11; and a marking pattern 13 located on the front side 101 of the wafer.

[0027] The protective layer 12 can be a stacked structure. The protective layer 12 may include a barrier layer covering the bottom surface and sidewalls of the conductive plug 11 and a dielectric layer covering the surface of the barrier layer. The barrier layer is used to prevent metal ions in the conductive plug 11 from migrating into the wafer 10, and the dielectric layer is used to prevent leakage of the conductive plug 11.

[0028] As the aspect ratio of the groove accommodating the conductive plug 11 and the protective layer 12 increases, poor deposition problems may occur at the bottom of the groove during the deposition of the protective layer 12. These problems are particularly severe in the bottom corner region, which also includes part of the sidewall of the groove. Poor deposition can prevent the protective layer 12 from achieving adequate protection, leading to performance defects in the semiconductor structure, such as metal ion diffusion within the conductive plug 11 and leakage current in the conductive plug 11.

[0029] In addition, since the marking pattern 13 is located on the front side 101, when processing the back side 102 of the wafer 10, it is necessary to identify and utilize the marking pattern 13 located on the front side 101, which is difficult and has a large alignment error.

[0030] To address the aforementioned technical problem of poor deposition and to ensure good heat dissipation of the conductive plug 11, current processes typically involve processing the bottom surface and sidewalls of the conductive plug 11. The specific steps are as follows:

[0031] refer to Figure 2 A first planarization process is performed to remove the wafer 10 located on the bottom surface of the conductive plug 11, thereby exposing the bottom surface of the conductive plug 11; (Refer to...) Figure 3 An etching process is performed to remove the protective layer 12 covering part of the sidewall of the conductive plug 11 and the wafer 10 located between adjacent conductive plugs 11, so as to expose part of the sidewall of the conductive plug 11, which usually has the problem of poor deposition of the protective layer 12.

[0032] Since the removal rate of planarization is usually greater than that of etching, first using planarization to expose the bottom surface of the conductive plug 11, and then using etching to expose part of the sidewalls of the conductive plug 11, can shorten the cycle of the entire process. However, planarization will generate a certain tensile stress. When planarization is performed with the bottom surface of the conductive plug 11 as the reference, the tensile stress will be applied to the conductive plug 11, causing the conductive plug 11 to continuously apply compressive stress to the surrounding structure during the process. This will cause the conductive plug 11 to delaminate from the protective layer 12, forming the first void 111, and causing part of the protective layer 12 to crack.

[0033] Among them, fragments of the broken protective layer 12 may fall into the first gap 111. When the protective layer 12 and the conductive plug 11 are resealed, the presence of fragments of the protective layer 12 may prevent the protective layer 12 and the conductive plug 11 from sealing effectively. In addition, when the protective layer 12 and the conductive plug 11 are sealed, the presence of fragments of the protective layer 12 may cause stress concentration problems, which may damage the intact protective layer 12.

[0034] refer to Figure 4 A dielectric material is deposited on the back side 102 of wafer 10, and a second planarization process is performed to form a dielectric layer 13 that exposes the bottom surface of the conductive plug 11.

[0035] Since the dielectric layer 13 exposes the bottom surface of the conductive plug 11, the second planarization process is also carried out with the bottom surface of the conductive plug 11 as the reference. In other words, the second planarization process will also pull the conductive plug 11, which will result in a second gap 131 between the conductive plug 11 and the dielectric layer 13, and cause the part of the dielectric layer 13 near the conductive plug 11 to crack.

[0036] Furthermore, protecting the sidewalls of the conductive plug 11 by covering it while exposing the bottom surface of the conductive plug 11 to dissipate heat can cause damage to the conductive plug 11 without other film covering it, and the exposure of the conductive plug 11 itself carries the risk of leakage.

[0037] To address the aforementioned problems, this invention provides a semiconductor structure and its formation method. When exposing the bottom surface of a conductive plug located within a wafer, an etching process is used instead of a planarization process to form a groove that exposes the bottom surface of the conductive plug. This avoids the tensile stress of the planarization process from damaging the conductive plug and the surrounding structure, thereby ensuring that the semiconductor structure has good performance.

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0039] Figures 5 to 12 This is a schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0040] refer to Figure 5 A wafer 20 is provided, the wafer 20 having a front side 201 and a back side 202 opposite to the front side 201, and a conductive plug 21 is provided inside the wafer 20, the conductive plug 21 extending from the front side 201 to the back side 202, and the bottom surface of the conductive plug 21 is located inside the wafer 20.

[0041] In this embodiment, a first preset distance exists between the back surface 202 of the wafer 20 and the bottom surface of the conductive plug 21 in a direction perpendicular to the back surface 202 of the wafer 20. This first preset distance is obtained by performing a thinning process and a planarization process on the back surface 202 of the wafer 20. Compared with the thinning process, the planarization process has a lower removal rate and higher surface finish, and can be used to remove deeper scratches formed during the thinning process.

[0042] Currently, planarization is a process in which a polishing head applies pressure to a polishing pad and rotates the pad, allowing the polishing slurry between the polishing pad and the wafer to be evenly distributed on the wafer surface. This enables the chemical components in the polishing slurry to react with the wafer surface material, converting insoluble substances into soluble substances or softening hard substances. These chemical reactants are then removed through the micro-mechanical friction of the abrasive particles in the polishing slurry, thus achieving planarization.

[0043] When abrasive particles rub against the surface of a structure, they apply tensile stress to that structure. When a structure is an independent component, because adjacent structures are made of different materials, they cannot effectively transmit force, and stress concentration may occur under stress. Therefore, this structure may compress adjacent structures, leading to delamination between the structure and adjacent structures, and causing damage to adjacent structures, such as breakage.

[0044] It should be noted that the tensile stress caused by abrasive grains gradually decreases in the direction away from the friction surface. Therefore, setting the distance between the bottom surface of the conductive plug 21 and the back surface 202 of the wafer 20 to be greater than or equal to the first preset distance helps to avoid the conductive plug 21 being affected by the tensile stress of the planarization process, avoid the conductive plug 21 delaminating from the surrounding film, and avoid the surrounding film cracking.

[0045] After providing wafer 20, an etching process is required on the back surface 202 of wafer 20 to form a groove that exposes the bottom surface of the conductive plug 21. The groove formation process includes the following steps:

[0046] refer to Figure 6 A patterned mask layer 23 is formed on the back side 202 using a mask. In the direction perpendicular to the back side 202, the orthographic projection of the bottom surface of the conductive plug 21 is located within the orthographic projection of the opening of the mask layer 23.

[0047] In this embodiment, the wafer 20 has multiple conductive plugs 21 for heat conduction. The conductive plugs 21 can be fabricated using a through-silicon via (TSV) process. The mask layer 23 has a single opening. (Reference) Figure 7 The orthographic projection of the bottom surface of any conductive plug 21 is located within the orthographic projection of the single opening, which helps to reduce the difficulty of mask fabrication.

[0048] In other embodiments, reference is made to Figure 8 The mask layer 33 has multiple openings, and the orthographic projection of one or more conductive plugs 31 is located within the orthographic projection of one opening. Thus, when there are other intermediate structures between adjacent conductive plugs 31, the intermediate structures will not be exposed or damaged when the wafer 30 is etched with the openings to form a groove that exposes the bottom surface of the conductive plugs 31.

[0049] refer to Figure 9 The back surface 202 of the wafer 20 is etched to form a groove 24 that exposes at least the bottom surface of the conductive plug 21; the mask layer is removed after the groove 24 is formed.

[0050] In this embodiment, the bottom surfaces of the multiple conductive plugs 21 have different heights in the direction perpendicular to the back surface 202 of the wafer 20, and the groove 24 exposes the bottom surface of any conductive plug 21. This helps to ensure that the bottom surface of each conductive plug 21 can cover the functional layer, so as to achieve the effect of the functional layer, such as protection and isolation.

[0051] In this embodiment, the groove 24 also exposes part of the sidewall of the conductive plug 21. Thus, the functional layer formed subsequently can cover part of the sidewall of the conductive plug 21, thereby compensating for the poor deposition of the protective layer 22 located on part of the sidewall of the conductive plug 21, and further improving the performance of the semiconductor structure.

[0052] In this embodiment, the height difference d between the bottom surface of the groove 24 and the bottom surface of the conductive plug 21 is 2nm-10nm, for example, 4nm, 6nm, or 8nm. This helps to ensure that the functional layer formed subsequently can completely cover the corner area of ​​the conductive plug 21, that is, cover the sidewall area of ​​the conductive plug 21 where the protective layer 22 is poorly deposited, thereby ensuring that the semiconductor structure has good performance. In addition, limiting the size of the height difference d helps to ensure that the functional layer material can better cover the sidewall of the conductive plug 21 when filling the functional layer, and also helps to ensure that the functional layer material fills the area between adjacent conductive plugs 21, avoiding premature sealing during filling due to the large depth-to-width ratio of the groove between adjacent conductive plugs 21, and ensuring that the functional layer material has a good filling effect.

[0053] In this embodiment, the bottom surface and sidewalls of the conductive plug 21 are covered with a protective layer 22. During the process of forming the groove 24, the etching process is also used to remove the protective layer 22 located on the bottom surface and part of the sidewalls of the conductive plug 21, so as to expose the bottom surface and part of the sidewalls of the conductive plug 21. In this way, it is beneficial to ensure that the functional layer can be uniformly coated on the surface of the conductive plug 21 to achieve its preset performance.

[0054] Before removing the protective layer 22, it may have already cracked. The surface of the cracked protective layer 22 away from the conductive plug 21 is usually uneven. Applying a functional layer to such an uneven surface can easily result in uneven coating, thus failing to achieve the preset performance. Furthermore, the protective layer 22 may delaminate from the conductive plug 21. In this case, the conductive plug 21 has poor structural stability and may vibrate due to movement of the semiconductor structure. Removing the protective layer 22 and forming a functional layer on the surface of the conductive plug 21 helps to fix the conductive plug 21, improves its structural stability, prevents vibration of the conductive plug 21 from damaging the functional layer, and further ensures that the functional layer can achieve its preset performance. (Reference) Figure 10 This forms a functional layer 25 covering the conductive plug 21.

[0055] In this embodiment, after forming the groove 24, a barrier layer 251, a dielectric layer 252, and a bonding layer 253 are formed sequentially to constitute the functional layer 25. The barrier layer 251 prevents metal ions within the conductive plug 21 from migrating into the wafer 20 and the dielectric layer 252. The dielectric layer 252 prevents leakage from the conductive plug 21. The bonding layer 253 is used for fusion bonding to achieve the connection and packaging of multiple semiconductor structures.

[0056] In this embodiment, before forming the bonding layer 253, the dielectric layer 252 needs to be planarized to ensure that the bonding layer 253 can be formed on the planarized surface, thereby enabling effective connection between different semiconductor structures without the need to set up a unique bonding structure for the connection object.

[0057] To avoid the planarization process of dielectric layer 252 affecting conductive plug 21, protective layer 22 covering conductive plug 21, and barrier layer 251, the distance between the surface of dielectric layer 252 away from barrier layer 251 and the bottom surface of conductive plug 21 in the direction perpendicular to the surface of dielectric layer 252 should be greater than or equal to a second preset distance. The size of the second preset distance is related to the materials of dielectric layer 252 and barrier layer 251. Specifically, the stronger the stress transmission capacity of the materials of dielectric layer 252 and barrier layer 251, the larger the second preset distance should be, so as to avoid large tensile stress acting on conductive plug 21.

[0058] In this embodiment, the functional layer 25 covers the bottom surface of the conductive plug 21, which helps to prevent the conductive plug 21 from being stretched by large stress during subsequent applications, thereby avoiding chip quality risks caused by stress stretching; in addition, it helps to prevent the conductive plug 21 from mis-energizing.

[0059] In this embodiment, the material of the barrier layer 251 includes silicon carbonitride, or includes a tantalum layer and a tantalum nitride layer stacked sequentially, with the tantalum layer covering the surface of the conductive plug 21 and the tantalum nitride layer covering the tantalum layer; the material of the dielectric layer 252 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0060] refer to Figure 11 In this embodiment, the heat dissipation performance of the functional layer 25 can be better than that of the wafer 20. Thus, heat from the front side 201 of the wafer 20 can be conducted through the conductive plug 21 and dissipated from the back side 202 of the wafer 20 through the functional layer 25, preventing the continuous accumulation of heat on the front side 201 of the wafer 20, thereby preventing damage to components located on the front side 201 from high heat; and preventing most of the heat from the front side 201 of the wafer 20 from being dissipated inside the wafer 20, preventing damage to components located inside the wafer 20 from high heat, and ensuring that the semiconductor structure has good performance.

[0061] The functional layer 25 may contain a variety of materials, and at least one material in the functional layer 25 has better heat dissipation performance than the wafer 20.

[0062] In this embodiment, the functional layer 25 not only covers the bottom surface of the conductive plug 21, but also covers part of the sidewall of the conductive plug 21. This increases the contact area between the functional layer 25 and the conductive plug 21, thereby accelerating the heat transfer rate from the conductive plug 21 to the functional layer 25 and ensuring that the heat on the front side 201 can be dissipated at a faster rate.

[0063] In this embodiment, after the functional layer 25 is formed, since the functional layer 25 does not obstruct the view, alignment and positioning can be performed on the bottom surface of the conductive plug 21 when processing the back side of the wafer 20, thereby improving the alignment accuracy of the processing. Preferably, the transparency of the functional layer 25 can be higher than that of the wafer 20.

[0064] In this embodiment, reference Figure 12 The conductive plug 21 and the groove 24 are arranged in a marking pattern; in other embodiments, the conductive plug or groove is a marking pattern.

[0065] In this embodiment, when exposing the bottom surface of the conductive plug located in the wafer, an etching process is used instead of a planarization process to form a groove that exposes the bottom surface of the conductive plug. This avoids the tensile stress of the planarization process from damaging the conductive plug and the film and structure located around the conductive plug, thereby ensuring that the semiconductor structure has good performance.

[0066] Accordingly, embodiments of the present invention also provide a semiconductor structure, which can be fabricated using the semiconductor structure formation method described above.

[0067] refer to Figure 10 The semiconductor structure includes: a wafer 20 having a front side 201 and a back side 202 opposite to the front side 201, a conductive plug 21 extending from the front side 201 to the back side 202, and the bottom surface of the conductive plug 21 being located within the wafer 20; a groove 24 having an opening at the top located on the plane of the back side 202 of the wafer 20, and the groove 24 exposing at least the bottom surface of the conductive plug 21; and a functional layer 25 covering the bottom surface of the conductive plug 21.

[0068] In this embodiment, the groove 24 exposes the bottom surface and part of the sidewall of the conductive plug 21, and the functional layer 25 covers the bottom surface and part of the sidewall of the conductive plug 21.

[0069] In this embodiment, in the direction perpendicular to the back surface 202 of the wafer 20, the height difference between the bottom surface of the groove 24 and the bottom surface of the conductive plug 21 is 2nm to 10nm, for example 3nm, 5nm or 7nm.

[0070] In this embodiment, the functional layer 25 is a stacked structure. The stacked structure 25 includes a barrier layer 251 covering the bottom surface of the conductive plug 21 and a dielectric layer 252 covering the barrier layer 251. The barrier layer 251 is used to prevent metal ions in the conductive plug 21 from migrating into the dielectric layer 252.

[0071] Specifically, the material of the barrier layer 251 includes silicon carbonitride, or the barrier layer 251 includes a tantalum layer and a tantalum nitride layer stacked sequentially, with the tantalum layer covering the surface of the conductive plug 21 and the tantalum nitride layer covering the tantalum layer.

[0072] In this embodiment, the heat dissipation performance of the functional layer 25 is better than that of the wafer 20; the transparency of the functional layer 25 is higher than that of the wafer 20; and the conductive plug 21 and the groove 24 are arranged in a marking pattern.

[0073] In this embodiment, the conductive plug is located in the groove and covered by the functional layer, which helps to avoid the influence of tensile stress and to prevent leakage, thus ensuring that the semiconductor structure has good performance.

[0074] Another embodiment of the present invention provides a semiconductor structure. Unlike the previous embodiment, in this embodiment, the bottom surfaces of the plurality of conductive plugs have the same height, and the bottom surfaces of the conductive plugs have rounded corners. The following will be combined with... Figure 13 Provide a detailed explanation. Figure 13 This is a schematic diagram of a semiconductor structure provided in another embodiment of the present invention. For parts that are the same as or corresponding to those in the previous embodiment, please refer to the corresponding description in the previous embodiment; they will not be repeated hereafter.

[0075] refer to Figure 13 The semiconductor structure includes multiple conductive plugs 31. In a direction perpendicular to the surface of the wafer 30, the bottom surfaces of the multiple conductive plugs 31 have the same height. In addition, the corners between the bottom surface and the sidewalls of the conductive plugs 31 are rounded.

[0076] This embodiment provides a novel semiconductor structure.

[0077] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A wafer is provided having a front side and a back side, and a conductive plug is provided inside the wafer. The conductive plug extends from the front side to the back side, and the bottom surface of the conductive plug is located inside the wafer. The bottom surface and sidewalls of the conductive plug are covered with a protective layer. An etching process is performed on the back side of the wafer to form a groove that exposes the bottom surface and part of the sidewall of the conductive plug. The etching process is also used to remove the protective layer located on the bottom surface and part of the sidewall of the conductive plug. A functional layer is formed covering the bottom surface and part of the sidewalls of the conductive plug.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, Prior to the etching process, the wafer back side is planarized.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The wafer contains a plurality of conductive plugs, and the bottom surfaces of the plurality of conductive plugs are at different heights in a direction perpendicular to the back surface of the wafer; the groove exposes the bottom surfaces and part of the sidewalls of the plurality of conductive plugs.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The functional layer includes a barrier layer covering the bottom surface and part of the sidewall of the conductive plug and a dielectric layer filling the groove. The barrier layer is used to prevent metal ions in the conductive plug from migrating into the dielectric layer.

5. The method for forming a semiconductor structure according to claim 4, characterized in that, The material of the dielectric layer includes at least one of silicon dioxide, silicon nitride, or silicon oxynitride, and the material of the barrier layer includes silicon carbonitride.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, The functional layer includes a bonding layer for performing a melt bonding process.

7. A semiconductor structure, characterized in that, include: A wafer having a front side and a back side, a conductive plug having a conductive plug extending from the front side to the back side, and the bottom surface of the conductive plug being located inside the wafer, the bottom surface and sidewalls of the conductive plug being covered with a protective layer. A groove, the top opening of which is located on the plane of the back side of the wafer, the groove exposing the bottom surface and part of the sidewall of the conductive plug, the groove being obtained by etching the wafer and the protective layer from the back side of the wafer, the remaining protective layer covering at least part of the sidewall of the conductive plug not exposed by the groove; A functional layer that covers the bottom surface and part of the sidewall of the conductive plug exposed by the groove.

8. The semiconductor structure according to claim 7, characterized in that, In a direction perpendicular to the back surface of the wafer, the height difference between the bottom surface of the groove and the bottom surface of the conductive plug is 2nm~10nm.

9. The semiconductor structure according to claim 7, characterized in that, The functional layer is a stacked structure, which includes a barrier layer covering the bottom surface and part of the sidewall of the conductive plug, and a dielectric layer filling the groove. The barrier layer is used to prevent metal ions in the conductive plug from migrating into the dielectric layer.

10. The semiconductor structure according to claim 9, characterized in that, The barrier layer is made of silicon carbonitride, or the barrier layer comprises a tantalum layer and a tantalum nitride layer stacked sequentially, the tantalum layer covering the bottom surface of the conductive plug, and the tantalum nitride layer covering the tantalum layer.

11. The semiconductor structure according to claim 7, characterized in that, The conductive plug and the groove are arranged in a marking pattern.

12. The semiconductor structure according to claim 7, characterized in that, The groove exposes the bottom surface and part of the sidewall of the multiple conductive plugs.

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