A heat dissipation type normally closed heterojunction field effect transistor and manufacturing method

Abstract

The present invention discloses a heat dissipation type normally closed gallium nitride heterojunction field effect transistor structure and a manufacturing method thereof, wherein the device (p-GaN / AlGaN / GaN HFET) comprises a source electrode, a drain electrode, a gate electrode and a passivation layer connected to a heterostructure. The present invention selects aluminum nitride (AlN) as a new passivation layer material, and replaces passivation layers such as silicon nitride and silicon oxide in traditional devices through a full nitride semiconductor process. In order to prevent the two-dimensional electron gas generated on the surface of the AlN passivation layer and the barrier layer from affecting the normally closed state of the device, a layer of AlN is grown using a band engineering design method, and then the passivation layer is etched at intervals to maintain the normally closed state of the device. The normally closed p-GaN / AlGaN / GaN HFET with an AlN passivation layer grown by the present invention can make the lattice temperature in the transistor uniformly distributed and the peak temperature lower when it is turned on, thereby improving the heat dissipation performance of the device. In addition, by using a full nitride semiconductor process to manufacture p-GaN / AlGaN / GaN HFET, the complexity of the device manufacturing process is not affected, and the manufacturing cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of third-generation wide bandgap semiconductor power devices, and in particular to a heat dissipation normally-off heterojunction field effect transistor and a manufacturing method thereof. Background Art

[0002] In semiconductor devices, the operating voltage, operating current and operating frequency of the device are very important indicators, which often determine the working ability of a device. Compared with the first-generation semiconductor materials (silicon, germanium) and the second-generation semiconductor materials (gallium arsenide, indium phosphide, etc.), the third-generation semiconductor material gallium nitride (GaN) has become the preferred material for high-power devices in extreme environments due to its excellent properties such as wide bandgap, high charge density, high voltage resistance, and high electron mobility. Since the two-dimensional electron gas formed at the AlGaN / GaN heterojunction interface has the characteristics of high mobility and high electron density, the high electron mobility transistor based on the AlGaN / GaN heterostructure has superior performance compared with the high electron mobility transistor based on the silicon heterostructure. As a third-generation semiconductor material, GaN and the AlGaN / GaN heterostructure HEMT formed by GaN have broad application potential and good market prospects.

[0003] In recent years, people have been studying GaN materials in depth: on the one hand, people have done a lot of work to optimize the normally-on AlGaN / GaN HEMT, which has a conductive channel when there is no external bias, and needs a negative bias to the gate to form a closed state, and is generally used in low-voltage and high-frequency fields; on the other hand, the normally-off AlGaN / GaN HEMT does not have a conductive channel when there is no external bias, and needs a positive bias to the gate to form an open state, and is generally used as a high-power switch. Because of the huge market potential and the possibility of integrating GaN power switches with integrated Si CMOS circuit technology, people have made many optimizations for normally-off heterojunction field-effect transistors for power switches, and proposed many manufacturing schemes, such as attenuating the two-dimensional electron gas in the area below the gate by local plasma etching, and promoting the depletion of the two-dimensional electron gas by injecting fluorine ions below the gate. The only method used for commercial manufacturing is to grow a p-GaN surface layer on the gate region of the AlGaN surface to deplete the two-dimensional electron gas on the surface of the GaN channel below the gate region. The introduction of this method has greatly promoted the development of normally-off normally-off heterojunction field-effect transistors.

[0004] Temperature fluctuations can affect the intrinsic carrier concentration in semiconductor devices, causing unstable current in the device, thus affecting the working stability of the device; in a high-temperature working environment, the intrinsic carrier concentration of the device will increase dramatically, even far exceeding the ionization concentration of impurities. This situation will destroy the original carrier concentration and transportation capacity in the device, which will seriously affect the normal operation of the device and even cause the device to fail to work. Therefore, another important indicator of normally closed normally closed heterojunction field effect transistors used as power devices under extreme conditions is the uniformity of lattice temperature. The temperature distribution of traditional devices varies greatly when they are turned on, and as the bias voltage applied to the source and drain increases, the lattice temperature distribution in the device will differ even more. At present, there is no effective method to optimize the working heat dissipation performance of normally closed normally closed heterojunction field effect transistors. Summary of the invention

[0005] The purpose of the present invention is to solve the technical problem that the working heat dissipation performance of a normally-off normally-off heterojunction field effect transistor cannot be effectively optimized in the prior art.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] A heat dissipation normally closed heterojunction field effect transistor comprises a passivation layer and a surface layer, wherein the passivation layer is an AlN passivation layer and the surface layer is a p-GaN surface layer.

[0008] Preferably, it also includes a substrate, a nucleation layer, a relaxation layer 1, a relaxation layer 2, a buffer layer, a channel layer and a barrier layer, wherein the substrate, the nucleation layer, the relaxation layer 1, the relaxation layer 2, the buffer layer, the channel layer, the barrier layer and the passivation layer are stacked in sequence.

[0009] Preferably, the nucleation layer is an AlN nucleation layer, and the relaxation layer 1 and the relaxation layer 2 are both AlGaN relaxation layers.

[0010] The present application also provides a method for manufacturing a heat dissipation normally closed heterojunction field effect transistor, which is used to prepare the heat dissipation normally closed heterojunction field effect transistor described above. During the manufacturing process, an AlN passivation layer that needs to be grown is designed through band engineering.

[0011] Preferably, during the manufacturing process, a full nitride semiconductor process is used to manufacture the heterojunction field effect transistor.

[0012] In addition, as a normally closed heterojunction field effect transistor, this device is different from the normally open heterojunction field effect transistor that uses AlN as a passivation layer: in the normally open device, the two-dimensional electron gas generated on the surface of AlN and AlGaN can improve the conductivity of the device, but because it also participates in the conduction, the heating of the device will be more serious; while for the normally closed device, the two-dimensional electron gas generated on the surface of AlN and AlGaN will affect the normally closed property of the device. Therefore, it is necessary to process AlN to block the flow of the two-dimensional electron gas it generates. The present invention chooses to perform band engineering design on AlN, grows a layer of lower quality and thinner AlN, so that the concentration of the two-dimensional electron gas generated at the heterojunction interface is reduced as much as possible, and at the same time, the AlN passivation layer is processed with interval grooves to block the flow of the two-dimensional electron gas. The AlN passivation layer treated in this way can not only ensure the improvement of the heat dissipation effect, but also ensure that the two-dimensional electron gas generated by the AlN / AlGaN heterojunction does not participate in the conduction.

[0013] The present application also provides a method for manufacturing a heat dissipation normally closed heterojunction field effect transistor, the specific preparation process is:

[0014] S1: prepare substrate;

[0015] S2: growing an AlN nucleation layer, an AlGaN relaxation 1 layer, an AlGaN relaxation 2 layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer in sequence on the substrate by MOCVD;

[0016] S3: cleaning samples;

[0017] S4: epitaxial growth of p-GaN surface layer;

[0018] S5: epitaxially grow a lower quality AlN passivation layer through band engineering design;

[0019] S6: Making a gate on the p-GaN surface layer,

[0020] S7: Photolithography of source and drain patterns;

[0021] S8: AlN passivation layer processing by spacing grooves

[0022] S9: making source and drain;

[0023] S10: Packaging.

[0024] The manufacturing method of the normally closed heterojunction field effect transistor described above, through band engineering design, first grows a layer of low-quality AlN passivation layer, and then performs interval groove processing on the passivation layer to block the flow of two-dimensional electron gas on the surface of the AlN / AlGaN heterojunction. The device treated in this way will not affect the generation of two-dimensional electron gas on the surface of the GaN channel layer, and can also block the flow of two-dimensional electron gas on the surface of the AlN / AlGaN heterojunction. And the prepared normally closed heterojunction field effect transistor uses AlN as a passivation layer, which can make the lattice temperature distribution of the transistor more uniform when it is working compared with traditional devices, and reduce its operating peak temperature, effectively improving the heat dissipation capacity of the transistor; at the same time, the full nitride semiconductor process is used in the manufacturing process to achieve manufacturing, reducing the complexity of the manufacturing process, thereby reducing the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a flow chart of a method for manufacturing a normally-off heterojunction field effect transistor in one embodiment of the present invention;

[0026] Figure 2 is a schematic cross-sectional view of a normally-off heterojunction field effect transistor in one embodiment of the present invention;

[0027] Figure 3 An energy band diagram below a heterojunction of a normally-off heterojunction field effect transistor in one embodiment of the present invention;

[0028] Figure 4 A schematic diagram of the location of two-dimensional electron gas generation in a normally-off heterojunction field effect transistor in one embodiment of the present invention;

[0029] Figure 5 The lattice temperature distribution diagram of a normally-off heterojunction field effect transistor and a traditional device under low current working state in one embodiment of the present invention.

[0030] Legend: 01, substrate; 02, AlN nucleation layer; 03, AlGaN relaxation 1 layer; 04, AlGaN relaxation 2 layer; 05, buffer layer; 06, GaN channel layer; 07, AlGaN barrier layer; 08, AlN passivation layer; 09, p-GaN surface layer; 10, source; 11, drain; 12, gate. DETAILED DESCRIPTION

[0031] Partial English interpretation:

[0032] MOCVD: Metal Organic Chemical Vapor Deposition

[0033] PECVD: Plasma Enhanced Chemical Vapor Deposition

[0034] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with specific embodiments.

[0035] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways than those described herein. Therefore, the present invention is not limited to the specific embodiments of the following disclosure.

[0036] A method for manufacturing a normally-off heterojunction field effect transistor, see Figure 1 , including the following steps:

[0037] S1: prepare substrate 01;

[0038] In one embodiment, the substrate 01 is a SiC substrate 01 .

[0039] S2: An AlN nucleation layer 02, an AlGaN relaxation 1 layer 03, an AlGaN relaxation 2 layer 04, an AlGaN buffer layer 05, a GaN channel layer 06 and an AlGaN barrier layer 07 are sequentially grown on the substrate 01 by MOCVD.

[0040] Specifically, in one embodiment, the SIC substrate 01 is placed in a MOCVD reactor and annealed at about 970° C. in an atmosphere of H 2 and NH 3 .

[0041] On SiC, trimethylaluminum (TMAl), trimethylgallium (TMGa), and ammonia (NH3) are used as Al source, Ga source, and N source respectively, and hydrogen (H2) and nitrogen (N2) are used as carrier gases. AlN nucleation layer 02, AlGaN relaxation 1 layer 03, AlGaN relaxation 2 layer 04, buffer layer 05, GaN channel layer 06, and AlGaN barrier layer 07 are grown in sequence by MOCVD.

[0042] In one embodiment, the composition of Al in the grown AlGaN is changed by controlling the gas flow of TMAl and TMGa.

[0043] S3: Clean the sample:

[0044] In one embodiment, the cleaning includes organic cleaning and inorganic cleaning, wherein the organic cleaning step is: first, the sample is placed in a mixture of concentrated sulfuric acid and hydrogen peroxide (concentrated sulfuric acid: hydrogen peroxide = 7:3) and soaked for 10 minutes, and then the sample is placed in a diluted mixture of ammonia (20%) and hydrogen peroxide (diluted ammonia: hydrogen peroxide = 6:1), heated in a water bath for 10 minutes, and the water bath temperature is set to 85°C; then the sample is placed in an aqueous solution of KOH: hydrogen peroxide = 1:2 and soaked for 10 minutes, and finally washed with deionized water;

[0045] The inorganic cleaning steps are as follows: firstly, the sample is ultrasonically placed in acetone for 10 minutes with a power of 100 W to remove organic impurities on the surface of the sample, then the sample is ultrasonically placed in an ethanol solution for 10 minutes with a power of 100 W, and finally, the sample is cleaned in deionized water and stored in an oven (100°C) for 4 minutes.

[0046] S4: epitaxial growth of p-GaN surface layer 09;

[0047] In one embodiment, the specific steps are:

[0048] a. Using MOCVD technology to grow Mg concentration of 5×10 19 cm -3 p-GaN, thickness is 50 nm;

[0049] Specifically, in one embodiment, the substrate 01 is placed in a MOCVD reactor, the temperature is set to rise to 600°C, and a certain amount of reaction precursors such as trimethylgallium (TMGa), ammonia (NH3) and bis(cyclopentadienyl)magnesium (Cp2Mg) are introduced into the reactor at normal pressure to generate the desired p-type GaN. TMGa and NH3 are the main reaction sources for growing GaN, and Cp2Mg is a p-type doping source. The growth rate and doping concentration can be adjusted by adjusting their respective flow rates.

[0050] b. Etching p-GaN except the gate region using inductively coupled plasma (ICP) etching technology;

[0051] In one embodiment, the photolithography machine is AZ1500, and after photolithography and development to expose the non-gate area, the photoresist and developer adhering to the surface of the device are washed away with deionized water, and then dried at 90° C. for 4 minutes to solidify the photoresist;

[0052] c. Use ICP etcher again, with Cl2 as the main etching gas, and the volume flow rates of Cl2, BCl3 and Ar are 14, 10 and 6 cm 2 / min, temperature of 10 ℃, ICP coil power of 600 W, chamber pressure of 4 mTorr, and etching rate of 40 nm / min, the exposed p-GaN was etched away, and then the photoresist was removed;

[0053] S5: Using the band engineering design method, epitaxially grow a low-quality AlN passivation layer 08;

[0054] Specifically, in one embodiment, the S5 comprises the following steps:

[0055] a. Using MOCVD to grow AlN passivation layer;

[0056] Specifically, in one embodiment, the sample is placed in a MOCVD reactor, the temperature is set to rise to 600°C, and a certain amount of TMAl, NH3 and other reaction precursors are introduced into the reactor at normal pressure to generate the desired AlN. TMAl and NH3 are the main reaction sources for growing AlN, and adjusting their respective flow rates can adjust the growth rate and quality.

[0057] b. Use ICP etching technology to etch away the AlN in the gate area;

[0058] In one embodiment, the photolithography machine is AZ1500. After photolithography and development to expose the gate region, the photoresist and developer adhering to the device surface are washed away with deionized water, and then dried at 90° C. for 4 minutes to solidify the photoresist.

[0059] Then an ICP etcher was used with Cl2 as the main etching gas, and the volume flow rates of Cl2, BCl3, and Ar were 14, 10, and 6 cm 2 / min, temperature of 10 ℃, ICP coil power of 600 W, chamber pressure of 4 mTorr, and etching rate of 40 nm / min, the exposed AlN was etched away, and then the photoresist was removed;

[0060] S6: Making a gate 12 on the p-GaN surface layer 09,

[0061] Specifically, in one embodiment, a PVD electron beam evaporation station is used to evaporate Al in the gate 12 region with a thickness of 70 nm, so that the gate 12 metal forms a Schottky contact with the p-GaN surface layer 09;

[0062] S7: Photolithography of the source 10 and the drain 11 patterns.

[0063] Specifically, the AlN passivation layer 08, the AlGaN barrier layer 07 and part of the GaN channel layer 06 in the source 10 and drain 11 regions are etched away using a photolithography etching technique;

[0064] In one embodiment, the photolithography machine is AZ1500. After the source 10 and drain 11 electrode regions are exposed by photolithography and development, the photoresist and developer adhering to the device surface are washed away with deionized water, and then dried at 90° C. for 4 minutes to solidify the photoresist.

[0065] Then an ICP etcher was used with Cl2 as the main etching gas, and the volume flow rates of Cl2, BCl3, and Ar were 14, 10, and 6 cm 2 / min, temperature of 10 ℃, ICP coil power of 600 W, chamber pressure of 4 mTorr, and etching rate of 40 nm / min, the AlN passivation layer 08 and AlGaN barrier layer 07 in the region where the source 10 and drain 11 are to be grown are etched away, and the thickness of the GaN channel layer 06 is etched to 0.02 μm, and then the photoresist is removed;

[0066] S8: performing an interval groove process on the AlN passivation layer 08 and a portion of the AlGaN barrier layer 07, so that a groove of 0.02 μm is formed every 1 μm in the passivation layer;

[0067] Specifically, in one embodiment, the S5 comprises the following steps:

[0068] a. In one embodiment, the photolithography machine is AZ1500. After the photolithography and development expose the area to be grooved, the photoresist and developer adhering to the surface of the device are washed away with deionized water, and the device is dried at 90 ° C for 4 min to solidify the photoresist.

[0069] b. Use ICP etcher again, with Cl2 as the main etching gas, and the volume flow rates of Cl2, BCl3 and Ar are 14, 10 and 6 cm 2 / min, temperature of 10 ℃, ICP coil power of 600 W, chamber pressure of 4 mTorr, and etching rate of 40 nm / min, the exposed AlN and 3 nm AlGaN were etched away, and then the photoresist was removed;

[0070] S9: forming a source electrode 10 and a drain electrode 11 on the region where the GaN channel layer 06 is etched away;

[0071] Specifically, in one embodiment, a PVD electron beam evaporation station is used to evaporate Al in the source and drain regions 11 with a thickness of 70 nm, so that the source 10 and drain 11 metals form Schottky contacts with the GaN channel layer 06;

[0072] S10: Package the sample to isolate the device from the outside air.

[0073] The present application also provides a normally closed heterojunction field effect transistor, which is manufactured using the above-mentioned manufacturing method. Figure 1 ,include

[0074] Specifically, in one embodiment, the SiC substrate 01 has an n-doping concentration of 10 14 cm -3 SiC with a thickness of 2 μm; the AlN nucleation layer 02 has a thickness of 0.005 μm and is not intentionally doped; the relaxation layer 1 material is an unintentionally doped Al 0.5 Ga0.5 N, with a thickness of 0.25 μm; the AlGaN relaxation 2 layer 04 material is non-intentionally doped Al 0.25 Ga 0.75 N, with a thickness of 0.25 μm; the buffer layer 05 is made of non-intentionally doped Al 0.05 Ga 0.95 N, with a thickness of 1.25 μm; the GaN channel layer 06 is Mg doped with a concentration of 10 -16 cm -3 GaN with a thickness of 0.2 μm; the AlGaN barrier layer 07 material is Mg doped with a concentration of 10 15 cm -3 , Si doping concentration is 10 16 cm -3 Al 0.2 Ga 0.95 N, thickness is 0.014 μm.

[0075] As a third-generation wide bandgap semiconductor material, AlN has good thermal conductivity and a thermal conductivity coefficient of about 3.2 W / cm·K, which is four times the thermal conductivity of the raw material silicon nitride, making it a good thermal conductive material. It has high room temperature strength, and its strength decreases slowly with increasing temperature. AlN is very stable and resistant to strong acids and alkalis, making it a good corrosion-resistant material. AlN has good dielectric properties and is an electrical insulator.

[0076] The Sentaurus TCAD simulation software is used to simulate this Example 1. The sProcess module and sDevice module in the software are used to write codes to construct the device structure and the physical model, and thermal analysis is performed on the constructed device structure.

[0077] like Figure 2 The figure shows a cross-sectional view of a normally closed normally closed heterojunction field effect transistor device in this embodiment 1, and its working principle is: when the gate 12 voltage is zero or the gate 12 voltage is lower than the threshold voltage, the two-dimensional electron gas below the gate 12 is exhausted, and the normally closed heterojunction field effect transistor is in a closed state, showing typical normally closed heterojunction field effect transistor characteristics; when the gate 12 voltage is greater than the threshold voltage, the two-dimensional electron gas below the gate 12 is restored, and the restored two-dimensional electron gas connects the two-dimensional electron gas at the interface of the GaN channel layer 06 and the AlGaN barrier layer 07 on both sides below the gate 12, and the normally closed heterojunction field effect transistor is in an open state. In the working state, the surface temperature distribution of the passivation layer of the normally closed heterojunction field effect transistor is effectively controlled, and the working peak temperature is effectively reduced.

[0078] Figure 3The energy band distribution comparison diagram below the heterojunction is obtained by simulating Example 1 and the traditional device using Sentaurus TCAD simulation software. It can be concluded from the figure that the conduction bands of the two devices below the gate 12 region are higher than the Fermi level, and the two-dimensional electron gas here is depleted, while the conduction bands at other positions are lower than the Fermi level, that is, the two-dimensional electron gas exists, and the energy band distribution diagram of Example 1 of the present invention is slightly different from the energy band distribution diagram of the traditional device, indicating that the concentration of the two-dimensional electron gas at this interface changes very little after the passivation layer is changed.

[0079] Figure 4 This is a schematic diagram of the two-dimensional electron gas of Example 1 using band engineering to grow an AlN passivation layer. In the figure, the concentration of the two-dimensional electron gas layer 1 (2DEG1) is relatively small, and due to the spacing groove processing, the two-dimensional electron gas layer 1 cannot participate in the conduction, so AlN is only used as a heat dissipation material; at the same time, the polarization effect produced by AlN and AlGaN does not drastically affect the concentration of the two-dimensional electron gas layer 2 (2DEG2), and the device can work normally.

[0080] Figure 5 The lattice temperature distribution diagram of the low current working state at room temperature is obtained by simulating the traditional device (a) and Example 1 (b) respectively using Sentaurus TCAD simulation software. It can be seen from the figure that when the traditional device is in a low current working state, the temperature distribution is uneven: the highest temperature appears on the surface between the gate 12 and the drain 11, which is higher than 303K; and the lowest temperature appears in the oxide isolation layer, which is 298K, and the difference between the highest and lowest temperatures is about 5K. Since AlN is a material with high thermal conductivity, the heat dissipation performance of the device is greatly improved. When Example 1 is in a low current working state, the temperature distribution is basically uniform, and the difference between the highest and lowest temperatures is less than 0.1K; at the same time, the peak temperature in Example 1 is about 5K lower than the peak temperature of the traditional device. It can be seen that the internal lattice temperature distribution of Example 1 is more uniform than that of the traditional device, and the peak temperature is lower than that of the traditional device. In addition, the effect of improving the heat dissipation performance in Example 1 will be more obvious under high power working conditions.

[0081] Based on the above, Example 1 achieves the purpose of enhancing the heat dissipation performance of the device without affecting the concentration of the two-dimensional electron gas in the channel layer, and making the lattice temperature distribution of the device more uniform.

[0082] The present application provides a method for manufacturing a normally closed heterojunction field effect transistor, wherein the AlN passivation layer 08 grown by band engineering design will not affect the concentration distribution of the two-dimensional electron gas at the interface between the barrier layer and the channel layer, nor will the two-dimensional electron gas generated on the lower surface of the AlN participate in the conduction. In addition, the prepared normally closed heterojunction field effect transistor uses AlN as a passivation layer, which can make the lattice temperature distribution of the transistor more uniform when it is working compared with traditional devices, and reduce its operating peak temperature, effectively improving the heat dissipation capacity of the transistor; at the same time, the full nitride semiconductor process is used in the manufacturing process to achieve manufacturing, reducing the complexity of the manufacturing process, thereby reducing the manufacturing cost.

[0083] It should be noted that the various standard parts used in the present invention are all available on the market, and non-standard parts can be specially customized. The connection methods adopted in the present invention, such as bolt connection, welding, etc., are also very common means in the mechanical field, and the inventor will not go into details here.

[0084] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention shall be included in the scope of the claims of the present invention.

Claims

1. A method for manufacturing a heat dissipation normally closed heterojunction field effect transistor, wherein the heat dissipation normally closed heterojunction field effect transistor comprises a passivation layer and a surface layer, wherein the passivation layer is an AlN passivation layer grown by band engineering design, and the AlN passivation layer is subjected to an interval groove treatment, and the AlN passivation layer and a part of the AlGaN barrier layer are etched to prevent the two-dimensional electron gas on the lower surface of the AlN passivation layer from participating in conduction; The heat dissipation normally closed heterojunction field effect transistor further comprises a substrate, a nucleation layer, a relaxation 1 layer, a relaxation 2 layer, a buffer layer, a channel layer and a barrier layer, wherein: The substrate, the nucleation layer, the relaxation layer 1, the relaxation layer 2, the buffer layer, the channel layer, the barrier layer and the passivation layer are stacked in sequence; the nucleation layer is an AlN nucleation layer, and the relaxation layer 1 and the relaxation layer 2 are both AlGaN relaxation layers; The specific process of preparation is: S1: prepare substrate; S2: growing an AlN nucleation layer, an AlGaN relaxation 1 layer, an AlGaN relaxation 2 layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer in sequence on the substrate by MOCVD; S3: cleaning samples; S4: epitaxial growth of p-GaN surface layer; S5: epitaxially grow a lower quality AlN passivation layer through band engineering design; a. Using MOCVD to grow AlN passivation layer; The sample is placed in a MOCVD reactor, the temperature is set to rise to 600°C, and a certain amount of TMAl and NH3 reaction precursors are introduced into the reactor at normal pressure to generate the required AlN passivation layer; TMAl and NH3 are the main reaction sources for growing the AlN passivation layer, and the growth rate and quality are adjusted by adjusting their respective flow rates; b. Use ICP etching technology to etch and remove the AlN passivation layer in the gate area; The photolithography machine used was AZ1500. After photolithography and development to expose the gate area, the photoresist and developer adhering to the device surface were washed away with deionized water, and then dried at 90°C for 4 minutes to solidify the photoresist. Then use ICP etcher, with Cl2 as main etching gas, and the volume flow rates of Cl2, BCl3 and Ar are 14, 10 and 6 cm 2 / min, temperature of 10°C, ICP coil power of 600W, chamber pressure of 4mTorr, and etching rate of 40nm / min, the exposed AlN passivation layer was etched away, and then the photoresist was removed; S6: Making a gate on the p-GaN surface layer, S7: Photolithography of source and drain patterns; S8: AlN passivation layer processing by spacing grooves S9: making source and drain; S10: Packaging.

2. The method for manufacturing a heat dissipation type normally-off heterojunction field effect transistor according to claim 1, characterized in that: The energy band engineering design method is: by regulating the thickness of the grown AlN passivation layer, the crystal quality, and the stress magnitude, the Fermi level of the AlN / AlGaN heterojunction surface is made lower, that is, the concentration of the generated two-dimensional electron gas is made lower.

3. The method for manufacturing a heat dissipation type normally-off heterojunction field effect transistor according to claim 1, characterized in that: During the manufacturing process, a full nitride semiconductor process is used to manufacture heterojunction field effect transistors.

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