Optimized low ron flatness gate driver

Abstract

This application relates to an optimized low Ron flatness gate driver. An analog switch (100) includes a first field effect transistor (FET) having a first terminal (104) coupled to an input voltage terminal (106), a second terminal (108) coupled to a common source (110), and a control terminal (114) coupled to a common gate (116). The switch (100) includes a second FET having a first terminal (120) coupled to an output voltage terminal (122), a second terminal (124) coupled to the common source (110), and a control terminal (128) coupled to the common gate (116). The switch (100) includes a switching current source having an input (130) coupled to a high voltage supply terminal (132) and an output (134) coupled to the common gate (116). The switch (100) includes a clamping circuit (164) having a first terminal (166) coupled to the common gate (116), a second terminal (168) coupled to the common source (110), and a third terminal (170) coupled to a low voltage supply terminal (140).

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 053,879, filed July 20, 2020, entitled “Optimized Low Ron Flatness Gate,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This manual generally deals with analog switches. Background Technology

[0004] Analog signal switches are used to aggregate inputs and outputs from multiple sources into a signal chain for processing. For example, in a commercial HVAC system, input signals from several temperature sensors can be multiplexed via analog switches into a single amplifier or analog-to-digital (A / D) converter.

[0005] A drawback of existing analog switches is that they introduce errors into the signal chain. Due to variations in the gate-source voltage (Vgs) applied to the biased analog switch, the switch's on-resistance Ron changes, introducing errors into the signal chain. Summary of the Invention

[0006] In one aspect, a switch includes: a first field-effect transistor (FET) having a first terminal coupled to an input voltage terminal, a second terminal coupled to a common source, and a control terminal coupled to a common gate. The switch also includes: a second FET having a first terminal coupled to an output voltage terminal, a second terminal coupled to a common source, and a control terminal coupled to a common gate. The switch further includes: a switching current source having an input terminal coupled to a high-voltage power supply terminal and an output terminal coupled to the common gate. The switching current source supplies gate current to the common gate. The switch includes a third FET coupled between the common gate and a low-voltage power supply terminal. When the third FET is turned on, it connects the common gate to the low-voltage power supply terminal, and when the third FET is turned off, it disconnects the common gate from the low-voltage power supply terminal. The switch also includes a fourth FET coupled between the common source and the low-voltage power supply terminal. When the fourth FET is turned on, it connects the common source to the low-voltage power supply terminal, and when the fourth FET is turned off, it disconnects the common source terminal from the low-voltage power supply terminal. The switch includes a clamping circuit having a first terminal coupled to a common gate, a second terminal coupled to a common source, and a third terminal adapted to be coupled to a low-voltage power supply terminal. The clamping circuit clamps the voltage across the common gate and common source to prevent damage to the first and second FETs and to bias the FETs.

[0007] On the other hand, the clamping circuit includes: an NFET having a drain coupled to a common gate, a gate coupled to the drain, and a source. The clamping circuit also includes: a source follower p-channel field-effect transistor (PFET) having a source coupled to the source of a third NFET, a gate coupled to a common source, and a drain coupled to a low-voltage terminal.

[0008] On the other hand, the switching current source includes: a first current mirror having a first terminal coupled to receive an input current and a second terminal coupled to a low-voltage terminal. The first current mirror provides a first mirror current. The switching current source includes: a second current mirror having a first terminal coupled to a high-voltage terminal and a second terminal coupled to receive the first mirror current. The second current mirror supplies a gate current to a common gate. The switching current source includes: an NFET having a source coupled to the first current mirror, a drain coupled to the second current mirror, and a gate adapted to receive an enable signal. The NFET couples the first current mirror to the second mirror in response to the enable signal.

[0009] In another aspect, a switch includes: a first n-channel field-effect transistor (NFET) having a drain coupled to an input voltage terminal, a source coupled to a common source, and a gate coupled to a common gate. The switch also includes: a second NFET having a drain coupled to an output voltage terminal, a source coupled to a common source, and a gate coupled to a common gate. The switch further includes: a switching current source having an input coupled to a high-voltage power supply terminal and an output coupled to the common gate. The switching current source supplies gate current to the common gate. The switch also includes: a third NFET having a drain coupled to the common gate, a source coupled to a low-voltage power supply terminal, and a gate adapted to receive an inhibit signal. The third NFET, in response to receiving an inhibit signal, connects the common gate to the low-voltage power supply terminal and disconnects the common gate from the low-voltage power supply terminal when the inhibit signal is removed. Finally, the switch includes: a fourth NFET having a drain coupled to a common source, a source coupled to a low-voltage power supply terminal, and a gate coupled to receive an inhibit signal. The fourth NFET, in response to receiving an inhibit signal, connects its common source to the low-voltage power supply terminal and disconnects its common source from the low-voltage power supply terminal when the inhibit signal is removed. The switch includes a clamping circuit having a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal adapted to be coupled to the low-voltage power supply terminal. The clamping circuit clamps the voltage across the common gate and common source.

[0010] On the other hand, the switching current source includes: a fifth NFET having a drain adapted to receive input current, a source coupled to a low-voltage power supply terminal, and a gate coupled to the drain. The switching current source also includes: a sixth NFET having a drain, a source coupled to a low-voltage power supply terminal, and a gate coupled to the gate of the fifth NFET. The sixth NFET mirrors the input current.

[0011] On the other hand, the switching current source includes: a first p-channel field-effect transistor (PFET) having a source, a drain coupled to a high-voltage power supply terminal, and a gate coupled to the drain. The switching current source also includes: a second PFET having a source coupled to the high-voltage power supply terminal, a drain coupled to a common gate, and a gate coupled to the gate of the first PFET. The second PFET mirrors the current through the first PFET and supplies gate current to the common gate. Finally, the switching current source includes: a seventh NFET having a drain coupled to the drain of the first PFET, a source coupled to the drain of a sixth NFET, and a gate adapted to receive an enable signal. In response to the enable signal, the seventh NFET couples the sixth NFET to the first PFET.

[0012] On the other hand, the clamping circuit includes: an eighth NFET having a drain coupled to a common gate, a gate coupled to the drain, and a source. The clamping circuit also includes: a source follower PFET having a source coupled to the source of the eighth NFET, a gate coupled to a common source, and a drain coupled to a low-voltage terminal. Attached Figure Description

[0013] Figure 1 This is a block diagram of an analog switch in an exemplary embodiment.

[0014] Figure 2 This is a schematic diagram of an analog switch in an exemplary embodiment.

[0015] Figures 3A-3B and Figure 4 The analog waveform in the analog switch is shown in an exemplary embodiment.

[0016] The same or similar (functional and / or structural) features are indicated by the same reference numerals or other reference numerals in the accompanying drawings. Detailed Implementation

[0017] Figure 1This is a block diagram of an analog switch 100 according to an exemplary embodiment. The analog switch 100 can be used, for example, to aggregate inputs and outputs from multiple sources into a signal chain, or to multiplex inputs from multiple sources. Switch 100 includes a clamping circuit CLAMP 164 that tracks an input voltage Vin. The input voltage Vin is used as a reference to generate a floating gate-source voltage. A floating gate-source voltage (also called a clamping voltage VCLAMP) is applied between the common gate and common source of switch 100 to bias switch 100. The clamping circuit CLAMP 164 increases the range of the on-resistance Ron flatness of switch 100 while biasing switch 100 with a low gate-source voltage. The advantage of biasing switch 100 with a low gate-source voltage is that no charge pump is required to turn on switch 100, which reduces the die area required to fabricate switch 100 in a semiconductor integrated circuit (IC) (e.g., switch 100 can be implemented on a single semiconductor die).

[0018] Switch 100 includes: a first FET MN1 having a first terminal 104 (e.g., drain) coupled to an input voltage terminal 106 and a second terminal 108 (e.g., source) coupled to a first common terminal 110 (referred to as common source 110). FET MN1 has a control terminal 114 (e.g., gate) coupled to a second common terminal 116 (referred to as common gate 116). Switch 100 includes: a second FET MN2 having a first terminal 120 (e.g., drain) adapted to be coupled to an output voltage terminal 122 and a second terminal 124 (e.g., source) coupled to common source 110. FET MN2 has a control terminal 128 (e.g., gate) coupled to common gate 116. In one exemplary embodiment, MN1 and MN2 are back-to-back coupled (e.g., the sources of FET MN1 and FET MN2 are coupled together) high-voltage FETs.

[0019] Switch 100 includes a switching current source I_SC having an input terminal 130 coupled to a voltage supply terminal 132 and an output terminal 134 coupled to a common gate 116. The switching current source I_SC supplies a gate current (e.g., of approximately 55 µA) to the common gate 116 to turn on / off FETs MN1 and FET MN2. An advantage of the switching current source I_SC is that it allows for a lower cutoff current when switch 100 is in the off state. In other embodiments, a constant current source may be used instead of the switching current source I_SC. The high-voltage power supply terminal 132 may be coupled to a high-voltage power supply VDD (e.g., approximately 24 V). The high-voltage power supply terminal 132 may be a voltage source supplying a voltage higher than the oxide breakdown voltage of MN1 and MN2.

[0020] Switch 100 includes a third FET MN3 coupled between a common gate 116 and a low-voltage power supply terminal 140. When MN3 is on (i.e., closed), FET MN3 couples the common gate 116 to the low-voltage power supply terminal 140, and when MN3 is off (i.e., open), FET MN3 disconnects the common gate 116 from the low-voltage power supply terminal 140. The low-voltage power supply terminal 140 may be coupled to a low-voltage power supply VSS (e.g., ground or approximately -24V) via a diode D1 (e.g., a Schottky diode).

[0021] Switch 100 includes a fourth FET MN4 coupled between a common source 110 and a low-voltage power supply terminal 140. When MN4 is turned on (i.e., closed), FET MN4 couples the common source 110 to the low-voltage power supply terminal 140, and when MN4 is turned off (i.e., open), it disconnects the common source 110 from the low-voltage power supply terminal 140.

[0022] In one exemplary embodiment, MN1 is an n-channel metal-oxide-semiconductor field-effect transistor (NFET) having a drain (104), a source (108), and a gate (114), and MN2 is an NFET having a drain (120), a source (124), and a gate (128). Sources 108 and 124 are coupled to form a common source 110, and gates 114 and 128 are coupled to form a common gate 116. Input voltage terminal 106 can be coupled to an input voltage Vin, high-voltage terminal 132 can be coupled to a high-voltage power supply VDD, and low-voltage terminal 140 can be coupled to a low-voltage power supply VSS. Switch 100 provides an output voltage Vout at output terminal 122.

[0023] Switch 100 includes a clamping circuit 164 having a first terminal 166 coupled to a common gate 116, a second terminal 168 coupled to a common source 110, and a third terminal 170 adapted to be coupled to a low-voltage power supply terminal 140. The clamping circuit 164 applies a clamping voltage VCLAMP across the common gate 116 and the common source 110. As described below, the clamping voltage VCLAMP biases MN1 and MN2 and protects MN1 and MN2 from damage. In one exemplary embodiment, VCLAMP is set at a level sufficient to bias MN1 and MN2 at Vgs (gate-source voltage) (e.g., less than 3.0V or 2.5V), and within the safe operating voltage range of MN1 and MN2.

[0024] Figure 2It is a schematic diagram of a switch 100 according to an exemplary embodiment. The switch 100 comprises: an NFET MN1 having a drain 104, a source 108 and a gate 114. The switch 100 comprises: an NFET MN2 having a drain 122, a source 124 and a gate 128. The sources 108 and 124 are coupled to form a common source 110, and the gates 114 and 128 are coupled to form a common gate 116.

[0025] The switch 100 comprises: an NFET MN3 having a drain 150 coupled to the common gate 116 and a source 152 coupled to a low-voltage terminal 140. The switch 100 comprises: an NFET MN4 having a drain 156 coupled to the common source 110 and a source 158 coupled to the low-voltage terminal 140. FET MN3 and FET MN4 have respective gates 154 and 155 coupled to receive an inhibition signal DISABLE. In Figure 2 the illustrated exemplary embodiment, the back gates of transistors MN3 and MN4 are connected to the low-voltage power supply terminal 140.

[0026] In one exemplary embodiment, the low-voltage power supply terminal 140 is coupled to a low-voltage power supply VSS via a diode D1, and is also coupled to an input voltage Vin via a diode D2 in some exemplary embodiments. Diodes D1 and D2 together act as a "diode OR", which sets the anodes of D1 and D2 at a voltage level equal to the lower of Vin or VSS. The effect is that when VSS>Vin and also when Vin<VSS, by pulling the common source 110 to the lower of Vin and VSS, the switch 100 can be turned off and conduction of the body diode from Vin to VSS (not shown in Figure 2 the figures) is prevented.

[0027] In one exemplary embodiment, the switching current source I_SC is implemented by a first current mirror CM1 and a second current mirror CM2, which are coupled together via a FET MN7 to turn on the switch 100. The first current mirror CM1 comprises: a fifth NFET MN5 having a drain 210 adapted to be coupled to receive an input current Is, and a source 212 coupled to the low-voltage power supply terminal 140. The NFET MN5 has a gate 214 coupled to the drain 210. The first current mirror CM1 comprises: a sixth NFET MN6 having a drain 220, a source 222 coupled to the low-voltage power supply terminal 140, and a gate 224 coupled to the gate 214 of MN4. The sixth NFET MN6 mirrors the input current Is flowing through MN5.

[0028] The second current mirror CM2 includes a first p-channel metal-oxide-semiconductor field-effect transistor (PFET) MP1, having a source 230 coupled to a high-voltage power supply terminal 130, a drain 232 coupled to the drain 232, and a gate 234 coupled to the drain 232. The second current mirror CM2 also includes a second PFET MP2, having a source 240 coupled to the high-voltage power supply terminal 130, a drain 242 coupled to a common gate 116, and a gate 244 coupled to the gate 234 of the PFET MP1. The second PFET MP2 mirrors the current through the first PFET MP1 and supplies gate current to the common gate 116 via a current mirror formed by transistors MP3 and MP4.

[0029] The switching current source I_SC includes a seventh NFET MN7 having a drain 250 coupled to a drain 232 of a first PFET MP1 and a source 252 coupled to a drain 220 of a sixth NFET MN6. The seventh NFET MN7 has a gate 256 coupled to receive an enable signal ENABLE. In response to the enable signal ENABLE, NFET MN7 couples the sixth NFET MN6 to the first PFET MP1.

[0030] In some implementations, to protect MP2 by preventing voltages VDD-VSS from being applied to it, a second current mirror CM2 is coupled to a common gate 116 using a pair of PFETs MP3 and MP4. PFET MP4 is coupled between PFET MP2 and the common gate 116, and PFET MP3 is coupled between PFET MP1 and NFET MN7. Therefore, the second current mirror CM2 is electrically connected to the common gate 116 via PFET MP4, and is electrically connected to the first current mirror CM1 via PFET MP3 and NFET MN7.

[0031] Because the gates 214 and 224 of MN5 and MN6 are interconnected, and the sources 212 and 222 of MN5 and MN6 are interconnected, the current through MN5 is mirrored by MN6. When MN7 is turned on by applying the enable signal ENABLE, the drain 232 of MP1 is coupled to the drain 220 of MN6, resulting in the current through MP1 flowing through MN6. Because the gates 234 and 244 of MP1 and MP2 are interconnected, and the sources 230 and 240 of MP1 and MP2 are interconnected, the current through MP1 is mirrored by MP2.

[0032] In one exemplary embodiment, the sizes of MN5 and MN6 are set such that the input current through MN5 is mirrored 10 times by MN6. Therefore, if the input current through MN5 is, for example, 1µA, the current through MN6 is approximately 10µA. Since the current through MN6 is approximately equal to the current through MP1, the 10µA current also flows through MP1. In one exemplary embodiment, the sizes of MP1 and MP2 are set such that the current through MP1 is mirrored 5 times by MP2. Therefore, if the current through MP1 is 10µA, the current through MP2 is approximately 50µA. The effect is that 50µA of gate current is supplied to the common gate 116 through MP4.

[0033] In one exemplary embodiment, the clamping circuit 164 includes: an NFET MN8 having a drain 260 coupled to a common gate 116 and a gate 262 coupled to the drain 260. The NFET MN8 has a source 264. The clamping circuit 164 includes: a source follower PFET MPSF having a source 270 coupled to the source 264 of the FET MN8 and a gate 272 coupled to a common source 110. The source follower PFET MPSF has a drain 274 coupled to a low-voltage terminal 140.

[0034] For example, consider supplying a 50µA gate current to the common gate 116. Consequently, the gate-source voltages (Vgs) of MN1 and MN2 begin to rise. When Vgs rises above the threshold voltage Vt (e.g., MN1 and MN2 are in the Miller region), MN1 and MN2 conduct, causing the input voltage Vin to appear at the common source 110 and Vout 122. As MN1 and MN2 conduct and enter the Rds enhancement region, the voltage at the common gate 116 rises again until the PFET MPSF turns on. The effect is that the clamping circuit 164 clamps the voltage between the common gate 116 and the common source 110 to VCLAMP and prevents the voltage at the common gate 116 from rising further. The clamping voltage VCLAMP is set below the secondary overvoltage protection limit (e.g., 6.5V) but above the threshold voltage Vt required to allow MN1 and MN2 to conduct. By clamping the voltage between the common gate 116 and the common source 110 at VCLAMP, the clamping circuit 164 prevents damage to FETs MN1 and FET MN2 and also biases FETs MN1 and FET MN2 so that they can conduct. In one exemplary embodiment, VCLAMP is set to less than 3.0V (e.g., approximately 2.5V).

[0035] Zener diode D1 is connected between the common source 110 and the common gate 116. Zener diode D1 has an anode connected to the common source 110 and a cathode connected to the common gate 116. When switch 100 is on, Zener diode D1 provides secondary overvoltage protection in the positive direction, and when switch 100 is off (i.e., MN1 and MN2 are off) and MN3 and MN4 are on, Zener diode D1 also provides secondary overvoltage protection in the negative direction (source-gate).

[0036] To apply the input signal Vin from input terminal 106 to output terminal 120, the disable signal DISABLE is removed from gates 154 and 156 of MN3 and MN4. As a result, common gate 116 and common source 110 are released from low-voltage terminal 140. Simultaneously, enable signal ENABLE is applied to gate 256 of MN7, thereby coupling the first current mirror CM1 to the second current mirror CM2. When gate current is supplied to common gate 116, the voltage at common gate 116 rises, thereby turning on NFETs MN1 and NFET MN2. As a result, input voltage Vin is coupled to common source 110 and Vout 122. Because the gate 272 of the source follower PFET MPSF is coupled to common source 110, the source follower MPSF conducts as the voltage at common source 110 rises above the threshold voltage required to turn on the source follower PFET MPSF. Therefore, the voltage at the source 270 of the source follower MPSF rises to above Vgs at the common source 110 (i.e., the voltage across the gate and source of the MPSF). Because the gate 262 of the NFET MN8 is coupled to the drain 260, the NFET MN8 conducts. The effect is that the voltage across the common gate 116 and common source 110 is approximately the sum of the voltage across the NFET MN8 (i.e., the voltage between the short-circuited drain / gate and source of MN8, sometimes referred to as a diode-connected NFET) and the Vgs of the source follower MPSF. By selecting MN8 and the source follower MPSF, the voltage across the common gate 116 and common gate 110 is set to the desired level. In one exemplary embodiment, by setting the width and length of MN8 and MPSF, the voltage across the common gate 116 and common source is set to approximately 2.5V, which is significantly lower than the secondary overvoltage protection provided by the Zener diode Z1 (e.g., 6.5V), but sufficient to bias NFETs MN1 and MN2 to conduct. Therefore, clamping circuit 164 clamps the voltage across the common gate 116 and common source 110 to a level that prevents damage to NFETs MN1 and MN2, while biasing MN1 and MN2 so that they can conduct.

[0037] In one exemplary embodiment, NFETs MN1 and MN2 are biased by VCLAMP at approximately 2.5V, instead of being biased at, for example, 5V. As a result, the on-resistance Ron (defined as the equivalent resistance between input terminal 106 and output terminal 122) exhibits a flat response over a wider input voltage range. Figures 3A-3B The diagram shows analog waveform 304 representing R-on against Vin and analog waveform 308 representing Vgs against Vin. Figure 3A In the diagram, the x-axis represents the input voltage Vin (volts), and the y-axis represents Ron (ohms). As Vin rises from 14V to approximately 21V, Ron remains flat, thus exhibiting flatness over a wide Vin range. When Vin reaches approximately VDD-3V, Ron begins to rise.

[0038] exist Figure 3B In the diagram, the x-axis represents the input voltage Vin, and the y-axis represents the gate-source voltage Vgs. As Vin rises to 21V, Vgs remains flat, thus providing a stable bias voltage for FETs MN1 and FET MN2 over a wide Vin range. Therefore, clamping circuit 164 provides a stable clamping voltage across the common gate 116 and common source 110 over a wide Vin range.

[0039] Figure 4 The diagram shows the analog waveform of Ron versus Vgs. The x-axis represents Vgs (volts), and the y-axis represents Ron (ohms). In one aspect, a lower Vgs (e.g., 3.0V) is chosen to bias switch 100. Figure 4 In the example, the bias point is around 3V. The effect is a significant improvement in Ron flatness over a wider input voltage range, but with an increase in Ron value of approximately 10% to 20%. In high-precision analog applications requiring a wide input signal range, a flat Ron across the input signal range is generally preferred over a lower Ron. By improving Ron flatness, less error is introduced into the signal chain due to Ron variation. The increased Ron value due to the low Vgs bias can be compensated by increasing the switching area by approximately 10%. The choice between slightly reduced Ron performance and switching area should be determined based on the application's performance and cost constraints.

[0040] On one hand, the PMOS source follower MPSF tracks the input voltage Vin and, in response, generates a constant Vgs (i.e., VCAMP) which is the sum of the gate-source voltage (Vgs) of MPSF and the drain-source voltage Vds of MN8. A voltage VCLAMP is applied between the common gate 116 and the common source 110. Using a constant VCLAMP across the entire Vin range, accurate and linear Ron can be obtained across the entire operating range.

[0041] In another aspect, an FET MN8 having the same characteristics as MN1 and MN2 is selected. By matching MN8 with MN1 and MN2, process-related errors caused by changes in Vt (threshold voltage) are reduced. In addition, back-to-back coupled MN1 and MN2 provide safe operation when VDD and VSS are not present (i.e., 0 or floating). When Vin is applied, the output terminal 122 remains isolated, and there is no leakage path to VDD or VSS. Consider the scenario where VDD and VSS are not applied and Vin>VDD. In this case, the signal at the input terminal 106 is not transmitted to the output terminal 122 or VDD, because the body diode of MN1 acts as a reverse blocking diode. Now consider the scenario where VDD and VSS are not applied and Vin<VSS. In this case, the body diode of MN1 is forward-biased, but the body diode of MN2 is reverse-biased, thereby blocking the signal at the input terminal 106 from reaching the output terminal 122.

[0042] Variations of the switch 100 are possible within the scope of the present disclosure. For example, the clamp circuit 164 may use a variable resistor instead of the NFET MN8. If a variable resistor is used, the clamp voltage across the common gate 116 and the common source 110 is the sum of the voltage across the variable resistor and the Vgs of the source follower MPSF. In addition, one diode or a plurality of series-coupled diodes, a Vbe multiplier or a Vt multiplier may be used to couple the low-voltage terminal 140 to the switch 100, and a diode may be used to couple the source 252 and the gate 256 of MN7.

[0043] In this specification, the term "couple" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B; or (b) in a second example, if the intervening component C does not substantially alter the functional relationship between device A and device B, then device A is coupled to device B via the intervening component C such that device B is controlled by device A via control signals provided by device A. Furthermore, in this specification, a device "configured" to perform a task or function may be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform that function, and / or may be configured (or reconfigurable) by the user after manufacturing to perform that function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the structure and / or layout of the device's hardware components and interconnections, or a combination thereof. Additionally, in this specification, circuitry or devices including certain components may alternatively be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0044] As used herein, the terms “terminal,” “node,” “interconnection,” and “pin” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0045] While some components may be described herein as being made using a particular process technology, these components can be replaced with those made using other process technologies. The circuits described herein can be reconfigured to include the replaced components, thereby providing functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component can alternatively be multiple resistors or capacitors, each coupled in series or parallel between the same two nodes as the single resistor or capacitor. Furthermore, the use of the phrase "ground terminal" in this specification includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of grounding connection applicable or suitable for the teachings of this specification. Unless otherwise stated, "about," "approximately," or "substantially" preceding a numerical value means + / - 10% of the stated value.

[0046] Within the scope of the claims, modifications may be made to the described embodiments, and other embodiments are also possible.

Claims

1. An analog switch, comprising: Input voltage terminals; Output voltage terminals; The first field-effect transistor, namely the first FET, has a first terminal coupled to the input voltage terminal, a second terminal coupled to the common source, and a control terminal coupled to the common gate. The second FET has a first terminal coupled to the output voltage terminal, a second terminal coupled to the common source, and a control terminal coupled to the common gate; A switching current source having an input terminal suitable for coupling to a voltage source and an output terminal coupled to the common gate; The third FET is coupled between the common gate and the low-voltage power supply terminal; A fourth FET is coupled between the common source and the low-voltage power supply terminal; as well as A clamping circuit having a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal coupled to the low-voltage power supply terminal.

2. The analog switch of claim 1, wherein the third FET is operable to connect the common gate to the low-voltage power supply terminal when the third FET is turned on, and to disconnect the common gate from the low-voltage power supply terminal when the third FET is turned off.

3. The analog switch of claim 1, wherein the fourth FET is operable to connect the common source to the low-voltage power supply terminal when the fourth FET is turned on, and to disconnect the common source from the low-voltage power supply terminal when the fourth FET is turned off.

4. The analog switch of claim 1, wherein the clamping circuit is operable to clamp the voltage across the common gate and the common source.

5. The switch according to claim 1, wherein the first FET and the second FET are n-channel field-effect transistors, i.e., NFETs.

6. The switch according to claim 1, wherein the third FET and the fourth FET are n-channel field-effect transistors, i.e., NFETs.

7. The switch according to claim 1, wherein the clamping circuit comprises: An NFET having a drain coupled to the common gate, a gate coupled to the drain, and a source; as well as A source follower p-channel field-effect transistor, also known as a source follower PFET, has a source coupled to the source of the NFET, a gate coupled to the common source, and a drain adapted to be coupled to the low-voltage power supply terminal.

8. The switch according to claim 1, wherein the switch current source comprises: A first current mirror has a first terminal adapted to be coupled to receive an input current and a second terminal adapted to be coupled to the low-voltage power supply terminal, the first current mirror being operable to provide a first mirror current. The second current mirror has a first terminal coupled to a high-voltage power supply terminal and a second terminal coupled to receive the first mirror current, and the second current mirror is operable to supply gate current to the common gate. as well as An NFET having a source coupled to a first current mirror, a drain coupled to a second current mirror, and a gate adapted to be coupled to receive an enable signal, the NFET being operable to couple the first current mirror to the second current mirror in response to the enable signal.

9. The switch of claim 1, wherein the clamping circuit applies a voltage of approximately 2.5V between the common source and the common gate to enhance the on-resistance flatness of the analog switch.

10. The switch of claim 1, wherein the clamping circuit applies a voltage of less than 3.0V between the common source and the common gate to enhance the on-resistance flatness of the analog switch.

11. An analog switch, comprising: Input voltage terminals; Output voltage terminals; The first field-effect transistor, namely the first FET, has a drain coupled to the input voltage terminal, a source coupled to a common source, and a gate coupled to a common gate. The second FET has a drain coupled to the output voltage terminal, a source coupled to the common source, and a gate coupled to the common gate; A switching current source having an input terminal suitable for coupling to a voltage source and an output terminal coupled to the common gate; The third FET has a drain coupled to the common gate, a source adapted to be coupled to a low-voltage power supply terminal, and a gate adapted to be coupled to receive an inhibit signal. The fourth FET has a drain coupled to the common source, a source adapted to be coupled to the low-voltage power supply terminal, and a gate adapted to be coupled to receive the disable signal; as well as A clamping circuit having a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal coupled to the low-voltage power supply terminal, the clamping circuit being operable to clamp the voltage across the common gate and the common source.

12. The switch according to claim 11, wherein the switch current source comprises: The fifth NFET has a drain adapted to receive input current, a source coupled to the low-voltage power supply terminal, and a gate coupled to the drain. as well as The sixth NFET has a drain, a source coupled to the low-voltage power supply terminal, and a gate coupled to the gate of the fifth NFET, and the sixth NFET is operable to mirror the input current.

13. The switch according to claim 12, wherein the switch current source comprises: The first p-channel field-effect transistor, namely the first PFET, has a source, a drain coupled to a high-voltage power supply terminal, and a gate coupled to the drain. The second PFET has a source coupled to the high-voltage power supply terminal, a drain coupled to the common gate, and a gate coupled to the gate of the first PFET. The second PFET is operable to mirror the current through the first PFET and supply gate current to the common gate. A seventh NFET having a drain coupled to the drain of the first PFET, a source coupled to the drain of the sixth NFET, and a gate adapted to be coupled to receive an enable signal, the seventh NFET being operable to couple the sixth NFET to the first PFET.

14. The switch of claim 11, wherein the clamping circuit comprises: The eighth NFET has a drain coupled to the common gate, a gate coupled to the drain, and a source. as well as A source follower PFET having a source coupled to the source of the eighth NFET, a gate coupled to the common source, and a drain coupled to the low-voltage power supply terminal.

15. The switch of claim 11, further comprising a diode having an anode coupled to the common source and a cathode coupled to the common gate.

16. An analog switch, comprising: Input voltage terminals; Output voltage terminals; The first field-effect transistor, namely the first FET, has a first terminal coupled to the input voltage terminal, a second terminal coupled to the common source, and a control terminal coupled to the common gate. The second FET has a first terminal coupled to the output voltage terminal, a second terminal coupled to the common source, and a control terminal coupled to the common gate; The third FET is coupled between the common gate and the low-voltage power supply terminal; A fourth FET is coupled between the common source and the low-voltage power supply terminal; A first current mirror has a first terminal and a second terminal coupled to the low-voltage power supply terminal, and the first current mirror is operable to provide a first mirror current at a third terminal of the first current mirror. A second current mirror has a first terminal and a second terminal adapted to be coupled to a voltage source, and the second current mirror is operable to provide a gate current at a third terminal of the second current mirror in response to the first mirror current. A fifth FET having a first terminal coupled to the third terminal of the first current mirror, a second terminal coupled to the second terminal of the second current mirror, and a control terminal, the fifth FET being operable to couple the first current mirror to the second current mirror in response to an enable signal applied to the control terminal of the fifth FET; as well as A clamping circuit having a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal coupled to the low-voltage power supply terminal.

17. The switch of claim 16, wherein the first FET and the second FET are n-channel field-effect transistors, i.e., NFETs.

18. The switch of claim 16, wherein the third FET and the fourth FET are n-channel field-effect transistors, i.e., NFETs.

19. The switch of claim 16, wherein the clamping circuit comprises: An NFET having a drain coupled to the common gate, a gate coupled to the drain, and a source; as well as A source follower p-channel field-effect transistor, also known as a source follower PFET, has a source coupled to the source of the NFET, a gate coupled to the common source, and a drain adapted to be coupled to the low-voltage power supply terminal.

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