Display panel and display device

Abstract

A display panel and a display device, wherein the display panel comprises: a substrate (010), a third conductive layer (300), a second insulating layer (620, 630), a first conductive layer (100), an interlayer insulating layer (640), a second conductive layer (200), at least one of a plurality of first data connection parts (211) being electrically connected to at least one of a plurality of data lines (VD) and at least one of a plurality of first data transmission lines (711) through a first data through hole (641-1); at least one row of sub-pixels in a first type of row of sub-pixels corresponds to at least one first data connection part (211). For the first scan line (GA1) and the first data connection part (211) corresponding to the same row of sub-pixels, and the first data line (121) and the first data transmission line (711) electrically connected by the first data connection part (211), the orthographic projection of the first data connection part (211) on the substrate (010) and the orthographic projection of the first scan line (GA1) on the substrate (010) have an overlapping area, and the orthographic projections of the first data line (121) and the first data transmission line (711) on the substrate (010) do not overlap with the orthographic projection of the first scan line (GA1) on the substrate (010).

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Electroluminescent diodes such as organic light emitting diodes (OLED), quantum dot light emitting diodes (QLED), and micro light emitting diodes (Micro LED) have the advantages of self-luminescence and low energy consumption, and are one of the hot topics in the current research field of electroluminescent display devices. Summary of the invention

[0003] The display panel provided by the embodiment of the present disclosure includes:

[0004] A base substrate, comprising a notch area, a display area and a first non-display area, wherein the first non-display area is located between the notch area and the display area; wherein the display area further comprises a plurality of sub-pixels;

[0005] A third conductive layer is located on the base substrate, and the third conductive layer includes a plurality of first scanning lines and a plurality of second scanning lines located in the display area; wherein one row of the sub-pixels corresponds to one of the first scanning lines and one of the second scanning lines;

[0006] A second insulating layer is located on a side of the third conductive layer away from the substrate;

[0007] A first conductive layer is located on a side of the second insulating layer away from the base substrate and includes a plurality of data lines and a plurality of first data transmission lines;

[0008] An interlayer insulating layer, located on a side of the first conductive layer away from the base substrate, and the interlayer insulating layer has a plurality of first data through holes;

[0009] A second conductive layer is located on a side of the interlayer insulating layer away from the base substrate and includes a plurality of first data connection portions;

[0010] The plurality of data lines are located in the display area, and the plurality of first data transmission lines are located in the first non-display area;

[0011] At least one of the plurality of first data connection parts is electrically connected to at least one of the plurality of data lines and at least one of the plurality of first data transmission lines through the first data vias;

[0012] All the row sub-pixels include a first type of row sub-pixels; at least one row of sub-pixels in the first type of row sub-pixels corresponds to at least one of the first data connection parts; for the first scan line and the first data connection part corresponding to the same row of sub-pixels, and the first data line and the first data transmission line electrically connected using the first data connection part, the orthographic projection of the first data connection part on the substrate substrate and the orthographic projection of the first scan line on the substrate substrate have an overlapping area, and the orthographic projection of the first data line and the first data transmission line on the substrate substrate do not overlap with the orthographic projection of the first scan line on the substrate substrate.

[0013] Optionally, in the embodiment of the present disclosure, the second conductive layer further includes: a plurality of second data transmission lines spaced apart from the first data connection portion; the plurality of second data transmission lines are located in the first non-display area;

[0014] The interlayer insulating layer further comprises: a plurality of second data through holes;

[0015] The plurality of data lines include a plurality of first data lines and a plurality of second data lines; wherein, one of the first data lines is electrically connected to one of the first data transmission lines through the first data connection portion; and one of the second data lines is electrically connected to one of the second data transmission lines through the second data via.

[0016] Optionally, in the embodiment of the present disclosure, the second scan line corresponding to the sub-pixels in a first row of every two adjacent rows of sub-pixels is electrically connected to the first scan line corresponding to the sub-pixels in a second row.

[0017] Optionally, in the embodiment of the present disclosure, the first conductive layer further comprises: a plurality of first scan connection portions which are insulated from the data line and the first data transmission line and are arranged at intervals; wherein the first scan line and the second scan line which are electrically connected to each other correspond to at least one of the first scan connection portions;

[0018] The second insulating layer includes a plurality of first scanning through holes and a plurality of second scanning through holes;

[0019] The first end of the first scanning connection portion is electrically connected to the corresponding first scanning line through at least one of the plurality of first scanning through holes, and the second end of the first scanning connection portion is electrically connected to the corresponding second scanning line through at least one of the plurality of second scanning through holes.

[0020] Optionally, in the embodiment of the present disclosure, an orthographic projection of the first data connection portion on the base substrate does not overlap with an orthographic projection of the first scanning connection portion on the base substrate.

[0021] Optionally, in the embodiment of the present disclosure, for the first scan line, the second scan line and the first data connection portion corresponding to the same row of sub-pixels, the orthographic projection of the first data connection portion on the substrate substrate is located between the orthographic projections of the first scanning through hole corresponding to the first scan line and the second scanning through hole corresponding to the second scan line on the substrate substrate.

[0022] Optionally, in the embodiment of the present disclosure, for the first scan line, the second scan line and the first data connection portion corresponding to the same row of sub-pixels, a line between the center of the orthographic projection of the first scanning through hole corresponding to the first scan line on the substrate and the center of the orthographic projection of the second scanning through hole corresponding to the second scan line on the substrate overlaps with the orthographic projection of the first data connection portion on the substrate.

[0023] Optionally, in the embodiment of the present disclosure, for the first scan line and the first data connection portion corresponding to the same row of sub-pixels, the orthographic projection of the first data connection portion on the substrate and the orthographic projection of the first scan line on the substrate have an overlapping area.

[0024] Optionally, in an embodiment of the present disclosure, some of the row sub-pixels in the first type of row sub-pixels correspond to two of the first data connection parts, and for the first scan line, the second scan line and the two first data connection parts corresponding to the same row sub-pixel, the orthographic projections of the two first data connection parts on the substrate substrate and the orthographic projections of the first scan line on the substrate substrate have an overlapping area, and the orthographic projections of the two first data connection parts on the substrate substrate and the orthographic projections of the second scan line on the substrate substrate do not overlap.

[0025] Optionally, in the embodiment of the present disclosure, for the first scan line, the second scan line and the two first data connection parts corresponding to the same row of sub-pixels,

[0026] The orthographic projection of the first one of the two first data connection portions on the substrate is close to the orthographic projection of the first scanning through hole corresponding to the first scanning line on the substrate; and / or,

[0027] The orthographic projection of the second first data connection portion of the two first data connection portions on the base substrate is close to the orthographic projection of the second scanning through hole corresponding to the second scanning line on the base substrate.

[0028] Optionally, in the embodiment of the present disclosure, the second conductive layer further includes: a plurality of second data connection parts; wherein, one second data transmission line is directly electrically connected to at least one second data connection part, and the second data connection part is electrically connected to one second data line through the second data via.

[0029] Optionally, in an embodiment of the present disclosure, along a first direction, the first data lines and the second data lines are arranged alternately;

[0030] Projections of the first data connection portions and the second data connection portions on a straight line extending along the first direction are arranged alternately.

[0031] Optionally, in an embodiment of the present disclosure, all the row sub-pixels include a second type of row sub-pixels; the second type of row sub-pixels are different from the first type of row sub-pixels;

[0032] At least one row of sub-pixels in the second type of row sub-pixels corresponds to at least one of the second data connection portions;

[0033] For the first scan line and the second data connection part corresponding to the same row of sub-pixels, and the second data line and the second data transmission line electrically connected using the second data connection part, the orthographic projection of the second data connection part on the substrate and the orthographic projection of the first scan line on the substrate have an overlapping area, and the orthographic projection of the second data line and the second data transmission line on the substrate do not overlap with the orthographic projection of the first scan line on the substrate.

[0034] Optionally, in the embodiment of the present disclosure, for a row of sub-pixels corresponding to two of the first data connection parts, the row of sub-pixels also corresponds to one of the second data connection parts;

[0035] For the first scan line and the second data connection part corresponding to the same row of sub-pixels, and the second data line and the second data transmission line electrically connected using the second data connection part, the orthographic projection of the second data connection part on the substrate and the orthographic projection of the first scan line on the substrate have an overlapping area, and the orthographic projection of the second data line and the second data transmission line on the substrate do not overlap with the orthographic projection of the first scan line on the substrate.

[0036] Optionally, in the embodiment of the present disclosure, the third conductive layer further includes a plurality of light emitting control lines located in the display area; wherein one row of the sub-pixels corresponds to one light emitting control line; and the light emitting control lines corresponding to two adjacent rows of sub-pixels are electrically connected;

[0037] The display panel further includes:

[0038] a fourth conductive layer, located between the first conductive layer and the third conductive layer;

[0039] The second insulating layer comprises:

[0040] a second gate insulating layer, located between the third conductive layer and the fourth conductive layer;

[0041] The interlayer dielectric layer is located between the fourth conductive layer and the first conductive layer.

[0042] Optionally, in the embodiment of the present disclosure, the first conductive layer further comprises: a plurality of first light-emitting connection parts which are insulated from the data line and the first data transmission line and arranged at intervals; wherein the light-emitting control lines electrically connected to each other correspond to at least one of the first light-emitting connection parts;

[0043] The second insulating layer includes a plurality of first light-emitting through holes and a plurality of second light-emitting through holes;

[0044] The first end of the first light-emitting connection part is electrically connected to a corresponding one of the light-emitting control lines through at least one of the plurality of first light-emitting through holes, and the second end of the first light-emitting connection part is electrically connected to another corresponding one of the light-emitting control lines through at least one of the plurality of second light-emitting through holes.

[0045] Optionally, in the embodiment of the present disclosure, the third conductive layer further comprises a plurality of first scanning transmission lines and a plurality of first light emitting transmission lines located in the first non-display area; wherein the first scanning transmission lines and the first light emitting transmission lines are arranged at intervals;

[0046] Part of the first scanning lines and the second scanning lines electrically connected to each other are directly electrically connected to one of the first scanning transmission lines; and part of the light emitting control lines electrically connected to each other are directly electrically connected to one of the first light emitting transmission lines;

[0047] The fourth conductive layer further comprises a plurality of second scanning transmission lines and a plurality of second light emitting transmission lines located in the first non-display area; wherein the second scanning transmission lines and the second light emitting transmission lines are arranged at intervals;

[0048] The interlayer dielectric layer further includes a plurality of third scanning through holes and a plurality of third light-emitting through holes;

[0049] The first scanning line and the second scanning line electrically connected to each other in the remaining part correspond to one second scanning transmission line, and the first scanning connection part is also electrically connected to the second scanning transmission line through the third scanning through hole;

[0050] The remaining part of the light-emitting control line electrically connected to each other corresponds to one of the second light-emitting transmission lines, and the first light-emitting connection part is also electrically connected to the second light-emitting transmission line through the third light-emitting through hole.

[0051] Optionally, in the embodiment of the present disclosure, the fourth conductive layer includes a plurality of third scan transmission lines located in the first non-display area;

[0052] The interlayer dielectric layer includes a plurality of fourth scanning through holes;

[0053] The first scan line and the second scan line electrically connected to each other correspond to one third scan transmission line, and the first scan connection portion is also electrically connected to the third scan transmission line through a fourth scan through hole;

[0054] The third conductive layer further includes a third light emitting transmission line located in the first non-display area; wherein the light emitting control lines electrically connected to each other are directly electrically connected to one of the third light emitting transmission lines.

[0055] Optionally, in the embodiment of the present disclosure, the fourth conductive layer includes a plurality of fourth light emitting transmission lines located in the first non-display area;

[0056] The interlayer dielectric layer includes a plurality of fourth light-emitting through holes;

[0057] The mutually electrically connected light-emitting control lines correspond to one of the fourth light-emitting transmission lines, and the first light-emitting connection portion is also electrically connected to the fourth light-emitting transmission line through a fourth light-emitting through hole;

[0058] The third conductive layer further includes a fourth scan transmission line located in the first non-display area; wherein the first scan line and the second scan line electrically connected to each other are directly electrically connected to one of the fourth scan transmission lines.

[0059] Optionally, in the embodiment of the present disclosure, for the light-emitting control line, the second scanning line and the second data connection part corresponding to the same row of sub-pixels, the orthographic projection of the second data connection part on the substrate is located between the orthographic projection of the second scanning through hole corresponding to the second scanning line and the first light-emitting through hole corresponding to the light-emitting control line on the substrate.

[0060] Optionally, in the embodiment of the present disclosure, the display panel further includes:

[0061] A first gate insulating layer, located between the third conductive layer and the substrate;

[0062] A semiconductor layer, located between the first gate insulating layer and the substrate;

[0063] At least one of the plurality of sub-pixels comprises: a first connection through hole, a second connection through hole and a third connection through hole; wherein the first connection through hole penetrates the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer; the second connection through hole penetrates the second gate insulating layer and the interlayer dielectric layer; the third connection through hole penetrates the interlayer dielectric layer;

[0064] The first conductive layer is electrically connected to the semiconductor layer through the first connecting through hole;

[0065] The first conductive layer is electrically connected to the second conductive layer through the second connecting through hole;

[0066] The first conductive layer is electrically connected to the third conductive layer through the third connecting via.

[0067] Optionally, in the embodiment of the present disclosure, the display panel further includes at least one first auxiliary through hole located in the first non-display area;

[0068] The first auxiliary through hole penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer, and the first auxiliary through hole is not filled with a conductive material.

[0069] Optionally, in the embodiment of the present disclosure, the distribution density of the first auxiliary through holes is less than or substantially equal to the distribution density of the first connecting through holes.

[0070] Optionally, in the embodiment of the present disclosure, the orthographic projection of the first auxiliary through hole on the base substrate does not overlap with the orthographic projections of the semiconductor layer, the first conductive layer, the third conductive layer and the fourth conductive layer on the base substrate.

[0071] Optionally, in the embodiment of the present disclosure, the display panel further includes at least one second auxiliary through hole located in the first non-display area;

[0072] The second auxiliary through hole penetrates the second gate insulating layer and the interlayer dielectric layer, and the second auxiliary through hole is not filled with conductive material.

[0073] Optionally, in the embodiment of the present disclosure, the distribution density of the second auxiliary through holes is less than or substantially equal to the distribution density of the second connecting through holes.

[0074] Optionally, in the embodiment of the present disclosure, the orthographic projection of the second auxiliary through hole on the base substrate does not overlap with the orthographic projections of the first conductive layer, the third conductive layer and the fourth conductive layer on the base substrate.

[0075] Optionally, in the embodiment of the present disclosure, the display panel further includes at least one third auxiliary through hole located in the first non-display area;

[0076] The third auxiliary through hole penetrates the interlayer dielectric layer, and the third auxiliary through hole is not filled with conductive material.

[0077] Optionally, in the embodiment of the present disclosure, the distribution density of the third auxiliary through holes is less than or approximately equal to the distribution density of the third connecting through holes.

[0078] Optionally, in the embodiment of the present disclosure, an orthographic projection of the third auxiliary through hole on the base substrate does not overlap with an orthographic projection of the first conductive layer and the fourth conductive layer on the base substrate.

[0079] The embodiment of the present disclosure also provides a display device, which includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] Figure 1 Structural schematic diagrams of some display panels provided by embodiments of the present disclosure;

[0081] Figure 2 A schematic diagram of the circuit structure of some sub-pixels provided in an embodiment of the present disclosure;

[0082] Figure 3 A schematic diagram of the layout structure of some sub-pixels provided in an embodiment of the present disclosure;

[0083] Figure 4a A schematic diagram of the layout structure of semiconductor layers in some sub-pixels provided in an embodiment of the present disclosure;

[0084] Figure 4b A schematic diagram of the layout structure of the third conductive layer in some sub-pixels provided in an embodiment of the present disclosure;

[0085] Figure 4c A schematic diagram of the layout structure of the fourth conductive layer in some sub-pixels provided in an embodiment of the present disclosure;

[0086] Figure 4d A schematic diagram of the layout structure of the first conductive layer in some sub-pixels provided in an embodiment of the present disclosure;

[0087] Figure 4e A schematic diagram of the layout structure of the second conductive layer in some sub-pixels provided in an embodiment of the present disclosure;

[0088] Figure 5 for Figure 3 A schematic cross-sectional view of the layout structure along the AA' direction in the schematic diagram shown;

[0089] Figure 6 Structural schematic diagrams of some further display panels provided by the embodiments of the present disclosure;

[0090] Figure 7a A schematic diagram of the layout structure of some local areas of some display panels provided in an embodiment of the present disclosure;

[0091] Figure 7b A schematic diagram of the layout structure of some local areas of further display panels provided in an embodiment of the present disclosure;

[0092] Figure 8a for Figure 7a A schematic cross-sectional structure diagram along the AA' direction in the schematic layout structure diagram of a local area of ​​the display panel shown;

[0093] Figure 8b for Figure 7a A schematic cross-sectional structure diagram along the BB' direction in the schematic layout structure diagram of a local area of ​​the display panel shown;

[0094] Figure 8c for Figure 7b A schematic cross-sectional structure diagram along the BB' direction in the schematic layout structure diagram of a local area of ​​the display panel shown;

[0095] Figure 9a A schematic diagram of the layout structure of some local areas of further display panels provided in an embodiment of the present disclosure;

[0096] Figure 9b A schematic diagram of the layout structure of some local areas of further display panels provided in an embodiment of the present disclosure;

[0097] Fig.10a for Figure 9a A schematic cross-sectional structure diagram along the AA' direction in the schematic layout structure diagram of a local area of ​​the display panel shown;

[0098] Fig.10b for Figure 9a A schematic cross-sectional structure diagram along the BB' direction in the schematic layout structure diagram of a local area of ​​the display panel shown;

[0099] Fig.10c for Figure 9b A schematic cross-sectional structure diagram along the BB' direction in the schematic layout structure diagram of a local area of ​​the display panel shown;

[0100] Fig.11 A schematic diagram of the layout structure of some local areas of further display panels provided in an embodiment of the present disclosure;

[0101] Fig.12 for Fig.11 A schematic cross-sectional structure diagram along the AA' direction in the schematic layout structure diagram of a local area of ​​the display panel shown;

[0102] Fig.13 A schematic diagram of the layout structure of some local areas of further display panels provided in an embodiment of the present disclosure;

[0103] Fig.14 for Fig.13 The schematic diagram of the cross-sectional structure along the AA′ direction in the schematic diagram of the layout structure of a local area of ​​the display panel shown. DETAILED DESCRIPTION

[0104] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present disclosure.

[0105] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0106] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, and are only intended to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0107] With the development of display technology, full-screen displays have attracted widespread attention due to their large screen-to-body ratio and ultra-narrow borders, which can greatly improve the visual effect of viewers compared to ordinary display screens. Generally, in display devices such as mobile phones that use full-screen displays, in order to achieve selfie and call functions, a front camera, an earpiece, etc. are usually set on the front of the display device. Generally, a notch area A2 for setting devices such as a front camera and an earpiece is generally provided in the display panel. However, due to the existence of the notch area A2, the scan line and the data line need to be arranged according to the notch area A2, which results in coupling between the scan line and the data line, causing signal interference and affecting the display effect.

[0108] In view of this, the embodiments of the present disclosure provide a display panel that can reduce the coupling effect between scan lines and data lines, reduce signal interference, and improve display effect.

[0109] like Figure 1As shown, the display panel provided by the embodiment of the present disclosure may include: a substrate 010. The substrate 010 may include a notch area A2, a display area A1, and a first non-display area A3, wherein the first non-display area A3 is located between the notch area A2 and the display area A1. The substrate 010 may be a glass substrate, a flexible substrate, a silicon substrate, etc., which are not limited here. When the display panel is applied to a display device, a camera, an earpiece, and other devices are generally provided. Therefore, in order to provide the camera, the earpiece, and other devices, the notch area A2 may be a hollow area of ​​the substrate substrate 010. For example, in the actual preparation process, the position corresponding to the notch area A2 in the substrate substrate 010 is cut to make it a hollow area, so as to provide the camera, the earpiece, and other devices in the display device. Alternatively, the substrate substrate 010 may not be cut, but the circuit on the substrate substrate 010 may be avoided so that the position corresponding to the notch area A2 is a transparent area to form the notch area A2.

[0110] In practical applications, the display panel may also include a frame area surrounding the display area A1. Electrostatic discharge circuits, gate drive circuits and other components may be disposed in the frame area. Of course, the display panel may not be provided with a frame area, which may be designed and determined according to the requirements of the actual application environment and is not limited here.

[0111] In the specific implementation, in the embodiment of the present disclosure, if Figure 1 As shown, the display area A1 may also include a plurality of pixel units PX arranged in an array. The pixel unit PX may include a plurality of sub-pixels spx. The sub-pixels spx may be arranged in an array in the display area A1. Figure 1 and Figure 2 As shown, the sub-pixel spx may include: a pixel driving circuit 0121 and a light-emitting device 0120. The pixel driving circuit 0121 has a transistor and a capacitor, and generates an electrical signal through the interaction between the transistor and the capacitor, and the generated electrical signal is input into the first light-emitting electrode of the light-emitting device 0120. And by applying a corresponding voltage to the second light-emitting electrode of the light-emitting device 0120, the light-emitting device 0120 can be driven to emit light.

[0112] Combination Figure 2 As shown, the pixel driving circuit 0121 may include: a driving control circuit 0122 , a first light emitting control circuit 0123 , a second light emitting control circuit 0124 , a data writing circuit 0126 , a storage circuit 0127 , a threshold compensation circuit 0128 and a reset circuit 0129 .

[0113] The driving control circuit 0122 may include a control terminal, a first terminal, and a second terminal. The driving control circuit 0122 is configured to provide the light emitting device 0120 with a driving current for driving the light emitting device 0120 to emit light. For example, the first light emitting control circuit 0123 is connected to the first terminal of the driving control circuit 0122 and the first voltage terminal VDD. The driving control circuit 0122 is configured to realize the connection between the driving control circuit 0122 and the first voltage terminal VDD to be turned on or off.

[0114] The second light emitting control circuit 0124 is electrically connected to the second end of the driving control circuit 0122 and the first light emitting electrode of the light emitting device 0120. The second light emitting control circuit 0124 is configured to realize the connection between the driving control circuit 0122 and the light emitting device 0120 is turned on or off.

[0115] The data writing circuit 0126 is electrically connected to a first terminal of the driving control circuit 0122. And the second light emitting control circuit 0124 is configured to write the signal on the data line VD into the storage circuit 0127 under the control of the signal on the scanning line GA2.

[0116] The storage circuit 0127 is electrically connected to the control terminal of the driving control circuit 0122 and the first voltage terminal VDD, and the storage circuit 0127 is configured to store a data signal.

[0117] The threshold compensation circuit 0128 is electrically connected to the control terminal and the second terminal of the driving control circuit 0122 , and the threshold compensation circuit 0128 is configured to perform threshold compensation on the driving control circuit 0122 .

[0118] The reset circuit 0129 is electrically connected to the control terminal of the driving control circuit 0122 and the first light emitting electrode of the light emitting device 0120. The reset circuit 0129 is configured to reset the control terminal of the driving control circuit 0122 and the first light emitting electrode of the light emitting device 0120 under the control of the signal on the gate line GA1.

[0119] Among them, the light-emitting device 0120 may include a first light-emitting electrode, a light-emitting functional layer, and a second light-emitting electrode that are stacked. Exemplarily, the first light-emitting electrode may be an anode, and the second light-emitting electrode may be a cathode. The light-emitting functional layer may include a light-emitting layer. Furthermore, the light-emitting functional layer may also include film layers such as a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. Of course, in actual applications, the light-emitting device 0120 can be designed and determined according to the needs of the actual application environment, and is not limited here.

[0120] For example, in combination Figure 2As shown, the driving control circuit 0122 includes: a driving transistor T1, the control end of the driving control circuit 0122 includes the gate of the driving transistor T1, the first end of the driving control circuit 0122 includes the first electrode of the driving transistor T1, and the second end of the driving control circuit 0122 includes the second electrode of the driving transistor T1.

[0121] For example, in combination Figure 2 As shown, the data writing circuit 0126 includes a data writing transistor T2. The storage circuit 0127 includes a storage capacitor CST. The threshold compensation circuit 0128 includes a threshold compensation transistor T3. The first light emission control circuit 0123 includes a first light emission control transistor T4. The second light emission control circuit 0124 includes a second light emission control transistor T5. The reset circuit 0129 includes a first reset transistor T6 and a second reset transistor T7.

[0122] Specifically, the first electrode of the data write transistor T2 is electrically connected to the first electrode of the drive transistor T1, the second electrode of the data write transistor T2 is configured to be electrically connected to the data line VD to receive the data signal, and the gate of the data write transistor T2 is configured to be electrically connected to the second scan line GA2 to receive the scan signal.

[0123] A first electrode of the storage capacitor CST is electrically connected to the first power supply terminal VDD, and a second electrode of the storage capacitor CST is electrically connected to the gate of the driving transistor T1 .

[0124] The first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1 , the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1 , and the gate of the threshold compensation transistor T3 is configured to be electrically connected to the second scan line GA2 to receive the compensation control signal.

[0125] The first electrode of the first reset transistor T6 is configured to be electrically connected to the first reset signal line VINIT1 to receive the first reset signal, the second electrode of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1, and the gate of the first reset transistor T6 is configured to be electrically connected to the first scan line GA1 to receive the control signal.

[0126] The first electrode of the second reset transistor T7 is configured to be electrically connected to the second reset signal line VINIT2 to receive the second reset signal, the second electrode of the second reset transistor T7 is electrically connected to the first light-emitting electrode of the light-emitting device 0120, and the gate of the second reset transistor T7 is configured to be electrically connected to the first scan line GA1 to receive the control signal.

[0127] The first electrode of the first light emitting control transistor T4 is electrically connected to the first power supply terminal VDD, the second electrode of the first light emitting control transistor T4 is electrically connected to the first electrode of the driving transistor T1, and the gate of the first light emitting control transistor T4 is configured to be electrically connected to the light emitting control line EM to receive a light emitting control signal.

[0128] The first electrode of the second light emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the second light emitting control transistor T5 is electrically connected to the first light emitting electrode of the light emitting device 0120, and the gate of the second light emitting control transistor T5 is configured to be electrically connected to the light emitting control line EM to receive a light emitting control signal.

[0129] The second light emitting electrode of the light emitting device 0120 is electrically connected to the second power supply terminal VSS. The first electrode and the second electrode of the transistor can be determined as a source electrode or a drain electrode according to actual application, which is not limited here.

[0130] Exemplarily, one of the first power supply terminal VDD and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal. Figure 2 In the illustrated embodiment, the first power supply terminal VDD is a voltage source to output a constant first voltage, the first voltage being a positive voltage, and the second power supply terminal VSS is a voltage source to output a constant second voltage, the second voltage being a negative voltage, etc. For example, in some examples, the second power supply terminal VSS may be grounded.

[0131] It should be noted that, in the embodiment of the present disclosure, the pixel driving circuit in the sub-pixel spx can be Figure 2 In addition to the structure shown, the structure may also include other numbers of transistors, which is not limited in the embodiments of the present disclosure.

[0132] Figure 3 A schematic diagram of the layout structure of a pixel driving circuit provided in some embodiments of the present disclosure. Figures 4a to 4e Schematic diagram of each layer of the pixel driving circuit provided in some embodiments of the present disclosure. Figures 3 to 4e The example shown takes a pixel driving circuit of a sub-pixel spx as an example. Figures 3 to 4e Also shown are the first scan line GA1, the second scan line GA2, the first reset signal line VINIT1 (the first reset signal line VINIT1 and the second reset signal line VINIT2 are the same signal line, in which case the first reset signal line VINIT1 is shown), the light emitting control line EM, the data line VD, and the first power signal line VDD1 and the second power signal line VDD2 electrically connected to the first power terminal VDD, which are electrically connected to the pixel driving circuit 0121. The first power signal line VDD1 and the second power signal line VDD2 are electrically connected to each other.

[0133] For example, Figure 3 and Figure 4a As shown, the semiconductor layer 500 of the pixel driving circuit 0121 is shown. The semiconductor layer 500 can be formed by patterning a semiconductor material. The semiconductor layer 500 can be used to make the active layers of the above-mentioned driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6 and the second reset transistor T7, and each active layer may include a source region, a drain region and a channel region between the source region and the drain region. For example, the active layers of each transistor are arranged in one piece.

[0134] For example, the semiconductor layer 500 may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the source region and the drain region may be regions doped with n-type impurities or p-type impurities.

[0135] It should be noted that in the display area A1, the semiconductor layer 500 can be patterned by a patterning process. The semiconductor layer 500 that is not patterned will be retained in the first non-display area A3. In addition, the semiconductor layer 500 in the first non-display area A3 and the display area A1 are arranged at intervals. Of course, the present disclosure includes but is not limited to this.

[0136] Exemplarily, a first gate insulating layer 610 (not shown) is formed on the semiconductor layer 500 to protect the semiconductor layer 500. Figure 3 and Figure 4b , a third conductive layer 300 of the pixel driving circuit 0121 is shown. The third conductive layer 300 is disposed on the first gate insulating layer 610, thereby being insulated from the semiconductor layer 500. The third conductive layer 300 may include the second electrode CC2a of the storage capacitor CST, the first scan line GA1, the second scan line GA2, the emission control line EM, and the gates of the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first emission control transistor T4, the second emission control transistor T5, the first reset transistor T6, and the second reset transistor T7.

[0137] For example, Figures 3 to 4bAs shown, the gate of the data writing transistor T2 may be the portion where the second scan line GA2 overlaps with the semiconductor layer 500, the gate of the first light emission control transistor T4 may be the first portion where the light emission control line EM overlaps with the semiconductor layer 500, the gate of the second light emission control transistor T5 may be the second portion where the light emission control line EM overlaps with the semiconductor layer 500, the gate of the first reset transistor T6 may be the first portion where the first scan line GA1 overlaps with the semiconductor layer 500, the gate of the second reset transistor T7 may be the second portion where the first scan line GA1 overlaps with the semiconductor layer 500, the threshold compensation transistor T3 may be a thin film transistor with a dual-gate structure, the first gate of the threshold compensation transistor T3 may be the first portion where the second scan line GA2 overlaps with the semiconductor layer 500, and the second gate of the threshold compensation transistor T3 may be the second portion where the protrusion protruding from the second scan line GA2 overlaps with the semiconductor layer 500. Figure 3 and 4b As shown, the gate of the driving transistor T1 may be the second electrode CC2a of the storage capacitor CST.

[0138] It should be noted that Figure 4a The dotted rectangular boxes in the figure show the parts where the third conductive layer 300 overlaps with the semiconductor layer 500 in the sub-pixel spx. The active layer of the threshold compensation transistor T3 includes a first channel region overlapping with the first gate of the threshold compensation transistor T3, a second channel region overlapping with the second gate of the threshold compensation transistor T3, and a source-drain region between the first channel region and the second channel region. The source-drain region is used to electrically connect the first channel region and the second channel region.

[0139] For example, Figure 3 and Figure 4b As shown, the first scan line GA1, the second scan line GA2 and the light emitting control line EM are arranged along the second direction F2, and the second scan line GA2 is located between the first scan line GA1 and the light emitting control line EM.

[0140] For example, Figure 3 and Figure 4b As shown, in the second direction F2, the second electrode CC2a of the storage capacitor CST is located between the second scan line GA2 and the emission control line EM. The protrusion protruding from the second scan line GA2 is located on a side of the second scan line GA2 away from the emission control line EM.

[0141] For example, Figure 3 and Figure 4bAs shown, in the second direction F2, the gate of the data writing transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6 and the gate of the second reset transistor T7 are all located on the first side of the gate of the driving transistor T1, and the gate of the first light emitting control transistor T4 and the gate of the second light emitting control transistor T5 are all located on the second side of the gate of the driving transistor T1.

[0142] For example, in some embodiments, Figure 3 and Figure 4b As shown, in the first direction F1, the gate of the data writing transistor T2 and the gate of the first light emission control transistor T4 are both located on the third side of the gate of the driving transistor T1, and the first gate of the threshold compensation transistor T3, the gate of the second light emission control transistor T5 and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1. The third side and the fourth side of the gate of the driving transistor T1 are two sides of the gate of the driving transistor T1 that are opposite to each other in the first direction F1.

[0143] Exemplarily, a second gate insulating layer 620 (not shown) is formed on the third conductive layer 300 to protect the third conductive layer 300. Figure 3 and Figure 4c As shown, the fourth conductive layer 400 of the pixel driving circuit 0121 is shown. The fourth conductive layer 400 is disposed on the second gate insulating layer 620. The fourth conductive layer 400 may include: a first electrode CC1a of the storage capacitor CST, a first reset signal line VINIT1, and a light shielding portion 344a. Exemplarily, the orthogonal projection of the first electrode CC1a of the storage capacitor CST on the substrate substrate 010 and the orthogonal projection of the second electrode CC2a of the storage capacitor CST on the substrate substrate 010 at least partially overlap to form the storage capacitor CST. The orthogonal projection of the light shielding portion 344a on the substrate substrate 010 and the orthogonal projection of the source and drain region in the active layer of the threshold compensation transistor T3 on the substrate substrate 010 have an overlapping area.

[0144] Exemplarily, an interlayer dielectric layer 630 (not shown) is formed on the fourth conductive layer 400 to protect the fourth conductive layer 400. Figure 3 and Figure 4d As shown, the first conductive layer 100 of the pixel driving circuit 0121 is shown, and the first conductive layer 100 is disposed on the interlayer dielectric layer 630. The first conductive layer 100 may include: a data line VD, a first power signal line VDD1, and bridges 341a, 342a, and 343a.

[0145] Exemplarily, an interlayer insulating layer 640 (not shown) is formed on the first conductive layer 100 to protect the first conductive layer 100. Figure 3 and Figure 4e As shown, the second conductive layer 200 of the pixel driving circuit 0121 is shown, and the second conductive layer 200 is disposed on the interlayer insulating layer 640. The second conductive layer 200 includes a second power signal line VDD2 and a transfer portion 351a.

[0146] Figure 5 for Figure 3 The schematic diagram of the layout structure is a schematic diagram of a cross-sectional structure along the AA' direction. A first gate insulating layer 610 is provided between the semiconductor layer 500 and the third conductive layer 300, a second gate insulating layer 620 is provided between the third conductive layer 300 and the fourth conductive layer 400, an interlayer dielectric layer 630 is provided between the fourth conductive layer 400 and the first conductive layer 100, and an interlayer insulating layer 640 is provided between the first conductive layer 100 and the second conductive layer 200.

[0147] Combination Figure 3 and Figure 5 As shown, the sub-pixel spx includes a first connection through hole, a second connection through hole, a third connection through hole and a fourth connection through hole; wherein the first connection through hole passes through the first gate insulation layer 610, the second gate insulation layer 620 and the interlayer dielectric layer 630; the second connection through hole passes through the second gate insulation layer 620 and the interlayer dielectric layer 630; the third connection through hole passes through the interlayer dielectric layer 630; and the fourth connection through hole passes through the interlayer insulation layer 640.

[0148] Exemplarily, the sub-pixel spx may include first connection through holes 381a, 382a, 384a, 387a and 388a. The sub-pixel spx may include a second connection through hole 385a. The sub-pixel spx may include third connection through holes 386a, 3832a and 389a. The sub-pixel spx includes fourth connection through holes 385a and 3831a. The data line VD is electrically connected to the source region of the data writing transistor T2 in the semiconductor layer 500 through at least one first connection through hole 381a. The first power signal line VDD1 is electrically connected to the source region of the corresponding first light emission control transistor T4 in the semiconductor layer 500 through at least one first connection through hole 382a. One end of the bridge portion 341a is electrically connected to the drain region of the corresponding threshold compensation transistor T3 in the semiconductor layer 500 through at least one first connection through hole 384a. The other end of the bridge portion 341a is electrically connected to the gate of the driving transistor T1 in the third conductive layer 300 (i.e., the second electrode CC2a of the storage capacitor CST) through at least one second connection through hole 385a. One end of the bridge portion 342a is electrically connected to the first reset signal line VINIT1 through at least one third connection through hole 386a, and the other end of the bridge portion 342a is electrically connected to the drain region of the second reset transistor T7 in the semiconductor layer 500 through at least one first connection through hole 387a. The bridge portion 343a is electrically connected to the drain region of the second light emission control transistor T5 in the semiconductor layer 500 through at least one first connection through hole 388a. The first power signal line VDD1 is electrically connected to the first electrode CC1a of the storage capacitor CST in the fourth conductive layer 400 through at least one third connection through hole 3832a. The first power signal line VDD1 is also electrically connected to the second power signal line VDD2 in the second conductive layer 200 through at least one fourth connection through hole 3831a. The transfer portion 351a is electrically connected to the bridge portion 343a by penetrating at least one fourth connection through hole 385a. The first power signal line VDD1 is also electrically connected to the light shielding portion 344a through at least one first connection through hole 389a to input a fixed voltage to the light shielding portion 344a.

[0149] For example, the first connection through holes 381a, 382a, 384a, 387a and 388a in the sub-pixel may be provided with one or two, etc. In practical applications, the design may be determined according to the requirements of the actual application environment, and is not limited here.

[0150] For example, one or two second connecting through holes 385a in a sub-pixel may be provided. In practical applications, the design may be determined according to the requirements of the practical application environment, and is not limited here.

[0151] For example, the third connection through holes 386a, 3832a and 389a in the sub-pixel may be provided with one or two, etc. In practical applications, the design may be determined according to the requirements of the practical application environment, and is not limited here.

[0152] For example, one or two fourth connection through holes 385a and 3831a in a sub-pixel may be respectively provided. In practical applications, the design may be determined according to the requirements of the practical application environment, and is not limited here.

[0153] Furthermore, a planarization layer, a first light-emitting electrode layer, a pixel defining layer, a light-emitting function layer, and a second light-emitting electrode layer are sequentially arranged on the side of the second conductive layer 200 away from the base substrate 010. Moreover, the first light-emitting electrode is electrically connected to the transfer portion 351a through a via hole penetrating the planarization layer.

[0154] For example, Figures 3 to 4e As shown, in the second direction F2, the first scan line GA1, the second scan line GA2, and the first reset signal line VINIT1 are all located at a first side of the gate of the driving transistor T1, and the light emitting control line EM is located at a second side of the driving transistor T1.

[0155] In a specific implementation, on the entire display substrate, the first power signal line VDD1 and the second power signal line VDD2 are electrically connected, so that the signal line electrically connected to the first power terminal VDD has a smaller resistance and a lower voltage drop, thereby improving the stability of the power voltage provided by the first power terminal VDD.

[0156] For example, the first scan line GA1, the second scan line GA2, and the light emitting control line EM may be located in the same layer (ie, the third conductive layer 300). The first power signal line VDD1 and the data line VD are located in the same layer (ie, the first conductive layer 100).

[0157] It should be noted that the position arrangement relationship of the transistors in each sub-pixel spx is not limited to Figures 3 to 4e In the example shown, the position of the above transistors can be specifically set according to actual application requirements.

[0158] It should be noted that the first direction F1 may be the row direction of the sub-pixels, and the second direction F2 may be the column direction of the sub-pixels. Alternatively, the first direction F1 may be the column direction of the sub-pixels, and the second direction F2 may be the row direction of the sub-pixels. In practical applications, it can be set according to actual application requirements and is not limited here.

[0159] In specific implementation, in the embodiment of the present disclosure, the display area may include multiple data lines, multiple scan lines, and multiple light-emitting control lines. The first non-display area may include multiple data transmission lines, multiple scan transmission lines, and multiple light-emitting transmission lines: wherein at least one of the multiple data lines is electrically connected to at least one of the multiple data transmission lines, at least one of the multiple scan lines is electrically connected to at least one of the multiple scan transmission lines, and at least one of the multiple light-emitting control lines is electrically connected to at least one of the multiple light-emitting transmission lines.

[0160] In the specific implementation, in the embodiment of the present disclosure, if Figure 6 As shown, the plurality of data lines in the first conductive layer 100 may include a data line VD1 and a data line VD2. The data lines VD1 and VD2 are both located in the display area A1, and the data lines VD1 and VD2 are arranged along the first direction F1. The data line VD1 extends from the lower side of the display area A1 to the upper side of the display area A1 along the second direction F2 and is arranged along the first direction F1. The data line VD2 extends along the second direction F2 and is divided by the notch area A2, that is, the data line VD2 may extend from the lower side of the display area A1 to the first non-display area A3, or may extend from the upper side of the display area A1 to the first non-display area A3.

[0161] In the specific implementation, in the embodiment of the present disclosure, if Figures 6 to 8a As shown, the first conductive layer 100 may further include: a plurality of first data transmission lines 711 arranged at intervals. The second conductive layer 200 may further include: a plurality of first data connection parts 211 arranged at intervals. And the interlayer insulating layer 640 has a plurality of first data through holes. Moreover, at least one of the plurality of first data connection parts 211 is electrically connected to at least one of the plurality of data lines VD2 and at least one of the plurality of first data transmission lines 711 through the first data through hole. In this way, the data lines in the first conductive layer 100 and the first data transmission lines 711 can be electrically connected to each other through the first data connection parts 211 in the second conductive layer 200. It should be noted that the data lines VD2 corresponding to the same column of sub-pixels spx and separated by the notch area A2 can be electrically connected to each other through the first data transmission line 711 to form a data line for inputting data signals to the sub-pixels spx in the column.

[0162] The display panel provided by the embodiment of the present disclosure, by disposing the first data connection part 211 in the second conductive layer 200, can make the data line VD2 in the first conductive layer 100 and the first data transmission line 711 electrically connected to each other through the first data connection part 211 in the second conductive layer 200. In this way, not only can the data lines VD2 corresponding to the sub-pixels spx in the same column and separated by the notch area A2 be electrically connected, but also the interference of the first data connection part 211 to the third conductive layer 300 and the fourth conductive layer 400 can be reduced, so as to improve the signal stability and the display effect.

[0163] Furthermore, since more bridges are provided in the first conductive layer 100, if the first data connection portion 211 is also provided in the first conductive layer 100, the area in the first conductive layer 100 for providing the bridge, the data line and the first power signal line will be reduced, which may cause a short circuit between the bridge, the data line, the first power signal line and the first data connection portion 211. Therefore, the above-mentioned display panel provided in the embodiment of the present disclosure can also reduce the risk of short circuit, further improve the stability of the display panel, and improve the competitiveness of the display panel.

[0164] In the specific implementation, in the embodiment of the present disclosure, if Figures 6 to 8a As shown, a plurality of first data transmission lines 711 are located in the first non-display area A3. Exemplarily, a plurality of first data transmission lines 711 may be arranged in an arc shape around the notch area A2. The interlayer insulating layer 640 may have: a plurality of first data through holes 641-1 and a plurality of first data through holes 641-2. Among them, one first data connection part 211 corresponds to at least one first data through hole 641-1 and at least one first data through hole 641-2. Moreover, one end of the first data connection part 211 may be electrically connected to the data line VD2 through the corresponding first data through hole 641-1, and the other end of the first data connection part 211 may be electrically connected to the first data transmission line 711 through the corresponding first data through hole 641-2. In practical applications, one first data connection part 211 may correspond to one, two, three or more first data through holes 641-1. One first data connection part 211 may also correspond to one, two, three or more first data through holes 641-2. These may be designed and determined according to the needs of practical applications and are not limited here.

[0165] In the specific implementation, in the embodiment of the present disclosure, if Figures 6 to 8aAs shown, the plurality of data lines VD2 may include a plurality of first data lines 121 and a plurality of second data lines 122. Exemplarily, along the first direction F1, the first data lines 121 and the second data lines 122 may be arranged alternately. For example, in the direction indicated by the arrow along the first direction F1, the odd-numbered data lines of the plurality of data lines VD2 may be used as the first data lines 121, and the even-numbered data lines of the plurality of data lines VD2 may be used as the second data lines 122. Of course, the first data lines 121 and the second data lines 122 may also be designed and determined according to the requirements of the actual application environment, which is not limited here.

[0166] In the specific implementation, in the embodiment of the present disclosure, if Figures 6 to 8a As shown, a first data line 121 can be electrically connected to a first data transmission line 711 through a first data connection portion 211. Exemplarily, a first data line 121 can correspond to a first data connection portion 211 and a first data transmission line 711. Moreover, the first data line 121 can be electrically connected to the corresponding first data transmission line 711 through the corresponding first data connection portion 211, so that the first data lines 121 corresponding to the sub-pixels spx in the same column and divided by the notch area A2 can be electrically connected to the first data transmission line 711 through the corresponding first data connection portion 211.

[0167] In the specific implementation, in the embodiment of the present disclosure, if Figures 6 to 8a As shown, the second conductive layer 200 may further include: a plurality of second data transmission lines 712 spaced apart from the first data connection portion 211; the interlayer insulating layer 640 may further include: a plurality of second data through holes 642. Among them, one second data line 122 is electrically connected to one second data transmission line 712 through the second data through hole 642. Exemplarily, one second data line 122 may correspond to one second data transmission line 712, and one second data transmission line 712 may correspond to at least one second data through hole 642, so that the second data line 122 may be electrically connected to the corresponding second data line 122 transmission line through the corresponding second data through hole 642. In practical applications, one second data transmission line 712 may correspond to one, two, three or more second data through holes 642. These may be designed and determined according to the needs of practical applications and are not limited here.

[0168] In the specific implementation, in the embodiment of the present disclosure, if Figure 6 to Figure 7b As shown, the plurality of second data transmission lines 712 are located in the first non-display area A3. For example, the plurality of second data transmission lines 712 can be arranged in an arc shape around the notch area A2. Further, the orthographic projection of the second data transmission line 712 on the base substrate 010 and the orthographic projection of the first data transmission line 711 on the base substrate 010 can be arranged at intervals. For example, Figure 6 to Figure 7bAs shown, the orthographic projection of the first data transmission line 711 on the substrate 010 and the orthographic projection of the second data transmission line 712 on the substrate 010 can be arranged alternately. Since the first data transmission line 711 and the second data transmission line 712 are located in different planes, the distance between the first data transmission line 711 and the second data transmission line 712 can be increased, and the signal interference between the first data transmission line 711 and the second data transmission line 712 can be further reduced.

[0169] Exemplarily, in order to reduce the occupied area, the orthographic projection of a second data transmission line 712 on the base substrate 010 and the orthographic projection of a first data transmission line 711 on the base substrate 010 may also have an overlapping area. Further, the orthographic projection of a second data transmission line 712 on the base substrate 010 and the orthographic projection of a first data transmission line 711 on the base substrate 010 may partially overlap, so that the occupied area of ​​the first data transmission line 711 and the second data transmission line 712 can be reduced to the greatest extent, thereby reducing the occupied area of ​​the first non-display area A3.

[0170] In the specific implementation, in the embodiment of the present disclosure, if Figure 6 to Figure 7b As shown, the plurality of scan lines may include a plurality of first scan lines GA1 and a plurality of second scan lines GA2 located in the display area A1, that is, the third conductive layer 300 may include a plurality of first scan lines GA1 and a plurality of second scan lines GA2 located in the display area A1; wherein, a row of sub-pixels spx corresponds to a first scan line GA1 and a second scan line GA2. Moreover, the second scan line GA2 corresponding to the q-1th row of sub-pixels G(q-1) in each of two adjacent rows of sub-pixels spx is electrically connected to the first scan line GA1 corresponding to the qth row of sub-pixels G(q). For example, Figure 7a and Figure 7b Four rows of sub-pixels spx are shown arranged along the second direction F2. Along the direction opposite to the arrow of the second direction F2, there may be the q-1th row of sub-pixels G(q-1), the qth row of sub-pixels G(q), the q+1th row of sub-pixels G(q+1) and the q+2th row of sub-pixels G(q+2). The second scan line GA2 corresponding to the q-1th row of sub-pixels G(q-1) is electrically connected to the first scan line GA1 corresponding to the qth row of sub-pixels G(q), and the second scan line GA2 corresponding to the qth row of sub-pixels G(q) is electrically connected to the first scan line GA1 corresponding to the q+1th row of sub-pixels G(q+1). The rest is similar, and so on, which will not be elaborated here. It should be noted that q is an integer. Figure 7a and Figure 7b Only some rows of sub-pixels spx in the display panel are shown.

[0171] In the specific implementation, in the embodiment of the present disclosure, if Figures 6 to 8aAs shown, the first conductive layer 100 may further include: a plurality of first scanning connection portions 131 insulated from the data line and the first data transmission line 711 and arranged at intervals; wherein the second scanning line GA2 corresponding to the sub-pixel G(q-1) in the q-1th row is electrically connected to the first scanning line GA1 corresponding to the sub-pixel G(q) in the qth row through at least one first scanning connection portion 131. And, the second insulating layer may further include a plurality of first scanning through holes 811 and a plurality of second scanning through holes 812; wherein the first end of the first scanning connection portion 131 is electrically connected to the corresponding first scanning line GA1 through at least one of the plurality of first scanning through holes 811, and the second end of the first scanning connection portion 131 is electrically connected to the corresponding second scanning line GA2 through at least one of the plurality of second scanning through holes 812. Exemplarily, the first scanning line GA1 and the second scanning line GA2 electrically connected to each other may correspond to one first scanning connection portion 131. One first scanning connection portion 131 may correspond to at least one first scanning through hole 811 and at least one second scanning through hole 812. For example, one first scan connection portion 131 may correspond to one first scan through hole 811 and one second scan through hole 812. The second scan line GA2 corresponding to the q-1th row of sub-pixels G(q-1) is electrically connected to the first scan line GA1 corresponding to the qth row of sub-pixels G(q), and the electrically connected second scan line GA2 corresponds to one first scan connection portion 131 with the first scan line GA1, and the first end of the first scan connection portion 131 is electrically connected to the corresponding first scan line GA1 through the corresponding first scan through hole 811, and the second end of the first scan connection portion 131 is electrically connected to the corresponding second scan line GA2 through the corresponding second scan through hole 812. The second scan line GA2 corresponding to the qth row of sub-pixels G(q) is electrically connected to the first scan line GA1 corresponding to the q+1th row of sub-pixels G(q+1), and the electrically connected second scan line GA2 corresponds to a first scan connection portion 131 with the first scan line GA1, and the first end of the first scan connection portion 131 is electrically connected to the corresponding first scan line GA1 through the corresponding first scan through hole 811, and the second end of the first scan connection portion 131 is electrically connected to the corresponding second scan line GA2 through the corresponding second scan through hole 812. The rest is similar, and so on, which will not be elaborated here. It should be noted that the second insulating layer may include: a second gate insulating layer 620 and an interlayer dielectric layer 630.

[0172] In the specific implementation, in the embodiment of the present disclosure, if Figures 6 to 8aAs shown, all row sub-pixels spx can include first-category row sub-pixels spx. At least one row of sub-pixels spx in the first-category row sub-pixels spx corresponds to at least one first data connection portion 211. Exemplarily, the first-category row sub-pixels spx can include some rows in all row sub-pixels spx. And, each row of sub-pixels spx in the first-category row sub-pixels spx can correspond to at least one first data connection portion 211. For example, each row of some row sub-pixels spx in the first-category row sub-pixels spx can correspond to one first data connection portion 211, and each row of the remaining row sub-pixels spx can correspond to two first data connection portions. Exemplarily, the first-category row sub-pixels spx can include Figure 7a and Figure 7b The qth row of sub-pixels G(q) is shown in .

[0173] In the specific implementation, in the embodiment of the present disclosure, if Figures 6 to 8a As shown, for the first scan line GA1, the second scan line GA2 and the first data connection portion 211 corresponding to the same row of sub-pixels spx, the orthographic projection of the first data connection portion 211 on the base substrate 010 does not overlap with the orthographic projection of the first scan connection portion 131 corresponding to the first scan line GA1 and the first scan connection portion 131 corresponding to the second scan line GA2 on the base substrate 010. In this way, the first data connection portion 211 and the first scan connection portion 131 can be spaced apart to reduce the risk of short circuit.

[0174] In the specific implementation, in the embodiment of the present disclosure, if Figures 6 to 8a As shown, for the first scan line GA1, the second scan line GA2, and the first data connection portion 211 corresponding to the same row of sub-pixels spx, the orthographic projection of the first data connection portion 211 on the substrate 010 is located between the first scanning through hole 811 corresponding to the first scan line GA1 and the orthographic projection of the second scanning through hole 812 corresponding to the second scan line GA2 on the substrate 010. Exemplarily, for the first scan line GA1, the second scan line GA2, and the first data connection portion 211 corresponding to the same row of sub-pixels spx, the line connecting the center of the orthographic projection of the first scanning through hole 811 corresponding to the first scan line GA1 on the substrate 010 and the center of the orthographic projection of the second scanning through hole 812 corresponding to the second scan line GA2 on the substrate overlaps with the orthographic projection of the first data connection portion 211 on the substrate 010.

[0175] It should be noted that the center of the above-mentioned orthographic projection may be the geometric center of the orthographic projection. However, in the actual manufacturing process, the shapes of the above-mentioned structures formed generally have a certain deviation from the regular shapes of the above-mentioned designs. In addition, the shapes of the above-mentioned structures actually manufactured may also have other changes from the designed shapes. Therefore, in the embodiments of the present disclosure, the center of the above-mentioned orthographic projection may have a certain offset from the geometric center of the above-mentioned orthographic projection.

[0176] In the specific implementation, in the embodiment of the present disclosure, if Figures 6 to 8a As shown, the second conductive layer 200 may further include: a plurality of second data connection parts 212; wherein, one second data transmission line 712 is directly electrically connected to at least one second data connection part 212, and the second data connection part 212 is electrically connected to one second data line 122 through a second data through hole 642. Exemplarily, one second data line 122 corresponds to one second data transmission line 712 and one second data connection part 212, and one second data connection part 212 corresponds to at least one second data through hole 642. Moreover, the second data connection part 212 is directly electrically connected to the corresponding second data transmission line 712, and the second data connection part 212 is electrically connected to the corresponding second data line 122 through the corresponding second data through hole 642. Exemplarily, in actual applications, one second data connection part 212 may correspond to one, two, three or more second data through holes 642. These may be designed and determined according to the requirements of actual applications, and are not limited here.

[0177] In the specific implementation, in the embodiment of the present disclosure, if Figure 7a and Figure 7b As shown, the projections of the first data connection portion 211 and the second data connection portion 212 on the straight line extending along the first direction F1 can be arranged alternately. Since the first data lines 121 and the second data lines 122 are arranged alternately along the first direction F1, by arranging the projections of the first data connection portion 211 and the second data connection portion 212 on the straight line extending along the first direction F1 alternately, the first data connection portion 211 electrically connected to the first data line 121 and the second data connection portion 212 electrically connected to the second data line 122 can be arranged correspondingly, thereby reducing signal interference.

[0178] In the specific implementation, in the embodiment of the present disclosure, if Figures 6 to 8a As shown, the orthographic projections of the first data connection portion 211 and the second data connection portion 212 on the base substrate 010 may not overlap with the orthographic projections of the first scan connection portion 131 , the first scan line GA1 , the second scan line GA2 and the light emitting control line EM on the base substrate 010 .

[0179] In the specific implementation, in the embodiment of the present disclosure, if Figure 7a and Figure 7b As shown, the light-emitting control lines corresponding to two adjacent rows of sub-pixels spx can be electrically connected. Exemplarily, the light-emitting control lines corresponding to the sub-pixels G(q-1) in the q-1th row are electrically connected to the light-emitting control lines corresponding to the sub-pixels G(q) in the qth row and the light-emitting control lines corresponding to the sub-pixels G(q+1) in the q+1th row are electrically connected, and the light-emitting control lines corresponding to the sub-pixels G(q+2) in the q+2th row are electrically connected to the light-emitting control lines corresponding to the sub-pixels G(q+3) in the q+3th row. The rest are similar, and so on, which will not be elaborated here.

[0180] In the specific implementation, in the embodiment of the present disclosure, if Figure 7a , Figure 7b and Figure 8a As shown, the first conductive layer 100 may further include: a plurality of first light-emitting connection parts 141 insulated from the data line and the first data transmission line 711 and arranged at intervals; wherein the mutually electrically connected light-emitting control line corresponds to at least one first light-emitting connection part 141. The second insulating layer may include a plurality of first light-emitting through holes 821 and a plurality of second light-emitting through holes 822. Also, the first end of the first light-emitting connection part 141 is electrically connected to a corresponding light-emitting control line through at least one of the plurality of first light-emitting through holes 821, and the second end of the first light-emitting connection part 141 is electrically connected to another corresponding light-emitting control line through at least one of the plurality of second light-emitting through holes 822. Exemplarily, the mutually electrically connected light-emitting control lines may correspond to one first light-emitting connection part 141, and one first light-emitting connection part 141 corresponds to at least one first light-emitting through hole 821 and at least one second light-emitting through hole 822. Also, the first end of the first light-emitting connection part 141 is electrically connected to the corresponding light-emitting control line through the corresponding first light-emitting through hole 821, and the second end of the first light-emitting connection part 141 is electrically connected to another corresponding light-emitting control line through the corresponding second light-emitting through hole 822. For example, the first end of the first light-emitting connection portion 141 is electrically connected to the light-emitting control line corresponding to the q-th row sub-pixel G(q) through the corresponding first light-emitting through hole 821, and the second end of the first light-emitting connection portion 141 is electrically connected to the light-emitting control line corresponding to the q+1-th row sub-pixel G(q+1) through the corresponding second light-emitting through hole 822. Exemplarily, one first light-emitting connection portion 141 may correspond to one, two, three or more first light-emitting through holes 821. One first light-emitting connection portion 141 may correspond to one, two, three or more second light-emitting through holes 822. These can be designed and determined according to the needs of actual applications and are not limited here.

[0181] In the specific implementation, in the embodiment of the present disclosure, if Figures 7a to 8aAs shown, the third conductive layer 300 may further include a plurality of first scanning transmission lines 311 and a plurality of first light-emitting transmission lines 321 located in the first non-display area A3; wherein the first scanning transmission lines 311 and the first light-emitting transmission lines 321 are arranged at intervals. Exemplarily, the orthographic projection of the first scanning transmission line 311 on the substrate substrate 010 and the orthographic projection of the first light-emitting transmission line 321 on the substrate substrate 010 may be arranged at intervals. Further, the orthographic projection of the first scanning transmission line 311 on the substrate substrate 010 and the orthographic projection of the first light-emitting transmission line 321 on the substrate substrate 010 may be arranged alternately. Further, the first scanning transmission line 311 and the first light-emitting transmission line 321 may be arranged in an arc shape around the first non-display area A3. Of course, these may be designed and determined according to the needs of actual applications and are not limited here.

[0182] In the specific implementation, in the embodiment of the present disclosure, if Figures 7a to 8a As shown, some of the first scan lines GA1 and the second scan lines GA2 that are electrically connected to each other are directly and correspondingly electrically connected to a first scan transmission line 311; and some of the light-emitting control lines that are electrically connected to each other are directly and electrically connected to a first light-emitting transmission line 321. In this way, the first scan line GA1 in the third conductive layer 300 can be directly and electrically connected to the first scan transmission line 311, and the light-emitting control line can be directly and electrically connected to the first light-emitting transmission line 321, thereby reducing the difficulty of designing these signal lines.

[0183] In the specific implementation, in the embodiment of the present disclosure, if Figures 7a to 8a As shown, the fourth conductive layer 400 may further include a plurality of second scanning transmission lines 411 and a plurality of second light-emitting transmission lines 421 located in the first non-display area A3; wherein the second scanning transmission lines 411 and the second light-emitting transmission lines 421 are arranged at intervals. Exemplarily, the orthographic projection of the second scanning transmission line 411 on the substrate substrate 010 and the orthographic projection of the second light-emitting transmission line 421 on the substrate substrate 010 may be arranged at intervals. Further, the orthographic projection of the second scanning transmission line 411 on the substrate substrate 010 and the orthographic projection of the second light-emitting transmission line 421 on the substrate substrate 010 may be arranged alternately. Further, the second scanning transmission line 411 and the second light-emitting transmission line 421 may be arranged in an arc shape around the first non-display area A3. Of course, these can be designed and determined according to the needs of actual applications and are not limited here.

[0184] In the specific implementation, in the embodiment of the present disclosure, if Figures 7a to 8aAs shown, the interlayer dielectric layer 630 may further include a plurality of third scanning through holes 813 and a plurality of third light-emitting through holes 823. In addition to the first scanning line GA1 and the second scanning line GA2 that are partially electrically connected to each other, the remaining first scanning lines GA1 and the second scanning lines GA2 that are electrically connected to each other correspond to a second scanning transmission line 411, and the first scanning connection portion 131 corresponding to the remaining first scanning lines GA1 that are electrically connected to each other is also electrically connected to the second scanning transmission line 411 through the third scanning through hole 813. In this way, the first scanning lines GA1 corresponding to the same row of sub-pixels spx and separated by the notch area A2 can be electrically connected through the second scanning transmission line 411. Exemplarily, a second scanning transmission line 411 may correspond to one, two, three or more third scanning through holes 813. These can be designed and determined according to the needs of actual applications and are not limited here.

[0185] In the specific implementation, in the embodiment of the present disclosure, if Figures 7a to 8a As shown, in addition to the aforementioned partially mutually electrically connected light-emitting control lines, the remaining mutually electrically connected light-emitting control lines correspond to a second light-emitting transmission line 421, and the first light-emitting connection portion 141 is also electrically connected to the second light-emitting transmission line 421 through a third light-emitting through hole 823. In this way, the light-emitting control lines corresponding to the same row of sub-pixels spx and separated by the notch area A2 can be electrically connected through the second light-emitting transmission line 421. Exemplarily, a second light-emitting transmission line 421 can correspond to one, two, three or more third light-emitting through holes 823. These can be designed and determined according to the needs of actual applications and are not limited here.

[0186] Furthermore, by disposing the first scan transmission line 311, the second scan transmission line 411, the first light-emitting transmission line 321, and the second light-emitting transmission line 421 in the first non-display area A3, and disposing the first scan transmission line 311 and the first light-emitting transmission line 321 in the third conductive layer 300, and disposing the second scan transmission line 411 and the second light-emitting transmission line 421 in the fourth conductive layer 400, signal interference between the first scan transmission line 311, the second scan transmission line 411, the first light-emitting transmission line 321, and the second light-emitting transmission line 421 can be reduced.

[0187] Exemplarily, the orthographic projection of the first scanning transmission line 311 on the substrate substrate 010 and the orthographic projection of part of the first data transmission line 711 on the substrate substrate 010 may have an overlapping area. Further, the orthographic projection of one first scanning transmission line 311 on the substrate substrate 010 and the orthographic projection of one first data transmission line 711 on the substrate substrate 010 may partially overlap. Exemplarily, the orthographic projection of the first light emitting transmission line 321 on the substrate substrate 010 and the orthographic projection of the remaining first data transmission lines 711 on the substrate substrate 010 may have an overlapping area. Further, the orthographic projection of one first light emitting transmission line 321 on the substrate substrate 010 and the orthographic projection of one of the remaining first data transmission lines 711 on the substrate substrate 010 may partially overlap. In this way, the occupied area of ​​the first non-display area can be reduced.

[0188] Exemplarily, the orthographic projection of the second scanning transmission line 411 on the substrate substrate 010 and the orthographic projection of part of the second data transmission line 712 on the substrate substrate 010 may have an overlapping area. Further, the orthographic projection of one second scanning transmission line 411 on the substrate substrate 010 and the orthographic projection of one second data transmission line 712 on the substrate substrate 010 may partially overlap. Exemplarily, the orthographic projection of the second light-emitting transmission line 421 on the substrate substrate 010 and the orthographic projection of the remaining second data transmission line 712 on the substrate substrate 010 may have an overlapping area. Further, the orthographic projection of one second light-emitting transmission line 421 on the substrate substrate 010 and the orthographic projection of one second data transmission line 712 in the remaining part on the substrate substrate 010 may partially overlap. In this way, the occupied area of ​​the first non-display area can be reduced.

[0189] In the specific implementation, in the embodiment of the present disclosure, if Figures 7a to 8a As shown, all row sub-pixels spx may also include second-category row sub-pixels spx; the second-category row sub-pixels spx are different from the first-category row sub-pixels spx. Moreover, at least one row of sub-pixels spx in the second-category row sub-pixels spx corresponds to at least one second data connection portion 212. Exemplarily, each row of sub-pixels spx in the second-category row sub-pixels spx corresponds to at least one second data connection portion 212. Exemplarily, each row of sub-pixels spx in the second-category row sub-pixels spx corresponds to one second data connection portion 212. It should be noted that the second-category row sub-pixels spx may be part of the rows in the display panel, and their specific positions may be designed and determined according to the requirements of the actual application environment, and are not limited here. Exemplarily, the second-category row sub-pixels spx may include Figure 7b The first row of sub-pixels and the third row of sub-pixels in .

[0190] In the specific implementation, in the embodiment of the present disclosure, if Figures 7a to 8aAs shown, for the first scan line GA1, the second scan line GA2 and the second data connection portion 212 corresponding to the same row of sub-pixels spx, the orthographic projection of the second data connection portion 212 on the base substrate 010 does not overlap with the orthographic projection of the first scan connection portion 131 corresponding to the first scan line GA1 and the orthographic projection of the first scan connection portion 131 corresponding to the second scan line GA2 on the base substrate 010. In this way, the second data connection portion 212 can be spaced apart from the first scan connection portion 131, reducing the risk of short circuit.

[0191] In the specific implementation, in the embodiment of the present disclosure, if Figures 7a to 8a As shown, for the first scan line GA1, the second scan line GA2, and the second data connection portion 212 corresponding to the same row of sub-pixels spx, the orthographic projection of the second data connection portion 212 on the substrate 010 is located between the first scanning through hole 811 corresponding to the first scan line GA1 and the orthographic projection of the second scanning through hole 812 corresponding to the second scan line GA2 on the substrate 010. Exemplarily, for the first scan line GA1, the second scan line GA2, and the second data connection portion 212 corresponding to the same row of sub-pixels spx, the line connecting the center of the orthographic projection of the second scanning through hole 812 corresponding to the first scan line GA1 on the substrate 010 and the center of the orthographic projection of the second scanning through hole 812 corresponding to the second scan line GA2 on the substrate overlaps with the orthographic projection of the second data connection portion 212 on the substrate 010.

[0192] In the specific implementation, in the embodiment of the present disclosure, if Figures 7a to 8a As shown, the orthographic projection of the second data connection portion 212 on the base substrate 010 does not overlap with the orthographic projection of the first light emitting connection portion 141 on the base substrate 010, the orthographic projection of the first scanning connection portion 131 on the base substrate 010, the orthographic projection of the first scanning line GA1 on the base substrate 010, and the orthographic projection of the second scanning line GA2 on the base substrate 010.

[0193] In the specific implementation, in the embodiment of the present disclosure, if Figures 7a to 8a As shown, for the light-emitting control line EM, the second scanning line GA2 and the second data connection part 212 corresponding to the same row of sub-pixels spx, the orthographic projection of the second data connection part 212 on the base substrate 010 is located between the orthographic projections of the second scanning through hole 812 corresponding to the second scanning line GA2 and the first light-emitting through hole 821 corresponding to the light-emitting control line on the base substrate 010.

[0194] Since in practical applications, the transistors in the sub-pixels spx generally need to be electrically connected, and the electrical connections of these transistors are related to their transistor characteristics, the uniform electrical connections of the transistors can make the characteristics of the transistors uniform. Generally, a wet etching method is used to prepare a through hole for electrical connection by an etching solution. However, when etching the through hole of the sub-pixel spx at the edge of the display area A1, the through hole does not need to be etched outside the edge of the display area A1, so that the etching degree of the through hole of the sub-pixel spx at the edge of the display area A1 is different from the etching degree of the through hole of the sub-pixel spx inside the display area A1, resulting in the transistors in the sub-pixel spx at the edge of the display area A1 and the transistors in the sub-pixel spx inside the display area A1. The characteristics are not uniform. In order to improve the uniformity of the characteristics of the transistors, in the specific implementation, in the embodiment of the present disclosure, the display panel and the target insulating layer located between the first conductive layer and the base substrate, the functional layer located between the target insulating layer and the base substrate, at least one of the multiple sub-pixels may include: a connecting through hole; wherein the connecting through hole penetrates the target insulating layer, and the first conductive layer is electrically connected to the functional layer through the connecting through hole. The first non-display area includes at least one auxiliary through hole: wherein the auxiliary through hole penetrates the target insulating layer and the auxiliary through hole is not filled with conductive material. Furthermore, in the first non-display area, at least two transmission lines among a plurality of data transmission lines, a plurality of scanning transmission lines, and a plurality of light transmission lines are surrounded to form an auxiliary area, and the auxiliary through hole is located in the auxiliary area. Further, exemplarily, the spacing between two adjacent auxiliary through holes can also be made less than or substantially equal to the spacing between two adjacent connecting through holes.

[0195] Since in actual applications, the first connecting through hole is used to realize the electrical connection of the transistors in the sub-pixel spx, and the electrical connection of these transistors is related to their transistor characteristics, the electrical connection of the transistor is uniform, and the characteristics of the transistor can be made uniform. Generally, a wet etching method is adopted to prepare the first connecting through hole by an etching liquid. However, when etching the first connecting through hole of the sub-pixel spx at the edge of the display area A1, the first connecting through hole does not need to be etched outside the edge of the display area A1, so that the etching degree of the first connecting through hole of the sub-pixel spx at the edge of the display area A1 is different from the etching degree of the first connecting through hole of the sub-pixel spx inside the display area A1, resulting in uneven characteristics of the transistors in the sub-pixel spx at the edge of the display area A1 and the transistors in the internal sub-pixel spx. In order to improve the uniformity of transistor characteristics, in a specific implementation, in the embodiment of the present disclosure, the functional layer may include a semiconductor layer; the target insulating layer may include: a first gate insulating layer, a second gate insulating layer, and an interlayer dielectric layer; the connecting via may include a first connecting via; the auxiliary via may include a first auxiliary via, and the first auxiliary via penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer. For example, Figures 7a to 8cAs shown, the display panel may further include at least one first auxiliary through hole 911 located in the first non-display area A3. The first auxiliary through hole 911 penetrates the first gate insulating layer 610, the second gate insulating layer 620 and the interlayer dielectric layer 630, and the first auxiliary through hole 911 is not filled with conductive material. Moreover, in the first non-display area A3, at least two transmission lines among a plurality of data transmission lines, a plurality of scanning transmission lines and a plurality of light transmission lines may surround and form an auxiliary area FB, and the first auxiliary through hole 911 may be located in the auxiliary area FB. In this way, the first auxiliary through hole 911 may be arranged outside the edge of the display area A1, that is, in the first non-display area A3, and the first auxiliary through hole 911 and the first connection through hole penetrate the same insulating layer. Thus, the first auxiliary through hole 911 is also etched in the first non-display area A3, and the etching effect of the first connection through hole etched in the display edge sub-pixel spx and the first connection through hole etched in the internal sub-pixel spx may be uniform, thereby improving the uniformity of the characteristics of the transistor.

[0196] In a specific implementation, an insulating material may be filled in the first auxiliary through hole 911. For example, the material of the interlayer insulating layer 640 may be filled in the first auxiliary through hole 911. In this way, when the interlayer insulating layer 640 is prepared, the first auxiliary through hole 911 may be directly filled, thereby improving the flatness of the interlayer insulating layer 640.

[0197] During specific implementation, the specific transmission lines used to surround the auxiliary area FB can be designed and determined according to actual application requirements, and are not limited here.

[0198] It should be noted that, since the semiconductor layer in the first non-display area A3 is not etched away when the semiconductor layer is patterned, the semiconductor layer is still retained in the first non-display area A3. Figure 8b and Figure 8c As shown. In this way, the depth of the first auxiliary through hole 911 in the direction perpendicular to the plane where the substrate is located is substantially the same as the depth of the first connecting through hole in the direction perpendicular to the plane where the substrate is located. In this way, the etching liquid can etch the first auxiliary through hole 911 and the first connecting through hole to substantially the same extent, thereby further improving the characteristic uniformity of the transistor.

[0199] For example, in a specific implementation, in the embodiment of the present disclosure, a plurality of first auxiliary through holes 911 may be provided in the first non-display area A3. For example, the distribution density of the first auxiliary through holes 911 may be made substantially equal to the distribution density of the first connection through holes. In this way, the etching effects of the first connection through holes etched in the display edge sub-pixels spx and the first connection through holes etched in the internal sub-pixels spx may be made uniform, thereby improving the uniformity of transistor characteristics.

[0200] For example, in a specific implementation, in the embodiment of the present disclosure, the distribution density of the first auxiliary through holes 911 can also be made smaller than the distribution density of the first connection through holes. Since other wirings or connection parts are also provided in the first non-display area A3, by reducing the distribution density of the first auxiliary through holes 911, the occupied area of ​​all the first auxiliary through holes 911 as a whole can be reduced, and the occupied area of ​​the first non-display area A3 can be reduced. In addition, by providing the first auxiliary through holes 911, the etching effects of the first connection through holes etched in the display edge sub-pixels spx and the first connection through holes etched in the internal sub-pixels spx can be made uniform, thereby improving the uniformity of the characteristics of the transistor.

[0201] It should be noted that the distribution density of the first auxiliary through holes 911 may be the number of the first auxiliary through holes 911 per unit area. The distribution density of the first connecting through holes may be the number of the first connecting through holes per unit area. In practical applications, the distribution density of the first auxiliary through holes 911 and the first connecting through holes may be designed and determined according to the requirements of the actual application environment, and is not limited here.

[0202] For example, in a specific implementation, in the disclosed embodiment, the spacing between two adjacent first auxiliary through holes can be made substantially equal to the spacing between two adjacent first connecting through holes. In this way, there is no need to additionally design the spacing between the first auxiliary through holes, and the spacing between the first connecting through holes can be used for design. Of course, the spacing between two adjacent first auxiliary through holes can also be made smaller than the spacing between two adjacent first connecting through holes. In this way, the first auxiliary through holes can be arranged more compactly, reducing the occupied area of ​​the first non-display area.

[0203] For example, in a specific implementation, in the embodiments of the present disclosure, if Figures 7a to 8c As shown, the orthographic projection of the first auxiliary through hole 911 on the base substrate 010 does not overlap with the orthographic projections of the semiconductor layer, the first conductive layer 100, the third conductive layer 300 and the fourth conductive layer 400 on the base substrate 010. This can reduce the impact on the conductive layer and the semiconductor layer when etching the first auxiliary through hole 911.

[0204] Since in practical applications, the second connection through hole is also used to realize the electrical connection of the transistors in the sub-pixel spx, and the electrical connection of these transistors is related to the transistor characteristics, the electrical connection of the transistor is uniform, and the characteristics of the transistor can be made uniform. Generally, a wet etching method is used to prepare the second connection through hole by an etching solution. However, when etching the second connection through hole of the sub-pixel spx at the edge of the display area A1, the second connection through hole does not need to be etched outside the edge of the display area A1, so that the etching degree of the second connection through hole of the sub-pixel spx at the edge of the display area A1 is different from the etching degree of the second connection through hole of the sub-pixel spx inside the display area A1, resulting in the transistors in the sub-pixel spx at the edge of the display area A1 and the transistors in the sub-pixel spx inside the display area A1. The characteristics are not uniform. In order to improve the uniformity of the characteristics of the transistors, in the specific implementation, in the embodiment of the present disclosure, the functional layer includes a third conductive layer; the target insulating layer includes: a second gate insulating layer and an interlayer dielectric layer; the connection through hole includes a second connection through hole; the auxiliary through hole includes a second auxiliary through hole, and the second auxiliary through hole runs through the second gate insulating layer and the interlayer dielectric layer. For example, Figure 7b and Figure 8c As shown, the display panel may further include at least one second auxiliary through hole 912 located in the first non-display area A3; wherein the second auxiliary through hole 912 penetrates the second gate insulation layer 620 and the interlayer dielectric layer 630, and the second auxiliary through hole 912 is not filled with a conductive material. In addition, the second auxiliary through hole 912 may also be located in the auxiliary region FB. In a specific implementation, an insulating material may be filled in the second auxiliary through hole 912. For example, the material of the interlayer insulation layer 640 may be filled in the second auxiliary through hole 912. In this way, when preparing the interlayer insulation layer 640, the second auxiliary through hole 912 may be directly filled, thereby improving the flatness of the interlayer insulation layer 640.

[0205] For example, in a specific implementation, in the embodiment of the present disclosure, a plurality of second auxiliary through holes 912 may be provided in the first non-display area A3. For example, the distribution density of the second auxiliary through holes 912 may be made substantially equal to the distribution density of the second connection through holes. In this way, the etching effects of the second connection through holes etched in the display edge sub-pixels spx and the second connection through holes etched in the internal sub-pixels spx may be made uniform, thereby improving the uniformity of transistor characteristics.

[0206] For example, in a specific implementation, in the embodiment of the present disclosure, the distribution density of the second auxiliary through holes 912 can also be made smaller than the distribution density of the second connection through holes. Since other wirings or connection parts are also provided in the first non-display area A3, by reducing the distribution density of the second auxiliary through holes 912, the occupied area of ​​all the second auxiliary through holes 912 as a whole can be reduced, and the occupied area of ​​the first non-display area A3 can be reduced. In addition, by providing the second auxiliary through holes 912, the etching effects of the second connection through holes etched in the display edge sub-pixels spx and the first connection through holes etched in the internal sub-pixels spx can be made uniform, thereby improving the uniformity of the characteristics of the transistor.

[0207] It should be noted that the distribution density of the second auxiliary through holes 912 may be the number of the second auxiliary through holes 912 per unit area. The distribution density of the second connecting through holes may be the number of the second connecting through holes per unit area. In practical applications, the distribution density of the second auxiliary through holes 912 and the second connecting through holes may be designed and determined according to the requirements of the actual application environment, and is not limited here.

[0208] It should be noted that, since the third conductive layer 300 in the first non-display area A3 will be etched away when the third conductive layer 300 is patterned, the third conductive layer 300 will not be retained in the first non-display area A3. Figure 8c As shown, in this way, the depth of the second auxiliary through hole 912 in the direction perpendicular to the plane where the substrate is located is greater than the depth of the second connecting through hole in the direction perpendicular to the plane where the substrate is located.

[0209] For example, in a specific implementation, in the embodiment of the present disclosure, the spacing between two adjacent second auxiliary through holes can be made substantially equal to the spacing between two adjacent second connecting through holes. In this way, there is no need to additionally design the spacing between the second auxiliary through holes, and the spacing between the second connecting through holes can be used for design. Of course, the spacing between two adjacent second auxiliary through holes can also be made smaller than the spacing between two adjacent second connecting through holes. In this way, the second auxiliary through holes can be arranged more compactly, reducing the occupied area of ​​the second non-display area.

[0210] For example, in a specific implementation, in the embodiments of the present disclosure, if Figure 7b As shown, the orthographic projection of the second auxiliary through hole 912 on the base substrate 010 does not overlap with the orthographic projections of the first conductive layer 100, the third conductive layer 300 and the fourth conductive layer 400 on the base substrate 010. This can reduce the impact on the conductive layer and the semiconductor layer when etching the second auxiliary through hole 912.

[0211] Since in actual applications, the third connecting through hole is also used to realize the electrical connection of the transistors in the sub-pixel spx, and the electrical connection of these transistors is related to their transistor characteristics, the electrical connection of the transistor is uniform, and the characteristics of the transistor can be made uniform. Generally, a wet etching method is adopted to prepare the third connecting through hole by an etching liquid. However, when etching the third connecting through hole of the sub-pixel spx at the edge of the display area A1, the third connecting through hole does not need to be etched outside the edge of the display area A1, so that the etching degree of the third connecting through hole of the sub-pixel spx at the edge of the display area A1 is different from the etching degree of the third connecting through hole of the sub-pixel spx inside the display area A1, resulting in the transistors in the sub-pixel spx at the edge of the display area A1 and the transistors in the sub-pixel spx inside the display area A1. Characteristics are not uniform. In order to improve the uniformity of the characteristics of the transistors, in the specific implementation, in the embodiment of the present disclosure, the functional layer includes a fourth conductive layer; the target insulating layer includes: an interlayer dielectric layer; the connecting through hole includes a third connecting through hole; the auxiliary through hole includes a third auxiliary through hole, and the third auxiliary through hole runs through the interlayer dielectric layer. For example, as Figure 7b and Figure 8c As shown, the display panel may further include at least one third auxiliary through hole 913 located in the first non-display area A3; the third auxiliary through hole 913 penetrates the interlayer dielectric layer 630, and the third auxiliary through hole 913 is not filled with a conductive material. In addition, the third auxiliary through hole 913 may also be located in the auxiliary region FB. In a specific implementation, an insulating material may be filled in the third auxiliary through hole 913. For example, the material of the interlayer insulating layer 640 may be filled in the third auxiliary through hole 913. In this way, when preparing the interlayer insulating layer 640, the third auxiliary through hole 913 may be directly filled, thereby improving the flatness of the interlayer insulating layer 640.

[0212] For example, in a specific implementation, in the embodiment of the present disclosure, a plurality of third auxiliary through holes 913 may be provided in the first non-display area A3. For example, the distribution density of the third auxiliary through holes 913 may be made substantially equal to the distribution density of the third connection through holes. In this way, the etching effects of the third connection through holes etched in the display edge sub-pixels spx and the third connection through holes etched in the internal sub-pixels spx may be made uniform, thereby improving the uniformity of transistor characteristics.

[0213] For example, in a specific implementation, in the embodiment of the present disclosure, the distribution density of the third auxiliary through holes 913 can also be made smaller than the distribution density of the third connection through holes. Since other wirings or connection parts are also provided in the first non-display area A3, by reducing the distribution density of the third auxiliary through holes 913, the occupied area of ​​all the third auxiliary through holes 913 as a whole can be reduced, and the occupied area of ​​the first non-display area A3 can be reduced. In addition, by providing the third auxiliary through holes 913, the etching effects of the third connection through holes etched in the display edge sub-pixels spx and the first connection through holes etched in the internal sub-pixels spx can be made uniform, thereby improving the uniformity of the characteristics of the transistors.

[0214] It should be noted that the distribution density of the third auxiliary through holes 913 may be the number of the third auxiliary through holes 913 per unit area. The distribution density of the third connecting through holes may be the number of the third connecting through holes per unit area. In practical applications, the distribution density of the third auxiliary through holes 913 and the third connecting through holes may be designed and determined according to the requirements of the actual application environment, and is not limited here.

[0215] It should be noted that, since the fourth conductive layer 400 in the first non-display area A3 will be etched away when the fourth conductive layer 400 is patterned, the fourth conductive layer 400 will not be retained in the first non-display area A3. Figure 8c As shown, in this way, the depth of the third auxiliary through hole 913 in the direction perpendicular to the plane where the substrate is located is greater than the depth of the third connecting through hole in the direction perpendicular to the plane where the substrate is located.

[0216] For example, in a specific implementation, in the disclosed embodiment, the spacing between two adjacent third auxiliary through holes can be made substantially equal to the spacing between two adjacent third connecting through holes. In this way, there is no need to additionally design the spacing between the third auxiliary through holes, and the spacing between the third connecting through holes can be used for design. Of course, the spacing between two adjacent third auxiliary through holes can also be made smaller than the spacing between two adjacent third connecting through holes. In this way, the third auxiliary through holes can be arranged more compactly, reducing the occupied area of ​​the first non-display area.

[0217] For example, in a specific implementation, in the embodiments of the present disclosure, if Figure 7b As shown, the orthographic projection of the third auxiliary through hole 913 on the base substrate 010 does not overlap with the orthographic projections of the first conductive layer 100 and the fourth conductive layer 400 on the base substrate 010. This can reduce the impact on the conductive layer and the semiconductor layer when etching the third auxiliary through hole 913.

[0218] It should be noted that Figure 8aAs shown, GA1-G(q) represents the first scan line corresponding to the qth row of sub-pixels. GA2-G(q) represents the second scan line corresponding to the qth row of sub-pixels. GA1-G(q+1) represents the first scan line corresponding to the q+1th row of sub-pixels. EM-G(q) represents the light-emitting control line corresponding to the qth row of sub-pixels. EM-G(q+1) represents the light-emitting control line corresponding to the q+1th row of sub-pixels. The same applies to the following and will not be repeated.

[0219] It should be noted that due to the limitation of process conditions or other factors, the same or equal to the above-mentioned features may not be completely the same or equal to each other, and there may be some deviations. Therefore, as long as the same or equal relationship between the above-mentioned features roughly meets the above-mentioned conditions, they all belong to the protection scope of the present disclosure. For example, the above-mentioned sameness can be the sameness allowed within the allowable error range.

[0220] The present disclosure also provides other display panels, such as Figures 9a to 10c As shown, some implementation methods in the above embodiment are modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0221] In the specific implementation, in the embodiments of the present disclosure. Figures 9a to 10a As shown, for the first scan line GA1 and the first data connection part 211 corresponding to the same row of sub-pixels spx, and the first data line 121 and the first data transmission line 711 electrically connected by the first data connection part 211, the orthographic projection of the first data connection part 211 on the substrate substrate 010 and the orthographic projection of the first scan line GA1 on the substrate substrate 010 have an overlapping area, and the orthographic projections of the first data line 121 and the first data transmission line 711 on the substrate substrate 010 do not overlap with the orthographic projection of the first scan line GA1 on the substrate substrate 010. In this way, it is avoided that the first scan line GA1 and the first data line 121 have a facing area. In addition, since the first data connection part 211 is located in the second conductive layer 200, the spacing between the first scan line GA1 and the first data connection part 211 can be made larger, so that the coupling capacitance between the first scan line GA1 and the first data connection part 211 can be reduced to a small extent, thereby reducing signal interference, and further improving the display effect.

[0222] In the specific implementation, in the embodiments of the present disclosure. Figures 9a to 10aAs shown, for the first scan line GA1 and the first data connection portion 211 corresponding to the same row of sub-pixels spx, the orthographic projection of the edge region of the first data connection portion 211 on the substrate 010 has an overlapping region with the orthographic projection of the first scan line GA1 on the substrate 010. Alternatively, for the first scan line GA1 and the first data connection portion 211 corresponding to the same row of sub-pixels spx, the orthographic projection of the center region of the first data connection portion 211 on the substrate 010 has an overlapping region with the orthographic projection of the first scan line GA1 on the substrate 010.

[0223] In the specific implementation, in the embodiments of the present disclosure. Figures 9a to 10a As shown, some of the row sub-pixels spx in the first type of row sub-pixels spx correspond to two first data connection parts. Figure 9a and Figure 9b The q+2th row of sub-pixels G(q+2) in the graph may correspond to two first data connection parts: 211a and 211b. Among them, for the first scan line GA1, the second scan line GA2 and the two first data connection parts corresponding to the same row of sub-pixels spx, the orthographic projections of the two first data connection parts 211a and 211b on the substrate 010 may have an overlapping area with the orthographic projection of the first scan line GA1 on the substrate 010, and the orthographic projections of the two first data connection parts 211a and 211b on the substrate 010 may not overlap with the orthographic projection of the second scan line GA2 on the substrate 010.

[0224] In the specific implementation, in the embodiments of the present disclosure. Figures 9a to 10a As shown, for the first scan line GA1, the second scan line GA2, and the two first data connection parts a and 211b corresponding to the same row of sub-pixels spx, the orthographic projection of the first first data connection part 211a of the two first data connection parts on the substrate 010 is close to the orthographic projection of the first scanning through hole 811 corresponding to the first scan line GA1 on the substrate 010. Exemplarily, compared with the second first data connection part 211b, the orthographic projection of the first first data connection part 211a of the two first data connection parts on the substrate 010 can be close to the orthographic projection of the first scanning through hole 811 corresponding to the first scan line GA1 on the substrate 010.

[0225] In the specific implementation, in the embodiments of the present disclosure. Figures 9a to 10aAs shown, for the first scan line GA1, the second scan line GA2 and the two first data connection parts corresponding to the same row of sub-pixels spx, the orthographic projection of the second first data connection part 211b of the two first data connection parts on the substrate substrate 010 is close to the orthographic projection of the second scanning through hole 812 corresponding to the second scan line GA2 on the substrate substrate 010. Exemplarily, compared with the first first data connection part 211a, the orthographic projection of the second first data connection part 211b of the two first data connection parts on the substrate substrate 010 can be close to the orthographic projection of the second scanning through hole 812 corresponding to the second scan line GA2 on the substrate substrate 010.

[0226] In the specific implementation, in the embodiments of the present disclosure. Figures 9a to 10a As shown, for the first scan line GA1 and the second data connection part 212 corresponding to the same row of sub-pixels spx, and the second data line 122 and the second data transmission line 712 electrically connected by the second data connection part 212, the orthographic projection of the second data connection part 212 on the substrate substrate 010 and the orthographic projection of the first scan line GA1 on the substrate substrate 010 have an overlapping area, and the orthographic projection of the second data line 122 and the second data transmission line 712 on the substrate substrate 010 do not overlap with the orthographic projection of the first scan line GA1 on the substrate substrate 010.

[0227] In the specific implementation, in the embodiments of the present disclosure. Figures 9a to 10a As shown, for a row of sub-pixels corresponding to two first data connection parts, the row of sub-pixels also corresponds to a second data connection part 212. For the first scan line GA1 and the second data connection part 212 corresponding to the same row of sub-pixels, and the second data line 122 and the second data transmission line 712 electrically connected by the second data connection part 212, the orthographic projection of the second data connection part 212 on the substrate substrate 010 and the orthographic projection of the first scan line GA1 on the substrate substrate 010 have an overlapping area, and the orthographic projection of the second data line 122 and the second data transmission line 712 on the substrate substrate 010 do not overlap with the orthographic projection of the first scan line GA1 on the substrate substrate 010.

[0228] It should be noted that if Fig.10b and Fig.10c As shown, the display panel is further provided with a first auxiliary through hole 911, a second auxiliary through hole 912 and a third auxiliary through hole 913. Moreover, the arrangement of the first auxiliary through hole 911, the second auxiliary through hole 912 and the third auxiliary through hole 913 can refer to the above embodiment, and will not be described here.

[0229] The present disclosure also provides some display panels, such as Fig.11 and Fig.12As shown, some implementation methods in the above embodiment are modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0230] In the specific implementation, in the embodiments of the present disclosure. Fig.11 and Fig.12 As shown, the fourth conductive layer 400 may further include a plurality of third scan transmission lines 413 located in the first non-display area A3. In addition, the interlayer dielectric layer 630 may further include a plurality of fourth scan through holes 814; the first scan line GA1 and the second scan line GA2 electrically connected to each other correspond to one third scan transmission line 413, and the first scan connection portion 131 is also electrically connected to the third scan transmission line 413 through the fourth scan through hole 814. The third conductive layer 300 may further include a third light-emitting transmission line 423 located in the first non-display area A3; wherein the light-emitting control lines electrically connected to each other are directly electrically connected to one third light-emitting transmission line 423. In this way, the third light-emitting transmission line 423 may be provided in the third conductive layer 300, and the third scan transmission line 413 may be provided in the fourth conductive layer 400.

[0231] Exemplarily, in order to reduce signal interference, the orthographic projection of the third scanning transmission line 413 on the base substrate 010 does not overlap with the orthographic projection of the third light emitting transmission line 423 on the base substrate 010. Further, the orthographic projection of the third scanning transmission line 413 on the base substrate 010 and the orthographic projection of the third light emitting transmission line 423 on the base substrate 010 are arranged at intervals.

[0232] Further, in order to reduce signal interference, the orthographic projection of the third scan transmission line 413 on the base substrate 010 and the orthographic projection of the second data transmission line 712 on the base substrate 010 may have an overlapping area. Further, the orthographic projection of the third scan transmission line 413 on the base substrate 010 and the orthographic projection of the second data transmission line 712 on the base substrate 010 may partially overlap. Since the third scan transmission layer is located in the fourth conductive layer 400 and the second data transmission line 712 is located in the second conductive layer 200, this can not only reduce the coupling capacitance between the third scan transmission line 413 and the second data transmission line 712, but also reduce the occupied area of ​​the first non-display area A3.

[0233] Further, in order to reduce signal interference, the orthographic projection of the third light emitting transmission line 423 on the substrate 010 and the orthographic projection of the first data transmission line 711 on the substrate 010 may have an overlapping area. Further, the orthographic projection of the third light emitting transmission line 423 on the substrate 010 and the orthographic projection of the first data transmission line 711 on the substrate 010 may partially overlap. Since the third light emitting transmission line 423 is located in the third conductive layer 300 and the first data transmission line 711 is located in the first conductive layer 100, this can not only reduce the coupling capacitance between the third light emitting transmission layer and the first data transmission line 711, but also reduce the occupied area of ​​the first non-display area A3.

[0234] It should be noted that the arrangement of the first auxiliary through hole 911 , the second auxiliary through hole 912 and the third auxiliary through hole 913 may refer to the above-mentioned embodiment, and will not be described in detail herein.

[0235] The present disclosure also provides some display panels, such as Fig.13 and Fig.14 As shown, some implementation methods in the above embodiment are modified. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0236] In the specific implementation, in the embodiments of the present disclosure. Fig.13 and Fig.14 As shown, the fourth conductive layer 400 may further include a plurality of fourth light-emitting transmission lines 424 located in the first non-display area A3; the interlayer dielectric layer 630 may further include a plurality of fourth light-emitting through holes 824; the light-emitting control line EM electrically connected to each other corresponds to one fourth light-emitting transmission line 424. In addition, the first light-emitting connection portion 141 is also electrically connected to the fourth light-emitting transmission line 424 through the fourth light-emitting through hole 824; the third conductive layer 300 may further include a fourth scanning transmission line 414 located in the first non-display area A3; wherein the first scanning line GA1 and the second scanning line GA2 electrically connected to each other are directly electrically connected to one fourth scanning transmission line 414. In this way, the fourth scanning transmission line 414 may be provided in the third conductive layer 300, and the fourth light-emitting transmission line 424 may be provided in the fourth conductive layer 400.

[0237] For example, in order to reduce signal interference, Fig.13 and Fig.14 As shown, the orthographic projection of the fourth scanning transmission line 414 on the substrate 010 may not overlap with the orthographic projection of the fourth light emitting transmission line 424 on the substrate 010. For example, the orthographic projection of the fourth scanning transmission line 414 on the substrate 010 may be spaced from the orthographic projection of the fourth light emitting transmission line 424 on the substrate 010.

[0238] Further, in order to reduce signal interference, the orthographic projection of the fourth scan transmission line 414 on the base substrate 010 and the orthographic projection of the first data transmission line 711 on the base substrate 010 may have an overlapping area. Further, the orthographic projection of the fourth scan transmission line 414 on the base substrate 010 and the orthographic projection of the first data transmission line 711 on the base substrate 010 may partially overlap. Since the fourth scan transmission layer is located in the third conductive layer 300 and the first data transmission line 711 is located in the first conductive layer 100, this can not only reduce the coupling capacitance between the fourth scan transmission layer and the first data transmission line 711, but also reduce the occupied area of ​​the first non-display area A3.

[0239] Further, in order to reduce signal interference, the orthographic projection of the fourth light emitting transmission line 424 on the substrate 010 and the orthographic projection of the second data transmission line 712 on the substrate 010 may have an overlapping area. Further, the orthographic projection of the fourth light emitting transmission line 424 on the substrate 010 and the orthographic projection of the second data transmission line 712 on the substrate 010 may partially overlap. Since the fourth light emitting transmission line 424 is located in the fourth conductive layer 400 and the second data transmission line 712 is located in the second conductive layer 200, this can not only make the coupling capacitance between the fourth light emitting transmission layer and the second data transmission line 712 larger, but also reduce the occupied area of ​​the first non-display area A3.

[0240] It should be noted that the arrangement of the first auxiliary through hole 911 , the second auxiliary through hole 912 and the third auxiliary through hole 913 may refer to the above-mentioned embodiment, and will not be described in detail herein.

[0241] Based on the same inventive concept, the embodiment of the present disclosure also provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure. The principle of solving the problem by the display device is similar to that of the above-mentioned display panel, so the implementation of the display device can refer to the implementation of the above-mentioned display panel, and the repeated parts will not be repeated here.

[0242] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0243] The display panel and the display device provided by the embodiments of the present disclosure, by arranging the first data connection part in the second conductive layer, can make the data line in the first conductive layer and the first data transmission line electrically connected to each other through the first data connection part in the second conductive layer. In this way, not only can the data lines corresponding to the sub-pixels in the same column and separated by the notch area be electrically connected, but also the interference of the first data connection part on the third conductive layer and the fourth conductive layer can be reduced, so as to improve the signal stability and the display effect.

[0244] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0245] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein: include: A base substrate, comprising a notch area, a display area and a first non-display area, wherein the first non-display area is located between the notch area and the display area; wherein the display area further comprises a plurality of sub-pixels; A third conductive layer is located on the base substrate, and the third conductive layer includes a plurality of first scanning lines and a plurality of second scanning lines located in the display area; wherein one row of the sub-pixels corresponds to one of the first scanning lines and one of the second scanning lines; A second insulating layer is located on a side of the third conductive layer away from the substrate; A first conductive layer is located on a side of the second insulating layer away from the base substrate and includes a plurality of data lines and a plurality of first data transmission lines; An interlayer insulating layer, located on a side of the first conductive layer away from the base substrate, and the interlayer insulating layer has a plurality of first data through holes; A second conductive layer is located on a side of the interlayer insulating layer away from the base substrate and includes a plurality of first data connection portions; The plurality of data lines are located in the display area, and the plurality of first data transmission lines are located in the first non-display area; At least one of the plurality of first data connection parts is electrically connected to at least one of the plurality of data lines and at least one of the plurality of first data transmission lines through the first data vias; All the row sub-pixels include a first type of row sub-pixels; at least one row of sub-pixels in the first type of row sub-pixels corresponds to at least one of the first data connection parts; for the first scan line and the first data connection part corresponding to the same row of sub-pixels, and the first data line and the first data transmission line electrically connected using the first data connection part, the orthographic projection of the first data connection part on the substrate substrate and the orthographic projection of the first scan line on the substrate substrate have an overlapping area, and the orthographic projection of the first data line and the first data transmission line on the substrate substrate do not overlap with the orthographic projection of the first scan line on the substrate substrate.

2. The display panel according to claim 1, wherein: The second conductive layer further comprises: a plurality of second data transmission lines spaced apart from the first data connection portion; the plurality of second data transmission lines are located in the first non-display area; The interlayer insulating layer further comprises: a plurality of second data through holes; The plurality of data lines include a plurality of first data lines and a plurality of second data lines; wherein, one of the first data lines is electrically connected to one of the first data transmission lines through the first data connection portion; and one of the second data lines is electrically connected to one of the second data transmission lines through the second data via.

3. The display panel according to claim 2, wherein: The second scanning line corresponding to the sub-pixels in a first row of every two adjacent rows of sub-pixels is electrically connected to the first scanning line corresponding to the sub-pixels in a second row.

4. The display panel according to claim 3, wherein: The first conductive layer further comprises: a plurality of first scanning connection parts which are insulated from the data line and the first data transmission line and are arranged at intervals; wherein the first scanning line and the second scanning line which are electrically connected to each other correspond to at least one of the first scanning connection parts; The second insulating layer includes a plurality of first scanning through holes and a plurality of second scanning through holes; The first end of the first scanning connection portion is electrically connected to the corresponding first scanning line through at least one of the plurality of first scanning through holes, and the second end of the first scanning connection portion is electrically connected to the corresponding second scanning line through at least one of the plurality of second scanning through holes.

5. The display panel according to claim 4, wherein: An orthographic projection of the first data connection portion on the base substrate does not overlap with an orthographic projection of the first scanning connection portion on the base substrate.

6. The display panel according to claim 5, wherein: For the first scan line, the second scan line and the first data connection part corresponding to the same row of sub-pixels, the orthographic projection of the first data connection part on the base substrate is located between the orthographic projections of the first scan through hole corresponding to the first scan line and the second scan through hole corresponding to the second scan line on the base substrate.

7. The display panel according to claim 6, wherein: For the first scan line, the second scan line and the first data connection portion corresponding to the same row of sub-pixels, a line between the center of the orthographic projection of the first scanning through hole corresponding to the first scan line on the substrate and the center of the orthographic projection of the second scanning through hole corresponding to the second scan line on the substrate overlaps with the orthographic projection of the first data connection portion on the substrate.

8. The display panel according to claim 7, wherein: For the first scan line and the first data connection portion corresponding to the same row of sub-pixels, an orthographic projection of a central region of the first data connection portion on the base substrate and an orthographic projection of the first scan line on the base substrate have an overlapping region.

9. The display panel according to any one of claims 5 to 8, wherein: Some of the row sub-pixels in the first type of row sub-pixels correspond to two of the first data connection parts. For the first scan line, the second scan line and the two first data connection parts corresponding to the same row sub-pixel, the orthographic projections of the two first data connection parts on the substrate and the orthographic projections of the first scan line on the substrate have an overlapping area, and the orthographic projections of the two first data connection parts on the substrate and the orthographic projections of the second scan line on the substrate do not overlap.

10. The display panel according to claim 9, wherein: For the first scan line, the second scan line and the two first data connection parts corresponding to the same row of sub-pixels, The orthographic projection of the first one of the two first data connection portions on the substrate is close to the orthographic projection of the first scanning through hole corresponding to the first scanning line on the substrate; and / or, The orthographic projection of the second first data connection portion of the two first data connection portions on the base substrate is close to the orthographic projection of the second scanning through hole corresponding to the second scanning line on the base substrate.

11. The display panel according to claim 10, wherein: The second conductive layer further includes: a plurality of second data connection parts; wherein one second data transmission line is directly electrically connected to at least one second data connection part, and the second data connection part is electrically connected to one second data line through the second data via.

12. The display panel according to claim 11, wherein: Along a first direction, the first data lines and the second data lines are arranged alternately; Projections of the first data connection portions and the second data connection portions on a straight line extending along the first direction are arranged alternately.

13. The display panel according to claim 12, wherein: All the row sub-pixels include a second type of row sub-pixels; the second type of row sub-pixels are different from the first type of row sub-pixels; At least one row of sub-pixels in the second type of row sub-pixels corresponds to at least one of the second data connection portions; For the first scan line and the second data connection part corresponding to the same row of sub-pixels, and the second data line and the second data transmission line electrically connected using the second data connection part, the orthographic projection of the second data connection part on the substrate and the orthographic projection of the first scan line on the substrate have an overlapping area, and the orthographic projection of the second data line and the second data transmission line on the substrate do not overlap with the orthographic projection of the first scan line on the substrate.

14. The display panel according to claim 13, wherein: For a row of sub-pixels corresponding to two of the first data connection parts, the row of sub-pixels also corresponds to one of the second data connection parts; For the first scan line and the second data connection part corresponding to the same row of sub-pixels, and the second data line and the second data transmission line electrically connected using the second data connection part, the orthographic projection of the second data connection part on the substrate and the orthographic projection of the first scan line on the substrate have an overlapping area, and the orthographic projection of the second data line and the second data transmission line on the substrate do not overlap with the orthographic projection of the first scan line on the substrate.

15. The display panel according to claim 14, wherein: The third conductive layer further includes a plurality of light-emitting control lines located in the display area; wherein one row of the sub-pixels corresponds to one light-emitting control line; and the light-emitting control lines corresponding to two adjacent rows of sub-pixels are electrically connected; The display panel further includes: a fourth conductive layer, located between the first conductive layer and the third conductive layer; The second insulating layer comprises: a second gate insulating layer, located between the third conductive layer and the fourth conductive layer; The interlayer dielectric layer is located between the fourth conductive layer and the first conductive layer.

16. The display panel according to claim 15, wherein: The first conductive layer further comprises: a plurality of first light-emitting connection parts which are insulated from the data line and the first data transmission line and are arranged at intervals; wherein the light-emitting control lines which are electrically connected to each other correspond to at least one of the first light-emitting connection parts; The second insulating layer includes a plurality of first light-emitting through holes and a plurality of second light-emitting through holes; The first end of the first light-emitting connection part is electrically connected to a corresponding one of the light-emitting control lines through at least one of the plurality of first light-emitting through holes, and the second end of the first light-emitting connection part is electrically connected to another corresponding one of the light-emitting control lines through at least one of the plurality of second light-emitting through holes.

17. The display panel according to claim 16, wherein: The third conductive layer further comprises a plurality of first scanning transmission lines and a plurality of first light emitting transmission lines located in the first non-display area; wherein the first scanning transmission lines and the first light emitting transmission lines are arranged at intervals; Part of the first scanning lines and the second scanning lines electrically connected to each other are directly electrically connected to one of the first scanning transmission lines; and part of the light emitting control lines electrically connected to each other are directly electrically connected to one of the first light emitting transmission lines; The fourth conductive layer further comprises a plurality of second scanning transmission lines and a plurality of second light emitting transmission lines located in the first non-display area; wherein the second scanning transmission lines and the second light emitting transmission lines are arranged at intervals; The interlayer dielectric layer further includes a plurality of third scanning through holes and a plurality of third light-emitting through holes; The first scanning line and the second scanning line electrically connected to each other in the remaining part correspond to one second scanning transmission line, and the first scanning connection part is also electrically connected to the second scanning transmission line through the third scanning through hole; The remaining part of the light-emitting control line electrically connected to each other corresponds to one of the second light-emitting transmission lines, and the first light-emitting connection part is also electrically connected to the second light-emitting transmission line through the third light-emitting through hole.

18. The display panel according to claim 16, wherein: The fourth conductive layer includes a plurality of third scanning transmission lines located in the first non-display area; The interlayer dielectric layer includes a plurality of fourth scanning through holes; The first scan line and the second scan line electrically connected to each other correspond to one third scan transmission line, and the first scan connection portion is also electrically connected to the third scan transmission line through a fourth scan through hole; The third conductive layer further includes a third light emitting transmission line located in the first non-display area; wherein the light emitting control lines electrically connected to each other are directly electrically connected to one of the third light emitting transmission lines.

19. The display panel according to claim 16, wherein: The fourth conductive layer includes a plurality of fourth light emitting transmission lines located in the first non-display area; The interlayer dielectric layer includes a plurality of fourth light-emitting through holes; The mutually electrically connected light-emitting control lines correspond to one of the fourth light-emitting transmission lines, and the first light-emitting connection portion is also electrically connected to the fourth light-emitting transmission line through a fourth light-emitting through hole; The third conductive layer further includes a fourth scan transmission line located in the first non-display area; wherein the first scan line and the second scan line electrically connected to each other are directly electrically connected to one of the fourth scan transmission lines.

20. The display panel according to claim 19, wherein: For the light-emitting control line, the second scanning line and the second data connection part corresponding to the same row of sub-pixels, the orthographic projection of the second data connection part on the base substrate is located between the orthographic projection of the second scanning through hole corresponding to the second scanning line and the first light-emitting through hole corresponding to the light-emitting control line on the base substrate.

21. The display panel according to claim 20, wherein: The display panel further includes: A first gate insulating layer, located between the third conductive layer and the substrate; A semiconductor layer, located between the first gate insulating layer and the substrate; At least one of the plurality of sub-pixels comprises: a first connection through hole, a second connection through hole and a third connection through hole; wherein the first connection through hole penetrates the first gate insulating layer, the second gate insulating layer and the interlayer dielectric layer; the second connection through hole penetrates the second gate insulating layer and the interlayer dielectric layer; the third connection through hole penetrates the interlayer dielectric layer; The first conductive layer is electrically connected to the semiconductor layer through the first connecting through hole; The first conductive layer is electrically connected to the second conductive layer through the second connecting through hole; The first conductive layer is electrically connected to the third conductive layer through the third connecting via.

22. The display panel according to claim 21, wherein: The display panel further includes at least one first auxiliary through hole located in the first non-display area; The first auxiliary through hole penetrates the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer, and the first auxiliary through hole is not filled with a conductive material.

23. The display panel according to claim 22, wherein: The distribution density of the first auxiliary through holes is less than or substantially equal to the distribution density of the first connecting through holes.

24. The display panel according to claim 22 or 23, wherein: An orthographic projection of the first auxiliary through hole on the base substrate does not overlap with an orthographic projection of the semiconductor layer, the first conductive layer, the third conductive layer, and the fourth conductive layer on the base substrate.

25. The display panel according to claim 24, wherein: The display panel further includes at least one second auxiliary through hole located in the first non-display area; The second auxiliary through hole penetrates the second gate insulating layer and the interlayer dielectric layer, and the second auxiliary through hole is not filled with conductive material.

26. The display panel according to claim 25, wherein: The distribution density of the second auxiliary through holes is less than or substantially equal to the distribution density of the second connecting through holes.

27. The display panel according to claim 25 or 26, wherein: The orthographic projection of the second auxiliary through hole on the base substrate does not overlap with the orthographic projections of the first conductive layer, the third conductive layer, and the fourth conductive layer on the base substrate.

28. The display panel according to claim 27, wherein: The display panel further includes at least one third auxiliary through hole located in the first non-display area; The third auxiliary through hole penetrates the interlayer dielectric layer, and the third auxiliary through hole is not filled with conductive material.

29. The display panel according to claim 28, wherein: The distribution density of the third auxiliary through holes is less than or substantially equal to the distribution density of the third connecting through holes.

30. The display panel according to claim 28 or 29, wherein: The orthographic projection of the third auxiliary through hole on the base substrate does not overlap with the orthographic projections of the first conductive layer and the fourth conductive layer on the base substrate.

31. A display device, wherein: Comprising a display panel as described in any one of claims 1-30.

Images