Data processing system

Abstract

A data processing system comprises a memory system 9, a processor 3 and a cache system 13. The cache system comprises a cache 16 and a data encoder 17 associated with the cache. The data encoder encodes uncompressed data blocks having a particular data size for storage in the memory system. When a data array has a data size equal to the particular data size or is capable of being combined with one or more other data arrays already written to the cache to provide a plurality of data arrays having a data size equal to the particular data size, the processor is configured to bypass the cache to output the data array from the processor to the data encoder for encoding as a data block or portion of a data block having the particular data size.

Description

Technical Field

[0001] This invention relates to data processing systems, and more particularly, to systems and methods for writing out data arrays generated by data processing systems such as graphics processing systems. Background Technology

[0002] Graphics processing operations that can be performed by a graphics processor (graphics processing unit (GPU)) typically process data in an uncompressed form. Once such an operation has produced a specific output (e.g., a frame), the output data can then be written to (e.g., a frame) a buffer (e.g., in main memory) for storage, followed by further processing (e.g., displaying the frame).

[0003] To reduce the amount of data that needs to be transferred to and from memory during graphics processing operations, and the associated power costs of moving such data back and forth, the data can be compressed before being written to memory. This allows the data to be stored in a compressed format. When the data is needed for further processing, the compressed data is then read from memory and decompressed, so that the data is then in a suitable format for graphics processing operations.

[0004] To facilitate the local storage of data to the graphics processing unit when performing graphics processing operations that use this data, a cache can be used. This helps reduce the need to fetch data from slower data storage devices, such as the main memory of the graphics processing system. However, such caches have a limited (constrained) amount of storage space.

[0005] The applicant believes there is still room for improvement in compression and caching operations in the graphics processing system. Summary of the Invention

[0006] When considered from a first aspect, the present invention provides a graphics processing system comprising: Memory system; Graphics processor; and The cache system includes: A cache, configured to store data for use by the graphics processor when performing graphics processing operations; and A data encoder, which is associated with the cache and configured to: Uncompressed data blocks of a specific size are encoded so that they can be stored in a compressed format in the memory system; Specifically, for the data array that will be output from the graphics processor to the memory system, the graphics processor is configured as follows: When the data array or a portion of the data array has a data size equal to the specific data size, or when the data array can be combined with one or more other data arrays already written to the cache to provide multiple data arrays together having a data size equal to the specific data size: Bypassing the cache, the graphics processor provides the data encoder with a portion of a data array equal to the specific data size, or the data array itself, so as to encode it into a data block or a portion of a data block having the specific data size.

[0007] When considered from a second aspect, the present invention provides a method for operating a graphics processing system, the graphics processing system comprising: Memory system; Graphics processor; and A cache system comprising: a cache configured to store data for use by a graphics processor when performing graphics processing operations; and a data encoder associated with the cache and configured to encode uncompressed blocks of data having a specific data size for storage in a compressed format in a memory system. The method includes: For a data array to be output from a graphics processor to a memory system, when the data array or a portion of the data array has a data size equal to the specific data size, or when the data array can be combined with one or more other data arrays already written to a cache to provide multiple data arrays together having a data size equal to the specific data size: The graphics processor bypasses the cache and provides the data encoder with a portion of a data array equal to the specific data size, or the data array itself, so as to encode it into a data block or a portion of a data block having the specific data size.

[0008] Therefore, the present invention provides a graphics processing system and a method for operating the graphics processing system. The graphics processing system includes, for example, a main memory system, a graphics processor (e.g., a GPU), and a cache system.

[0009] The memory system stores data that the graphics processor may need. The graphics processor may be configured to perform graphics processing operations (using, for example, data in an uncompressed format), such as generating rendering output (e.g., frames for display). The graphics processor may be configured to operate on (e.g., generate) data arrays (e.g., data frames).

[0010] The cache system includes a cache configured to store (e.g., data received from a memory system) for use by a graphics processor. The cache system also includes a data encoder associated with the cache. The data encoder is configured to encode (compress) uncompressed data before it is output to the memory system, and to send the compressed data to the memory system for storage, for example. The uncompressed data to be encoded and output to the memory system may originate from the graphics processor and / or the cache.

[0011] The data encoder is configured to encode uncompressed data blocks, for example, using a block-based encoding technique. These “compressed blocks” of data (e.g., each compressed block) have a specific data size (in their uncompressed form), for example, due to the nature of the encoding technique and / or the way the data is stored in the memory system. The encoded (compressed) data can then be stored in the memory system in a compressed format.

[0012] The graphics processor is configured to process data arrays. When a data array has been processed (e.g., written to the graphics processor's buffer), the graphics processor needs to output this array so that it can proceed to process the next array.

[0013] When an array (e.g., tiles) of data to be output (e.g., written) from the graphics processor to the memory system (already manipulated (e.g., generated) by the graphics processor) and the data size of the array is greater than or equal to a specific data size (such that the array or a portion of the array has a data size equal to the specific data size of a (separate) data block compressed by a data encoder), the graphics processor bypasses the cache and directly provides the array or a portion of the data array with the specific compressed block data size (i.e., some or all) to the data encoder. The data array or a portion of the data array (with the specific data size) can then be encoded (encoded as a "compressed block") by the encoder.

[0014] Similarly, when the data array to be output can be combined with one or more other data arrays that have already been written to the cache by the graphics processor (and are therefore stored in the cache) to provide a combined total data size equal to a specific data size (multiple arrays having that combined total data size) (i.e., the multiple arrays together as data blocks having a data size equal to the specific data size), the graphics processor bypasses the cache and provides the data array directly to the data encoder. This data array can then be combined with one or more other data arrays from the cache (which together have that specific data size) and encoded by the encoder (encoded as "compressed blocks").

[0015] Therefore, in these cases, the graphics processor can directly provide the encoder with part or all of the data array as data blocks (of a specific size) for encoding.

[0016] The present invention therefore provides a more streamlined process for outputting a data array from a graphics processor to memory. The process of encoding (and sending to memory) the output data is simplified by identifying, for example, when at least some of the data array can be sent as a whole compressed block or when such at least some data array can be combined with other data from the cache (e.g., via a data encoder) to provide a whole compressed block, based on the size of the data array output by the graphics processor. It will be appreciated that this process is faster and more efficient.

[0017] This is because for data arrays sent directly to the encoder (e.g., a portion thereof), data does not need to be first written to a cache and then evicted from the encoder (as is the case with other data arrays that can be combined to provide compressed blocks). This saves time and power.

[0018] (It will be understood that the data arrays that will be combined into a compressed block are not necessarily output as a continuous array by the graphics processor. Instead, these arrays can be output at intervals of several processing cycles of the graphics processor. The cache is a convenient location used to temporarily store these arrays (instead of sending them all directly to the data encoder) until the multiple arrays have been processed and are ready to be encoded into a compressed block.)

[0019] This also means that data directly output to the encoder does not need to be allocated to lines in a cache that typically has limited storage capacity. This prevents the eviction of existing data stored in the cache that the graphics processor may need in the near future in order to make room for data output by the graphics processor.

[0020] The ability of a graphics processor to directly output a data array (e.g., a portion of the data array) to an encoder as a whole or a partial compressed block provides the flexibility to handle arrays of various data sizes processed by the graphics processor, especially when used with compression schemes that employ data encoders and memory with compressed blocks of, for example, fixed data sizes.

[0021] The graphics processing system of the present invention includes a memory system, a graphics processor, and a cache system.

[0022] The cache system of the present invention and the memory (memory system) of the graphics processing system to which it is interposed may include (e.g., the graphics processing system is part of the entire data processing system) any suitable and desired memory and memory system of the graphics processing system, such as and preferably, the main memory of the graphics processing system (e.g., in the case where there is a separate memory system for the graphics processor) or the main memory of the data processing system shared with other elements of the data processing system (such as the host processor (CPU)).

[0023] The graphics processor of a graphics processing system may include any suitable and desired graphics processor capable of operating to perform graphics processing operations on an array of data. The graphics processor should and preferably includes one or more (and preferably multiple) processing (shader) cores, which (e.g., each processing core) are capable of operating to perform graphics processing operations on the data (array) to be processed by the graphics processor.

[0024] The data array to be output from the graphics processor to the memory system may include any suitable and desired data array that the graphics processor can generate. The data array preferably comprises an array of data elements, each data element having an associated data value. Preferably, the graphics processor is configured to generate array data in an uncompressed format; that is, the data array comprises an uncompressed data array.

[0025] The data array may include, for example, and preferably, an image (or a portion thereof) being generated by a graphics processor, and therefore the data will include data elements (sampling locations) of the data array and appropriate color values ​​represented by the data array. In this case, the data array may include, for example, tiles or frames (tile or frame buffers) of image data being generated by the graphics processor for display, and / or data being generated by the graphics processor, such as graphic textures.

[0026] In other arrangements, the data may include geometric data, such as the geometric data of vertices and / or primitives being processed by the graphics processor. Thus, preferably, the array of data that the graphics processor operates on and disposes of in the manner of the invention includes image data (e.g., textures, tiles, or frames) or geometric data (positions and / or attributes).

[0027] The data array to be output from the graphics processor to the memory system may include all outputs, such as the frame currently generated by the graphics processor (i.e., such that only a single data array will be output for the entire output frame).

[0028] However, in one implementation, the array is a portion (smaller than the entire frame) of a frame of data (e.g., an image). Therefore, the entire data frame is generated and output to the memory system as multiple data arrays, for example, representing corresponding regions of the frame.

[0029] Therefore, in one implementation, the operation according to the invention is performed for multiple arrays (e.g., some or all of which constitute an entire data frame) (e.g., each array). As discussed below, there are several ways in which this operation can be carried out.

[0030] In cases where a graphics processor operates to generate multiple data arrays that constitute the entire output frame, each data array into which the frame is divided for processing by the graphics processor can represent any suitable and desired region (region, e.g., tile) of the entire frame. In one implementation, each data array represents a different region of the entire data frame (but the arrays may overlap if desired). Each array will represent an appropriate region (region) of the data frame, such as multiple data locations within the frame (e.g., pixels of image data).

[0031] Therefore, in a preferred embodiment, each array comprises a patch of pixels from an image data frame.

[0032] The data arrays to be stored from the graphics processor to memory can have any suitable and desired size and shape. Their shape is preferably rectangular, such as a square. In one embodiment, the arrays each have a size between 2×2 data elements (sampling locations, such as pixels) and 64×64 data elements and include both 2×2 and 64×64 data elements, for example, where each side of the rectangular array has 2... n The size of each data element, where n It is an integer (e.g., between 1 and 6 and inclusive). For each of the two sides of the rectangular array, the integer is... n They can be different.

[0033] In a preferred embodiment, each rectangular array has 64 data elements (sampling locations, e.g., pixels). Therefore, each rectangular array can have a size of 32×2, 16×4, or 8×8 data elements (e.g., oriented horizontally or vertically) (e.g., corresponding to a rendered tile). Of course, arrays of other sizes (e.g., larger, smaller, or with different aspect ratios) are possible.

[0034] Each data element of the data array can include any suitable and desired block of data. In one implementation, each data element of the array includes 4 bytes (32 bits) of data. Therefore, for example, when a rectangular array has 64 data elements (e.g., each), the rectangular array has a total data size of 256 bytes. Of course, other data sizes for data elements and arrays are possible.

[0035] In one set of embodiments, the graphics processor includes a (local) storage device, such as a (tile) buffer, configured to store, for example, data that has already been processed (of an array to be output to memory) while other data (of an array to be output to memory) is being processed, and then to provide (e.g., write) the data of the array (at least a portion thereof) to a data encoder or cache (where appropriate). Thus, data of an array to be output to memory can accumulate in the (tile) buffer, and then be provided (e.g., write) to the data encoder or cache. Preferably, the graphics processor is arranged to write an array (e.g., tiles) of data it is processing (e.g., frames) into the (tile) buffer for output to memory (via a data encoder, and, for example, via a cache where appropriate).

[0036] The (tile) buffer can have any suitable and desired size. In one embodiment, the (tile) buffer is capable of storing any (and all) size array of data that a graphics processor can process for and then output to memory. Therefore, the buffer is preferably capable of storing (e.g., the largest) tiles of data that a graphics processor is (e.g., capable of) processing.

[0037] For example, the buffer may be able to store a data array with a size of up to 64×64 data elements, each data element comprising 4 bytes of data (giving a total size of 16,384 bytes). This allows the buffer to store arrays (and, for example, multiple arrays) of any suitable and desired size that a graphics processor can handle, up to and including the size of the buffer itself.

[0038] When a graphics processor includes one or more (e.g., multiple) processing (shader) cores, each (shader) core may include a (local) storage device, such as a (tile) buffer, configured to store data that has been processed by the (shader) core (and is to be output to an array of memory). Preferably, each (shader) core of the graphics processor is arranged to write an array (e.g., tiles) of data it is processing to its corresponding (tile) buffer for output to memory (via a data encoder, and, for example, via a cache where appropriate).

[0039] For an array (e.g., tiles) that has been processed and is ready to be output to a memory system, the cache is bypassed when at least a portion (some or all) of the array has a specific data size. The encoder is then able to encode the array or that portion of the array as a "compressed block." In this case, the array or a portion of the array is sent directly to the encoder, bypassing the cache. There are several scenarios in which this can occur, which preferably depends on the size of the array that has been processed by the graphics processor and is ready to be output to memory.

[0040] For example, when the array to be output has a data size equal to a specific data size, the entire array is provided directly to the data encoder, bypassing the cache. In another example, when the array to be output has a data size greater than a specific data size, a portion of the array (i.e., less than the entire array) (with a data size equal to the specific data size) is provided directly to the data encoder, bypassing the cache.

[0041] On the other hand, if the array to be output has a data size smaller than a specific data size, but the array can be combined with one or more data arrays already stored in the cache to provide multiple arrays together having a specific data size, the array is again provided directly to the data encoder, bypassing the cache.

[0042] Otherwise, if the array to be output has a data size smaller than a certain data size, it is preferable to write the array to a cache (e.g., to combine it with one or more arrays that are subsequently processed and output).

[0043] When a graphics processor includes multiple processing (shader) cores, each processing core can operate together with a cache system and cache in accordance with the manner of this invention.

[0044] For example, when a data array with a data size smaller than a certain data size is to be stored in a cache for use in compressing blocks and then passed to a data encoder, the cache will receive and store the data from the graphics processor (or conversely, data generated by the graphics processor may not necessarily be handled in the manner described in this invention). The cache is therefore preferably arranged to receive and store data from the memory system so that it can be used by the graphics processor (e.g., when requested by the graphics processor).

[0045] The data is preferably stored in a cache in an uncompressed (decoded) format.

[0046] The cache system located between the memory system and the graphics processor can be any suitable and desired cache system that is operable and configured to hold data between the graphics processor (the processing core of the graphics processor) and the memory system.

[0047] A cache system may include a single cache "level", in which case the cache system will be the cache level associated with the data encoder (and the cache level stores data, for example, in uncompressed form for use by the graphics processor when performing graphics processing operations).

[0048] In this implementation, the cache system includes multiple cache levels (cache hierarchy), such as L2 cache and L3 cache. In this case, the cache associated with the data encoder is one level of the cache system (where other levels of the cache system do not have associated data encoders). In this case, the cache associated with the data encoder is the cache level closer to the graphics processor (the processing core of the graphics processor). Preferably, the cache level associated with the data encoder in the cache hierarchy (which provides data to it and receives data from the graphics processor (e.g., its processing core)) is an L2 cache.

[0049] For example, when an array of data is to be stored in a cache and then passed to a data encoder for assembly into compressed blocks, the cache (which is associated with the data encoder) to which the graphics processor writes data and from which the data encoder reads (or provides to, for example, evicted from) the cache (which undergoes the specific operations of this invention) can be configured and operated in any suitable and desired manner, such as according to the normal cache arrangement of the graphics processor and graphics processing system discussed.

[0050] In one implementation, the cache includes multiple cache lines, each capable of storing a corresponding data entry. Each cache line may be capable of storing any suitable and desired amount of data, such as 64 bytes of data, and may be correlated with the size of the compressed block in any suitable and desired manner.

[0051] In one implementation, the specific data size of a compressed block (when uncompressed) corresponds to an integer number (one or more, e.g., all) of cache lines. In another implementation, each cache line is capable of storing an integer number of compressed blocks (when uncompressed).

[0052] Accordingly, the output array or portion thereof can be associated with the size of each cache line in any suitable and desired manner. Thus, in one embodiment, the array or portion thereof output from the graphics processor corresponds to an integer number (one or more, e.g., all) of cache lines. In another embodiment, each cache line is capable of storing an integer number of arrays (or portions thereof). However, it will be understood that, according to some embodiments of the invention, the array or portion thereof may not be written to the cache but may be output directly to the encoder.

[0053] A graphics processing system may include a single physical cache, or may divide the cache into multiple separate physical portions (“slices”), each slice storing, for example, corresponding data for a specific processing core of the graphics processor. When the cache comprises multiple separate physical portions associated with a specific processing core of the graphics processor, preferably, when output comes from an array of particular processing cores, the portion of the cache associated with that processing core is bypassed (for arrays having a size greater than or equal to a particular data size).

[0054] A cache system (including a cache and an associated data encoder) can interface with a graphics processor (e.g., its processing core) to enable data transfer therebetween in any suitable and desired manner. In one embodiment, the graphics processing system includes a suitable interconnect, such as an asynchronous switching network (ASN), which interfaces between the cache system (e.g., an L2 cache and / or a data encoder) and the graphics processor (e.g., its processing core). This interconnect may also interface between the (e.g., L2) cache and the data encoder.

[0055] In one embodiment, the interconnect includes an arbiter configured to direct, when appropriate, data to the encoder or, for example, to a cache output array or a portion thereof. Therefore, preferably, the arbiter is configured to: Determine when to output to the data encoder or, for example, to a cache (e.g., at least a portion thereof); and When it has been determined that a data array (e.g., at least a portion thereof) will be output to the data encoder, the data array (e.g., at least a portion thereof) will be directed to the data encoder, and when it has been determined that a data array (e.g., at least a portion thereof) will be output to the cache, the data array (e.g., at least a portion thereof) will be directed to the cache.

[0056] An arbitrator may be configured to determine when an array or portion of a data array is directed to a data encoder or, for example, a cache in any suitable and desired manner. An arbitrator may be configured to determine when a data array (e.g., at least a portion thereof) has a data size equal to that of a particular data, or when a data array (e.g., at least a portion thereof) can be combined with one or more data arrays already in a cache, or when a data array will be able to be combined with one or more data arrays (in full) that have not yet been output.

[0057] However, in one implementation, the arbitrator is configured to use signals (e.g., including sideband information) from the graphics processor (e.g., its processing core) of the output data array (e.g., at least a portion thereof) to determine when to direct the array or a portion of the data toward a cache or data encoder. Preferably, as will be discussed below, the graphics processor (e.g., its processing core) is configured to emit (e.g., sideband) signals (e.g., accompanying the data array) indicating the destination to which the data array will be output (e.g., written).

[0058] Therefore, preferably, the graphics processor is configured (and the method includes the graphics processor) to determine when an array or data or a portion of a data array has a data size equal to a specific data size (to be output from the graphics processor to the memory system), or when a data array can be combined with one or more other data arrays already written to a cache to provide multiple data arrays having a data size equal to the specific data size together, and to provide a corresponding indication of that, such as a sideband signal.

[0059] In one embodiment, the graphics processor includes a write-out unit configured to output a data array from the graphics processor (e.g., control the output of the data array). Preferably, the write-out unit is associated with a buffer of the graphics processor (and, for example, controls the output of data from the buffer).

[0060] Therefore, preferably, the write unit is configured to determine, for example, using a predetermined data size criterion, when to output an array (e.g., at least a portion thereof) to a data encoder or write to a cache, or when multiple arrays can be combined, as outlined herein. For example, the write unit may receive instructions (e.g., from the application being used or a driver for the graphics processor) indicating the data size of the array (or arrays) to be processed or output. For example, the write unit may use this information to determine whether to output an array (e.g., at least a portion thereof) to a data encoder or cache.

[0061] The write unit will be configured accordingly to output an array (e.g., at least a portion thereof) to the data encoder when it is determined that an output array will be output to the data encoder (e.g., at least a portion thereof), and to write an array to the cache when it is determined that an output array will be output to the cache.

[0062] Preferably, the write unit is configured to emit (e.g., sideband) signals (e.g., accompanying the data array being output (e.g., at least a portion thereof)) indicating the destination to which the data array will be output (e.g., written). The signal may also be emitted to request the output (e.g., evicting) of other data arrays already stored in the cache to the data encoder (which will be discussed further below).

[0063] The data encoder is configured to encode (compress) uncompressed data when it is about to be output to a memory system, and to send the compressed data to the memory system for storage, for example. According to the invention, when data is about to be output from the graphics processor to the memory system, the data encoder is operable to encode (compress) uncompressed data from the graphics processor (i.e., directly received arrays or portions of arrays) and (if necessary) data from a cache (e.g., other arrays).

[0064] The data encoder is configured to encode uncompressed data in “compressed” blocks of a specific data size. A compressed block can therefore be formed from: a single data array (e.g., a portion of a data array) having a specific data size; or multiple data arrays that together have a specific data size and are combined to provide a compressed block.

[0065] According to the specific operation of the present invention, the data encoder may operate in any suitable and desired manner, such as and preferably in accordance with the normal mode of data encoding operation in the graphics processing system under discussion.

[0066] Therefore, for example, preferably, when compressed data is to be read (retrieved) from the memory system, the data encoder is also arranged to decode (decompress) this data from the memory system for use in an uncompressed format (e.g., for storage in a cache and / or for use by a graphics processor). Therefore, preferably, the data encoder is arranged to read data from the memory system in uncompressed form and, for example, store that data in a cache, and return the data to the memory system in compressed form.

[0067] In these embodiments where the data encoder is arranged to decode (decompress) compressed data from the memory system, this data is preferably written to a cache for storage in an uncompressed format. This data, then in the cache, can be used by the graphics processor in graphics processing operations.

[0068] A data encoder associated with a cache and capable of operating to compress data, in particular, from the graphics processor (and from the cache when needed), for writing to the memory system can be any suitable and desired data encoder that can operate in this manner.

[0069] Generally, a data encoder should and preferably be operable to read data from a graphics processor (e.g., its (tile) buffer) (and from a cache when needed) and process that data (e.g., compress the data), and then store that data in the memory system (and in the case of a multi-level cache system, preferably in another level of the cache system closer to the memory system than the cache level associated with the data encoder).

[0070] The data encoder should and preferably includes a suitable codec (data encoder / decoder) that is operable and configured to encode (compress) data to be output from the graphics processor (and, if necessary, from the cache) to the memory system, and to decode (decompress) data to be read from the memory system (e.g., into the cache).

[0071] The data encoder may include multiple codecs. These multiple codecs may be configured to encode and decode the data using various (e.g., different) encoding and decoding techniques respectively.

[0072] In one set of embodiments, the data encoder includes a (local) storage device, such as a buffer, configured to store the data to be encoded or decoded, for example, while data is being encoded or decoded and / or, where appropriate, before the data is written to a cache, graphics processor, or (to) a memory system. Thus, the data is temporarily buffered in the data encoder while it is being encoded / decoded, before outputting the data, etc.

[0073] A data encoder (a codec for a data encoder) can use any suitable and desired encoding and, for example, decoding techniques. Therefore, a data encoder can be configured to perform any suitable and desired encoding (e.g., compression) and, for example, decoding (e.g., decompression) operations, depending on the compression format available for the data.

[0074] The data encoder is configured to encode uncompressed data blocks (encoded as "compressed blocks"), and therefore preferably, the data encoder is configured to encode and, for example, decode the data using block-based encoding (compression) techniques.

[0075] In this case, a block-based compression scheme will be used to encode (compress) the data, and the data will therefore be stored in the memory system as corresponding (compressed) data blocks.

[0076] Therefore, in one embodiment, the method includes (and the data encoder is configured to) encode (and, for example, compress) a data block (including, where appropriate, a portion of a data array, the data array), and output (e.g., send, write) the encoded (compressed) data block to a memory.

[0077] The data block can be encoded (compressed) using any suitable and desired encoding (compression) technique. In one set of embodiments, the method includes (and the data encoder is configured to) encode the data block using frame buffer compression techniques described in the applicant's patents US 8,542,939 B2, US 9,014,496 B2, US 8,990,518 B2, and US 9,116,790 B2. In another set of embodiments, the method further includes, or alternatively (and the data encoder is configured to), encoding the data block using a fixed-rate compression technique.

[0078] When a data encoder compresses multiple (“compressed”) data blocks (each corresponding to a portion of the data array or data array of each data block) of a data frame, the respective data blocks are encoded (compressed) individually, and then those blocks are stored in compressed form as the respective blocks. Similarly, when multiple compressed data blocks are to be decompressed, the data encoder decodes them individually.

[0079] The data encoder encodes (and preferably each) data block with a specific data size. Therefore, in the operation of at least a preferred embodiment of the invention, for example, whenever the data encoder encodes a data block, it encodes data blocks of the same size.

[0080] This specific data size can be any suitable and desired data size for which the data encoder is configured to encode the data block. Preferably, for a specific instance using a graphics processor, the specific data size for which the data encoder is configured to encode the block is set (e.g., predetermined). This specific data size can be set, for example, by the application being used or by the driver for the graphics processing system.

[0081] In one implementation, the data encoder is configured to encode uncompressed data blocks of 256 or 512 bytes; that is, the specific data size can be 256 or 512 bytes. Of course, other specific data sizes for compressed blocks are possible according to the invention.

[0082] It will be understood that, in some implementations, the specific data size of the compressed block (in its uncompressed form) to be encoded by the data encoder may correspond to an integer number of cache lines of the cache associated with the data encoder, such as 4 or 8 cache lines. (Therefore, for a 64-byte cache line, each data block in its uncompressed form may, for example, comprise and be stored as a 256- or 512-byte data block.)

[0083] A data encoder can be included in the cache system in any suitable and desired manner and associated with the cache in question (e.g., cache level).

[0084] As discussed above, when a cache system comprises multiple cache levels, the data encoder can be associated with any suitable and desired (single) level of the cache system, and in one set of implementations, the data encoder is associated with the L2 cache.

[0085] In one set of implementations, the data encoder is integrated with the cache (cache level) itself (e.g., directly), such that the cache itself includes the data encoder. Therefore, for example, an L2 cache may include a data encoder.

[0086] In the case where a cache (cache level) is provided as multiple corresponding "physical" caches (as a set of multiple cache "slices"), then in a set of implementations, each corresponding cache "part" (slice) is associated with (and has its own corresponding data encoder) a corresponding data encoder for that cache part (slice). For example, (e.g., L2) cache may include multiple parts (slices), each configured to: receive data from the memory system and provide data to the graphics processor for use in performing graphics processing operations; and receive data from the graphics processor for transmission to the memory system, wherein each of the multiple parts (e.g., slices) of the (e.g., L2) cache includes a corresponding (its own) data encoder.

[0087] Therefore, in one set of embodiments, the cache system includes multiple data encoders associated with corresponding portions (e.g., slices) of a (e.g., L2) cache. When the cache system includes multiple data encoders associated with corresponding portions of the cache, preferably, when the data array comes from a graphics processor (e.g., from a processing core associated with a particular cache portion and therefore a data encoder), the portion of the cache associated with that particular processing core (for arrays having a size greater than or equal to a particular data size) is bypassed, and the array (at least a portion thereof) is output directly to the corresponding data encoder.

[0088] In one set of implementations, when the graphics processing system includes an interconnect (e.g., to control the passing of data in and out of a cache), the data encoder is associated with (e.g., integrated with) that interconnect (e.g., rather than incorporating the data encoder into the cache itself). Therefore, the interconnect may include a data encoder. In this case, there may be a single data encoder integrated with the interconnect, shared by all cache "slices".

[0089] When a data array, which has already been processed by the graphics processor and, for example, has been completely written into the graphics processor's buffer, is to be output from the graphics processor to the memory system, the data of the array is output to a data encoder (directly or via a cache, where appropriate) before being sent to the memory. According to the invention, it will be understood that, depending on the size of the array to be output from the graphics processor, the array (e.g., a portion thereof) is output directly to a data encoder or a cache, where appropriate.

[0090] To determine how to output the data array (directly to the data encoder or cache, and whether to output the entire array at once or a portion thereof), it will be understood that the data size of the array should be known or deterministic. The data size of the array to be output can be determined in any suitable and desired manner.

[0091] In a preferred embodiment, the data size of one or more arrays in a series of arrays being processed by the graphics processor is set, for example, by an application in use or by a driver for the graphics processing system. Therefore, the graphics processor may be arranged to receive (e.g., from an application or driver) one or more instructions to set the data size of one or more arrays in a series of arrays.

[0092] Therefore, these instructions can inform the graphics processor of the size of the array of data to be processed and output by the graphics processor, or the graphics processor can determine that data size. Knowing a specific data size helps the graphics processor determine when a data array (e.g., a portion thereof) can be output to a data encoder for encoding into a compressed block, or when multiple data arrays can be combined for encoding into a compressed block.

[0093] The size of the data array being processed by the graphics processor can be set in any suitable and desired manner, whether implicitly or explicitly. For example, one or more of the data amounts and dimensions (e.g., the height, width, and number of data elements) of each data element can be set for one or more arrays, such as a series of arrays being processed by the graphics processor. Thus, the graphics processor (e.g., its write unit) knows or is able to determine the size of the data array to be output.

[0094] According to the present invention, many different image formats can be used, such as the data size of the data elements of the array (e.g., tiles) described above. In one embodiment, the image format of the array being processed by the graphics processor has 32 bits (4 bytes) per data element (pixel), such as the RGBA8888 image format. For an array (tile) with 64 data elements (e.g., 8×8, 16×4, 32×2), this gives a data size of 256 bytes for the array. For an array with 16 data elements (e.g., 4×4, 8×2), this gives a data size of 64 bytes for the array.

[0095] Of course, other image formats are possible. For example, an image format with 16 bits per data element (pixel) would give a data size of 256 bytes for an array of 128 data elements. This could be a 16×8, 32×4, or 64×2 array, for example.

[0096] When the array to be output (e.g., tiles) has (e.g., is determined to have) a data size equal to a specific data size, the graphics processor (e.g., its write-out unit) simply outputs the data array to the data encoder, for example, along with any appropriate (e.g., sideband) signal. No data (of the data array) needs to be (and preferably does not) written to the cache, and therefore, cache lines are preferably not allocated for such data.

[0097] Such a data array may, for example, comprise appropriate (e.g., 8×8 sampling positions) rendering tiles. When each sampling position has a data size of 4 bytes, this size of the array (8×8) can therefore have a data size of 256 bytes. Of course, other sizes are possible. Thus, in some embodiments, the data blocks encoded by the data encoder correspond to data tiles processed by the graphics processor.

[0098] When the array to be output (e.g., tiles) has (e.g., determined to have) a data size greater than a specific “compressed block” data size, it is preferable again, for example, to output the array directly to the data encoder as multiple separate portions of the data array, each with a specific data size, along with any suitable (e.g., sideband) signal. Similarly, no (array) data needs to be (and preferably not) written to the cache, and therefore cache lines are preferably not allocated for such data.

[0099] Preferably, for each of the plurality of data portions of the data array, each having a data size equal to a specific data size, the graphics processor (e.g., its write-out unit) is configured to bypass the cache and output a portion of the data array to the data encoder when the data array to be output has a data size greater than the specific data size. In this way, multiple portions of the array (each with a specific data size) are output to the data encoder so that the data array can be output from the graphics processor. Preferably, each of the plurality of portions of the data array having a data size equal to the specific data size represents some, rather than all, areas and (individual) areas of the data array being output.

[0100] Therefore, in some implementations, the data block encoded by the data encoder comprises a portion of a data tile generated by the graphics processor. Preferably, such a tile generated by the graphics processor (e.g., each) comprises multiple data portions to be written from the graphics processor (e.g., each data portion has a data size equal to a specific data size). Thus, for example, when the tile has a size of 16×16 data elements, each data element has a data size of 4 bytes (giving a total data size of 1024 bytes for the tile), and the specific data size is 256 bytes, four 8×8 portions, each with a data size of 256 bytes, are written out, and each portion is encoded as a compressed block. Of course, other arrangements are possible.

[0101] When an array of data to be output (e.g., tiles) has a data size smaller than a specific data size and can be combined with an array stored in a cache to provide compressed blocks, the array is output to the data encoder, for example, along with any appropriate (e.g., sideband) signal (directly or, in some aspects or embodiments, via a cache). Similarly, when the array is output directly to the data encoder, no data (of the array) needs to be (and preferably not) written to the cache, and therefore, cache lines are preferably not allocated for such data.

[0102] In these implementations, the data encoder is arranged to encode blocks of data comprising multiple arrays to be written from the graphics processor (some written via cache), the combined arrays having a data size equal to a specific data size. In this case, the specific data size is greater than the data size of a single array and equal to the combined data size of the multiple arrays.

[0103] The data block to be encoded (e.g., each) can therefore correspond to an appropriate number of arrays (e.g., tiles) of data generated by the graphics processor (e.g., frames). The data block to be encoded can be formed from multiple arrays of different sizes, or can (and preferably) from multiple arrays of the same size. A particular data size can therefore be an integer multiple of the data size of a single array (and therefore an array written directly from the graphics processor to the data encoder).

[0104] For these arrays smaller than the data block to be encoded, each data array to be combined into a compressed block may include appropriate (e.g., 4×4 sampling positions) rendered tiles (e.g., virtual tiles). When each sampling position has 4 bytes of data size, this size (4×4) of the data array can therefore have a data size of 64 bytes. Thus, four such arrays (e.g., tiles) can be combined to provide a 256-byte compressed block. Of course, other arrangements are possible.

[0105] Preferably, such multiple data arrays (e.g., tiles) are contiguous arrays (regions) in the generated data frame. Conveniently (e.g., preferably), these multiple arrays are stored in contiguous regions of memory (such that, for example, they have adjacent memory addresses). When at least some of these multiple arrays are written to the cache, for storage prior to being encoded into a compressed block in a set of arrays, preferably, the array is stored in an adjacent cache line of the cache (e.g., because the graphics processor writes them sequentially).

[0106] Preferably, for multiple data arrays of a specific data size that are to be output from the graphics processor to memory, and which are, for example, contiguous arrays in a data frame being processed, arrays of these multiple arrays are written to a cache until all but one of the arrays are stored in the cache. The final array of the multiple arrays can then be output directly to the data encoder (bypassing the cache) to provide the remaining arrays of the multiple arrays stored in the cache to the compressed block.

[0107] Therefore, in a preferred embodiment, for a data array to be output from the graphics processor to the memory system, the graphics processor (e.g., its write-out unit) is configured (and the method includes): When a data array has a data size smaller than a specific data size and this array cannot be combined with one or more other data arrays already written to the cache to provide multiple data arrays with a data size equal to the specific data size (and preferably, this array is one of multiple data arrays that together have a specific data size and are, for example, connected arrays in a data frame being processed): The graphics processor (e.g., its write unit) writes the data array from the graphics processor to the cache (e.g., for storage to be encoded into portions of data blocks with a specific data size in the future).

[0108] Therefore, such an array will preferably be able to be combined with one or more other data arrays (which together provide multiple data arrays with a data size equal to a specific data size), but they have not yet (all) been written to the cache. The array can be stored in the cache until all the arrays (which together have a specific data size and are, for example, connected arrays in the data frame being processed) have been generated and the final array of the multiple arrays is about to be output (bypassing the cache and outputting directly to the data encoder).

[0109] The array is then preferably retrieved from the cache and sent to the data encoder, where it is combined with an array from a plurality of arrays provided directly to the encoder to provide a compressed block.

[0110] For arrays written to the cache, preferably, the cache is configured to allocate one or more cache lines for each array to be written to. As summarized above, preferably, the capacity of a cache line is equal to the size of the data array to be written to the cache (and therefore a single cache line can be allocated for each data array to be written to the cache). If necessary, data already present in one or more data lines allocated to the data arrays is evicted from these cache lines.

[0111] Preferably, the graphics processor (e.g., its write-out unit) is configured such that the method includes the graphics processor (e.g., its write-out unit) determining when multiple data arrays (to be output from the graphics processor to the memory system) together have a data size equal to a specific data size. According to the invention, this helps the graphics processor determine that a series of arrays to be output may provide compressed blocks, such that the graphics processor can then appropriately (e.g., track and) output the arrays among the multiple arrays.

[0112] The graphics processor (GPU) can determine, in any suitable and desired manner, that multiple arrays to be output from the GPU to memory can be combined to provide compressed blocks (for encoding by the data processor). Preferably, the GPU (e.g., its write-out unit) is configured such that the multiple data arrays together have a data size equal to a specific data size. This can be performed, for example, in a manner similar to that outlined above for individual arrays.

[0113] In one implementation, the graphics processor (e.g., its write unit) is configured to determine when multiple arrays to be output by the graphics processor are contiguous arrays in a data frame being processed. This can help indicate whether the multiple arrays are capable of providing compressed blocks.

[0114] A graphics processing unit (GPU) (e.g., its processing cores) can output multiple arrays capable of providing compressed blocks as a series of consecutive arrays. However, there may be instances where arrays among the multiple arrays are not written out consecutively. For example, there may be numerous (e.g., up to 1000 s) processing loops between arrays among the multiple arrays, making it impossible to process and write them out sequentially, for example, the GPU may process and write out other arrays in between. When this occurs, determining (e.g., identifying) the multiple arrays that will provide compressed blocks can (and preferably) be used to track the arrays among the multiple arrays that will be combined together to provide compressed blocks.

[0115] For each of a plurality of arrays to be output (and for example, already determined to be combinable to provide compressed blocks), the graphics processor may determine, in any suitable and desired manner, whether to output the array directly to the data encoder (bypassing the cache) or to write the array to the cache. Preferably, the graphics processor (e.g., its write unit) is configured to output the data array directly to the data encoder or to the cache accordingly after this determination.

[0116] In a preferred embodiment, the graphics processor (e.g., its write-out unit) is configured (and the method includes): for a plurality of arrays to be output (and, for example, determined to be combinable) to provide compressed blocks, determining when one of the arrays is the final array among the plurality of arrays to be output by the graphics processor; and when the array is the final array, bypassing a cache to output the array to a data encoder. Preferably, the graphics processor is configured to write the array to a cache when the array is not (i.e., not) the final array.

[0117] An array among multiple arrays can be determined as the final array (or not the final array) in any suitable and desired manner. In a preferred embodiment, the graphics processor (e.g., its write-out unit) is configured (and the method includes) to track the array among the multiple arrays as the graphics processor generates the array (e.g., writes it to the graphics processor's (e.g., tile) buffer). This helps the graphics processor identify the final array among the multiple arrays, allowing it to be output directly to the data encoder and other arrays among the multiple arrays to be retrieved from the cache.

[0118] An array can be tracked by the graphics processor (GPU) tracking the data size (e.g., accumulating) of the arrays among multiple arrays while processing the array (e.g., writing to a buffer), such that the final array among the multiple arrays is identified by the array that brings the multiple arrays to a specific data size. However, in a preferred embodiment, the array can be tracked by the GPU (e.g., its write-out unit) counting the arrays among multiple arrays while processing the array (e.g., writing to a buffer). The GPU (e.g., its write-out unit) can therefore include a counter (e.g., a register) configured to count the arrays among multiple arrays while writing to the array (writing to a buffer).

[0119] The number of arrays among multiple arrays that will provide compressed blocks can be determined (or set by) information provided by the application being used or by the driver for the graphics processing system. For example, the number of arrays among multiple arrays can be determined based on the data size of the array to be processed by the graphics processor and the specific data size being used by the data encoder.

[0120] When a graphics processor includes multiple processing (e.g., shader) cores, preferably, the same processing core of the graphics processor processes, for example, multiple arrays that are processed and will provide compressed blocks, sequentially. Therefore, preferably (e.g., each) a processing core is configured to track the arrays that the processing core is processing to determine when to output the arrays (which will provide compressed blocks) directly to the data encoder, and preferably, to determine when to write the arrays of the multiple arrays to the cache.

[0121] Tracking multiple arrays (e.g., their final arrays) themselves while writing out multiple arrays can be novel and advantageous. Therefore, according to another aspect, the present invention provides a graphics processing system comprising: Memory system; Graphics processor; and The cache system includes: A cache, configured to store data for use by the graphics processor when performing graphics processing operations; and A data encoder, which is associated with the cache and configured to encode uncompressed data blocks for storage in a compressed format in the memory system; The graphics processor is configured to output to the memory system from the graphics processor and to provide multiple arrays for uncompressed data blocks encoded by the data encoder, wherein: Determine whether the array among the multiple data arrays to be output from the graphics processor to the memory system is the final array among the multiple arrays to be output from the graphics processor; and When the data array is not the final array among multiple arrays to be output from the graphics processor: Write the data array from the graphics processor to the cache; and When the data array is the final array among multiple arrays to be output from the graphics processor: Output the final data array from multiple arrays from the graphics processor; and This causes the data encoder to receive additional arrays from the cache that have already been written to the cache. Therefore, the data encoder can encode the multiple arrays into data blocks for transmission to the memory system in a compressed format.

[0122] When considered from another perspective, the present invention provides a method for operating a graphics processing system, the graphics processing system comprising: Memory system; Graphics processor; and A cache system comprising: a cache configured to store data for use by a graphics processor when performing graphics processing operations; and a data encoder associated with the cache and configured to encode uncompressed blocks of data for storage in a compressed format in a memory system. For multiple arrays that are to be output from a graphics processor to a memory system and together provide uncompressed blocks of data encoded by a data encoder, the method includes: The graphics processor determines whether one of the multiple data arrays to be output from the graphics processor to the memory system is the final array among the multiple arrays to be output from the graphics processor; and When the data array is not the final array among multiple arrays to be output from the graphics processor: The graphics processor writes the data array from the graphics processor to the cache; and When the data array is the final array among multiple arrays to be output from the graphics processor: The graphics processing unit outputs the final data array from multiple arrays; From the cache to the data encoder, other arrays in multiple arrays that have already been written to the cache; and The data encoder encodes the multiple arrays into data blocks for transmission to the memory system in a compressed format.

[0123] Those skilled in the art will appreciate that these aspects of the invention may and preferably include any one or all of the optional and preferred features of the invention described herein. For example, preferably, the plurality of arrays to be encoded into data blocks together have a data size equal to a specific data size. Preferably, the plurality of arrays to be encoded into data blocks are contiguous arrays in a data frame being processed.

[0124] Preferably, the graphics processor is configured (and the method includes) to determine when multiple data arrays (to be output from the graphics processor to the memory system) are available to provide uncompressed data blocks for encoding by the data encoder (e.g., because they have a specific data size together and / or are contiguous arrays).

[0125] Based on these aspects, the graphics processor is therefore configured to identify when to output the final array of the multiple data arrays being generated (e.g., to a data encoder) and to provide the other arrays of the multiple arrays from a cache (where they are stored) to the data encoder. The data encoder is then able to encode the multiple arrays together into a compressed block.

[0126] Preferably, this is achieved by the graphics processor (e.g., its write-out unit) signaling (e.g., via an arbitrator) to a cache to request (e.g., evict) other arrays (or all arrays) from that cache (and the cache, in response to this signal, sends the array from the cache to the data encoder). Preferably, this is also achieved by the graphics processor (e.g., its write-out unit) signaling to the encoder for encoding (e.g., via an arbitrator) to encode multiple arrays into compressed blocks (and the encoder encodes the multiple arrays for transmission to memory). In one set of embodiments, for example as outlined in the first and second aspects of the invention, the final data array is output directly to the data encoder, bypassing the cache. In another set of embodiments, the final data array (and therefore all arrays) is written to the cache before being provided to the data encoder.

[0127] Once the destination to which the data array will be output has been determined, preferably, the graphics processor (e.g., its write unit) is configured to issue a (e.g., a sideband) signal (e.g., accompanying the data array) that includes an indication of the destination to which the data array will be written.

[0128] Preferably, the graphics processor (e.g., its write unit) is configured to issue a signal (e.g., to an interconnect (e.g., its arbitrator) instructing that an array (e.g., at least a portion thereof) to be output directly to the data encoder (e.g., for encoding) will be output to the data encoder. Preferably, the signal instructs that the array (e.g., at least a portion thereof) will be encoded as a compressed block or a portion thereof.

[0129] Similarly, a graphics processor (e.g., its write unit) is configured to issue a signal (e.g., to an interconnect (e.g., its arbiter)) instructing that a data array to be written to the cache array is to be stored. Preferably, the signal instructs that the array (e.g., at least a portion thereof) is to be stored in the cache for later encoding into a compressed block.

[0130] When the system includes an interconnect (e.g., its arbitrator), preferably the interconnect (e.g., its arbitrator) is configured to use signals from a graphics processor (e.g., its write unit) (e.g., including an indication of the destination of an array (e.g., at least a portion thereof)) to guide the array (e.g., at least a portion thereof) output from the graphics processor to a data encoder or cache (i.e., according to the indication of the destination in the signals).

[0131] Preferably, the graphics processor (e.g., its write unit) is configured to issue a signal that causes the array of multiple arrays stored in a cache to be sent to the data encoder when outputting multiple arrays (which together will provide a compressed block) (e.g., its final array) from the graphics processor.

[0132] The signal can be sent to the cache, for example, via an interconnect (e.g., its arbitrator). The cache can be configured to send an array of multiple arrays stored in the cache to the data encoder upon receiving the signal.

[0133] In one implementation, the signal is sent to the data encoder, for example, via an interconnect (e.g., its arbitrator). The data encoder is preferably configured to request an array from one of the multiple arrays stored in the cache upon receiving the signal. Preferably, the cache is configured to send the array from the multiple arrays stored in the cache to the data encoder upon receiving the request.

[0134] The signal that causes the retrieval of an array from the cache can include any suitable and desired signal. Preferably, the signal includes an indication of an array from the multiple arrays stored in the cache or an indication of an array from the multiple arrays to be sent to the data encoder.

[0135] For example, the signal may include an indication of the identity of multiple arrays (e.g., their individual arrays) that will together provide a compressed block. The signal may include an indication that the array is the final array among the multiple arrays that will together provide a compressed block. The signal may include an indication of the ordered position of each of the multiple arrays that will together provide a compressed block.

[0136] In this latter case, preferably, writing the final array to the cache triggers the cache to provide all of the multiple arrays to the data encoder in the same or similar manner as triggering the provision of other arrays from the cache when writing the final array directly to the data encoder. Therefore, in one embodiment, the graphics processor is configured to signal the cache to provide (e.g., evict) multiple arrays (other than the final array) from the cache to the data encoder.

[0137] In response to receiving a signal from the graphics processor indicating that an array of multiple arrays stored in the cache will be retrieved from the cache, the interconnect (e.g., its arbitrator) may request the array of multiple arrays to be sent from the cache to the data encoder in any suitable and desired manner, depending on the nature of the signal. For example, the interconnect (e.g., its arbitrator) may be configured to identify the final array among the multiple arrays (using the signal). Preferably, the interconnect (e.g., its arbitrator) is configured to signal the cache to send the array of multiple arrays to the data encoder when it has identified the final array among the multiple arrays (e.g., via the data encoder).

[0138] Data can be retrieved from the cache in any suitable and desired manner. When the data array to be output can be combined with the array in the cache to provide a compressed block and thus (in some embodiments) output to the data encoder, preferably, one or more other arrays already written to the cache are provided (and evicted, for example) from the cache to the data encoder. Therefore, preferably, these data arrays are requested from the cache, for example, by signaling, and in response to the request, these data arrays are provided from the cache to the data encoder.

[0139] When the final array is written to the cache, preferably, all arrays of the multiple data arrays that will provide compressed blocks are provided from the cache (e.g., by request and response). Preferably, writing the final array to the cache triggers the output (e.g., eviction) of multiple arrays from the cache.

[0140] As outlined above, when the final data array is output, any suitable and desired component of the system may request the data array to form the compressed block. Thus, for example, a graphics processor (e.g., its write unit) may request the data array when outputting the final data array, an interconnect (e.g., its arbiter) may request the data array when directing the final data array to a data encoder or cache, or the data encoder may request the data array after receiving the final data array.

[0141] For example, when the final array is written to the cache for the first time, the request may be directed to all arrays (including the final array) among the multiple data arrays that will provide compressed blocks. Alternatively, for example, when the final array is output directly to the data encoder, the request may be directed to other arrays among the multiple data arrays that will provide compressed blocks along with the final array.

[0142] Preferably, the graphics processor, interconnect (e.g., its arbiter), or data encoder that requests the data array (e.g., for the compressed block) sends a write request to the cache (e.g., where the other) data array is stored, when appropriate. Such a write request from the interconnect or data encoder may be triggered by a signal (e.g., including a flag) from the graphics processor (e.g., its write unit) accompanying the final array of the multiple output data arrays (e.g., sidebands).

[0143] Requests for data arrays in the multiple arrays can be made at any suitable and desired time. In a preferred embodiment, the graphics processor (e.g., its write unit) is configured to signal when the final array (of the multiple data arrays that will provide the compressed block) is being processed by the graphics processor or is about to be output, indicating that a request is to be made to output additional data arrays from the multiple arrays stored in the cache to the data encoder. This facilitates, for example, the time that the data encoder might have to wait for from the cache before it is able to encode the multiple arrays into a compressed block.

[0144] For example, after the data array has been fully written into the graphics processor's buffer and the output destination of the data array has been determined, the graphics processor (e.g., its write-out unit) may output (e.g., write out) the data array (e.g., at least a portion thereof) to the data encoder or, for example, the cache in any suitable and desired manner when appropriate.

[0145] When at least a portion of the array is to be output to the data encoder, all data of that at least portion of the array may be written to the data encoder (as a data packet in one operation). However, in one embodiment, the at least portion of the array is "streamed" to the data encoder, for example, such that the data of that at least portion of the array is consumed (e.g., encoded) as the data is written out.

[0146] Therefore, for example, when the data array to be output has a data size larger than a certain data size, the entire data array can be streamed to the data encoder, so that the data encoder can then encode a portion of the array into corresponding compressed blocks upon receiving the data array. This helps to streamline the process of outputting and encoding data.

[0147] As will be understood from the foregoing, embodiments of the present invention are implemented in a system including a memory system, a cache system, and a graphics processing unit (GPU). Data used to perform graphics processing operations (e.g., to generate rendering output (e.g., an image to be displayed)) is preferably stored in the memory of the memory system. The graphics processor is preferably arranged to trigger the fetching of required data from the memory and the storage of the data in the cache system.

[0148] The graphics processor then preferably reads the necessary data from a cache system for performing graphics processing operations (e.g., generating rendering output). Once generated in this way, the output from the graphics processing operations (e.g., rendering output) is then written back to the memory system and, in one embodiment, displayed on a display of an electronic device such as a telephone, tablet computer, television, or computer screen.

[0149] A graphics processor (graphics processing unit) may, and preferably implements and executes a graphics processing pipeline to perform graphics processing operations.

[0150] The graphics processing pipeline may and preferably includes any one or more processing levels that a graphics processing pipeline may typically include, and preferably includes all processing levels, such as and preferably, primitive setup level, rasterizer, renderer (preferably in the form of a programmable fragment shader (shader core) or includes a programmable fragment shader).

[0151] In one embodiment, the graphics processor (processing pipeline) also includes one or more programmable shader levels, such as one or more of the following, and preferably all of them: vertex shader level, shell shader, tessellation level (e.g., where tessellation is performed by executing a shader program), domain (evaluation) shader level (shader), geometry shader level (shader), and fragment shader.

[0152] The graphics processing unit (processing pipeline) may also include any other suitable and desired processing stages that the graphics processing pipeline may include, such as a depth (or depth and stencil) tester, a mixer, a tile buffer, a write unit, etc.

[0153] In one embodiment, the graphics processing system includes a host processor that executes applications that may require graphics processing by the graphics processor. In one embodiment, the system also includes suitable storage devices (e.g., memory), caches, etc., as described above.

[0154] This invention can be used in and with any suitable and desired graphics processing system and processor.

[0155] As an example, the present invention can be used with a tile-based renderer (a tile-based graphics processing system). Therefore, in one embodiment, the graphics processor (processing pipeline) is a tile-based graphics processor (processing pipeline). However, other arrangements are of course possible.

[0156] Although the invention has been specifically described above with reference to cache and encoding operations in relation to a graphics processor in a graphics processing system, the applicant has recognized that using a data encoder associated with a cache in the manner described above will be useful in other cache arrangements and systems, not just in the context of a graphics processor.

[0157] Therefore, it is believed that the operation and system according to the present invention may be novel and advantageous in itself when used more generally in data processing systems.

[0158] Therefore, another aspect of the present invention provides a data processing system comprising: Memory system; processor; and The cache system includes: A cache, configured to store data for use by the processor when performing data processing operations; and A data encoder, which is associated with the cache and configured to: Uncompressed data blocks of a specific size are encoded so that they can be stored in a compressed format in the memory system; For the data array that will be output from the processor to the memory system, the processor is configured as follows: When the data array or a portion of the data array has a data size equal to the specific data size, or when the data array can be combined with one or more other data arrays already written to the cache to provide multiple data arrays together having a data size equal to the specific data size: Bypassing the cache, the processor provides the data encoder with a portion of a data array equal to the specific data size, or the data array itself, so as to encode it into a data block or a portion of a data block having the specific data size.

[0159] Another aspect of the present invention provides a method for operating a data processing system, the data processing system comprising: Memory system; processor; and A cache system comprising: a cache configured to store data for use by a processor when performing data processing operations; and a data encoder associated with the cache and configured to encode uncompressed blocks of data having a specific data size for storage in a compressed format in a memory system. The method includes: For a data array to be output from the processor to the memory system, when the data array or a portion of the data array has a data size equal to the specific data size, or when the data array can be combined with one or more other data arrays already written to the cache to provide multiple data arrays together having a data size equal to the specific data size: The processor bypasses the cache and provides the data encoder with a portion of a data array equal to the specific data size, or the data array itself, so as to encode it into a data block or a portion of a data block having the specific data size.

[0160] Another aspect of the present invention provides a data processing system, the data processing system comprising: Memory system; processor; and The cache system includes: A cache, configured to store data for use by the processor when performing data processing operations; and A data encoder, which is associated with the cache and configured to encode uncompressed data blocks for storage in a compressed format in the memory system; The processor is configured to output data from the processor to the memory system and, together, provide multiple arrays for uncompressed data blocks encoded by the data encoder. Determine whether the array among the multiple data arrays to be output from the processor to the memory system is the final array among the multiple arrays to be output from the processor; and When the data array is not the final array among multiple arrays to be output from the processor: Write the data array from the processor to the cache; and When the data array is the final array among multiple arrays to be output from the processor: The processor outputs the final data array from multiple arrays; and This causes the data encoder to receive additional arrays from the cache that have already been written to the cache. Therefore, the data encoder can encode the multiple arrays into data blocks for transmission to the memory system in a compressed format.

[0161] Another aspect of the present invention provides a method for operating a data processing system, the data processing system comprising: Memory system; processor; and A cache system comprising: a cache configured to store data for use by a processor when performing data processing operations; and a data encoder associated with the cache and configured to encode uncompressed blocks of data for storage in a compressed format in a memory system. For multiple arrays that are to be output from the processor to the memory system and together provide uncompressed data blocks encoded by a data encoder, the method includes: The processor determines whether one of the multiple data arrays to be output from the processor to the memory system is the final array among the multiple arrays to be output from the processor; and When the data array is not the final array among multiple arrays to be output from the processor: The processor writes the data array from the processor to the cache; and When the data array is the final array among multiple arrays to be output from the processor: The processor outputs the final data array from multiple arrays; From the cache to the data encoder, other arrays in multiple arrays that have already been written to the cache; and The data encoder encodes the multiple arrays into data blocks for transmission to the memory system in a compressed format.

[0162] Those skilled in the art will understand that these aspects of the invention may and preferably include any one or all of the features of the invention described herein.

[0163] In one implementation, the various functions of the invention are performed on a single processing platform.

[0164] In one embodiment, the data or graphics processing system and / or (e.g., graphics) processor further includes one or more memory and / or memory devices storing the data described herein and / or storing software for performing the processes described herein, and / or communicating with said one or more memory and / or memory devices. The data or graphics processing system and / or (e.g., graphics) processor may also communicate with a host microprocessor and / or a display for displaying images based on data generated by (e.g., graphics) processor (processing pipeline).

[0165] This invention can be implemented in any suitable system, such as a suitably configured microprocessor-based system. In some embodiments, the techniques described herein are implemented in computer- and / or microprocessor-based systems.

[0166] The various functions of the present invention can be performed in any desired and suitable manner. For example, the functions of the present invention can be implemented in hardware or software when needed. Thus, for example, the various functional elements and stages of the present invention may include suitable processors, controllers, functional units, circuits, processing logic, microprocessor arrangements, etc., capable of operating to perform various functions, such as suitable dedicated hardware elements (processing circuits) and / or programmable hardware elements (processing circuits) that can be programmed to operate in a desired manner.

[0167] It should also be noted here that, as those skilled in the art will understand, various functions of the present invention can be repeated and / or performed in parallel on a given processor. Similarly, various processing levels may share processing circuitry when desired.

[0168] Furthermore, any one or more processing levels of the present invention may be embodied, for example, in the form of one or more fixed functional units (hardware) (processing circuits) and / or in the form of programmable processing circuits that can be programmed to perform desired operations. Similarly, any one or more processing levels and processing level circuits of the present invention may be provided as separate circuit elements to other processing levels or any one or more processing levels and processing level circuits, and / or any one or more processing levels and processing level circuits may be formed at least partially by shared processing circuits.

[0169] Those skilled in the art will also understand that all described embodiments of the present invention may, where appropriate, include any one or all of the features described herein.

[0170] The method according to the invention can be implemented at least in part using software, such as a computer program. Therefore, it will be understood that, when considered in other respects, the invention provides: computer software, which, when installed on a data processor, is particularly suitable for performing the methods described herein; computer program elements comprising computer software code portions for performing the methods described herein when the program elements are run on the data processor; and a computer program comprising code suitable for performing all steps of the methods described herein when the program is run on a data processing system. The data processing system may be a microprocessor, a programmable FPGA (Field-Programmable Gate Array), etc.

[0171] The invention also extends to computer software carriers that include software that, when used to operate a graphics processor, renderer, or other system including a data processor, causes the steps of the methods of the invention to be performed in conjunction with said graphics processor, renderer, or system. Such computer software carriers can be physical storage media, such as ROM chips, CD-ROMs, RAM, flash memory, or disks, or they can be signals, such as electronic signals, optical signals, or radio signals, such as signals to satellites, etc.

[0172] It will also be understood that not all steps of the method of the present invention need to be performed by computer software, and therefore, according to a broader aspect, the present invention provides computer software mounted on a computer software carrier for performing at least one step of the method described herein, and such software.

[0173] This invention can therefore be suitably embodied as a computer program product for use with a computer system. Such embodiments may include a series of computer-readable instructions fixed on a tangible, non-transitory medium, such as a computer-readable medium, for example, a disk, CD-ROM, ROM, RAM, flash memory, or hard disk. It may also include a series of computer-readable instructions that can be invisibly transmitted to a computer system via a modem or other interface device, through a tangible medium (including but not limited to optical or analog communication lines), or using wireless technologies (including but not limited to microwave, infrared, or other transmission technologies). This series of computer-readable instructions embodies all or part of the functions described above.

[0174] Those skilled in the art will understand that such computer-readable instructions can be written in a variety of programming languages ​​to be used with many computer architectures or operating systems. Furthermore, such instructions can be stored using any current or future memory technology (including, but not limited to, semiconductor, magnetic, or optical technologies), or transmitted using any current or future communication technology (including, but not limited to, optical, infrared, or microwave technologies). It is conceivable that such computer program products can be distributed as removable media with accompanying printed or electronic documentation (e.g., shrink-wrapping software), pre-loaded with a computer system on, for example, a system ROM or a fixed disk, or distributed via a network (e.g., the Internet or the World Wide Web) from a server or electronic bulletin board. Attached Figure Description

[0175] The various embodiments described herein will now be described by way of example only, with reference to the accompanying drawings, in which: Figure 1 An exemplary graphics processing system in which the present invention can be implemented is shown; Figure 2 Showing more details Figure 1 The implementation scheme of the high-speed cache system of the graphics processing system; Figure 3 The implementation scheme of the data encoder is shown in more detail; Figure 4 Showing more details Figure 1 Another implementation scheme for the high-speed cache system of the graphics processing system; Figure 5 This is a flowchart illustrating the operation of outputting data from a graphics processor to a memory in an embodiment of the present invention; Figure 6 and Figure 7 This illustrates a tile that will be output from the graphics processor to the memory in an embodiment of the present invention; Figure 8 The use of embodiments of the present invention is shown in Figure 4 The cache system shown in the figure executes the operation of writing data from the graphics processor to memory; Figure 9 This illustrates a set of tiles that will be output from the graphics processor to the memory in an embodiment of the present invention; Figure 10 The following is an illustration of the operation in which the data encoder requests data from the cache according to an embodiment of the present invention; Figure 11 Another embodiment of the invention is shown for use in Figure 4 The cache system shown in the diagram executes the operation of writing data from the graphics processor to memory; and Figure 12Another embodiment of the invention is shown for use in Figure 4 The cache system shown in the figure writes data from the graphics processor to memory.

[0176] Where appropriate, similar reference numerals are used for similar elements and features in the accompanying drawings. Detailed Implementation

[0177] Several embodiments of the present invention will now be described in the context of graphics processing systems.

[0178] Figure 1 An exemplary graphics processing system 1 in which the present invention and this embodiment can be implemented is shown.

[0179] exist Figure 1 The exemplary graphics processing system 1 shown includes a host processor, which includes a central processing unit (CPU) 2 in the form of a system-on-a-chip (SoC) 7, a graphics processor (graphics processing unit (GPU)) 3, a video codec 4, a display controller 5, and a memory controller 6. Figure 1 As shown, these units communicate via interconnect 8 and have access to the off-chip memory system (memory) 9. In this system, the GPU 3, video codec 4, and / or CPU 2 generate frames (images) to be displayed, and the display controller 5 then provides the frames to the display 10 for display.

[0180] In using this system, an application 11 (such as a game) executing on the host processor (CPU) 2 will, for example, need to display frames on the display 10. To do this, the application 11 will send appropriate commands and data to the driver 12 for the graphics processing unit 3 executing on the CPU 2. The driver 12 will then generate appropriate commands and data to cause the graphics processing unit 3 to render appropriate frames for display and store those frames in appropriate frame buffers, such as in main memory 9. The display controller 5 will then read those frames into the buffer for the display, and those frames will then be read from there and displayed on the display panel of the display 10.

[0181] As part of this process, the graphics processor 3 reads data from the memory 9, such as textures and geometry to be rendered, processes that data, and then returns the data to the memory 9 (e.g., in the form of processed textures and / or frames to be displayed). The display controller 5 then reads the data from the memory, for example, as discussed above, for display on the display 10. Therefore, data transfer is required between the graphics processor 3 (specifically, between the processing core of the graphics processor 3) and the memory 9.

[0182] To facilitate this operation and reduce the amount of data output to memory 9 during graphics processing operations, graphics processing system 1 also includes a cache system 13 disposed between interconnect 8 and memory 9. The cache system 13 is operable to transfer data between memory 9 and graphics processor 3. The cache system 13 thus helps control the sending of blocks of data (e.g., pixels) generated by graphics processor 3 to memory 9.

[0183] Figure 2 The components of the graphics processing system 1 (including components of the cache system 13) are shown schematically and in more detail, relating to the operation of this embodiment and specifically to the transfer of data from the graphics processor 3 to the memory 9. Those skilled in the art will understand that there may be... Figure 2 Other components of the system not shown in the diagram.

[0184] Figure 2 The memory 9 and the graphics processor 3 are shown. The graphics processor includes multiple processing (shader) cores 14. Each shader core 14 includes a write unit 15 and a buffer 21. The buffer 21 stores data processed by its shader core 14 and to be output from its shader core. The write unit 15 controls the output of data from the buffer 21 of its shader core 14.

[0185] like Figure 2 As shown, there is a cache system 13 between the memory 9 and the processing (shader) core 14 of the graphics processor 3. This cache system is operable to transfer data from the memory 9 to the graphics processor 3 (and specifically, to the processing core (shader core) 14 of the graphics processor 3), and conversely, to transfer data generated by the processing core 14 of the graphics processor 3 back to the memory 9.

[0186] exist Figure 2 The cache system shown is illustrated as including an L2 cache 16 from which data is provided to the shader core 14. Other cache hierarchy arrangements are possible, such as including multiple cache levels as needed. Figure 2 As shown, in this embodiment, data is transferred from memory 9 to L2 cache 16, and from L2 cache 16 to shader core 14 (and vice versa).

[0187] To facilitate the processing of compressed data from memory 9 via memory controller 6 (and the return of compressed data to memory 9 as needed), such as Figure 2 As shown, the L2 cache 16 is associated with the data encoder 17 (in the form of a memory page compression unit (MPC)).

[0188] This data encoder 17 is operable to decompress data received from memory 9, then store that data in uncompressed form in L2 cache 16 for use by the shader core 14 of the graphics processor 3, and conversely, to compress data (to be evicted from L2 cache 16 or received directly from shader core 14), and then send that data back to memory 9. The operation of this data encoder (MPC) 17 will be discussed in more detail below.

[0189] Figure 3 An embodiment of the data encoder (memory page compression unit) 17 in this embodiment is shown. For example... Figure 3 As shown, each of the data encoders 17 includes a corresponding read unit 22 and a write unit 23 (circuit), which are respectively operable to read data from and write data to the L2 cache and memory system. The data encoder 17 also includes a suitable control unit (circuit) 24 that receives read and write requests from the shader core and the L2 cache controller, and controls the data encoder 17 to respond appropriately to those requests.

[0190] like Figure 3 As shown, the data encoder 17 also includes one or more codecs 25, 26 and a set of data buffers 27 for temporarily storing data in the data encoder 17 while processing data and / or while waiting to write data to the L2 cache or memory system.

[0191] The data encoder 17 may include any desired number of codecs, each capable of operating to perform different encoding (compression) schemes. For example, one codec may be configured to perform an appropriate variable-rate compression scheme, while another codec is configured to perform an alternative, such as a fixed-rate compression scheme.

[0192] Of course, other arrangements are possible.

[0193] like Figure 2 As shown, the graphics processing system 1 also includes appropriate interconnects 8 for transferring data between the L2 cache 16 and / or the data encoder 17 and the shader core 14. In this embodiment, the interconnects 8 include an asynchronous switching network (ASN) 18 and an arbitrator 19. The arbitrator 19 is configured to determine whether data from the shader core 14 will be routed to the L2 cache 16 or the data encoder 17.

[0194] In this embodiment, the data being processed by the graphics processor 3 (e.g., the data array of data frames) is stored in the memory 9 as corresponding data blocks (blocks of data frames), wherein each data block is stored in the memory 9 in compressed form but in uncompressed form in the L2 cache 16 for use by the shader core 14 of the graphics processor 3.

[0195] In one implementation, a “compressed block” of data stored in compressed form in memory 9 comprises 256 bytes of data. This size of data block may, for example, correspond to an integer number (e.g., four) of cache lines. Of course, other sizes of compressed blocks and cache line capacities are possible, depending, for example, on the relative cache line size used in the graphics processing system in question.

[0196] Figure 4 The arrangement of the L2 cache 16, the data encoder (memory page compression unit) 17, and the shader core 24 in a possible implementation of this embodiment is shown.

[0197] L2 cache 16 is shown as being configured as a corresponding separate physical cache segment (slice) 20. Figure 4 In the arrangement shown, there is a single data encoder 17 that operates on all L2 cache slices 20 and is coupled to and associated with an interconnect (ASN) 18 that operates between the L2 cache 16 and the shader core 14 of the graphics processor.

[0198] It will be understood that other arrangements are possible. For example, in other implementations, each corresponding L2 slice may have its own associated data encoder, rather than a single data encoder associated with the entire L2 cache.

[0199] Figure 5 refer to Figures 1 to 4 The graphics processing system 1 shown illustrates the operation of an embodiment of the present invention.

[0200] First, the GPU 3's shader core 14 processes tiles of image data and writes the tiles to the shader core 14's tile buffer 21 for output to memory 9. The application 11 using the GPU 3 or the driver 12 for the GPU 3 sets the size of the tiles to be processed by the GPU 3. The write unit 15 associated with the tile buffer 21 then prepares to output the tiles to memory 9 (step 101). Figure 5 ).

[0201] Based on information about the tile being processed provided by application 11 or driver 12, write unit 15 determines the data size of the tile to be output. The tile size is compared with the specific data size of the compressed block (the block size that the data encoder (MPC unit) 17 of the cache system encodes (compresses) the data for storage in compressed format in memory 9) (step 102). Figure 5 For example, a compressed block can have a data size of 256 bytes.

[0202] When the data size of a tile is greater than or equal to the data size of a compressed block, this means that the write unit 15 of shader core 14 can directly send (e.g., write, stream) the tile data to data encoder 17 for encoding into a compressed block for transmission to memory 9, thus bypassing the cache. The write unit 15 repeatedly performs this process on a region of the tile having a data size equal to that of the compressed block (step 103). Figure 5 ).

[0203] Figure 6 A plot 31, in an embodiment of the invention, is schematically shown being processed by GPU 3 and is to be output from GPU to memory 9. Plot 31 has a size of 8×8 pixels (comprising four 4×4 sub-plots 32). Using the RGBA8888 image format with 32 bits (4 bytes) per pixel, plot 31 has a data size of 256 bytes. When the compressed block has a data size of 256 bytes, this size of plot 31 (256 bytes) is directly output to data encoder 17 to be encoded as a compressed block.

[0204] In this simpler case, the tile size is equal to the compressed block size, and therefore the entire tile 31 is sent to the data encoder 17 in a single iteration.

[0205] When the tile size is larger than the compressed block size, the tile is divided into multiple parts equal to the compressed block size, and these parts are repeatedly sent to the data encoder 17.

[0206] Figure 7 The diagram schematically illustrates a tile 33 being processed by GPU 3 and to be output from GPU to memory 9 in an embodiment of the invention. This tile 33 has a size of 16×16 pixels and uses the RGBA8888 image format with 32 bits (4 bytes) per pixel, having a data size of 1024 B. When the compressed block has a data size of 256 B, this tile size (1024 B) can therefore be divided into four 256 B 8×8 regions 34 (equivalent to...). Figure 6 As shown in Figure 31, each area is used to write out the encoded compressed block.

[0207] Area 34 of tile 33 is directly sent to data encoder 17 for encoding, so that no temporary storage line for this data is allocated in L2 cache 16 (step 104). Figure 5 As will be understood, this is an efficient process for outputting data from the tile buffer 21, and allows the limited resources of the L2 cache 16 to be reserved for data that may be needed by the shader core 14.

[0208] Once encoded, (e.g., each) compressed block is sent to off-chip memory 9. This process is then repeated for each tile processed by each shader core 14 of GPU 3 (step 105). Figure 5 ).

[0209] Figure 8 Used in Figure 4 The cache system shown schematically illustrates this process. When outputting from the tile buffer 21 of shader core 14 to memory 9, the number of tiles equal to the number of compacted blocks (e.g., in...) is... Figure 6 or Figure 7 When a tile (e.g., a portion thereof) of a specific size (as shown in the figure) is directly output 51 to the data encoder 17 for encoding, instead of being temporarily stored in the L2 cache 16.

[0210] Interconnector (ASN) 18 (e.g., including such as Figure 2 The arbiter 19 shown learns (e.g., based on sideband information provided by the write unit 15 of the shader core 14, which accompanies the tile (e.g., a portion thereof)) that the tile being written (e.g., a portion thereof) has a data size equal to that of the compressed block. The interconnect 18 (e.g., its arbiter 19) directs the tile being written (e.g., a portion thereof) directly to the data encoder 17.

[0211] Once a tile (e.g., a portion thereof) has been encoded (compressed), the data encoder 17 sends 52 encoded compressed blocks to the memory 9.

[0212] Now we will refer to it again. Figures 1 to 4 The operation of the graphics processing system 1 is described in terms of tiles with a data size larger than the size of compressed blocks, output from the shader core 14 of the GPU 3.

[0213] Figure 9A set of tiles 35, processed by GPU 3 and to be output from GPU to memory 9, is schematically shown in an embodiment of the invention. Tiles 36 within this set of tiles 35 may each have a size of, for example, 4×4 pixels and use the RGBA8888 image format (32 bits per pixel, 4 bytes), resulting in a data size of 64 bytes per tile. For a compressed block with a data size of 256 bytes, four 64-byte tiles can be combined into a compressed block and used for encoding as a compressed block. Multiple sets of tiles processed by a specific shader core 14 of GPU 3 and thus conveniently encoded as compressed blocks typically originate from contiguous regions of data frames, such as... Figure 9 As shown in the diagram. Such tiles can be stored in the contiguous area of ​​memory 9.

[0214] A set of 35 such tiles 36 of image data being processed by the shader core 14 of GPU 3 is written to the tile buffer 21 of the shader core 14 for output to memory 9. The application 11 using GPU 3 or the driver 12 for GPU 3 sets the size and number of tiles 36 in the set 35 that will be processed by GPU 3. The write unit 15 associated with the tile buffer 21 then prepares to output the tiles 36 to memory 9 (step 101). Figure 5 ).

[0215] Based on information provided by application 11 or driver 12 regarding the group of tiles 35 being processed, write unit 15 determines the data size and number of tiles 36 to be output in each group 35. Write unit 15 is thus able to determine which group of tiles can provide compressed blocks by comparing the tile size with a specific data size and knowing how many tiles are in each group 35.

[0216] For these tiles 36 that have a data size larger than the data size of the compressed block, the write unit 15 of the shader core 14 determines whether the tile 36 is the final tile in a set of tiles 35 that can be combined to form the compressed block (step 106). Figure 5 ).

[0217] When it is determined that the tile being processed, 36, is not the final tile in a set of tiles 35 (step 106), Figure 5 ), allocate line 16 of L2 cache for tile 36 and write the tile to that line (step 107, Figure 5 Interconnect 18 (e.g., its arbiter 19) learns (e.g., based on sideband information provided by the write unit 15 of shader core 14 accompanying tile 36) that the tile 36 being written has a data size smaller than the compressed block. Interconnect 18 (e.g., its arbiter 19) directs the tile 36 being written to L2 cache 16.

[0218] The lines of L2 cache 16 can each have a capacity of, for example, 64 bytes. A tile 36 with a data size of 64 bytes will therefore fill such a cache line.

[0219] GPU 3's shader core 14 then processes the next tile 36 in the set of tiles 35. When it is determined that this tile 36 is not the final tile 36 in the set of tiles 35 (step 106), Figure 5 ), and allocate another (e.g., a different) line of L2 cache 16 for tile 36 and write the tile to that line (step 107, Figure 5 ).

[0220] When it is determined that the final piece 36 in the group of pieces 35 will be processed (step 106), Figure 5 Instead of being allocated and written to a line in L2 cache 16, tile 36 is written directly to data encoder 17 (step 108). Figure 5 ).

[0221] After receiving this final tile 36 from the set of tiles 35, the data encoder 17 determines that other tiles 36 from the set of tiles 35 are needed to form a compressed block. The data encoder 17 requests these tiles 36 from the L2 cache 16. Figure 10 This process is illustrated in the diagram.

[0222] Figure 10 The diagram shows the final tile from which data encoder 17 receives data from shader core 14. This data reception triggers data encoder 17 to issue requests for other tiles in this set from L2 cache 16. These tiles are shown as being located in cache lines 0 through N-1 of L2 cache 16. These cache lines are evicted, and the evicted data of the tiles is sent to data encoder 17.

[0223] Once the data encoder 17 has received data from the evicted cache line of the L2 cache 16, the data encoder 17 has all the data for compressing the block. The data encoder 17 combines and encodes (compresses) all the tiles in the group into a single compressed block.

[0224] Then the encoded compressed block is written to off-chip memory 9. This process is then repeated for each tile (or group of tiles) processed by each shader core 14 of GPU 3 (step 105). Figure 5 ).

[0225] Figure 11 Used in Figure 4The cache system shown schematically illustrates this process. First, blocks from a set of blocks that are to be output from the block buffer 21 of the shader core 14 to memory 9 and are not the final blocks in that set of blocks are written from the shader core 14 to the L2 cache 16 (e.g., their associated slice 20). When the final block in that set of blocks is to be written from the block buffer 21 of the shader core 14 to memory 9, this block is directly output to the data encoder 17, rather than being temporarily stored in the L2 cache 16.

[0226] When outputting blocks from a set of blocks from the block buffer 21, the interconnect (ASN) 18 (e.g., including such...) Figure 2 The arbiter 19 shown learns (e.g., based on sideband information provided by the write unit 15 of the shader core 14, which accompanies each tile) the ordered position of the tile. The interconnect 18 (e.g., its arbiter 19) thus tracks the tile when outputting it and, where appropriate, directs the tile directly to the L2 cache or data encoder 17.

[0227] Receiving the final block in the set of blocks, tracked by interconnect 18 (e.g., its arbitrator 19), triggers data encoder 17 to request other blocks in the set of blocks from L2 cache 16. These other blocks are retrieved from the cache 63 to data encoder 17. Data encoder 17 combines and encodes (compresses) all blocks in the set of blocks into a single compressed block, and sends this encoded compressed block 64 to off-chip memory 9.

[0228] Figure 12 Another embodiment of the invention is shown for use in Figure 4 The cache system shown in the image executes the process of writing data from the graphics processor to memory. Figure 12 The operation of the implementation scheme shown in the figure is in Figure 11 The changes to the implementation scheme shown in the figure.

[0229] exist Figure 11 and Figure 12 The difference between the operations of the embodiments shown is that when the final block in the set of blocks is output from the block buffer 21 of the shader core 14 to the memory 9, the final block is written to L2 cache 16 via 71, that is, in the same manner as the other blocks in the set of blocks were previously written to L2 cache 16 via 71. Therefore, in Figure 12 In the implementation shown, the final map is first written to L2 cache 16 via 71, instead of being directly output to data encoder 17 (bypassing L2 cache 16), as... Figure 8 , Figure 10 and Figure 11 As shown in the image.

[0230] When the final tile is written out to L2 cache 16 at step 71, the write unit 15 of shader core 14 issues a write request (in the sideband signal) to L2 cache 16 that receives the final tile. This request triggers the writing (e.g., evicting) of all tiles in the set of tiles from the cache at step 72 to data encoder 17.

[0231] The data encoder 17 then combines and encodes (compresses) all the tiles in the group into a single compressed block, and sends this encoded compressed block to the off-chip memory 9.

[0232] As can be understood from the above, in at least a preferred embodiment, the present invention provides a graphics processing system and a method of operating the graphics processing system, wherein since an array (e.g., a tile) (e.g., a portion thereof) is equal to a compressed block or the final array in a set of arrays that will provide the compressed block, the array (e.g., a portion thereof) that can be directly output to the data encoder is written to the data encoder, bypassing the cache.

[0233] This helps simplify the process of writing data for encoding, making the process faster and more efficient. This is because for a data array (e.g., a portion thereof) written directly to the encoder, there is no need to first write the data to a cache and then evict it to the encoder, thus saving time and power. It also avoids having to allocate rows in the cache for a data array (e.g., a portion thereof).

Claims

1. A data processing system, the data processing system comprising: Memory system; processor; and A cache system, the cache system comprising: A cache, configured to store data for use by the processor when performing data processing operations; and A data encoder, which is associated with the cache and configured to: Uncompressed data blocks with a specific data size are encoded so that they can be stored in the memory system in a compressed format; Wherein, for the data array to be output from the processor to the memory system, the processor is configured as follows: When the data array or a portion of the data array has a data size equal to the specific data size, or when the data array can be combined with one or more other data arrays already written to the cache to provide multiple data arrays together having a data size equal to the specific data size: Bypassing the cache, the processor provides the data encoder with a portion of the data array or the data array equal to the specific data size, so as to encode it into a data block or a portion of the data block having the specific data size; and The processor is configured as follows: When the data array to be output has a data size greater than the specific data size, the data array is output as multiple data parts of the data array, each data part having a data size equal to the specific data size, and is output to the data encoder bypassing the cache.

2. The data processing system according to claim 1, wherein the processor is configured as: Determine when the data array or a portion of the data array has a data size equal to the specific data size, or when the data array can be combined with one or more other data arrays already written to the cache to provide multiple data arrays together having a data size equal to the specific data size; and When it has been determined that the data array or a portion of the data array to be output from the processor to the memory system has the specific data size, or that the data array can be combined with one or more other arrays to provide data blocks of the specific data size, the cache is bypassed and a portion of the data array or the data array equal to the specific data size is output to the data encoder.

3. The data processing system according to claim 1 or 2, wherein the processor is configured to: When a data array has a data size smaller than the specified data size and the data array cannot be combined with one or more other data arrays already written to the cache to provide multiple data arrays with a data size equal to the specified data size: The data array is written from the processor to the cache.

4. The data processing system according to claim 1 or 2, wherein the processor is configured to: For multiple arrays having the specific data size that will be output from the processor to the memory system: Determine when one of the plurality of arrays is the final array among the plurality of arrays to be output by the processor; When the array is the final array, the array is output to the data encoder, bypassing the cache. as well as When the array is not the final array, the array is written to the cache.

5. The data processing system according to claim 1 or 2, wherein the processor is configured to: When it is about to bypass the cache and output the data array to the data encoder, a signal indicating that the data array will be output to the data encoder is issued; as well as When it is time to write data to the cache array for storage, a signal indicating that the data array is to be written to the cache is issued; and The data processing system includes an arbitrator, which is configured to: The signal from the processor is used to guide the data array output from the processor to the data encoder or cache indicated by the signal.

6. A graphics processing system comprising the data processing system according to claim 1 or 2, wherein the processor comprises a graphics processor configured to perform graphics processing operations.

7. A data processing system, the data processing system comprising: Memory system; processor; and A cache system, the cache system comprising: A cache, configured to store data for use by the processor when performing data processing operations; and A data encoder, which is associated with the cache and configured to: Uncompressed data blocks with a specific data size are encoded so that they can be stored in the memory system in a compressed format; Wherein, for the data array to be output from the processor to the memory system, the processor is configured as follows: When the data array or a portion of the data array has a data size equal to the specific data size, or when the data array can be combined with one or more other data arrays already written to the cache to provide multiple data arrays together having a data size equal to the specific data size: Bypassing the cache, the processor provides the data encoder with a portion of the data array or the data array equal to the specific data size, so as to encode it into a data block or a portion of the data block having the specific data size; and The processor is configured as follows: When a data array has a data size smaller than the specified data size and the data array cannot be combined with one or more other data arrays already written to the cache to provide multiple data arrays with a data size equal to the specified data size: The data array is written from the processor to the cache.

8. A method for operating a data processing system, the data processing system comprising: Memory system; processor; and A cache system comprising: a cache configured to store data for use by the processor when performing data processing operations; and a data encoder associated with the cache and configured to encode uncompressed blocks of data having a specific data size for storage in a compressed format in the memory system. The method includes: For a data array to be output from the processor to the memory system, when the data array or a portion of the data array has a data size equal to the specific data size, or when the data array can be combined with one or more other data arrays already written to the cache to provide multiple data arrays together having a data size equal to the specific data size: The processor bypasses the cache and provides the data encoder with a portion of the data array or the data array equal to the specific data size, so as to encode it into a data block or a portion of the data block having the specific data size; and The method includes: When the data array to be output has a data size greater than the specific data size, the processor outputs the data array as multiple data parts of the data array, each data part having a data size equal to the specific data size, and the processor bypasses the cache to output each data part to the data encoder.

9. The method of claim 8, wherein the method comprises: The processor determines when the data array or a portion of the data array has a data size equal to the specific data size, or when the data array can be combined with one or more other data arrays already written to the cache to provide multiple data arrays together having a data size equal to the specific data size; as well as When it has been determined that the data array or a portion of the data array to be output from the processor to the memory system has the specific data size, or that the data array can be combined with one or more other arrays to provide data blocks of the specific data size, the processor bypasses the cache and outputs a portion of the data array or the data array equal to the specific data size to the data encoder.

10. The method according to claim 8 or 9, wherein the method comprises: When a data array has a data size smaller than the specified data size and the data array cannot be combined with one or more other data arrays already written to the cache to provide multiple data arrays with a data size equal to the specified data size: The processor writes the data array from the processor to the cache.

11. The method according to claim 8 or 9, wherein the method comprises: For multiple arrays having the specific data size that will be output from the processor to the memory system: The processor determines when one of the plurality of arrays is the final array among the plurality of arrays to be output by the processor; When the array is the final array, the processor bypasses the cache and outputs the array to the data encoder; as well as When the array is not the final array, the processor writes the array into the cache.

12. The method according to claim 8 or 9, wherein the method comprises: When the processor is about to bypass the cache and output the data array to the data encoder, it issues a signal indicating that it will output the data array to the data encoder. as well as When it is time to write a data array to the cache for storage, the processor sends a signal indicating that it is time to write the data array to the cache. as well as The arbiter of the data processing system uses the signal from the processor to direct the data array output from the processor to the data encoder or the cache indicated by the signal.

13. A method for operating a data processing system, the data processing system comprising: Memory system; processor; and A cache system comprising: a cache configured to store data for use by the processor when performing data processing operations; and a data encoder associated with the cache and configured to encode uncompressed blocks of data having a specific data size for storage in a compressed format in the memory system. The method includes: For a data array to be output from the processor to the memory system, when the data array or a portion of the data array has a data size equal to the specific data size, or when the data array can be combined with one or more other data arrays already written to the cache to provide multiple data arrays together having a data size equal to the specific data size: The processor, bypassing the cache, provides the data encoder with a portion of the data array or the data array equal to the specific data size, for encoding into a data block or a portion of the data block having the specific data size; and When a data array has a data size smaller than the specified data size and the data array cannot be combined with one or more other data arrays already written to the cache to provide multiple data arrays with a data size equal to the specified data size: The processor writes the data array from the processor to the cache.

14. A computer-readable storage medium storing computer software code that, when executed on a data processor, performs a method for operating a data processing system according to any one of claims 8 to 13.

Images