Memristor cell and method of operating a memory array

Abstract

The present disclosure provides a method, device for operating a memristor cell and a memory array. The method for operating the memristor cell comprises: determining a conductance range of a set target conductance state of the memristor cell; performing a first programming operation on the memristor cell according to the conductance range and an initial conductance state of the memristor cell, so that a first current conductance state of the memristor cell satisfies the conductance range; and performing a second programming operation on the memristor cell according to the first current conductance state and an error range of the set target conductance state, so that a second current conductance state of the memristor cell satisfies the error range. Therefore, the programming operation of the memristor cell and the memory array is realized by two-step programming operation, the parallel programming operation for each memristor cell in the memory array can be realized, the programming speed is effectively improved, the programming accuracy is taken into account, and the consumption of programming pulse is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor devices and integrated circuit technology, and in particular to a method and apparatus for operating a memristor cell and a memory array. Background Technology

[0002] As the reliability of traditional charge-based Flash memory continues to deteriorate with the shrinking of technology nodes, memories and memory arrays based on new storage principles using memristors have been proposed and extensively studied. Among them, memristors are considered suitable as memory units in embedded storage systems due to their advantages such as low programming power consumption, fast read and write speeds, high integration density, parallel operation, and multi-bit storage, and are also suitable as in-memory computing units in neural network systems. Summary of the Invention

[0003] (a) Technical problems to be solved

[0004] To address at least one of the technical problems existing in the multi-bit programming operation of memristor cells and memory arrays in the prior art, this disclosure provides an operation method and apparatus for memristor cells and memory arrays.

[0005] (II) Technical Solution

[0006] One aspect of this disclosure provides a method for operating a memristor cell, comprising: determining a conductance range of a predetermined target conductance state of the memristor cell; performing a first programming operation on the memristor cell based on the conductance range and an initial conductance state of the memristor cell, such that a first current conductance state of the memristor cell satisfies the conductance range; and performing a second programming operation on the memristor cell based on an error range between the first current conductance state and the predetermined target conductance state, such that a second current conductance state of the memristor cell satisfies the error range.

[0007] According to embodiments of this disclosure, determining the conductance range of a set target conductance state of a memristor cell includes: determining a set conductance range as the conductance range from a plurality of set conductance ranges based on the characteristics of the memristor cell itself.

[0008] According to embodiments of this disclosure, performing a first programming operation on a memristor cell based on a conductance range and an initial conductance state of the memristor cell, such that a first current conductance state of the memristor cell satisfies the conductance range, includes: determining a first word line voltage for performing the first programming operation based on the initial conductance state and the conductance range; and applying the first word line voltage to the word line of the memory cell corresponding to the memristor cell to perform the first programming operation on the memristor cell.

[0009] According to embodiments of this disclosure, in applying a first word line voltage to the word line of the memory cell corresponding to the memristor cell to perform a first programming operation on the memristor cell, the method further includes: applying a first bit line voltage to the bit line of the memory cell; and grounding the source line of the memory cell; wherein the first programming operation is a single-pulse SET operation.

[0010] According to embodiments of this disclosure, performing a second programming operation on a memristor cell based on an error range between a first current conductance state and a set target conductance state, such that the second current conductance state of the memristor cell satisfies the error range, includes: performing a single-pulse SET operation on the memristor cell when the first current conductance state is less than the lower limit of the error range of the set target conductance state; and / or performing a single-pulse RESET operation on the memristor cell when the first current conductance state is greater than the upper limit of the error range of the set target conductance state; and repeatedly performing the single-pulse SET operation and / or the single-pulse RESET operation on the memristor cell such that the second current conductance state of the memristor cell satisfies the error range; wherein the second programming operation includes the single-pulse SET operation and / or the single-pulse RESET operation.

[0011] According to embodiments of this disclosure, when the first current conductance state is less than the lower limit of the error range of the set target conductance state, the single-pulse SET operation performed on the memristor cell includes: applying a second word line voltage to the word line of the memory cell corresponding to the memristor cell; applying a second bit line voltage to the bit line of the memory cell; and grounding the source line of the memory cell.

[0012] According to embodiments of this disclosure, when a first current conductance state is greater than the upper limit of the error range of a set target conductance state, performing a single-pulse RESET operation on the memristor cell includes: applying a first source line voltage to the source line of the memory cell corresponding to the memristor cell; applying a third word line voltage to the word line of the memory cell; and grounding the bit line of the memory cell.

[0013] According to an embodiment of this disclosure, in performing a second programming operation on a memristor unit based on the error range between a first current conductance state and a set target conductance state, the method further includes: reading the number of programming pulses in the second programming operation; and terminating the second programming operation when the number of programming pulses reaches a set pulse count threshold.

[0014] Another aspect of this disclosure provides an operating apparatus for a memristor cell, comprising a conductance determination module, a first programming module, and a second programming module. The conductance determination module is used to determine the conductance range of a set target conductance state of the memristor cell; the first programming module is used to perform a first programming operation on the memristor cell based on the conductance range and the initial conductance state of the memristor cell, such that a first current conductance state of the memristor cell satisfies the conductance range; and the second programming module is used to perform a second programming operation on the memristor cell based on an error range between the first current conductance state and the set target conductance state, such that a second current conductance state of the memristor cell satisfies the error range.

[0015] Another aspect of this disclosure provides a method for operating a memory array, the memory array comprising a plurality of memory cells arranged in sequence, each memory cell comprising a memristor cell, wherein the method comprises: determining a conductance range of a predetermined target conductance state corresponding to each memristor cell in the plurality of memory cells; performing a parallel first programming operation on each memristor cell in the memory array column-wise according to the conductance range and the initial conductance state corresponding to each memristor cell, such that a first current conductance state of each memristor cell satisfies the conductance range; and performing a parallel second programming operation on each memristor cell in the memory array row-wise according to an error range between the first current conductance state of each memristor cell and the predetermined target conductance state, such that a second current conductance state of each memristor cell satisfies the error range.

[0016] According to embodiments of this disclosure, in performing a first programming operation on each memristor cell in a memory array sequentially column-wise based on the conductance range and the initial conductance state corresponding to each memristor cell, the method includes: determining a first word line voltage for the memory cell corresponding to each memristor cell based on the conductance range and the initial conductance state; applying the first word line voltage to the word line of the memory cell; applying a first bit line voltage to the corresponding bit line of the memory cell; and grounding the corresponding source line of the memory cell to perform the first programming operation on each memristor cell.

[0017] According to embodiments of this disclosure, in performing a second programming operation on each memristor cell of the memory array row by row according to the error range of the first current conductance state of each memristor cell and the set target conductance state, the operation includes: performing a parallel single-pulse SET operation on the memristor cell of at least one memory cell in the memory row of the memory array when the first current conductance state of the memristor cell of at least one memory cell is less than the lower limit of the error range; and / or performing a parallel single-pulse RESET operation on the memristor cell of at least one memory cell when the first current conductance state of the memristor cell of at least one memory cell in the memory row of the memory array is greater than the upper limit of the error range; and repeatedly performing the single-pulse SET operation and / or the single-pulse RESET operation on each corresponding memristor cell of the memory array such that the second current conductance state of each memristor cell satisfies the error range.

[0018] Another aspect of this disclosure provides an operating device for a memory array, the memory array comprising a plurality of memory cells arranged in sequence, each memory cell comprising a memristor cell, wherein the operating device comprises a conductance determination module, a first programming module, and a second programming module. The conductance determination module is used to determine the conductance range of a set target conductance state corresponding to each memristor cell in the plurality of memory cells; the first programming module is used to perform a parallel first programming operation on each memristor cell in the memory array column-wise according to the conductance range and the initial conductance state corresponding to each memristor cell, such that a first current conductance state of each memristor cell satisfies the conductance range; and the second programming module is used to perform a parallel second programming operation on each memristor cell in the memory array row-wise according to the error range between the first current conductance state of each memristor cell and the set target conductance state, such that a second current conductance state of each memristor cell satisfies the error range.

[0019] (III) Beneficial Effects

[0020] This disclosure provides a method and apparatus for operating a memristor cell and a memory array. The method for operating the memristor cell includes: determining the conductance range of a target conductance state of the memristor cell; performing a first programming operation on the memristor cell based on the conductance range and the initial conductance state of the memristor cell, such that a first current conductance state of the memristor cell satisfies the conductance range; and performing a second programming operation on the memristor cell based on an error range between the first current conductance state and the target conductance state, such that a second current conductance state of the memristor cell satisfies the error range. Therefore, by implementing programming operations in two steps for the memristor cell and its memory array, parallel programming operations for each memristor cell can be achieved within the memory array, effectively improving programming speed while maintaining programming accuracy and reducing programming pulse consumption. This achieves high-speed, high-precision, and low-power programming operations for the memristor cell and its memory array. Attached Figure Description

[0021] Figure 1 A flowchart illustrating an operation method of a memristor cell according to an embodiment of the present disclosure is shown schematically.

[0022] Figure 2 The schematic diagram illustrates the equivalent circuit diagram of the array structure of the memory array corresponding to the memristor cell according to an embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram illustrating two programming operations of a memristor cell according to an embodiment of the present disclosure is shown.

[0024] Figure 4 This schematic diagram illustrates the composition of an operating arrangement for a memristor cell according to an embodiment of the present disclosure;

[0025] Figure 5 A flowchart illustrating an operation method of a memory array according to an embodiment of the present disclosure is shown schematically;

[0026] Figure 6 This diagram schematically illustrates an application scenario of the first step of the programming operation in the method of operating a memory array according to an embodiment of the present disclosure;

[0027] Figure 7 This diagram schematically illustrates an application scenario of the second step of the programming operation in the method of operating a memory array according to an embodiment of the present disclosure; and

[0028] Figure 8 A schematic diagram illustrating the operational apparatus composition of a memory array according to an embodiment of the present disclosure is provided. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0030] It should be noted that implementations not illustrated or described in the accompanying drawings or the main text of the specification are all forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various elements and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or substitute them.

[0031] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure.

[0032] Furthermore, the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are merely illustrative of embodiments of this disclosure. Additionally, any reference numerals placed between parentheses in the claims should not be construed as limiting the scope of the claims.

[0033] Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0034] The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify the corresponding elements does not in itself imply that the element has any ordinal number, nor does it represent the order of one element with another element or the order of manufacturing methods. The use of these ordinal numbers is only to enable a named element to be clearly distinguished from another element with the same name.

[0035] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose. Furthermore, in the unit claims enumerating several means, several of these means may be embodied by the same hardware item.

[0036] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various aspects of the disclosure, in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof. However, this approach to disclosure should not be construed as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, the aspects of the disclosure consist of fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the disclosure.

[0037] In the application scenarios of memristors in embedded storage systems and neural network systems, efficient and accurate multi-bit programming of memristors is one of the key challenges in the industry. Multi-bit programming involves rapidly and accurately programming device cells from their initial state to within a target conductance error range. Currently available multi-bit programming methods for memristor cells and corresponding memory arrays can be mainly divided into two categories: unidirectional write-verify schemes and bidirectional write-verify schemes.

[0038] (1) The one-way write-verify operation scheme performs a read operation after each programming. Once the conductivity value after programming is greater than (or less than) the set threshold conductivity, the programming is considered complete. The change in conductivity value is monotonic.

[0039] (2) The two-way write-verify operation scheme increases or decreases the conductance value in the next programming based on the difference between the read conductance value and the target conductance value. Programming is only considered to be over when the programmed conductance value falls within the set target conductance error range or the number of programming pulses exceeds the set maximum number of pulses. The change of conductance value during programming is non-monotonic.

[0040] Both of the above-mentioned operation schemes involve programming from an initial conductance state (typically a high or low conductance state). Compared to the unidirectional operation scheme, the bidirectional operation scheme achieves higher programming accuracy due to the bidirectional threshold set for the target conductance. However, this comes at the cost of consuming more programming pulses. The monotonic change in conductance in the unidirectional operation scheme results in a decrease in programming accuracy, although it reduces the number of pulses required for programming. Although there are existing operation schemes at the array level based on these two programming methods, the technical challenge of reducing programming pulse consumption while achieving high programming accuracy remains a major challenge for memristor cells / arrays in realizing high-speed, high-precision multi-bit programming.

[0041] To address at least one of the technical problems existing in the multi-bit programming operation of memristor cells and memory arrays in the prior art, this disclosure provides a method and apparatus for operating memristor cells and memory arrays. This method enables programming of memristor cells and their corresponding memory arrays in just two programming steps, solving the technical problem that it is difficult to simultaneously achieve programming speed, programming accuracy, and pulse consumption in the multi-bit programming operation of memristor cells and their corresponding memory arrays in the prior art. Parallel programming operations for each memristor cell can be implemented in the memory array, effectively improving programming speed while maintaining programming accuracy and reducing programming pulse consumption. In other words, it achieves high-speed, high-precision, and low-power programming operations for memristor cells and their memory arrays.

[0042] like Figure 1 As shown, one aspect of this disclosure provides a method for operating a memristor cell, including steps S101-S103.

[0043] In step S101, the conductance range of the target conductance state of the memristor cell is determined;

[0044] In step S102, based on the conductance range and the initial conductance state of the memristor cell, a first programming operation is performed on the memristor cell, such that the first current conductance state of the memristor cell satisfies the conductance range; and

[0045] In step S103, a second programming operation is performed on the memristor unit according to the error range between the first current conductance state and the set target conductance state, so that the second current conductance state of the memristor unit satisfies the error range.

[0046] like Figure 2 As shown, the memristor unit M and the transistor are both components of the memory cell (the structure shown in the dashed box). Multiple memory cells are arranged in rows and columns in sequence to form a memory cell. Figure 2 The memory array shown has each memory cell as a 1T1R structure. Multiple memristor cells M are arranged to form a memristor array. The top electrode of each memristor cell is connected to the bit line BL corresponding to that memory cell, the bottom electrode is connected to the drain (i.e., bit terminal) of the corresponding transistor, the source of the transistor is connected to the source line SL corresponding to that memory cell, and the gate of the transistor is connected to the word line WL corresponding to that memory cell. Therefore, by selecting different word lines WL, bit lines BL, and source lines SL, programming operations can be performed on the memristor cells of any memory cell in the memory array, or parallel programming operations can be performed on each memristor cell of any number of memory cells in the memory array. Specifically, as... Figure 2 The memory cell within the dashed box shown can be programmed using a SET operation when a positive voltage is applied to the bit line BL and word line WL of the memory cell, while the source line SL is grounded. This allows for enhanced regulation of the memristor's conductance state. Conversely, when a positive voltage is applied to the source line SL and word line WL of the memory cell, while the bit line BL is grounded, a RESET operation can be performed on the memristor to suppress its conductance state.

[0047] For a single memory cell's memristor unit, a reference conductance state can be pre-set as the target conductance state based on the actual programming needs for adjusting the memristor's conductance and the unit's inherent characteristics (determined by its materials, structure, and manufacturing process). This target conductance state serves as the reference conductance for subsequent programming operations. The conductance range of the target conductance state is the conductance range of the currently set target conductance position, and this range can be set according to actual programming needs. Therefore, by defining the conductance range of the target conductance state, more precise adjustment of the memristor's conductance can be achieved during subsequent programming operations.

[0048] The initial conductance state of a memristor cell is typically a high-resistance, low-conductance state, which can be the initial conductance state of the memristor cell and is generally lower than the set target conductance state. Based on the relationship between the determined initial conductance state and the lower or upper limit of the conductance range of the set target conductance state corresponding to the memristor cell, it can be determined whether to perform a first programming operation on the memristor cell. This first programming operation aims to make the current conductance state of the memristor cell move closer to the target conductance state from the initial conductance state and fall within the corresponding conductance range of the target conductance state. For example... Figure 3 As shown, the first programming operation causes the current conductance state of the memristor cell to change from the initial conductance state to the first current conductance state, which falls within the conductance range of its set target conductance state, i.e., satisfies the conductance range.

[0049] Therefore, during the first programming operation, the memristor cell can be adjusted from its initial conductance state to near the target conductance state (e.g., by applying a single pulse to the corresponding memory cell). Specifically, based on the conductance range of the set target conductance state, the current conductance of the memristor cell can be adjusted to the target range using a SET single pulse. Therefore, compared to the prior art which requires gradually adjusting the current conductance state to the target conductance range, the entire process is completed in one step, achieving coarse adjustment of the memristor cell's conductance state. This significantly reduces the pulse time and energy consumed during the gradual adjustment process when the set target conductance state is far from the initial conductance state, greatly improving the speed of the programming operation while reducing programming overhead.

[0050] Due to the inherent characteristics of the memristor cell, the target conductance state cannot be strictly consistent with the current conductance state in practical applications. Within this conductance range, a reference error range can be set around the target conductance state. Only when the current conductance state of the memristor cell falls within this error range can it be said that the conductance state of the memristor cell satisfies the target conductance state, that is, the current conductance state is closest to or the same as the target conductance state.

[0051] The first programming operation changes the current conductance state of the memristor cell from its initial conductance state to a first current conductance state. Continuing with the second programming operation, the memristor cell changes from its first current conductance state to a second current conductance state. When the second current conductance state meets the aforementioned error range, it indicates that the current conductance state is closest to or the same as the set target conductance state, and the programming operation of the memristor cell is successful. The first and second programming operations are programming operations that adjust the conductance of the memristor cell, specifically implemented by applying pulse voltages to the word lines, bit lines, and source lines of the memory cell corresponding to the memristor cell.

[0052] Therefore, in the second programming step, the current conductance of the memristor cell can be adjusted to the error range set by the target conductance (e.g., through bidirectional write-verify programming). That is, using the coarsely adjusted first conductance state as the initial conductance state, the first conductance state can be adjusted to the second conductance state through bidirectional write-verify programming using pulses such as SET and / or RESET, so that the second conductance state ultimately matches the target conductance error range. Therefore, the second programming operation further fine-tunes the first current conductance state obtained through the coarse adjustment in the first programming operation, ensuring that its second conductance state conforms to the error range of the set target conductance state. This allows for faster adjustment of the device to the target conductance error range, achieving high-speed, high-precision, low-power multi-bit programming.

[0053] As can be seen, the above-described operation method of this disclosure can further combine a second programming operation on the basis of the first programming operation, so that the conductance state of the memristor unit meets the error range of the set target conductance state, and is the same as or closest to the set target conductance state, thereby completing the multi-bit programming operation of the memristor unit. This achieves a balance between programming speed, programming accuracy and programming loss, so as to be better applied to embedded storage systems or neural network systems, and greatly improves the programming efficiency of multi-bit programming operations.

[0054] In summary, the embodiments of this disclosure provide a two-step programming operation scheme that can significantly improve the multi-bit programming efficiency of memristor cells. This is mainly reflected in the following: In the first programming operation, the initial conductance state of the memristor cell is adjusted to near the target conductance state in one step using programming operations such as a single SET pulse. This significantly reduces the pulse time and energy consumed during the gradual adjustment of conductance when the target conductance state is far from the initial conductance state. Based on the first current conductance state after the first programming operation, the second programming operation can further adjust the first current conductance state of the memristor cell to a second current conductance state within the error range of the target conductance state more quickly, thereby achieving high-speed, high-precision, and low-power multi-bit programming.

[0055] like Figures 1-3 As shown, according to an embodiment of this disclosure, in step S101, determining the conductance range of the set target conductance state of the memristor cell includes;

[0056] Based on the characteristics of the memristor unit itself, a set conductance range is determined from multiple set conductance ranges as the conductance range.

[0057] like Figure 3 As shown, at least one of the conductance states S1-S8 can be used as the target conductance state of a memristor cell. Furthermore, based on the conductance state ranges #1-#4 set by the conductance states S1-S8, the conductance range of the target conductance state corresponding to the memristor cell can be determined to be one of the set conductance state ranges #1-#4. For example, based on the correspondence between conductance states S1-S8 and set conductance state ranges #1-#4 (e.g., conductance states S1 and S2 correspond to set conductance state range #1, conductance states S3 and S4 correspond to set conductance state range #2, etc.), the conductance range of the target conductance state S6 can be determined to be set conductance state range #3. The set conductance state range is a distribution reference range of conductance states defined according to actual programming needs.

[0058] Therefore, by defining the conductance range of the target conductance state, it is possible to achieve a more precise adjustment effect when adjusting the conductance of the memristor unit in subsequent programming operations.

[0059] According to an embodiment of this disclosure, in step S102, a first programming operation is performed on the memristor cell based on the conductance range and the initial conductance state of the memristor cell, such that the first current conductance state of the memristor cell satisfies the conductance range, including:

[0060] Based on the initial conductance state and conductance range, determine the first word line voltage for performing the first programming operation;

[0061] A first word line voltage is applied to the word line of the memory cell corresponding to the memristor cell to perform a first programming operation on the memristor cell.

[0062] Each conductance range can define different operating voltages for different programming operations. For the same programming operation, the type of operating voltage defined in different conductance ranges can be the same, but the magnitude can differ. The difference in the magnitude of the operating voltage can be determined based on the position of the initial conductance state. When this operating voltage is applied to the word line, bit line, or source line of a memory cell, a programming operation can be performed on the selected memory cell, thereby causing a corresponding change in the conductance of the memristor cell. For example... Figure 3As shown, for the SET programming operation, when it is necessary to adjust the initial conductance state to the conductance range #3 corresponding to the target conductance state S6, the word line voltage required for the initial conductance state to be in the conductance range #1 corresponding to the conductance state S1 can be greater than the word line voltage required for the initial conductance state to be in the conductance range #2 corresponding to the conductance state S3. This word line voltage can be directly applied to the first step of the SET programming operation. This allows for fine-tuning of the initial conductance state, enabling the memristor cell's conductance state to be adjusted to near the target conductance state in a single programming step. This effectively improves programming speed and reduces programming power consumption while maintaining programming accuracy.

[0063] According to embodiments of this disclosure, in applying a first word line voltage to the word line of the memory cell corresponding to the memristor cell to perform a first programming operation on the memristor cell, the method further includes:

[0064] Apply the first line voltage to the bit line of the memory cell; and

[0065] Ground the source line of the memory cell;

[0066] The first programming operation is a single-pulse SET operation.

[0067] Before performing the first programming operation, the initial conductance state of the memristor cell to be programmed and the conductance range of the target conductance state are determined. Based on this conductance range, the first word line voltage for performing the first programming operation is determined. Simultaneously, the first bit line voltage and source line voltage corresponding to the first word line voltage are also determined. Based on the determined first word line voltage, first bit line voltage, and source line voltage for the first programming operation, the programming operation can be performed on the corresponding memristor cell. Specifically, the first word line voltage is applied to the word line of the memory cell corresponding to the memristor cell, the first bit line voltage is applied to the bit line of the memory cell, and the source line voltage is applied to its source line. When the first programming operation is a single-pulse SET operation, the source line voltage is 0, and the source line of the memory cell can be grounded.

[0068] As can be seen, by setting the initial conductance state of the memristor cell (generally a low conductance state), and then determining the conductance range of the target conductance state (e.g., ... Figure 3 The operating voltage of the first programming operation, which can be determined by the conductivity range (#1-#4) shown, is applied to the word line voltage and bit line voltage of the corresponding memory cell. At the same time, the source line of the memory cell is grounded, making the source line voltage 0. This completes the first step of programming based on the single-pulse SET programming operation, so that the current conductivity state of the corresponding memristor cell is adjusted from the initial conductivity state to the first current conductivity state that meets the set target conductivity state within the conductivity range (#3).

[0069] Clearly, by performing a single-pulse SET operation on the memristor unit through the first programming operation, the conductance state of the memristor unit can be coarsely adjusted to near the target conductance state, which effectively improves the programming speed and reduces the programming power consumption while ensuring programming accuracy.

[0070] The corresponding SET operation is a single-pulse operation. Compared with the traditional method of continuously applying the same pulse or applying pulses with different parameters to program the memristor unit, only a single pulse operation is needed to program the memristor unit. This greatly improves the programming speed while ensuring programming accuracy, and has high scientific research value and commercial application value.

[0071] According to an embodiment of this disclosure, in step S103, a second programming operation is performed on the memristor cell based on the error range between the first current conductance state and the set target conductance state, such that the second current conductance state of the memristor cell satisfies the error range, including:

[0072] When the first current conductance state is less than the lower limit of the error range of the set target conductance state, a single-pulse SET operation is performed on the memristor cell; and / or

[0073] When the first current conductance state is greater than the upper limit of the error range of the set target conductance state, a single-pulse RESET operation is performed on the memristor unit; and

[0074] Repeatedly perform single-pulse SET and / or single-pulse RESET operations on the memristor cell to ensure that the second current conductance state of the memristor cell meets the error range;

[0075] The second programming operation includes a single-pulse SET operation and / or a single-pulse RESET operation.

[0076] After the single-pulse SET programming operation in the first programming operation, the first current conductance state of the memristor cell can be located within the conductance range of the set target conductance state. That is, the first current conductance state is basically located near the set target conductance state, possibly slightly smaller or slightly larger than the set target conductance state. To further ensure that the current conductance state of the memristor cell can be infinitely close to the set target conductance state, an error range is defined for the set target conductance state. This error range generally falls within the conductance range of the set target conductance state. This error range is a selection range of conductance values, which generally has a lower limit (corresponding to the lower limit of the range) and an upper limit (corresponding to the upper limit of the range). Typically, only when the conductance value of the current conductance state is greater than or equal to the lower limit of the error range, and less than or equal to the upper limit of the error range, can it be said that the conductance state of the memristor cell is within the error range, thus completing the fine adjustment of the conductance state.

[0077] Therefore, by utilizing the conductance state enhancement adjustment characteristic of the single-pulse SET operation and the conductance state suppression adjustment characteristic of the single-pulse RESET operation, the conductance state of memristor cells that do not conform to the above error range can be further fine-tuned. Specifically, this can be determined based on the relationship between the first current conductance state of the memristor cell after the first programming operation and the upper and lower limits of the error range, as follows:

[0078] If the first current conductance state is less than the lower limit of the error range, a single-pulse SET operation is performed on the memristor cell to enhance the conductance of the first current conductance state, so that the second current conductance state of the memristor cell after conductance enhancement is at least greater than the lower limit of the error range of the target conductance state.

[0079] If the first current conductance state is greater than the upper limit of the error range, a single-pulse RESET operation is performed on the memristor cell to suppress the conductance of the first current conductance state, so that the second current conductance state of the memristor cell after conductance suppression is at least less than the upper limit of the error range of the target conductance state.

[0080] The relationship between the second current conductance state after conductance enhancement or suppression and the error range is further evaluated. When the second current conductance state falls within the error range (i.e., the second current conductance state is greater than the lower limit of the error range but less than the upper limit), the error range is satisfied. When the second current conductance state falls outside the error range (i.e., the second current conductance state is still less than the lower limit of the error range or greater than the upper limit of the error range), the error range is not satisfied. In this case, the single-pulse SET operation or single-pulse RESET operation needs to be repeated until the current conductance state of the memristor cell can satisfy the error range, i.e., the single-pulse multi-bit programming operation is successful.

[0081] As can be seen, based on the results of the first programming operation, the second programming operation, combined with bidirectional write-verify programming, can enable repeated operations on the memristor cell until its current conductance state meets the error range of its corresponding target conductance state. This ensures fine-tuning of the conductance state of the memristor cell, taking into account programming accuracy, programming speed, and programming power consumption.

[0082] Corresponding to the aforementioned single-pulse SET operation, the corresponding RESET operation is also a single-pulse operation. Compared to the traditional technical solution of continuously applying the same pulse or applying pulses with different parameters to program the memristor unit, only one single-pulse operation is needed to program the memristor unit, thereby greatly improving the programming speed while ensuring programming accuracy. It has high scientific research value and commercial application value.

[0083] According to embodiments of this disclosure, when a first current conductance state is less than the lower limit of the error range of a set target conductance state, performing a single-pulse SET operation on the memristor cell includes:

[0084] Apply a second word line voltage to the word line of the memory cell corresponding to the memristor cell;

[0085] Apply a second bit line voltage to the bit line of the memory cell; and

[0086] The source line of the memory cell is grounded.

[0087] In the second programming operation described above, the operating voltage for performing a further single-pulse SET operation on the first current conductance state can be determined by the conductance range #3 of the first current conductance state. This operating voltage includes the second word line voltage, the second bit line voltage, and the source line voltage applied to the corresponding memory cell. Specifically, the second word line voltage can be applied to the word line of the memory cell corresponding to the memristor cell, the second bit line voltage can be applied to the bit line of the memory cell, and the source line voltage can be applied to its source line. When the second programming operation is a single-pulse SET operation, the source line voltage is 0, and the source line of the memory cell can be grounded.

[0088] Therefore, a memristor cell whose first current conductance state is less than the lower limit of the error range of the set target conductance state can be further programmed with conductance enhancement, so that the second current conductance state of the memristor cell after conductance enhancement is at least greater than the lower limit of the error range of the target conductance state.

[0089] According to embodiments of this disclosure, the single-pulse RESET operation performed on the memristor cell when the first current conductance state is greater than the upper limit of the error range of the set target conductance state includes:

[0090] Apply a first source line voltage to the source line of the memory cell corresponding to the memristor cell;

[0091] Apply a third word line voltage to the word line of the memory cell; and

[0092] Ground the bit lines of the memory cell.

[0093] In the second programming operation described above, the operating voltage for performing a further single-pulse RESET operation on the first current conductance state can be determined by the conductance range #3 of the first current conductance state. This operating voltage includes the third word line voltage, bit line voltage, and first source line voltage applied to the corresponding memory cell. Specifically, the third word line voltage can be applied to the word line of the memory cell corresponding to the memristor cell, the bit line voltage can be applied to the bit line of the memory cell, and the first source line voltage can be applied to its source line. When the second programming operation is a single-pulse RESET operation, the bit line voltage is 0, and the bit line of the memory cell can be grounded.

[0094] Therefore, a memristor cell whose first current conductance state is greater than the upper limit of the error range of the set target conductance state can be further programmed with conductance suppression, so that the second current conductance state of the memristor cell after conductance suppression is at least less than the upper limit of the error range of the target conductance state.

[0095] According to embodiments of this disclosure, in step S103, performing a second programming operation on the memristor unit based on the error range between the first current conductance state and the set target conductance state, the method further includes:

[0096] Read the number of programming pulses in the second programming operation;

[0097] When the number of programming pulses reaches the set pulse count threshold, the second programming operation is terminated.

[0098] Furthermore, due to limitations in the materials, structure, and fabrication processes of memristor cells and corresponding transistors, the upper limit of the number of single-pulse programming operations (i.e., the number of programming pulses) that the corresponding memory cells can withstand must be considered during positive pulse voltage programming operations. Specifically, the operating voltage repeatedly applied to the word line and bit line or word line and source line during the repeated single-pulse SET and / or single-pulse RESET operations in the second programming process described above is a positive pulse voltage, and each operation is a single-pulse programming operation.

[0099] Therefore, when the number of repeated programming pulses is less than the set pulse number threshold, as long as the second current conductance state does not meet the above error range, the single-pulse SET operation and / or single-pulse RESET operation can continue to be performed until the number of programming pulses equals the set pulse number threshold. At this time, the second programming operation can be stopped. Even if the second current conductance state still does not meet the above error range, programming still needs to be ended, that is, programming fails, and the memristor unit is determined to be a programming failure device unit.

[0100] This allows for better structural protection of the memory array containing the memristor cells, preventing a problem in a single memristor cell from causing problems in part or all of the memory array.

[0101] like Figure 4 As shown, another aspect of this disclosure provides an operating device 400 for a memristor unit, which includes a conductance determination module 410, a first programming module 420, and a second programming module 430.

[0102] The conductance determination module 410 is used to determine the conductance range of the set target conductance state of the memristor cell;

[0103] The first programming module 420 is used to perform a first programming operation on the memristor cell according to the conductance range and the initial conductance state of the memristor cell, so that the first current conductance state of the memristor cell satisfies the conductance range; and

[0104] The second programming module 430 is used to perform a second programming operation on the memristor unit according to the error range between the first current conductance state and the set target conductance state, so that the second current conductance state of the memristor unit meets the error range.

[0105] The memristor unit operating device 400 can at least be used to implement the memristor unit operating method of the above steps S101-S103, and its corresponding technical effects and functions will not be elaborated here.

[0106] like Figures 5-8 As shown, another aspect of this disclosure provides a method for operating a memory array, the memory array including a plurality of memory cells arranged in sequence, each memory cell including a memristor cell, wherein the method includes steps S501-S503.

[0107] In step S501, the conductance range of the target conductance state corresponding to each memristor cell in the plurality of memory cells is determined;

[0108] In step S502, based on the conductance range and the initial conductance state of each memristor cell, a parallel first programming operation is performed sequentially column-wise on each memristor cell in the memory array, such that the first current conductance state of each memristor cell satisfies the conductance range; and

[0109] In step S503, based on the error range of the first current conductance state and the set target conductance state of each memristor cell, a parallel second programming operation is performed on each memristor cell of the memory array row by row, so that the second current conductance state of each memristor cell satisfies the error range.

[0110] For a memory array, if the operation method of steps S101-S103 described above is executed for each memristor cell, the operation order of the array cells in each step can be defined, such as sequentially operating row by row or column by column, or sequentially operating in parallel by row and column respectively. In the embodiments of this disclosure, parallel operation of multiple memory cells by column can be implemented in the first programming operation, and parallel operation of multiple memory cells by row can be implemented in the second programming operation.

[0111] like Figure 6 As shown in the dashed box, this is a memory column cell of the memory array. This memory column cell includes four memory cells in the first column, from row 1 to row 4. In the first programming operation, a single-pulse SET operation is performed in parallel on every four corresponding memristor cells in each memory column cell. Then, the same single-pulse SET operation is performed in parallel on the other memory column cells of the memory array, column by column, until every memristor cell in all memory column cells has completed the single-pulse SET operation. This ensures that after the conductance of its corresponding initial conductance state is enhanced by the single-pulse SET operation, the first current conductance state matches the conductance range of the set target conductance state, i.e., the first current conductance state is located near the set target conductance state. The specific operation for each memristor cell can be found in the first programming operation section of the memristor cell operation method described above, and will not be repeated here.

[0112] Furthermore, such as Figure 7 As shown in the dashed box, this is a memory row cell of the memory array. This memory row cell includes four memory cells in the first row, from column 1 to column 4. In the second programming operation, a single-pulse SET or single-pulse RESET operation can be performed in parallel on every four corresponding memristor cells in each memory row cell, row by row. Then, the same single-pulse SET or single-pulse RESET operation is performed in parallel on the other memory row cells of the memory array, row by row, until each memristor cell in all memory column cells completes the single-pulse SET or single-pulse RESET operation, ensuring that its corresponding second current conductance state conforms to the error range of the set target conductance state. This completes the fine-tuning of the conductance state of the corresponding memristor cell. The execution of the single-pulse SET or single-pulse RESET operation can be determined based on the relationship between the upper and lower limits of the error range between the second current conductance state and the set target conductance state. Furthermore, to ensure that the current conductance state of all memristor cells conforms to this error range, the single-pulse SET or single-pulse RESET operation can be repeatedly performed multiple times based on the relationship between the second current conductance state and the upper and lower limits. For the operation of each memristor cell, please refer to the second programming operation in the above-mentioned operation method for memristor cells, which will not be repeated here.

[0113] Since the target conductance states of different memristor cells are not the same, when applying the above two-step programming scheme to memory array operations, column parallel operation is used in the first programming step and row parallel operation is used in the second programming step, which can further improve the efficiency of multi-bit programming.

[0114] Therefore, the operation method of the memory array in the above-described embodiments of the present disclosure can significantly improve the multi-bit programming efficiency for each memristor cell in the memory array, realize high-speed and high-precision array-level multi-bit programming, and make the memory array better applicable to scenarios such as embedded storage systems and neural network systems.

[0115] like Figures 5-7 As shown, according to an embodiment of this disclosure, in step S502, the first programming operation is performed sequentially column-by-column on each memristor cell in the memory array based on the conductance range and the initial conductance state corresponding to each memristor cell, including:

[0116] Based on the conductance range and initial conductance state, determine the first word line voltage for the memory cell corresponding to each memristor cell;

[0117] A first word line voltage is applied to the word line of the memory cell, a first bit line voltage is applied to the corresponding bit line of the memory cell, and the corresponding source line of the memory cell is grounded to perform a first programming operation on each memristor cell.

[0118] For the first programming operation of the memory array, the initial conductance state of each corresponding memristor cell in the memory array can be set to a low conductance state, that is, the low conductance state can be used as the starting conductance state. Specifically, as follows: Figure 6 As shown, an operation is performed on a memory column consisting of a row of memory cells. Based on the target conductance (one of S1-S8) of each memristor cell in the memory column, within the conductance range (conductance range #1-#4), different gate voltages (i.e., word line voltages V) are applied to the word line WL of each row of the memory column corresponding to that memristor cell. WL0 -V wL3 At the same time, a different SET single-pulse voltage (i.e., bit line voltage V) corresponding to the word line voltage is applied to the bit line BL. BL Simultaneously, the bit line voltages of other memory column cells are set to 0, and the source line voltages of the entire memory array are set to 0. This allows a parallel single-pulse SET operation to be performed on each memristor cell of that memory column cell, adjusting the current conductance state of each memristor cell to its respective target conductance range. Afterward, the same parallel single-pulse SET operation is performed on each memory column cell in turn.

[0119] Therefore, compared to the existing technology which requires gradually adjusting the current conductance state to the target conductance range, the first step of the SET programming operation for the memory array can be completed in one step, realizing the coarse adjustment of the conductance state of each memristor cell in the memory array. This significantly reduces the pulse time and energy consumed in the traditional gradual adjustment process, greatly improves the speed of the programming operation, and reduces programming consumption.

[0120] According to embodiments of this disclosure, in step S503, the second programming operation is performed row-by-row on each memristor cell of the memory array based on the error range between the first current conductance state and the set target conductance state of each memristor cell, including:

[0121] When the first current conductance state of the memristor cell of at least one memory cell in the memory row of the memory array is less than the lower limit of the error range, a parallel single-pulse SET operation is performed on the memristor cell of at least one memory cell; and / or

[0122] When the first current conductance state of the memristor cell of at least one memory cell in the memory row of the memory array is greater than the upper limit of the error range, a parallel single-pulse RESET operation is performed on the memristor cell of at least one memory cell.

[0123] For each memristor cell in the memory array, a single-pulse SET operation and / or a single-pulse RESET operation are repeatedly performed to ensure that the second current conductance state of each memristor cell satisfies the error range.

[0124] The second programming operation of the memory array can be performed based on the first programming operation of the memory array described above. Specifically, by adjusting the gate voltage, using RESET single pulse and SET single pulse, and using bidirectional write-verify programming in parallel, the conductance state of the corresponding memristor cell in a row of memory cells is adjusted to the error range of the set target conductance. Then, the parallel operation is performed on each row in sequence until the conductance state of all memristor cells can meet the above error range.

[0125] Specifically, such as Figure 7As shown, when operating on a row of memory cells, if the current conductance state of the memory row cell is less than the lower limit of the error range of the user-defined target conductance state, a single-pulse SET operation can be used as the starting operation for the second programming operation (or a single-pulse RESET operation can be used as the starting operation for the second programming operation, which is not limited). For memristor cells in the memory row cell that have completed the first programming operation and whose current conductance state is less than the error range, a single-pulse SET operation is performed. Specifically, based on the conductance range (conductance range #1-#4) of the memristor cell (one of S1-S8), a gate voltage (i.e., word line voltage V) is applied to the word line WL of the corresponding row of the memory row cell. WL Simultaneously apply a SET single-pulse voltage (i.e., bit line voltage V) corresponding to the word line voltage to each bit line BL of that row. BL Simultaneously, the word line voltages of other memory row cells are set to 0, and the source line voltages of the entire memory array are set to 0, thereby performing a parallel single-pulse SET operation on each memristor cell of that memory row cell. Afterwards, the same parallel single-pulse SET operation is performed on each of the other memory row cells, ensuring that the current conductance value of all memristor cells is at least greater than the lower limit of the error range.

[0126] When the current conductance value of the memristor cell in each row of the memory array is greater than the lower limit of the error range of its corresponding target conductance state, the single-pulse SET operation of the second programming operation stops, and a single-pulse RESET operation is performed. For example... Figure 7 As shown, when operating on a row of memory cells, if the current conductance state of the memory row cell is greater than the upper limit of the error range of the user-defined target conductance state, a single-pulse RESET operation can be used as a supplementary operation to the single-pulse SET operation in the second programming process. For memristor cells in the memory row cell whose current conductance state is greater than the upper limit of the error range after the single-pulse SET operation in the second programming process, a single-pulse RESET operation is performed. Specifically, based on the conductance range (conductance range #1-#4) of the memristor cell (one of S1-S8), a gate voltage (i.e., word line voltage V) is applied to the word line WL of the corresponding row of the memory row cell. WL Simultaneously apply the word line voltage V to each source line SL corresponding to that row. WL The corresponding RESET single-pulse voltage (i.e., source line voltage V) SLSimultaneously, the word line voltages of other memory row cells are set to 0, and the bit line voltages of the entire memory array are set to 0, thereby performing a parallel single-pulse RESET operation on each memristor cell of that memory row cell. Afterwards, the same parallel single-pulse RESET operation is performed on each of the other memory row cells, ensuring that the current conductance value of all memristor cells is at least less than the upper limit of this error range. The word line voltage can satisfy V... WL =5V.

[0127] The SET and RESET single-pulse operations are repeated until the conductance states of all memory cells in the memory array fall within the error range of their respective target conductance states, or the number of programming pulses reaches the upper limit of the set pulse number threshold. The programming ends when the former indicates successful programming of all memristor cells, and the latter indicates the existence of memristor cells that have failed to be programmed, and identifies and confirms these failed memory cells. Therefore, the second programming operation further fine-tunes the current conductance state obtained through the coarse adjustment in the first programming operation, ensuring that the conductance state of the corresponding memristor cell conforms to the error range. This allows for faster adjustment of the device to the target conductance state error range, achieving high-speed, high-precision, low-power multi-bit programming.

[0128] It should be further noted that, in the second programming operation of the memory array mentioned above, a row-by-row single-pulse RESET operation can be used as the initial programming operation, followed by a row-by-row single-pulse SET operation. Repeating the single-pulse RESET operation and the single-pulse SET operation can achieve successful programming.

[0129] Furthermore, it should be specifically noted that the above description refers to performing a parallel single-pulse SET operation on all rows, followed by a parallel single-pulse RESET operation on all rows. Correspondingly, it is also possible to perform a single-pulse SET operation on a single row, then a parallel single-pulse RESET operation on that row, and repeat the above parallel single-pulse SET and RESET operations on all memristor cells in that row that do not meet the relevant error range upper and lower limits, until the current conductance state of all memristor cells in that row meets the aforementioned error range. Finally, the parallel single-pulse SET and RESET operations on each row are repeated one by one, thereby ensuring that the current conductance state of each memristor cell in all rows falls within the aforementioned error range. Those skilled in the art can directly and unambiguously derive the specific content of this technical solution based on the above disclosure, and will not elaborate further here.

[0130] Therefore, by performing a column-parallel first programming operation on the memory array combined with a row-parallel second programming operation, the multi-bit programming speed of the memristor cells in the memory array can be significantly improved while ensuring programming accuracy and reducing programming power consumption. In other words, high-speed, high-precision, and low-power programming operations of the memristor cells and their memory array are realized.

[0131] As can be seen, the above-described memory array operation method of this disclosure can further combine a second programming operation on the basis of the first programming operation, so that the conductance state of each memristor cell of the memory array meets the error range of the set target conductance state, and is the same as or closest to the set target conductance state, thereby completing the multi-bit programming operation of the memristor cells of the memory array. This achieves a balance between programming speed, programming accuracy and programming loss during the multi-bit programming process of the memory array, so as to be better applied to embedded storage systems or neural network systems, and greatly improves the programming efficiency of the multi-bit programming operation of the memory array.

[0132] like Figure 8 As shown, another aspect of this disclosure provides an operating device 800 for a memory array, the memory array including a plurality of memory cells arranged in sequence, each memory cell including a memristor cell, wherein the operating device 800 includes a conductance determination module 810, a first programming module 820 and a second programming module 830.

[0133] The conductance determination module 810 is used to determine the conductance range of the set target conductance state corresponding to each memristor cell in multiple memory cells;

[0134] The first programming module 820 is used to perform a parallel first programming operation on each memristor cell in the memory array sequentially column-wise according to the conductance range and the initial conductance state of each corresponding memristor cell, so that the first current conductance state of each memristor cell satisfies the conductance range; and

[0135] The second programming module 830 is used to perform parallel second programming operations on each memristor cell of the memory array in a row-by-row manner, based on the error range of the first current conductance state and the set target conductance state of each memristor cell, so that the second current conductance state of each memristor cell satisfies the error range.

[0136] The memory array operation device 800 can at least be used to implement the memory array operation method of steps S501-S503 above, and its corresponding technical effects and functions will not be elaborated here.

[0137] The embodiments of this disclosure have now been described in detail with reference to the accompanying drawings.

[0138] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for operating a memristor cell, wherein, include: Determine the conductance range of the target conductance state of the memristor cell; wherein, based on the characteristics of the memristor cell itself, one set conductance range is determined from multiple set conductance ranges as the conductance range; Based on the conductance range and the initial conductance state of the memristor cell, a first programming operation is performed on the memristor cell such that the first current conductance state of the memristor cell satisfies the conductance range; wherein, the first programming operation is a single-pulse SET operation; and Based on the error range between the first current conductance state and the set target conductance state, a second programming operation is performed on the memristor unit, such that the second current conductance state of the memristor unit satisfies the error range; wherein the error range falls within the conductance range.

2. The operating method according to claim 1, wherein, The step of performing a first programming operation on the memristor cell based on the conductance range and the initial conductance state of the memristor cell, such that the first current conductance state of the memristor cell satisfies the conductance range, includes: Based on the initial conductance state and the conductance range, a first word line voltage is determined for performing the first programming operation; The first word line voltage is applied to the word line of the memory cell corresponding to the memristor cell to perform the first programming operation on the memristor cell.

3. The operating method according to claim 2, wherein, The step of applying the first word line voltage to the word line of the memory cell corresponding to the memristor cell to perform the first programming operation on the memristor cell further includes: Apply a first line voltage to the bit line of the memory cell; and The source line of the memory cell is grounded.

4. The operating method according to claim 1, wherein, Performing a second programming operation on the memristor cell based on the error range between the first current conductance state and the set target conductance state, such that the second current conductance state of the memristor cell satisfies the error range, includes: When the first current conductance state is less than the lower limit of the error range of the set target conductance state, a single-pulse SET operation is performed on the memristor unit; and / or When the first current conductance state is greater than the upper limit of the error range of the set target conductance state, a single-pulse RESET operation is performed on the memristor unit; and The single-pulse SET operation and / or single-pulse RESET operation are repeatedly performed on the memristor unit so that the second current conductance state of the memristor unit satisfies the error range; The second programming operation includes a single-pulse SET operation and / or a single-pulse RESET operation.

5. The operating method according to claim 4, wherein, The step of performing a single-pulse SET operation on the memristor unit when the first current conductance state is less than the lower limit of the error range of the set target conductance state includes: A second word line voltage is applied to the word line of the memory cell corresponding to the memristor cell; A second bit line voltage is applied to the bit line of the memory cell; and The source line of the memory cell is grounded.

6. The operating method according to claim 4, wherein, The step of performing a single-pulse RESET operation on the memristor unit when the first current conductance state is greater than the upper limit of the error range of the set target conductance state includes: A first source line voltage is applied to the source line of the memory cell corresponding to the memristor cell; A third word line voltage is applied to the word line of the memory cell; and The bit lines of the memory cell are grounded.

7. The operating method according to claim 1, wherein, The second programming operation performed on the memristor unit based on the error range between the first current conductance state and the set target conductance state further includes: Read the number of programming pulses in the second programming operation; When the number of programming pulses reaches the set pulse count threshold, the second programming operation is terminated.

8. An operating device for a memristor unit, wherein, include: A conductance determination module is used to determine the conductance range of a set target conductance state of the memristor unit; wherein, a set conductance range is determined from multiple set conductance ranges based on the characteristics of the memristor unit itself as the conductance range; A first programming module is configured to perform a first programming operation on the memristor unit based on the conductance range and the initial conductance state of the memristor unit, such that the first current conductance state of the memristor unit satisfies the conductance range; wherein the first programming operation is a single-pulse SET operation; and The second programming module is used to perform a second programming operation on the memristor unit according to the error range between the first current conductance state and the set target conductance state, so that the second current conductance state of the memristor unit satisfies the error range; wherein the error range falls within the conductance range.

9. A method of operating a memory array, the memory array comprising a plurality of memory cells arranged in sequence, each memory cell comprising a memristor cell, wherein, The operation method includes: Determine the conductance range of a target conductance state for each memristor cell in the plurality of memory cells; wherein, a set conductance range is determined from the plurality of set conductance ranges based on the characteristics of the memristor cell itself as the conductance range; Based on the conductance range and the initial conductance state of each memristor cell, a parallel first programming operation is performed sequentially column-wise on each memristor cell in the memory array, such that the first current conductance state of each memristor cell satisfies the conductance range; wherein, the first programming operation is a single-pulse SET operation; and Based on the error range of the first current conductance state of each memristor cell and the set target conductance state, a parallel second programming operation is performed on each memristor cell of the memory array row by row, such that the second current conductance state of each memristor cell satisfies the error range; wherein the error range falls within the conductance range.

10. The operating method according to claim 9, wherein, The step of performing a first programming operation on each memristor cell in the memory array sequentially column-by-column according to the conductance range and the initial conductance state corresponding to each memristor cell includes: Based on the conductance range and the initial conductance state, a first word line voltage is determined for the memory cell corresponding to each memristor cell; The first word line voltage is applied to the word line of the memory cell, the first bit line voltage is applied to the corresponding bit line of the memory cell, and the corresponding source line of the memory cell is grounded, so as to perform the first programming operation on each memristor cell.

11. The operating method according to claim 9, wherein, The step of performing a second programming operation on each memristor cell of the memory array row by row, based on the error range between the first current conductance state and the set target conductance state of each memristor cell, includes: When the first current conductance state of the memristor cell of at least one memory cell in the memory row of the memory array is less than the lower limit of the error range, a parallel single-pulse SET operation is performed on the memristor cell of the at least one memory cell; and / or When the first current conductance state of the memristor cell of at least one memory cell in the memory row of the memory array is greater than the upper limit of the error range, a parallel single-pulse RESET operation is performed on the memristor cell of the at least one memory cell. The single-pulse SET operation and / or the single-pulse RESET operation are repeatedly performed on each corresponding memristor cell of the memory array, such that the second current conductance state of each memristor cell satisfies the error range.

12. An operating apparatus for a memory array, the memory array comprising a plurality of memory cells arranged in sequence, each memory cell comprising a memristor cell, wherein, The operating device includes: A conductance determination module is used to determine the conductance range of a set target conductance state for each memristor cell in the plurality of memory cells; wherein, a set conductance range is determined from a plurality of set conductance ranges as the conductance range based on the characteristics of the memristor cell itself. A first programming module is configured to perform a parallel first programming operation on each memristor cell in the memory array sequentially, column by column, according to the conductance range and the initial conductance state of each corresponding memristor cell, such that the first current conductance state of each memristor cell satisfies the conductance range; wherein the first programming operation is a single-pulse SET operation; and The second programming module is used to perform a parallel second programming operation on each memristor cell of the memory array in a row-by-row manner, based on the error range between the first current conductance state of each memristor cell and the set target conductance state, so that the second current conductance state of each memristor cell satisfies the error range; wherein the error range falls within the conductance range.

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