Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a device region and a dummy device region, the substrate comprising an isolation layer, a gate structure located on the isolation layer, a first mask layer located on the gate structure, a source-drain plug located on the isolation layer between the gate structures, and a second mask layer located on the source-drain plug. In an embodiment of the present invention, the first mask layer and the second mask layer on the dummy device region are removed respectively, and accordingly, the first opening and the second opening respectively expose the gate structure and the source-drain plug in the dummy device region, and the gate structure exposed by the first opening and the source-drain plug exposed by the second opening are removed in the same step, and a gate groove at the bottom of the first opening and a source-drain groove at the bottom of the second opening are formed simultaneously, and accordingly, a dielectric layer can be formed in the gate groove and the source-drain groove in the same step, and the dielectric layer can simultaneously block the gate structure and the source-drain plug, which is conducive to simplifying the formation process of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve integration and reduce costs, the key dimensions of components are constantly decreasing, and the circuit density inside the integrated circuit is increasing. This development makes it impossible for the wafer surface to provide enough area to make the required interconnection lines.

[0003] In order to meet the interconnection requirements after the critical dimensions are reduced, the conduction between different metal layers or between the metal layer and the substrate is currently achieved through an interconnection structure. The interconnection structure includes interconnection lines and contact hole plugs formed in the contact openings. The contact hole plugs are connected to the semiconductor device, and the interconnection lines realize the connection between the contact hole plugs, thereby forming a circuit.

[0004] The contact plugs in the transistor structure include a gate contact plug located on the surface of the gate structure for connecting the gate structure with an external circuit, and a source-drain contact plug located on the surface of the source-drain doped layer for connecting the source-drain doped layer with an external circuit.

[0005] At present, in order to further reduce the area of ​​transistors, the contact over active gate (COAG) process has been introduced. Compared with the traditional gate contact plug located above the gate structure in the isolation area, the COAG process can place the gate contact plug above the gate structure in the active area (AA), thereby further saving the chip area. Summary of the invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to optimize the electrical performance of the semiconductor structure.

[0007] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a device area and a dummy device area, the substrate comprising an isolation layer, a gate structure located on the isolation layer, a first mask layer located on the gate structure, a source / drain plug located on the isolation layer between the gate structures, and a second mask layer located on the source / drain plug; removing the first mask layer on the gate structure in the dummy device area, forming a first opening in the first mask layer to expose the gate structure; removing the second mask layer on the source / drain plug in the dummy device area, forming a second opening in the second mask layer to expose the source / drain plug; using the remaining first mask layer and second mask layer as masks to remove the gate structure exposed by the first opening and the source / drain plug exposed by the second opening, forming a gate groove at the bottom of the first opening, and forming a source / drain groove at the bottom of the second opening; and forming a dielectric layer in the gate groove and the source / drain groove.

[0008] Optionally, a dry etching process is used to remove the first mask layer on the gate structure in the dummy device area.

[0009] Optionally, in the step of removing the first mask layer on the gate structure of the dummy device region, an etching rate of the first mask layer is greater than an etching rate of the second mask layer.

[0010] Optionally, the material of the first mask layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0011] Optionally, a dry etching process is used to remove the second mask layer on the source and drain plugs in the dummy device area.

[0012] Optionally, in the step of removing the second mask layer on the source / drain plug in the dummy device region, an etching rate of the second mask layer is greater than an etching rate of the first mask layer.

[0013] Optionally, the material of the second mask layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0014] Optionally, the first mask layer on the source / drain plug in the dummy device area is removed, and the step of forming a first opening includes: forming a first blocking layer covering the device area and exposing the first mask layer in the dummy device area; removing the first mask layer in the dummy device area using the first blocking layer as a mask; the method for forming the semiconductor structure also includes: after removing the first mask layer in the dummy device area, removing the first blocking layer.

[0015] Optionally, the first opening is formed; after the first opening is formed, the second opening is formed; the second mask layer on the source and drain plugs in the dummy device area is removed, and the step of forming the second opening includes: forming a second blocking layer covering the first opening and the device area and exposing the second mask layer in the dummy device area; removing the second mask layer in the dummy device area using the second blocking layer as a mask; the method for forming the semiconductor structure also includes: after removing the second mask layer in the dummy device area, removing the second blocking layer.

[0016] Optionally, a dry etching process is adopted with the remaining first mask layer and second mask layer as masks to remove the gate structure exposed by the first opening and the source / drain plug exposed by the second opening.

[0017] Optionally, process parameters for removing the gate structure exposed by the first opening and the source / drain plug exposed by the second opening using the first mask layer and the second mask layer as masks include: etching gas includes one or both of CH3F and SF6; the flow rate of etching gas is 50 sccm to 500 sccm; auxiliary gas includes O2; chamber pressure is 5 mToor to 200 mToor; etching power is 50 W to 500 W.

[0018] Optionally, in the step of providing a substrate, the substrate also includes: a substrate; a fin located on the substrate; the isolation layer located on the substrate on the side of the fin, and the isolation layer covers a portion of the side wall of the fin; the gate structure spans the fin on the isolation layer and covers a portion of the top wall and a portion of the side wall of the fin; the substrate also includes: a source-drain doped layer located in the fin on both sides of the gate structure; the source-drain plug is located on the top of the source-drain doped layer; the substrate also includes: an interlayer dielectric layer located on the source-drain doped layer on the side of the gate structure, and the top surface of the interlayer dielectric layer is lower than or flush with the top surface of the gate structure.

[0019] Optionally, the method for forming the semiconductor structure further includes: after forming the dielectric layer, forming a gate plug on top of the gate structure.

[0020] Optionally, the material of the gate structure includes metal.

[0021] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including: a substrate, the substrate including a device area and a dummy device area, the substrate including an isolation layer, a gate structure located on the isolation layer, a first mask layer located on the gate structure, a source-drain plug located on the isolation layer between the gate structures, and a second mask layer located on the source-drain plug; a first opening located in the first mask layer, the first opening exposing the gate structure of the dummy device area; a second opening located in the second mask layer, the second opening exposing the source-drain plug of the dummy device area.

[0022] Optionally, the material of the first mask layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0023] Optionally, the material of the second mask layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0024] Optionally, the substrate also includes: a substrate; a fin located on the substrate; an isolation layer located on the substrate on the side of the fin, the isolation layer covering a portion of the side wall of the fin; the gate structure spans the fin on the isolation layer and covers a portion of the top wall and a portion of the side wall of the fin; the substrate also includes: a source-drain doped layer located in the fin on both sides of the gate structure; the source-drain plug is located on the top of the source-drain doped layer; the substrate also includes: an interlayer dielectric layer located on the source-drain doped layer on the side of the gate structure, and the top surface of the interlayer dielectric layer is lower than or flush with the top surface of the gate structure.

[0025] Optionally, the material of the gate structure includes metal.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] In the method for forming a semiconductor structure provided in an embodiment of the present invention, the substrate includes a device area and a dummy device area, the substrate includes an isolation layer, a gate structure located on the isolation layer, a first mask layer located on the gate structure, a source / drain plug located on the isolation layer between the gate structures, and a second mask layer located on the source / drain plug; the first mask layer on the gate structure in the dummy device area is removed to form a first opening exposing the gate structure; the second mask layer on the source / drain plug in the dummy device area is removed to form a second opening exposing the source / drain plug. In an embodiment of the present invention, the first mask layer and the second mask layer on the dummy device area are removed respectively, and accordingly, the remaining first mask layer and the second mask layer expose the gate structure and the source-drain plug in the dummy device area, and the remaining first mask layer and the second mask layer are used as masks to remove the gate structure exposed by the first opening and the source-drain plug exposed by the second opening in the same step, and a gate groove at the bottom of the first opening and a source-drain groove at the bottom of the second opening are formed at the same time. Accordingly, a dielectric layer can be formed in the gate groove and the source-drain groove in the same step, and the dielectric layer can block the gate structure and the source-drain plug at the same time, which is beneficial to simplifying the formation process of the semiconductor structure and improving the formation efficiency of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 5 A schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0029] Figures 6 to 13 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] As can be seen from the background technology, the devices currently formed still have the problem of poor performance. The reasons for the poor performance of the devices are now analyzed in combination with a method for forming a semiconductor structure.

[0031] refer to Figures 1 to 5 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0032] like Figure 1 As shown, a substrate is provided, the substrate including a device area I and a dummy device area II, the substrate including an isolation layer 1, a gate structure 2 located on the isolation layer 1, a first mask layer 3 located on the gate structure 2, a source-drain plug 4 located on the isolation layer 1 between the gate structures 2, and a second mask layer 5 located on the source-drain plug 4.

[0033] like Figure 2As shown, a first blocking layer 6 is formed to expose the first mask layer 3 in the pseudo device area II; using the first blocking layer 6 as a mask, the first mask layer 3 on the gate structure 2 in the pseudo device area II is removed to form a first opening 7 to expose the gate structure 2; the gate structure 2 exposed by the first opening 7 is removed to form a gate groove 8.

[0034] like Figure 3 As shown, a first dielectric layer 9 is formed in the first opening 7 and the gate groove 8 .

[0035] like Figure 4 As shown, a second blocking layer 10 is formed to expose the second mask layer 5 in the dummy device area II; using the second blocking layer 10 as a mask, the second mask layer 5 on the source and drain plugs 4 in the dummy device area II is removed to form a second opening 11 exposing the source and drain plugs 4; the source and drain plugs 4 exposed by the second opening 11 are removed to form a source and drain groove 12.

[0036] like Figure 5 As shown, a second dielectric layer 13 is formed in the gate groove 8 and the source-drain groove 12 .

[0037] In advanced semiconductor processes, the spacing between the gate structures 2 is getting smaller and smaller, the mask for forming the first opening 7 and the mask for forming the second opening 11 are located in different layouts, the first opening 7 and the second opening 11 are formed in different steps, after the first opening 7 is formed, the gate groove 8 is formed according to the first opening 7, after the second opening 11 is formed, the source-drain groove 12 is formed according to the second opening 11, the gate groove 8 and the source-drain groove 12 are formed in different steps, and the corresponding first dielectric layer 9 and the second dielectric layer 13 are formed in different steps, which makes the formation process of the semiconductor structure complicated, which is not conducive to improving the formation efficiency of the semiconductor structure.

[0038] In order to solve the technical problem, the method for forming the semiconductor structure includes: providing a substrate, the substrate including a device area and a dummy device area, the substrate including an isolation layer, a gate structure located on the isolation layer, a first mask layer located on the gate structure, a source / drain plug located on the isolation layer between the gate structures, and a second mask layer located on the source / drain plug; removing the first mask layer on the gate structure in the dummy device area, forming a first opening in the first mask layer to expose the gate structure; removing the second mask layer on the source / drain plug in the dummy device area, forming a second opening in the second mask layer to expose the source / drain plug; using the remaining first mask layer and second mask layer as masks to remove the gate structure exposed by the first opening and the source / drain plug exposed by the second opening, forming a gate groove at the bottom of the first opening, and forming a source / drain groove at the bottom of the second opening; and forming a dielectric layer in the gate groove and the source / drain groove.

[0039] In the method for forming a semiconductor structure provided in an embodiment of the present invention, the substrate includes a device area and a dummy device area, the substrate includes an isolation layer, a gate structure located on the isolation layer, a first mask layer located on the gate structure, a source / drain plug located on the isolation layer between the gate structures, and a second mask layer located on the source / drain plug; the first mask layer on the gate structure in the dummy device area is removed to form a first opening exposing the gate structure; the second mask layer on the source / drain plug in the dummy device area is removed to form a second opening exposing the source / drain plug. In an embodiment of the present invention, the first mask layer and the second mask layer on the dummy device area are removed respectively, and accordingly, the remaining first mask layer and the second mask layer expose the gate structure and the source-drain plug in the dummy device area, and the remaining first mask layer and the second mask layer are used as masks to remove the gate structure exposed by the first opening and the source-drain plug exposed by the second opening in the same step, and a gate groove at the bottom of the first opening and a source-drain groove at the bottom of the second opening are formed at the same time. Accordingly, a dielectric layer can be formed in the gate groove and the source-drain groove in the same step, and the dielectric layer can block the gate structure and the source-drain plug at the same time, which is beneficial to simplifying the formation process of the semiconductor structure and improving the formation efficiency of the semiconductor structure.

[0040] Figures 6 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0041] refer to Figure 6 and Figure 7 , Figure 6 and Figure 7The cross-sectional views at different positions provide a substrate 200, wherein the substrate 200 includes a device region I and a dummy device region II, and the substrate 200 includes an isolation layer 100, a gate structure 101 located on the isolation layer 100, a first mask layer 102 located on the gate structure 101, source and drain plugs 103 located on the isolation layer 100 between the gate structures 101, and a second mask layer 104 located on the source and drain plugs 103.

[0042] This embodiment takes the formed semiconductor structure as a fin field effect transistor as an example.

[0043] In the step of providing the substrate 200 , the substrate 200 further includes: providing a substrate 105 and a fin 301 located on the substrate 105 .

[0044] The substrate 105 provides a process foundation for the subsequent formation of a semiconductor structure.

[0045] In this embodiment, the substrate 105 is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0046] The isolation layer 100 is located on the substrate 105 where the fin 301 is exposed, and the isolation layer 100 covers a portion of the sidewall of the fin 301 .

[0047] The isolation layer 100 is used to isolate the gate structure 101 from the substrate 105 , and to isolate the source-drain plug 103 from the substrate 105 .

[0048] The isolation layer 100 is used to electrically isolate adjacent devices.

[0049] In this embodiment, the material of the isolation layer 100 includes silicon oxide. Silicon oxide is a commonly used dielectric material with low cost and high process compatibility, which is conducive to reducing the process difficulty and process cost of forming the isolation layer 100; in addition, the dielectric constant of silicon oxide is small, which is also conducive to improving the function of the rear isolation layer 100 for isolating adjacent devices.

[0050] The gate structure 101 spans across the fin 301 and covers a portion of a top wall and a portion of a side wall of the fin 301 .

[0051] The gate structure 101 is used to open or close the channel when the semiconductor structure is working.

[0052] Specifically, the material of the gate structure 101 includes metal.

[0053] In this embodiment, the gate structure 101 includes a work function layer 1011 and a metal gate layer 1012 located on the work function layer 1011 .

[0054] When the semiconductor structure is working, the work function layer 1011 is used to adjust the threshold voltage of the transistor.

[0055] In this embodiment, the material of the metal gate layer 1012 includes magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer includes one or more of Co, Ru and W.

[0056] It should be noted that a spacer layer 106 is formed on the sidewall of the gate structure 101 .

[0057] In the subsequent process of removing the first mask layer 102 on the gate structure 101 to form a first opening exposing the gate structure 101, the sidewall layer 106 is used to limit the formation position of the first opening, so that the source and drain plugs 103 on the isolation layer 100 between the gate structures 101 are not easily etched by mistake, which is beneficial to improving the electrical performance of the semiconductor structure.

[0058] The material of the spacer layer 106 is a low-K dielectric material, which is beneficial to reducing the capacitive coupling effect between the gate structure 101 and the source-drain plug 103 and improving the electrical performance of the semiconductor structure.

[0059] The material of the spacer layer 106 includes: SiON, SiBCN, SiCN, carbon-doped SiN or oxygen-doped SiN. In this embodiment, the material of the spacer layer 106 is C- or N-containing silicon nitride.

[0060] In the step of providing the substrate 200, the first mask layer 102 is used to protect the top of the gate structure 101 from being damaged, and in the subsequent step of removing the second mask layer 104 on the top of the source / drain plug 103, the etching rate of the first mask layer 102 is lower than the etching rate of the second mask layer 104. The first mask layer 102 is used to protect the top of the gate structure 101 from being damaged, which is beneficial to improving the control ability of the gate structure 101 over the channel when the semiconductor structure is working, so that the electrical performance of the semiconductor structure is improved.

[0061] In this embodiment, the material of the first mask layer 102 is a dielectric material.

[0062] Specifically, the material of the first mask layer 102 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbon nitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the material of the first mask layer 102 includes silicon nitride.

[0063] In the step of providing the substrate 200 , a source-drain doped layer 302 is formed in the fins 301 on both sides of the gate structure 101 ; an interlayer dielectric layer 303 is formed on the source-drain doped layer 302 on both sides of the gate structure 101 , and the top surface of the interlayer dielectric layer 303 is lower than or flush with the top of the gate structure 101 .

[0064] When the semiconductor structure is working, the source-drain doped layer 302 is used to provide stress to the channel and improve the migration rate of carriers in the channel.

[0065] In this embodiment, the semiconductor structure is used to form NMOS (Negative channel Metal Oxide Semiconductor), and the source and drain doping layer 302 is silicon carbide or silicon phosphide doped with N-type ions. In this embodiment, N-type ions are doped into silicon carbide or silicon phosphide to replace the position of silicon atoms in the lattice. The more N-type ions are doped, the higher the concentration of majority carriers is, and the stronger the conductive performance is. In this embodiment, the N-type ions include: phosphorus, arsenic or antimony.

[0066] In other embodiments, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor). The source and drain doping layers are doped with P-type ion silicon germanium. In this embodiment, P-type ions are doped into silicon germanium to replace the position of silicon atoms in the lattice. The more P-type ions are doped, the higher the concentration of majority carriers is, and the stronger the conductivity is. In this embodiment, the P-type ions include: boron, gallium or indium.

[0067] The source-drain plug 103 is located on the top of the source-drain doped layer 302. The source-drain plug 103 is used to connect the source-drain doped layer 302.

[0068] Specifically, the source-drain plugs 103 are located in the interlayer dielectric layer 303 .

[0069] In this embodiment, the source-drain plug 103 is a stacked structure. Specifically, the source-drain plug 103 includes a barrier layer (not shown in the figure) and a source-drain metal layer (not shown in the figure) located on the barrier layer.

[0070] The barrier layer prevents the material in the source-drain plug 103 from diffusing into the spacer layer 106 and the interlayer dielectric layer 303 , and prevents the gate structure 101 from bridging the source-drain plug 103 , which is beneficial to improving the electrical performance of the semiconductor structure.

[0071] Specifically, the material of the barrier layer includes one or more of TaN, Ta, Ti, TiN, ZrN and ZrTiN. In this embodiment, the material of the barrier layer is TaN.

[0072] In this embodiment, the material of the source-drain metal layer includes one or more of Co, Ru and W.

[0073] In the step of providing the substrate 200, the second mask layer 104 is used to protect the top of the source-drain plug 103 from being damaged, and in the subsequent step of removing the first mask layer 102 on the gate structure 101 in the dummy device area II, the etching rate of the second mask layer 104 is lower than the etching rate of the first mask layer 102. The second mask layer 104 is used to protect the top of the source-drain plug 103 from being damaged. When the semiconductor structure is working, the source-drain doping layer 302 connected to the source-drain plug 103 provides sufficient stress to the channel, thereby increasing the migration rate of carriers in the channel, thereby improving the electrical performance of the semiconductor structure.

[0074] In this embodiment, the material of the second mask layer 104 is a dielectric material.

[0075] Specifically, the material of the second mask layer 104 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbon nitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the material of the second mask layer 104 includes silicon carbide.

[0076] It should be noted that the step of providing the substrate 200 includes: providing a substrate 105 and a fin 301 located on the substrate 105; forming the isolation layer 100 on the substrate 105 at the side of the fin 301, and the isolation layer 100 covers a portion of the side wall of the fin 301; forming a dummy gate structure across the fin 301 on the isolation layer 100, and the dummy gate structure covers a portion of the top wall and a portion of the side wall of the fin 301; forming a source-drain doped layer 302 in the fin 301 on both sides of the dummy gate structure; forming an interlayer dielectric layer 303 on the source-drain doped layer 302 at the side of the dummy gate structure, and the interlayer dielectric layer 303 The top surface of 03 is lower than or flush with the top surface of the dummy gate structure; the dummy gate structure is removed to form a gate opening in the interlayer dielectric layer 303; a gate structure 101 is formed in the gate opening; the gate structure 101 is etched back by a portion of the thickness to form a first groove on the top of the gate structure 101; a first mask layer is formed in the first groove; the interlayer dielectric layer 303 is etched to form a second groove in the interlayer dielectric layer 303 to expose the source-drain doped layer 302; a source-drain plug 103 is formed in the second groove; the source-drain plug 103 is etched back by a portion of the thickness to form a second mask layer on the top of the source-drain plug 103.

[0077] refer to Figure 8 and Fig. 9 , Figure 8 and Fig. 9 Based on Figure 7 The schematic cross-sectional view shows that the first mask layer 102 on the gate structure 101 in the dummy device region II is removed, and a first opening 107 is formed in the first mask layer 102 to expose the gate structure 101 .

[0078] The first opening 107 is prepared for the subsequent formation of a gate groove that disconnects the gate structure 101 .

[0079] In the step of removing the first mask layer 102 on the gate structure 101 of the dummy device region II, the etching rate of the first mask layer 102 is greater than the etching rate of the second mask layer 104. The second mask layer 104 can protect the top of the source-drain plug 103 from being easily damaged. When the semiconductor structure is working, the source-drain doped layer 302 connected to the source-drain plug 103 provides sufficient stress to the channel, improves the migration rate of carriers in the channel, and improves the electrical performance of the semiconductor structure.

[0080] In this embodiment, the first mask layer 102 on the gate structure 101 in the dummy device region II is etched using a dry etching process to form a first opening 107 exposing the gate structure 101. The dry etching process has anisotropic etching characteristics, has good etching profile controllability, and in the process of etching the first mask layer 102, the second mask layer 104 on the side of the first mask layer 102 is less damaged, which is conducive to making the morphology of the first opening 107 meet the process requirements, and is not easy to cause damage to the source and drain plugs 103, preparing for the subsequent removal of the gate structure 101 in the dummy device region II.

[0081] The step of forming the first opening 107 includes: forming a first blocking layer 108 covering the device area I and exposing the first mask layer 102 in the dummy device area II; and removing the first mask layer 102 in the dummy device area II using the first blocking layer 108 as a mask.

[0082] The first shielding layer 108 is a material that is easy to remove, which can reduce damage to the remaining first mask layer 102 and the second mask layer 104 when the first shielding layer 108 is subsequently removed.

[0083] The material of the first shielding layer 108 is an organic material, such as BARC (bottom anti-reflective coating) material, ODL (organic dielectric layer) material, photoresist, DARC (dielectric anti-reflective coating) material, DUO (Deep UV Light Absorbing Oxide) material or APF (Advanced Patterning Film) material. In this embodiment, the material of the first shielding layer 108 includes photoresist.

[0084] The method for forming the semiconductor structure further comprises: Fig. 9 As shown, after removing the first mask layer 102 in the dummy device region II, the first blocking layer 108 is removed.

[0085] In this embodiment, an ashing process is used to remove the first shielding layer 108 .

[0086] refer to Fig.10 and Fig.11 , removing the second mask layer 104 on the source / drain plug 103 in the dummy device region II to form a second opening 110 exposing the source / drain plug 103 .

[0087] The second opening 110 is prepared for subsequently forming a source-drain groove that disconnects the source-drain plug 103 .

[0088] In the step of removing the second mask layer 104 on the source / drain plug 103 of the dummy device region II, the etching rate of the second mask layer 104 is greater than the etching rate of the first mask layer 102. The first mask layer 102 is used to protect the top of the gate structure 101 from being easily damaged, which is beneficial to improving the control ability of the gate structure 101 over the channel when the semiconductor structure is working, so that the electrical performance of the semiconductor structure is improved.

[0089] In this embodiment, a dry etching process is used to remove the second mask layer 104 on the source / drain plug 103 in the dummy device region II, so as to form a second opening 110 exposing the source / drain plug 103. The dry etching process has anisotropic etching characteristics, has good etching profile controllability, and causes less damage to the first mask layer 102 on the side of the second mask layer 104 during the etching of the second mask layer 104, which is conducive to making the morphology of the second opening 110 meet the process requirements and prepare for the subsequent removal of the source / drain plug 103 in the dummy device region II.

[0090] The step of forming the second opening 110 includes: forming a second blocking layer 109 covering the first opening 107 and the device area I and exposing the second mask layer 104 in the dummy device area II; and removing the second mask layer 104 in the dummy device area II using the second blocking layer 109 as a mask.

[0091] The second shielding layer 109 is made of a material that is easy to remove, and can reduce damage to the first mask layer 102 and the second mask layer 104 when the second shielding layer 109 is subsequently removed.

[0092] The material of the second shielding layer 109 is an organic material, such as a BARC material, an ODL material, a photoresist, a DARC material, a DUO material or an APF material. In this embodiment, the material of the second shielding layer 109 includes a photoresist.

[0093] The method for forming the semiconductor structure further comprises: Fig.11 As shown, after removing the second mask layer 104 in the dummy device area II, the second blocking layer 109 is removed.

[0094] In this embodiment, an ashing process is used to remove the second shielding layer 109 .

[0095] refer to Fig.12 , using the remaining first mask layer 102 and second mask layer 104 as masks, remove the gate structure 101 exposed by the first opening 107 and the source-drain plug 103 exposed by the second opening 110, forming a gate groove 111 at the bottom of the first opening 107 and a source-drain groove 112 at the bottom of the second opening 110.

[0096] The substrate 200 includes a device region I and a dummy device region II, and the substrate 200 includes an isolation layer 100, a gate structure 101 located on the isolation layer 100, a first mask layer 102 located on the gate structure 101, a source-drain plug 103 located on the isolation layer 100 between the gate structures 101, and a second mask layer 104 located on the source-drain plug 103; the first mask layer 102 on the gate structure 101 of the dummy device region II is removed to form a first opening 107 exposing the gate structure 101; the second mask layer 104 on the source-drain plug 103 of the dummy device region II is removed to form a second opening 110 exposing the source-drain plug 103. In the embodiment of the present invention, the first mask layer 102 and the second mask layer 104 on the dummy device area II are removed respectively, and accordingly, the remaining first mask layer 102 and the second mask layer 104 expose the gate structure 101 and the source-drain plug 103 in the dummy device area II, and the remaining first mask layer 102 and the second mask layer 104 are used as masks to remove the gate structure 101 exposed by the first opening 107 and the source-drain plug 103 exposed by the second opening 110 in the same step, and the gate groove 111 at the bottom of the first opening 107 and the source-drain groove 112 at the bottom of the second opening 110 are formed at the same time, and accordingly, a dielectric layer can be formed in the gate groove 111 and the source-drain groove 112 in the same step, and the dielectric layer can block the gate structure 101 and the source-drain plug 103 at the same time, which is beneficial to simplifying the formation process of the semiconductor structure and improving the formation efficiency of the semiconductor structure.

[0097] The gate groove 111 and the source / drain groove 112 provide a process space for the subsequent formation of a dielectric layer.

[0098] In the step of etching the gate structure 101 using the first mask layer 102 and the second mask layer 104 as masks, the etching rate of the gate structure 101 is greater than the etching rate of the first mask layer 102 and the second mask layer 104 .

[0099] In the step of etching the source-drain plug 103 using the first mask layer 102 and the second mask layer 104 as masks, the etching rate of the source-drain plug 103 is greater than the etching rate of the first mask layer 102 and the second mask layer 104 .

[0100] In this embodiment, the gate structure 101 exposed by the first opening 107 and the source-drain plug 103 exposed by the second opening 110 are removed by dry etching process using the remaining first mask layer 102 and second mask layer 104 as masks. The dry etching process has anisotropic etching characteristics, and the etched area is easily limited to the area exposed by the first opening 107 and the second opening 110, and has good etching profile controllability, which is conducive to making the morphology of the gate groove 111 and the source-drain groove 112 meet the process requirements, and the gate structure 101 can be disconnected by the gate groove 111, and the source-drain plug 103 can be disconnected by the source-drain groove 112. In this embodiment, the material of the gate structure 101 and the source-drain plug 103 includes metal, and the gate structure 101 and the source-drain plug 103 exposed by the first opening 107 and the second opening 110 are etched by the dry etching process, which is conducive to simplifying the formation process of the source-drain groove 112 and the gate groove 111, and improving the formation efficiency of the semiconductor structure.

[0101] The process parameters for removing the gate structure 101 exposed by the first opening 107 and the source / drain plug 103 exposed by the second opening 110 using the first mask layer 102 and the second mask layer 104 as masks include: the etching gas includes one or both of CH3F and SF6; the flow rate of the etching gas is 50 sccm to 500 sccm; the auxiliary gas includes O2; the chamber pressure is 5 mToor to 200 mToor; and the power is 50 W to 500 W.

[0102] It should be noted that the flow rate of the etching gas should not be too large or too small. If the flow rate of the etching gas is too large, it is easy to produce a large etching rate, and it is easy to mistakenly etch the gate structure 101 and the source-drain plug 103 in the device area I. When the semiconductor structure is working, the gate structure 101 has a weak control ability over the channel, and the current in the source-drain plug 103 is unstable, resulting in the source-drain doping layer 302 having a weak stress on the channel, and the migration rate of the carriers in the channel is small, and the electrical performance of the semiconductor structure is poor. If the flow rate of the etching gas is too small, the removal rate of the gate structure 101 exposed by the first opening 107 and the source-drain plug 103 exposed by the second opening 110 is too slow, which is not conducive to improving the formation efficiency of the semiconductor structure. In this embodiment, the flow rate of the etching gas is 50 sccm to 500 sccm.

[0103] The auxiliary gas O2 is used to increase the etching selectivity ratio of the gate structure 101 to the first mask layer 102 and the second mask layer 104, and the etching selectivity ratio of the source-drain plug 103 to the first mask layer 102 and the second mask layer 104 during the etching process, so that the gate structure 101 and the source-drain plug 103 under the first mask layer 102 and the second mask layer 104 in the device area I are not easily damaged, which is beneficial to improving the electrical performance of the semiconductor structure.

[0104] It should be noted that the chamber pressure should not be too high or too low. If the chamber pressure is too low, the density of the plasma of the etching gas in the chamber is low, which may lead to a low etching rate of the gate structure 101 exposed by the first opening 107 and the source drain plug 103 exposed by the second opening 110, which is not conducive to improving the formation efficiency of the source drain groove 112 and the gate groove 111. If the chamber pressure is too high, the decomposition rate of the byproducts generated during the etching process will be too slow, and accordingly, the rate at which the byproducts are discharged from the chamber will be too slow, resulting in poor morphology of the source drain groove 112 and the gate groove 111. If the chamber pressure is too high, it may also lead to a fast removal rate of the gate structure 101 exposed by the first opening 107 and the source drain plug 103 exposed by the second opening 110, which may easily reduce the process controllability and reaction rate uniformity of the etching process, resulting in poor process stability. In this embodiment, the chamber pressure is 10mTorr to 300mTorr.

[0105] It should be noted that the etching power should not be too large or too small. If the etching power is too large, the gate structure 101 exposed by the first opening 107 and the source-drain plug 103 exposed by the second opening 110 are removed at a faster rate, which is easy to reduce the process controllability and reaction rate uniformity of the etching process, resulting in poor process stability. If the etching power is too small, it takes too much process time to form the source-drain groove 112 and the gate groove 111. In this embodiment, the etching power is 50W to 500W.

[0106] refer to Fig.13 , a dielectric layer 113 is formed in the gate groove 111 and the source / drain groove 112 .

[0107] The dielectric layer 113 in the gate groove 111 is used to electrically isolate the gate structure 101 in the device area I on both sides of the dummy device area II, and the dielectric layer 113 in the source and drain groove 112 is used to electrically isolate the source and drain plugs 103 in the device area I on both sides of the dummy device area II.

[0108] It should be noted that, in the step of forming the dielectric layer 113 in the gate groove 111 and the source-drain groove 112 , the dielectric layer 113 is also formed in the first opening 107 and the second opening 110 .

[0109] In this embodiment, the material of the dielectric layer 113 includes silicon oxide.

[0110] The step of forming a dielectric layer 113 in the gate groove 111 and the source-drain groove 112 includes: forming a dielectric material layer on the gate groove 111, the source-drain groove 112, the first opening 107, the second opening 110, and the first mask layer 102 and the second mask layer 104; removing the dielectric material layer above the first mask layer 102 and the second mask layer 104, and the remaining dielectric material layer located in the gate groove 111, the source-drain groove 112, the first opening 107 and the second opening 110 serves as the dielectric layer 113.

[0111] In this embodiment, the dielectric material layer is formed by a flowable chemical vapor deposition (FCVD) process. The flowable chemical vapor deposition process has good filling ability and is suitable for filling openings with high aspect ratios, which is beneficial to reducing the probability of defects such as voids being formed in the dielectric material layer, and correspondingly is beneficial to improving the film quality of the dielectric layer 113.

[0112] The method for forming the semiconductor structure further includes: after forming the dielectric layer 113 , forming a gate plug (not shown in the figure) on the top of the gate structure.

[0113] The gate plug is formed above the gate structure 101 in the active area, thereby eliminating the portion of the gate structure 101 located in the dummy device area II, which is beneficial to saving chip area, improving the integration of the semiconductor structure, further reducing the chip size, and improving the integration of the semiconductor structure.

[0114] In this embodiment, the gate plug is made of copper. Copper has a low resistivity, which is beneficial to improving the signal delay of the back-end RC and increasing the processing speed of the chip. It is also beneficial to reduce the resistance of the gate plug, which reduces power consumption accordingly. In other embodiments, the gate plug may also be made of tungsten or cobalt.

[0115] The steps of forming a gate plug include: after forming the dielectric layer 113, forming an intermetallic dielectric layer (IMD) on the first mask layer 102, the second mask layer 104 and the dielectric layer 113; forming a third opening in the intermetallic dielectric layer to expose the top of the gate structure 101; forming a gate contact material layer on the third opening and the intermetallic dielectric layer; removing the gate contact material layer above the intermetallic dielectric layer, and the remaining gate contact material layer located in the third opening serves as the gate plug.

[0116] In this embodiment, the gate contact material layer is formed by electroplating (ECP) process. In other embodiments, the gate contact material layer can also be formed by metal-organic chemical vapor deposition (MOCVD, Metal-organic Chemical Vapor Deposition).

[0117] In this embodiment, a chemical mechanical polishing process is used to remove the gate contact material layer higher than the intermetallic dielectric layer. Chemical mechanical planarization (CMP) is a global surface flattening technology. The CMP process can accurately and evenly remove the intermetallic dielectric layer located on the first mask layer 102 and the second mask layer 104, which is beneficial to improve the flatness of the top surface of the gate plug.

[0118] Correspondingly, an embodiment of the present invention further provides a semiconductor structure. Fig.11 A schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.

[0119] The semiconductor structure includes: a substrate 200, the substrate 200 includes a device region I and a dummy device region II, the substrate 200 includes an isolation layer 100, a gate structure 101 located on the isolation layer 100, a first mask layer 102 located on the gate structure 101, a source-drain plug 103 located on the isolation layer 100 between the gate structures 101, and a second mask layer 104 located on the source-drain plug 103; a first opening 107, located in the first mask layer 102, the first opening 107 exposes the gate structure 101 of the dummy device region II; a second opening 110, located in the second mask layer 104, the second opening 110 exposes the source-drain plug 103 of the dummy device region II.

[0120] In the semiconductor structure provided by the embodiment of the present invention, the first opening 107 is located in the first mask layer 102, and the first opening 107 exposes the gate structure 101 of the dummy device region II; the second opening 110 is located in the second mask layer 104, and the second opening 110 exposes the source-drain plug 103 of the dummy device region II. Subsequently, the gate structure 101 exposed by the first opening 107 and the source-drain plug 103 exposed by the second opening 110 are removed in the same step using the remaining first mask layer 102 and the second mask layer 104 as masks, and a gate groove is formed at the bottom of the first opening 107, and a source-drain groove is formed at the bottom of the second opening 110. In the same step, a dielectric layer is formed in the gate groove and the source-drain groove, which is conducive to simplifying the formation process of the semiconductor structure, and is conducive to simplifying the formation process of the semiconductor structure and improving the formation efficiency of the semiconductor structure. The gate structure 101 and the source-drain plug 103 exposed by the first opening 107 and the second opening 110 are generally etched by a dry etching process, which is beneficial to simplify the process of forming the source-drain groove and the gate groove and improve the formation efficiency of the semiconductor structure.

[0121] This embodiment takes the formed semiconductor structure as a fin field effect transistor as an example.

[0122] The base 200 further includes: providing a substrate 105 and a fin 301 (such as Figure 6 shown).

[0123] In this embodiment, the substrate 105 is a silicon substrate. In other embodiments, the substrate material may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0124] The isolation layer 100 is located on the substrate 105 where the fin 301 is exposed, and the isolation layer 100 covers a portion of the sidewall of the fin 301 .

[0125] The isolation layer 100 is used to isolate the gate structure 101 from the substrate 105 at the bottom of the isolation layer 100 , and to isolate the source-drain plug 103 from the substrate 105 at the bottom of the isolation layer 100 .

[0126] The isolation layer 100 is used to electrically isolate adjacent devices.

[0127] In this embodiment, the material of the isolation layer 100 includes silicon oxide. Silicon oxide is a commonly used dielectric material with low cost and high process compatibility, which is conducive to reducing the process difficulty and process cost of forming the isolation layer 100; in addition, the dielectric constant of silicon oxide is small, which is also conducive to improving the function of the rear isolation layer 100 for isolating adjacent devices.

[0128] The gate structure 101 spans across the fin 301 and covers a portion of a top wall and a portion of a side wall of the fin 301 .

[0129] The gate structure 101 is used to open or close the channel when the semiconductor structure is working.

[0130] Specifically, the material of the gate structure 101 includes metal.

[0131] In this embodiment, the gate structure 101 includes a work function layer 1011 and a metal gate layer 1012 located on the work function layer 1011 .

[0132] When the semiconductor structure is working, the work function layer 1011 is used to adjust the threshold voltage of the transistor.

[0133] In this embodiment, the material of the metal gate layer 1012 includes magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer includes one or more of Co, Ru and W.

[0134] It should be noted that a spacer layer 106 is formed on the sidewall of the gate structure 101 .

[0135] The spacer layer 106 is used to define the formation position of the first opening, so that the source-drain plugs 103 on the isolation layer 100 between the gate structures 101 are not easily etched by mistake, which is beneficial to improving the electrical performance of the semiconductor structure.

[0136] The material of the spacer layer 106 is a low-K dielectric material, which is beneficial to reducing the capacitive coupling effect between the gate structure 101 and the source-drain plug 103 and improving the electrical performance of the semiconductor structure.

[0137] The material of the spacer layer 106 includes: SiON, SiBCN, SiCN, carbon-doped SiN or oxygen-doped SiN. In this embodiment, the material of the spacer layer 106 is C- or N-containing silicon nitride.

[0138] In the step of forming the second opening 110, the first mask layer 102 is used to protect the top of the gate structure 101 from being damaged. The etching rate of the first mask layer 102 is lower than the etching rate of the second mask layer 104. The first mask layer 102 is used to protect the top of the gate structure 101 from being damaged. When the semiconductor structure is working, it is beneficial to improve the control ability of the gate structure 101 over the channel, so that the electrical performance of the semiconductor structure is improved.

[0139] In this embodiment, the material of the first mask layer 102 is a dielectric material.

[0140] Specifically, the material of the first mask layer 102 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbon nitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the material of the first mask layer 102 includes silicon nitride.

[0141] The substrate 200 further includes: a source-drain doping layer 302 (such as Figure 6 ), located in the fins 301 on both sides of the gate structure 101.

[0142] When the semiconductor structure is working, the source-drain doped layer 302 is used to provide stress to the channel and improve the migration rate of carriers in the channel.

[0143] In this embodiment, the semiconductor structure is used to form NMOS (Negative channel Metal Oxide Semiconductor), and the source and drain doping layer 302 is silicon carbide or silicon phosphide doped with N-type ions. In this embodiment, N-type ions are doped into silicon carbide or silicon phosphide to replace the position of silicon atoms in the lattice. The more N-type ions are doped, the higher the concentration of majority carriers is, and the stronger the conductive performance is. In this embodiment, the N-type ions include: phosphorus, arsenic or antimony.

[0144] In other embodiments, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor). The source and drain doping layers are doped with P-type ion silicon germanium. In this embodiment, P-type ions are doped into silicon germanium to replace the position of silicon atoms in the lattice. The more P-type ions are doped, the higher the concentration of majority carriers is, and the stronger the conductivity is. In this embodiment, the P-type ions include: boron, gallium or indium.

[0145] The source-drain plug 103 is located on the top of the source-drain doped layer 302. The source-drain plug 103 is used to connect the source-drain doped layer 302.

[0146] The substrate 200 further includes an interlayer dielectric layer 303 (such as Figure 6 As shown), it is located on the source / drain doped layer 302 at the side of the gate structure 101, and the top surface of the interlayer dielectric layer 303 is lower than or flush with the top of the gate structure 101.

[0147] Specifically, the source-drain plugs 103 are located in the interlayer dielectric layer 303 .

[0148] In this embodiment, the source-drain plug 103 is a stacked structure. Specifically, the source-drain plug 103 includes a barrier layer (not shown in the figure) and a source-drain metal layer (not shown in the figure) located on the barrier layer.

[0149] The barrier layer prevents the material in the source-drain plug 103 from diffusing into the spacer layer 106 and the interlayer dielectric layer 303 , and prevents the gate structure 101 from bridging the source-drain plug 103 , which is beneficial to improving the electrical performance of the semiconductor structure.

[0150] Specifically, the material of the barrier layer includes one or more of TaN, Ta, Ti, TiN, ZrN and ZrTiN. In this embodiment, the material of the barrier layer is TaN.

[0151] In this embodiment, the material of the source-drain metal layer includes one or more of Co, Ru and W.

[0152] In the step of forming the first opening 107, the second mask layer 104 is used to protect the top of the source-drain plug 103 from being easily damaged. The etching rate of the second mask layer 104 is lower than the etching rate of the first mask layer 102. The second mask layer 104 is used to protect the top of the source-drain plug 103 from being easily damaged. When the semiconductor structure is working, the source-drain doping layer 302 connected to the source-drain plug 103 provides sufficient stress to the channel, thereby increasing the migration rate of carriers in the channel, thereby improving the electrical performance of the semiconductor structure.

[0153] In this embodiment, the material of the second mask layer 104 is a dielectric material.

[0154] Specifically, the material of the second mask layer 104 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbon nitride oxide, silicon nitride oxide, boron nitride and boron carbonitride. In this embodiment, the material of the first mask layer 102 includes silicon carbide.

[0155] The first opening 107 is prepared for the subsequent formation of a gate groove that disconnects the gate structure 101 .

[0156] In the step of forming the first opening 107, the etching rate of the first mask layer 102 is greater than the etching rate of the second mask layer 104. The second mask layer 104 can protect the top of the source-drain plug 103 from being easily damaged. When the semiconductor structure is working, the source-drain doped layer 302 connected to the source-drain plug 103 provides sufficient stress to the channel, thereby increasing the migration rate of carriers in the channel, thereby improving the electrical performance of the semiconductor structure.

[0157] The second opening 110 is prepared for subsequently forming a source-drain groove that disconnects the source-drain plug 103 .

[0158] In the step of forming the second opening 110, the etching rate of the second mask layer 104 is greater than the etching rate of the first mask layer 102. The first mask layer 102 is used to protect the top of the gate structure 101 from being damaged, which is beneficial to improving the control ability of the gate structure 101 over the channel when the semiconductor structure is working, so that the electrical performance of the semiconductor structure is improved.

[0159] The semiconductor structure can be formed by the forming method of the above embodiment, or by other forming methods. For the specific description of the semiconductor structure of this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0160] Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a device region and a dummy device region, the substrate comprising an isolation layer, a gate structure located on the isolation layer, a first mask layer located on the gate structure, a source-drain plug located on the isolation layer between the gate structures, and a second mask layer located on the source-drain plug; removing the first mask layer on the gate structure of the dummy device region, and forming a first opening in the first mask layer to expose the gate structure; removing the second mask layer on the source / drain plug in the dummy device region, and forming a second opening in the second mask layer to expose the source / drain plug; Using the remaining first mask layer and the second mask layer as masks, remove the gate structure exposed by the first opening and the source-drain plug exposed by the second opening, forming a gate groove at the bottom of the first opening and a source-drain groove at the bottom of the second opening; A dielectric layer is formed in the gate groove and the source-drain groove.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first mask layer on the gate structure in the dummy device region is removed by a dry etching process.

3. The method for forming a semiconductor structure according to claim 1, wherein: In the step of removing the first mask layer on the gate structure of the dummy device region, an etching rate of the first mask layer is greater than an etching rate of the second mask layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first mask layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

5. The method for forming a semiconductor structure according to claim 1, wherein: The second mask layer on the source / drain plugs in the dummy device region is removed by a dry etching process.

6. The method for forming a semiconductor structure according to claim 1, wherein: In the step of removing the second mask layer on the source / drain plug in the dummy device region, an etching rate of the second mask layer is greater than an etching rate of the first mask layer.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second mask layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

8. The method for forming a semiconductor structure according to claim 1, wherein: The step of removing the first mask layer on the source / drain plug in the dummy device region to form a first opening includes: forming a first blocking layer covering the device area and exposing the first mask layer in the dummy device area; Using the first shielding layer as a mask, removing the first mask layer in the dummy device area; The method for forming a semiconductor structure further includes: after removing the first mask layer in the dummy device area, removing the first blocking layer.

9. The method for forming a semiconductor structure according to claim 1, wherein: forming the first opening; After forming the first opening, forming the second opening; The step of removing the second mask layer on the source / drain plug in the dummy device region to form a second opening comprises: forming a second blocking layer covering the first opening and the device region and exposing the second mask layer in the dummy device region; Using the second shielding layer as a mask, removing the second mask layer in the dummy device area; The method for forming a semiconductor structure further includes: after removing the second mask layer in the dummy device area, removing the second blocking layer.

10. The method for forming a semiconductor structure according to claim 1, wherein: The gate structure exposed by the first opening and the source-drain plug exposed by the second opening are removed by a dry etching process using the remaining first mask layer and the second mask layer as masks.

11. The method for forming a semiconductor structure according to claim 10, wherein: The process parameters for removing the gate structure exposed by the first opening and the source / drain plug exposed by the second opening using the first mask layer and the second mask layer as masks include: the etching gas includes one or both of CH3F and SF6; the flow rate of the etching gas is 50 sccm to 500 sccm; the auxiliary gas includes O2; the chamber pressure is 5 mToor to 200 mToor; and the etching power is 50 W to 500 W.

12. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a substrate, the substrate further comprises: substrate; A fin portion, located on the substrate; The isolation layer is located on the substrate at the side of the fin, and the isolation layer covers a portion of the sidewall of the fin; The gate structure crosses the fin on the isolation layer and covers a portion of the top wall and a portion of the side wall of the fin; The substrate further includes: a source-drain doping layer located in the fins on both sides of the gate structure; The source-drain plug is located on the top of the source-drain doping layer; The substrate further includes an interlayer dielectric layer located on the source-drain doped layer at the side of the gate structure, and the top surface of the interlayer dielectric layer is lower than or flush with the top surface of the gate structure.

13. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the semiconductor structure further includes: after forming the dielectric layer, forming a gate plug on the top of the gate structure.

14. The method for forming a semiconductor structure according to claim 1, wherein: The material of the gate structure includes metal.

15. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a device region and a dummy device region, the substrate comprising an isolation layer, a gate structure located on the isolation layer, a first mask layer located on the gate structure, a source-drain plug located on the isolation layer between the gate structures, and a second mask layer located on the source-drain plug; A first opening, located in the first mask layer, wherein the first opening exposes the gate structure of the dummy device region; The second opening is located in the second mask layer, and the second opening exposes the source and drain plugs in the dummy device region.

16. The semiconductor structure according to claim 15, wherein: The material of the first mask layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

17. The semiconductor structure according to claim 15, wherein: The material of the second mask layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

18. The semiconductor structure according to claim 15, wherein: The substrate further comprises: substrate; A fin portion, located on the substrate; The isolation layer is located on the substrate at the side of the fin, and the isolation layer covers a part of the sidewall of the fin; The gate structure crosses the fin on the isolation layer and covers a portion of the top wall and a portion of the side wall of the fin; The substrate further includes: a source-drain doping layer located in the fins on both sides of the gate structure; The source-drain plug is located on the top of the source-drain doping layer; The substrate further includes an interlayer dielectric layer located on the source-drain doped layer at the side of the gate structure, and the top surface of the interlayer dielectric layer is lower than or flush with the top surface of the gate structure.

19. The semiconductor structure according to claim 15, wherein: The material of the gate structure includes metal.

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