Asynchronous ram continuous read-write method, device and communication system

Abstract

The application relates to the field of RAM read-write technology, and particularly discloses an asynchronous RAM continuous read-write method, wherein one address in the current asynchronous RAM is taken as a FLAG address, the asynchronous RAM continuous read-write method comprises the following steps: determining whether a read or write operation can be performed according to the state of the FLAG address; when it is determined that the write operation can be performed, continuously writing data and then writing the data depth into the asynchronous RAM address 0; and when it is determined that the read operation can be performed, continuously reading data after reading the data depth in the asynchronous RAM address 0. The application further discloses an asynchronous RAM continuous read-write device, an FPGA, a CPU and a communication system. The asynchronous RAM continuous read-write method provided by the application can solve the problem that the data in the RAM may be conflicted when the RAM is read and written across clock domains.

Description

Technical Field

[0001] This invention relates to the field of RAM read / write technology, and in particular to an asynchronous RAM continuous read / write method, an asynchronous RAM continuous read / write device, an FPGA, a CPU, and a communication system. Background Technology

[0002] RAM is a widely used type of storage resource in hardware design (such as FPGA design). In dual-CPU communication systems, RAM typically has only one set of data bus, address bus, and read / write control lines. Therefore, when two CPUs want to access the same RAM resource, an arbitration circuit is required to determine which is which. When two CPUs access shared RAM simultaneously, the arbitration circuit forces the CPU that accesses later to wait until the other CPU finishes its access. This significantly reduces the data exchange rate. Asynchronous dual-port RAM, however, has completely independent data lines, address lines, and read / write control lines, allowing two CPUs to access the same internal RAM resource simultaneously without either CPU being in a waiting state, thus enabling high-speed access to large amounts of data.

[0003] Asynchronous dual-port RAM is a memory that uses dual-port concurrent read / write control logic to perform simultaneous read / write operations on both ports in real time. Its core component is a memory array for data storage, which can be shared by both ports and has the following functions: (1) It can realize time-sharing and simultaneous access to data of dual-port RAM by two ports, including simultaneous access to data at the same address, without requiring any port to be inserted into a waiting state.

[0004] (2) The access operations of different bit data on the two ports can be controlled separately, so that the two ports can read and write different bit data.

[0005] Asynchronous RAM involves the following technologies: When two ports read from a dual-port RAM, the following four situations exist: 1) Two ports simultaneously read and write data to different address units; 2) Both ports simultaneously read data from the same address unit; 3) Both ports simultaneously write data to the same address unit; 4) Both ports can read and write to the same address unit simultaneously, with one port writing data and the other reading data.

[0006] Of the four scenarios above, scenarios 1 and 2 do not result in errors when accessing the two ports, while scenarios 3 and 4 involve contention. To avoid communication failures due to contention, common methods for operating the two ports include: Method 1: Using the BUSY signal output method. When the left and right ports do not access the same address unit, both BUSY signals are high, allowing normal storage. When the left and right ports access the same address unit simultaneously, the BUSY signal of one port is low, prohibiting data access. In this case, the port whose access request signal appears first will have its corresponding BUSY signal high, allowing access; the port whose access request signal appears later will have its corresponding BUSY signal low, prohibiting data writing. It is important to note that the time difference between the access request signals of the two ports must be greater than 5ns to determine the order of their appearance. If the time difference is less than 5ns, only one of the two BUSY signals will be low, not both. This ensures that the port with a high BUSY signal can access data normally, while the port with a low BUSY signal cannot access data, thus avoiding errors in dual-port access.

[0007] Method 2: Employing interrupt functionality. Asynchronous dual-port RAM provides interrupt functionality, using the last two adjacent memory locations (e.g., 0xFFE / 0xFFF in a 12-bit address configuration) as flag addresses. When the left port writes an access address to 0xFFF, the interrupt flag on the right port is set and cleared when the right port reads from 0xFFF; to set the interrupt flag on the left port, the right port must write a message to 0xFFE, which is cleared when the left port reads from 0xFFE. The message used to write the flag can be defined as the interrupt content.

[0008] Both of the above methods are solutions for asynchronous RAM when dealing with a single address conflict. If the asynchronous RAMs are in the same clock domain, no problem will occur; however, problems may arise if they are in different clock domains.

[0009] Therefore, how to solve the read / write conflict that may occur when asynchronous RAM read / write is in different CPU clock domains has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0010] This invention provides an asynchronous RAM continuous read / write method, an asynchronous RAM continuous read / write device, an FPGA, a CPU, and a communication system, which solves the read / write conflict problem that may occur when asynchronous RAM read / write is performed in different CPU clock domains in related technologies.

[0011] As a first aspect of the present invention, an asynchronous RAM continuous read / write method is provided, wherein one of the addresses in the current asynchronous RAM is used as a FLAG address, and the asynchronous RAM continuous read / write method includes: Determine whether a read or write operation is possible based on the status of the FLAG address; When it is determined that a write operation can be performed, after the continuous writing of data is completed, the data depth is written to asynchronous RAM address 0; Once it is determined that a read operation can be performed, data is read continuously after the data depth in asynchronous RAM address 0 is completed.

[0012] Furthermore, determining whether a read or write operation can be performed based on the status of the FLAG address includes: Read the data from the FLAG address; If a write operation is to be performed, it is determined whether the data in the FLAG address is 0; If the data in the FLAG address is 0, then it is determined that a write operation can be performed; To perform a read operation, determine whether the data in the FLAG address is 1; If the data in the FLAG address is 1, then a read operation can be performed.

[0013] Furthermore, if a write operation is to be performed and the data in the FLAG address is 1, then the step of determining whether the data in the FLAG address is 0 is repeated until the data in the FLAG address is 0. If a read operation is to be performed and the data in the FLAG address is 0, then the step of determining whether the data in the FLAG address is 1 is repeated until the data in the FLAG address is 1.

[0014] Furthermore, the step of writing the data depth to asynchronous RAM address 0 after continuous data writing is completed when it is determined that a write operation can be performed includes: When it is determined that a write operation can be performed, data is continuously written to the asynchronous RAM addresses 1 to N. Write the data depth N into the asynchronous RAM address 0; Write 1 to the data in the FLAG address; Where N is a natural number greater than 1.

[0015] Furthermore, the step of continuously reading data after completing the reading of the data depth in asynchronous RAM address 0 when it is determined that a read operation can be performed includes: When it is determined that a read operation can be performed, the value at asynchronous RAM address 0 is read, and this value is the data depth N; After reading the data depth N, continuously read the data from asynchronous RAM address 1 to address N; Write the data in the FLAG address to 0; Where N is a natural number greater than 1.

[0016] As another aspect of the present invention, an asynchronous RAM continuous read / write device is provided for implementing the asynchronous RAM continuous read / write method described above, wherein one of the addresses in the current asynchronous RAM is used as a FLAG address, and the asynchronous RAM continuous read / write device includes: The determination module is used to determine whether a read or write operation can be performed based on the status of the FLAG address. The write module is used to write the data depth to asynchronous RAM address 0 after continuous data writing is completed when it is determined that a write operation can be performed. The read module is used to continuously read data after completing the reading of the data depth in asynchronous RAM address 0 when it is determined that a read operation can be performed.

[0017] As another aspect of the present invention, an FPGA is provided, which includes the asynchronous RAM continuous read / write device described above.

[0018] As another aspect of the present invention, a CPU is provided, which includes the asynchronous RAM continuous read / write device described above.

[0019] As another aspect of the present invention, a communication system is provided, comprising: asynchronous RAM and the FPGA described above, or asynchronous RAM and the CPU described above; The FPGA or the CPU is used to read data from the asynchronous RAM or write data to the asynchronous RAM; The asynchronous RAM includes two interfaces, and one of the addresses within the asynchronous RAM is set to a FLAG address.

[0020] The asynchronous RAM continuous read / write method provided by this invention distinguishes the FLAG address from address 0, where the data depth N is located. Compared to the prior art where both the FLAG address and the data depth are stored in address 0, this method resolves the potential conflict that may occur when reading and writing data within the RAM across clock domains, especially when the two main clocks of the asynchronous RAM are asynchronous. Therefore, the asynchronous RAM continuous read / write method provided by this invention can improve the reliability of FPGA or CPU data reading from asynchronous RAM. Attached Figure Description

[0021] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof. In the drawings: Figure 1 A flowchart of the asynchronous RAM continuous read / write method provided by the present invention.

[0022] Figure 2 This is a schematic diagram of the asynchronous RAM interface provided by the present invention.

[0023] Figure 3 A schematic diagram of the structure for setting a separate FLAG address for the asynchronous RAM provided by the present invention.

[0024] Figure 4 A flowchart of asynchronous RAM sequential write operations provided by the present invention.

[0025] Figure 5 A flowchart of asynchronous RAM continuous read operation provided by the present invention. Detailed Implementation

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] In this invention, for asynchronous dual-port RAM with interrupt functionality, when the asynchronous RAMs are in different clock domains, if one port performs a read operation while the other port performs a write operation on the same address at the same time, data read or write errors may occur. Therefore, this embodiment provides a method for continuous read / write of asynchronous RAM. Figure 1 This is a flowchart of an asynchronous RAM continuous read / write method provided by an embodiment of the present invention, wherein one of the addresses in the current asynchronous RAM is used as a FLAG address (i.e., a flag bit), such as... Figure 1 As shown, the asynchronous RAM continuous read / write method includes: S110. Determine whether a read or write operation can be performed based on the status of the FLAG address; First, it should be noted that the interface of the asynchronous RAM, such as... Figure 2 As shown, it can specifically include interface A and interface B, where the function definition of interface A is as follows: A_CLK is the master clock for interface A in the asynchronous RAM; A_EN is the read / write enable for interface A in the asynchronous RAM (1 indicates write enable, 0 indicates read enable); A_ADDR is the read / write address for interface A in the asynchronous RAM; A_WR_DATA is the write data to be written to interface A in the asynchronous RAM; and A_RD_DATA is the data read from interface A in the asynchronous RAM. The control logic takes effect as follows: (1) When A_EN is high, the value on the A_ADDR bus is the address to be written to the asynchronous RAM; (2) When A_EN is low, the value on the A_ADDR bus is the address to be read from the asynchronous RAM; (3) When WR_EN is high, the value on the A_WR_DATA bus is the data to be written to the corresponding address A_ADDR of the asynchronous RAM; (4) When WR_EN is low, the value on the A_RD_DATA bus is the data to be read from the corresponding address A_ADDR of the asynchronous RAM; WR_EN represents a signal emitted by the external CPU or FPGA.

[0030] Meanwhile, the A_EN signal, A_ADDR signal, A_WR_DATA, and A_RD_DATA need to be synchronized with the A_CLK edge (rising edge or falling edge).

[0031] The other end, interface B, has the same function as interface A, so it will not be described in detail here.

[0032] To avoid errors when interface A and interface B simultaneously operate on the same address in the asynchronous RAM, this embodiment of the invention provides a continuous BURST operation method. For example... Figure 3 As shown, based on an asynchronous RAM, one of the multiple addresses of the asynchronous RAM is set as the FLAG address.

[0033] Specifically, determining whether a read or write operation can be performed based on the status of the FLAG address includes: Read the data from the FLAG address; If a write operation is to be performed, it is determined whether the data in the FLAG address is 0; If the data in the FLAG address is 0, then it is determined that a write operation can be performed; To perform a read operation, determine whether the data in the FLAG address is 1; If the data in the FLAG address is 1, then a read operation can be performed.

[0034] It should be understood that if a write operation is to be performed and the data in the FLAG address is 1, then the step of determining whether the data in the FLAG address is 0 is repeated until the data in the FLAG address is 0. If a read operation is to be performed and the data in the FLAG address is 0, then the step of determining whether the data in the FLAG address is 1 is repeated until the data in the FLAG address is 1.

[0035] S120. When it is determined that a write operation can be performed, after the continuous writing of data is completed, the data depth is written to asynchronous RAM address 0. In embodiments of the present invention, such as Figure 4 The diagram shown is a flowchart of the specific real-time method for continuous RAM writing.

[0036] First, the data in the FLAG address must be read, and it must be determined whether the data in the FLAG address is 0. If it is 0, it is determined that data can be written to the current asynchronous RAM.

[0037] When it is determined that a write operation can be performed, data is continuously written to the asynchronous RAM addresses 1 to N. Write the data depth N into the asynchronous RAM address 0; Write 1 to the data in the FLAG address; Where N is a natural number greater than 1.

[0038] In this embodiment of the invention, data is first written to addresses 1 to N in the asynchronous RAM, and then the data depth N (here, data depth can be simply understood as the number of data, for example, N sets of data, then the data depth is N sets) is written to address 0 of the asynchronous RAM. Finally, the data in the FLAG address needs to be rewritten to 1, which means that the asynchronous RAM has been written with data.

[0039] For example, in the write control logic of asynchronous RAM in an FPGA, the FLAG flag at address 0 is first retrieved. If the FLAG at address 0 is equal to 0, then the write of data to address N and N sets of data can begin.

[0040] Specifically, this includes writing data starting from address 1, and after writing to address N, writing the flag bit in address 0. At the same time, the data depth N is assigned to the depth signal Nnet.

[0041] It should be understood that the data depth N here is written to asynchronous RAM address 0, which is not the same address as the FLAG address.

[0042] For example, if the asynchronous RAM includes 1000 addresses, and the data depth to be written here is 100 (i.e., N=100), then data will be written to asynchronous RAM addresses 1 to 100 respectively, and asynchronous RAM address 0 will be written to a data depth of N. The FLAG address can be understood as one of the 1000 addresses excluding the aforementioned addresses 0 to 100.

[0043] In this embodiment of the invention, the FLAG address is distinguished from the address 0 where the data depth N is located. When writing data, the FLAG address is read first to determine whether it is equal to 0 (if it is equal to 1, it means that the data written last time has not been read or has not been read completely). If it is equal to 0 and it is determined that it can be written, the data is written first, and then the data depth is written.

[0044] It should be understood that, when performing asynchronous RAM read / write operations on an FPGA, the FPGA reads the flag bit of address 0 in real time. Once it reads data from address 0 and obtains the flag bit = 1, it enters continuous read control mode.

[0045] S130. When it is determined that a read operation can be performed, read data continuously after completing the reading of the data depth in asynchronous RAM address 0.

[0046] In embodiments of the present invention, such as Figure 5 The diagram shown is a flowchart of the specific real-time method for continuous RAM reading.

[0047] First, the data in the FLAG address is read, and it is determined whether the data in the FLAG address is 1. If it is 1, it is determined that data can be read in the current asynchronous RAM.

[0048] When it is determined that a read operation can be performed, the value at asynchronous RAM address 0 is read, and this value is the data depth N; After reading the data depth N, continuously read the data from asynchronous RAM address 1 to address N; Write the data in the FLAG address to 0; Where N is a natural number greater than 1.

[0049] In this embodiment of the invention, the data depth N in RAM address 0 is read first, then the data in asynchronous RAM from address 1 to address N is read continuously, and finally the data in FLAG address is rewritten to 0, which means that the asynchronous RAM has finished reading the data.

[0050] For example, after the FPGA enters the continuous read control mode, it first processes the depth information through an asynchronous clock to obtain the depth value to be read in this read, and then writes the value into the read control logic.

[0051] The method involves first reading data from addresses 1 to N, and then writing the flag bit at address 0. In other words, the data is read first, and then the flag bit is cleared to 0. This completes a continuous process of reading asynchronous RAM.

[0052] It should be understood that in this embodiment of the invention, the FLAG address is distinguished from the address 0 where the data depth N is located. When reading data, the FLAG address is read first to determine whether it is equal to 1 (if it is equal to 0, it means that there is no data to be read in the asynchronous RAM). If it is equal to 1 and it is determined that it can be read, the data depth is read first, and then the data is read continuously.

[0053] The asynchronous RAM continuous read / write method provided in this invention distinguishes the FLAG address from address 0, where the data depth N is located. Compared to the prior art where both the FLAG address and data depth are stored in address 0, this method resolves the potential conflict when reading and writing data within the RAM across clock domains, especially when the two main clocks of the asynchronous RAM are asynchronous. Therefore, the asynchronous RAM continuous read / write method provided by this invention improves the reliability of FPGA or CPU data reading from asynchronous RAM.

[0054] As another embodiment of the present invention, an asynchronous RAM continuous read / write device is provided for implementing the asynchronous RAM continuous read / write method described above, wherein one of the addresses in the current asynchronous RAM is used as the FLAG address, and the asynchronous RAM continuous read / write device includes: The determination module is used to determine whether a read or write operation can be performed based on the status of the FLAG address. The write module is used to write the data depth to asynchronous RAM address 0 after continuous data writing is completed when it is determined that a write operation can be performed. The read module is used to continuously read data after completing the reading of the data depth in asynchronous RAM address 0 when it is determined that a read operation can be performed.

[0055] The working principle of the asynchronous RAM continuous read / write device provided in this embodiment of the invention can be referred to the description of the asynchronous RAM continuous read / write method above, and will not be repeated here.

[0056] As another embodiment of the present invention, an FPGA is provided, which includes the asynchronous RAM continuous read / write device described above.

[0057] As another embodiment of the present invention, a CPU is provided, which includes the asynchronous RAM continuous read / write device described above.

[0058] As another embodiment of the present invention, a communication system is provided, comprising: asynchronous RAM and the FPGA described above, or asynchronous RAM and the CPU described above; The FPGA or the CPU is used to read data from the asynchronous RAM or write data to the asynchronous RAM; The asynchronous RAM includes two interfaces, and one of the addresses within the asynchronous RAM is set to a FLAG address.

[0059] The working principles of the FPGA, CPU, and communication system provided in this embodiment of the invention can be referred to the description of the asynchronous RAM continuous read / write method above, and will not be repeated here.

[0060] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. An asynchronous RAM continuous read / write method, characterized in that, The asynchronous RAM continuous read / write method includes using one of the addresses in the current asynchronous RAM as the FLAG address: Determine whether a read or write operation is possible based on the status of the FLAG address; When it is determined that a write operation can be performed, after the continuous writing of data is completed, the data depth is written to asynchronous RAM address 0; Once it is determined that a read operation can be performed, data is read continuously after the data depth in asynchronous RAM address 0 is completed. The step of determining whether a read or write operation can be performed based on the status of the FLAG address includes: Read the data from the FLAG address; If a write operation is to be performed, it is determined whether the data in the FLAG address is 0; If the data in the FLAG address is 0, then it is determined that a write operation can be performed; To perform a read operation, determine whether the data in the FLAG address is 1; If the data in the FLAG address is 1, then it is determined that a read operation can be performed; The step of writing the data depth to asynchronous RAM address 0 after continuous data writing is completed when it is determined that a write operation can be performed includes: When it is determined that a write operation can be performed, data is continuously written to the asynchronous RAM addresses 1 to N. Write the data depth N into the asynchronous RAM address 0; Write 1 to the data in the FLAG address; Where N is a natural number greater than 1; The step of continuously reading data after completing the reading of the data depth in asynchronous RAM address 0 when it is determined that a read operation can be performed includes: When it is determined that a read operation can be performed, the value at asynchronous RAM address 0 is read, and this value is the data depth N; After reading the data depth N, continuously read the data from asynchronous RAM address 1 to address N; Write the data in the FLAG address to 0; Where N is a natural number greater than 1.

2. The asynchronous RAM continuous read / write method according to claim 1, characterized in that, If a write operation is to be performed and the data in the FLAG address is 1, then the step of determining whether the data in the FLAG address is 0 is repeated until the data in the FLAG address is 0. If a read operation is to be performed and the data in the FLAG address is 0, then the step of determining whether the data in the FLAG address is 1 is repeated until the data in the FLAG address is 1.

3. An asynchronous RAM continuous read / write device, used to implement the asynchronous RAM continuous read / write method according to any one of claims 1 to 2, characterized in that, The asynchronous RAM continuous read / write device includes: (The device uses one of the addresses in the current asynchronous RAM as the FLAG address.) The determination module is used to determine whether a read or write operation can be performed based on the status of the FLAG address. The write module is used to write the data depth to asynchronous RAM address 0 after continuous data writing is completed when it is determined that a write operation can be performed. The read module is used to continuously read data after completing the reading of the data depth in asynchronous RAM address 0 when it is determined that a read operation can be performed.

4. An FPGA, characterized in that, Includes the asynchronous RAM continuous read / write device as described in claim 3.

5. A CPU, characterized in that, Includes the asynchronous RAM continuous read / write device as described in claim 3.

6. A communication system, characterized in that, include: Asynchronous RAM and the FPGA of claim 4, or asynchronous RAM and the CPU of claim 5; The FPGA or the CPU is used to read data from the asynchronous RAM or write data to the asynchronous RAM; The asynchronous RAM includes two interfaces, and one of the addresses within the asynchronous RAM is set to a FLAG address.

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